From f1b7e8976668075e6215191680cfb6a194b3c2ce Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Thu, 3 Jun 2021 15:22:19 -0700 Subject: arm64: dts: qcom: sc7180: Add DisplayPort node Add DP device node on sc7180. Signed-off-by: Kuogee Hsieh Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1622758940-13485-1-git-send-email-khsieh@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 9 ++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 76 ++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 77ae7561d436..43126c56e320 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -778,6 +778,15 @@ hp_i2c: &i2c9 { status = "okay"; }; +&mdss_dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hot_plug_det>; + data-lanes = <0 1>; + vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; + vdda-0p9-supply = <&vdda_usb_ss_dp_core>; +}; + &pm6150_adc { charger-thermistor@4f { reg = ; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a5d58eb92896..0d33c671751b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2928,6 +2928,13 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; mdp_opp_table: mdp-opp-table { @@ -3044,6 +3051,75 @@ status = "disabled"; }; + + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sc7180-dp"; + status = "disabled"; + + reg = <0 0x0ae90000 0 0x1400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7180_CX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; dispcc: clock-controller@af00000 { -- cgit v1.2.3 From e1746c6d3e4bc516bfdce6946720c512a4e27e19 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Wed, 27 Jan 2021 16:20:29 +0200 Subject: arm64: dts: qcom: ipq6018: enable USB2 support Signed-off-by: Kathiravan T [baruch: adjust regs address/size; drop binding updates; drop unsupported quirk properties] Signed-off-by: Baruch Siach Link: https://lore.kernel.org/r/59a0d43f34b69406cd320f16edc4e7fabe022bfd.1611756920.git.baruch@tkos.co.il Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 +++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 99cefe88f6f2..5aec18308712 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -78,3 +78,11 @@ nand-bus-width = <8>; }; }; + +&qusb_phy_1 { + status = "ok"; +}; + +&usb2 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9fa5b028e4f3..d4a3d4e4a7e9 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -524,6 +524,54 @@ }; }; + qusb_phy_1: qusb@59000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x059000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; + status = "disabled"; + }; + + usb2: usb2@7000000 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x070F8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names = "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <24000000>; + resets = <&gcc GCC_USB1_BCR>; + status = "disabled"; + + dwc_1: dwc3@7000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x7000000 0x0 0xcd00>; + interrupts = ; + phys = <&qusb_phy_1>; + phy-names = "usb2-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + }; wcss: wcss-smp2p { -- cgit v1.2.3 From af5f967c72d1e655d1f7f135b977bac883ab5757 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Fri, 29 Jan 2021 22:42:00 +0530 Subject: arm64: dts: qcom: ipq6018: Update WCSS PIL driver compatible Updated WCSS PIL driver node with IPQ6018 specific compatible to enable SoC specific driver data. Signed-off-by: Gokul Sriram Palanisamy Link: https://lore.kernel.org/r/1611940320-24830-4-git-send-email-gokulsri@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index d4a3d4e4a7e9..b61ed0194523 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -477,7 +477,7 @@ }; q6v5_wcss: remoteproc@cd00000 { - compatible = "qcom,ipq8074-wcss-pil"; + compatible = "qcom,ipq6018-wcss-pil"; reg = <0x0 0x0cd00000 0x0 0x4040>, <0x0 0x004ab000 0x0 0x20>; reg-names = "qdsp6", -- cgit v1.2.3 From 6df9102f19bc3b51596f6d47f9b03fd36c5eb8e0 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Sat, 30 Jan 2021 10:50:12 +0530 Subject: arm64: dts: qcom: ipq8074: Add scm on IPQ8074 SoCs Enables scm support, clock is not needed for enabling scm interface. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Link: https://lore.kernel.org/r/1611984013-10201-9-git-send-email-gokulsri@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 95d6cb8cd4c0..c1c5d8011a27 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -76,6 +76,12 @@ method = "smc"; }; + firmware { + scm { + compatible = "qcom,scm-ipq8074", "qcom,scm"; + }; + }; + soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; -- cgit v1.2.3 From 2b6187abafeac92c36da11841d899e446eaaba67 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 14 Jul 2021 14:26:10 -0400 Subject: arm64: dts: qcom: sm8150: Add CPU opp tables Add OPP tables to scale DDR and L3 with CPUs for SM8150 SoCs. This gives a significant performance boost for cpu-ddr loads. Below is the results for mbw benchmark with and without the opp tables. /mbw 1500 Without l3/ddr scaling With l3 ddr/scaling MEMCPY(MiB/s) 3574 10448 DUMB(MiB/s) 3500 11721 MCBLOCK(MiB/s) 8976 23595 Signed-off-by: Thara Gopinath Link: https://lore.kernel.org/r/20210714182610.92972-1-thara.gopinath@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 315 +++++++++++++++++++++++++++++++++++ 1 file changed, 315 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 612dda0fef43..965670489830 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include / { @@ -52,6 +53,9 @@ dynamic-power-coefficient = <232>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -73,6 +77,9 @@ dynamic-power-coefficient = <232>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -92,6 +99,9 @@ dynamic-power-coefficient = <232>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -110,6 +120,9 @@ dynamic-power-coefficient = <232>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -128,6 +141,9 @@ dynamic-power-coefficient = <369>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -146,6 +162,9 @@ dynamic-power-coefficient = <369>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -164,6 +183,9 @@ dynamic-power-coefficient = <369>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -182,6 +204,9 @@ dynamic-power-coefficient = <421>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -264,6 +289,296 @@ }; }; + cpu0_opp_table: cpu0_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp2: opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp3: opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <800000 12902400>; + }; + + cpu0_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <800000 12902400>; + }; + + cpu0_opp5: opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + opp-peak-kBps = <800000 15974400>; + }; + + cpu0_opp6: opp-768000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <1804000 19660800>; + }; + + cpu0_opp7: opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <1804000 19660800>; + }; + + cpu0_opp8: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <1804000 22732800>; + }; + + cpu0_opp9: opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <1804000 22732800>; + }; + + cpu0_opp10: opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <2188000 25804800>; + }; + + cpu0_opp11: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <2188000 31948800>; + }; + + cpu0_opp12: opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + opp-peak-kBps = <3072000 31948800>; + }; + + cpu0_opp13: opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + cpu0_opp14: opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + cpu0_opp15: opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <3072000 40550400>; + }; + + cpu0_opp16: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <3072000 40550400>; + }; + + cpu0_opp17: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <3072000 43008000>; + }; + + cpu0_opp18: opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <3072000 43008000>; + }; + }; + + cpu4_opp_table: cpu4_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp1: opp-710400000 { + opp-hz = /bits/ 64 <710400000>; + opp-peak-kBps = <1804000 15974400>; + }; + + cpu4_opp2: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <2188000 19660800>; + }; + + cpu4_opp3: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 22732800>; + }; + + cpu4_opp4: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <3072000 25804800>; + }; + + cpu4_opp5: opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <3072000 31948800>; + }; + + cpu4_opp6: opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <4068000 31948800>; + }; + + cpu4_opp7: opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <4068000 31948800>; + }; + + cpu4_opp8: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 40550400>; + }; + + cpu4_opp9: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <4068000 40550400>; + }; + + cpu4_opp10: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <4068000 43008000>; + }; + + cpu4_opp11: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + cpu4_opp12: opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <6220000 49152000>; + }; + + cpu4_opp13: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <7216000 49152000>; + }; + + cpu4_opp14: opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <8368000 49152000>; + }; + + cpu4_opp15: opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu4_opp16: opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu4_opp17: opp-2419200000 { + opp-hz = /bits/ 64 <2419200000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + + cpu7_opp_table: cpu7_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu7_opp1: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <2188000 19660800>; + }; + + cpu7_opp2: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 22732800>; + }; + + cpu7_opp3: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <3072000 25804800>; + }; + + cpu7_opp4: opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <3072000 31948800>; + }; + + cpu7_opp5: opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <4068000 31948800>; + }; + + cpu7_opp6: opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <4068000 31948800>; + }; + + cpu7_opp7: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 40550400>; + }; + + cpu7_opp8: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <4068000 40550400>; + }; + + cpu7_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <4068000 43008000>; + }; + + cpu7_opp10: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + cpu7_opp11: opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <6220000 49152000>; + }; + + cpu7_opp12: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <7216000 49152000>; + }; + + cpu7_opp13: opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <8368000 49152000>; + }; + + cpu7_opp14: opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp15: opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp16: opp-2419200000 { + opp-hz = /bits/ 64 <2419200000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp17: opp-2534400000 { + opp-hz = /bits/ 64 <2534400000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp18: opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp19: opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + cpu7_opp20: opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm8150", "qcom,scm"; -- cgit v1.2.3 From a9ff4e16585c9f6f9d06eefc525334b0c6a66b39 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 12 Jul 2021 15:37:32 +0200 Subject: arm64: dts: qcom: Add device tree for Xiaomi Redmi 2 (wingtech-wt88047) The Xiaomi Redmi 2 is a MSM8916 smartphone that was made by Wingtech (codename: wt88047). It's fairly similar to the other MSM8916 devices. The device tree contains initial support for the Xiaomi Redmi 2 with: - UART (untested, probably available via some test points) - eMMC/SD card - Buttons - Vibrator - WiFi/Bluetooth (WCNSS) - USB Note that the Xiaomi Redmi 2 is available in variants with different names (e.g. Redmi 2 Prime, Redmi 2 Pro, ...). As far as I know the main difference between those is the amount of RAM and supported LTE bands. This difference is automatically handled by bootloader/modem firmware so there is no need for separate device trees. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210712133735.318250-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-wingtech-wt88047.dts | 208 +++++++++++++++++++++ 2 files changed, 209 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4f0597091976..a571bfdddd61 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts new file mode 100644 index 000000000000..5ee35a9b7dc6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2020 Stephan Gerhold + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include + +/ { + model = "Xiaomi Redmi 2 (Wingtech WT88047)"; + compatible = "wingtech,wt88047", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + non-removable; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_keys_default: gpio-keys-default { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default { + pins = "gpio110"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; -- cgit v1.2.3 From 678b0fcc77c3f3662ac102ab8c69a23bfbcc1c84 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 12 Jul 2021 15:37:33 +0200 Subject: arm64: dts: qcom: msm8916-wingtech-wt88047: Add touchscreen The Xiaomi Redmi 2 has a FocalTech touchscreen. The exact model is not mentioned anywhere, but it works just fine with the mainline edt-ft5x06 driver when using the "edt,edt-ft5506" compatible. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210712133735.318250-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-wingtech-wt88047.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 5ee35a9b7dc6..a4d8d6ff2289 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -42,6 +42,30 @@ }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@38 { + /* Likely some other model but works just fine with this one */ + compatible = "edt,edt-ft5506"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8916_l17>; + iovcc-supply = <&pm8916_l6>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_default>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -198,6 +222,22 @@ bias-pull-up; }; + touchscreen_default: touchscreen-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + + reset { + pins = "gpio12"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + }; + usb_id_default: usb-id-default { pins = "gpio110"; function = "gpio"; -- cgit v1.2.3 From f9af9f61b095733e399f871beb5df5dffc37dddf Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 12 Jul 2021 15:37:34 +0200 Subject: arm64: dts: qcom: msm8916-wingtech-wt88047: Add notification LED The Xiaomi Redmi 2 has a notification LED connected to an Awinic AW2013 controller, add it to the device tree. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210712133735.318250-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-wingtech-wt88047.dts | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index a4d8d6ff2289..9d9e85e75411 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -6,6 +6,7 @@ #include "msm8916-pm8916.dtsi" #include #include +#include / { model = "Xiaomi Redmi 2 (Wingtech WT88047)"; @@ -66,6 +67,40 @@ }; }; +&blsp_i2c6 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + #address-cells = <1>; + #size-cells = <0>; + + vcc-supply = <&pm8916_l16>; + + led@0 { + reg = <0>; + led-max-microamp = <15000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@1 { + reg = <1>; + led-max-microamp = <15000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@2 { + reg = <2>; + led-max-microamp = <15000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + }; +}; + &blsp1_uart2 { status = "okay"; }; -- cgit v1.2.3 From b7d9750272d1cf000d052498c67c695615d1af39 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 12 Jul 2021 15:37:35 +0200 Subject: arm64: dts: qcom: msm8916-wingtech-wt88047: Add IMU The Xiaomi Redmi 2 has an InvenSense MPU-6880 supported by the inv_mpu6050 driver in Linux. Add it to the device tree. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210712133735.318250-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-wingtech-wt88047.dts | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 9d9e85e75411..4e20cc0008f7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -43,6 +43,28 @@ }; }; +&blsp_i2c2 { + status = "okay"; + + imu@68 { + compatible = "invensense,mpu6880"; + reg = <0x68>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_default>; + + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -257,6 +279,14 @@ bias-pull-up; }; + imu_default: imu-default { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen-default { pins = "gpio13"; function = "gpio"; -- cgit v1.2.3 From a8c7f3100e708d5f55692f0607ca80c5dcd21ce8 Mon Sep 17 00:00:00 2001 From: Judy Hsiao Date: Thu, 8 Jul 2021 17:08:10 +0800 Subject: arm64: dts: qcom: sc7180: Set adau wakeup delay to 80 ms Set audu wakeup delay to 80 ms for fixing pop noise during capture begin. Fixes: ba5f9b5d7ff3 ("arm64: dts: qcom: sc7180: Add wakeup delay for adau codec") Signed-off-by: Judy Hsiao Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20210708090810.174767-1-judyhsiao@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 6f9c07147551..a758e4d22612 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -23,7 +23,7 @@ ap_h1_spi: &spi0 {}; adau7002: audio-codec-1 { compatible = "adi,adau7002"; IOVDD-supply = <&pp1800_l15a>; - wakeup-delay-ms = <15>; + wakeup-delay-ms = <80>; #sound-dai-cells = <0>; }; -- cgit v1.2.3 From 63fa4322469648ae1023bb92a8b0d6a2f4bdaf2c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 7 Jul 2021 00:07:01 +0100 Subject: arm64: dts: qcom: sm8250: fix usb2 qmp phy node Use 'lanes' as SuperSpeed lanes device node instead of just 'lane' to fix issues with TypeC support. Fixes: 46a6f297d7dd ("arm64: dts: qcom: sm8250: Add USB and PHY device nodes") Cc: robh+dt@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Dmitry Baryshkov Tested-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20210706230702.299047-2-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4798368b02ef..9a6eff1813a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2210,7 +2210,7 @@ <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "phy", "common"; - usb_2_ssphy: lane@88eb200 { + usb_2_ssphy: lanes@88eb200 { reg = <0 0x088eb200 0 0x200>, <0 0x088eb400 0 0x200>, <0 0x088eb800 0 0x800>; -- cgit v1.2.3 From 98aee1e3cdcd74debc093cfc9297287063e88a0f Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 6 Jul 2021 19:08:14 +0530 Subject: arm64: dts: qcom: sm8150: Add UFS ICE capability Add support for UFS ICE (Qualcomm Inline Crypto Engine) in sm8150 SoC dts. I tested this on SA8155p-adp board, which is a publicly available development board that uses the sa8155p Qualcomm Snapdragon SoC. SA8155p platform is similar to the SM8150, so use this as base for now. I tested the UFS ICE feature using 'fscrypt' test utility. Cc: Bjorn Andersson Cc: Eric Biggers Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210706133814.621536-1-bhupesh.sharma@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 965670489830..1c84d78d0a19 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1331,7 +1331,9 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>; + reg = <0 0x01d84000 0 0x2500>, + <0 0x01d90000 0 0x8000>; + reg-names = "std", "ice"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -1350,7 +1352,8 @@ "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; + "rx_lane1_sync_clk", + "ice_core_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -1359,7 +1362,8 @@ <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; freq-table-hz = <37500000 300000000>, <0 0>, @@ -1368,7 +1372,8 @@ <0 0>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <0 300000000>; status = "disabled"; }; -- cgit v1.2.3 From 2aa2b50de12d96eaf282b886330afe98c389e1e2 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 27 Jun 2021 17:16:14 +0530 Subject: arm64: dts: qcom: Use correct naming for dwc3 usb nodes in dts files The dwc3 usb nodes in several arm64 qcom dts are currently named differently, somewhere as 'usb@' and somewhere as 'dwc3@', leading to some confusion when one sees the entries in sysfs or dmesg: [ 1.943482] dwc3 a600000.usb: Adding to iommu group 1 [ 2.266127] dwc3 a800000.dwc3: Adding to iommu group 2 Name the usb nodes as 'usb@' for consistency, which is the correct convention as per the 'snps,dwc3' dt-binding as well (see [1]). [1]. Documentation/devicetree/bindings/usb/snps,dwc3.yaml Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210627114616.717101-2-bhupesh.sharma@linaro.org [bjorn: Extended to also fix ipq6018] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index b61ed0194523..01ca4b8b9d2b 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -557,7 +557,7 @@ resets = <&gcc GCC_USB1_BCR>; status = "disabled"; - dwc_1: dwc3@7000000 { + dwc_1: usb@7000000 { compatible = "snps,dwc3"; reg = <0x0 0x7000000 0x0 0xcd00>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index f9f0b5aa6a26..662f2f246b9b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -430,7 +430,7 @@ power-domains = <&gcc USB30_GDSC>; qcom,select-utmi-as-pipe-clk; - dwc3@f9200000 { + usb@f9200000 { compatible = "snps,dwc3"; reg = <0xf9200000 0xcc00>; interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 1c84d78d0a19..62b88183174f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2709,7 +2709,7 @@ resets = <&gcc GCC_USB30_SEC_BCR>; - usb_2_dwc3: dwc3@a800000 { + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 9a6eff1813a6..d4432e357fcf 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2321,7 +2321,7 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; - usb_1_dwc3: dwc3@a600000 { + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; @@ -2372,7 +2372,7 @@ resets = <&gcc GCC_USB30_SEC_BCR>; - usb_2_dwc3: dwc3@a800000 { + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 0d16392bb976..a631d58166b1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1273,7 +1273,7 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; - usb_1_dwc3: dwc3@a600000 { + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; @@ -1317,7 +1317,7 @@ resets = <&gcc GCC_USB30_SEC_BCR>; - usb_2_dwc3: dwc3@a800000 { + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = ; -- cgit v1.2.3 From 5dc43d3b362cdd904a5253498b271d20a26d135d Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 27 Jun 2021 17:16:15 +0530 Subject: arm64: dts: qcom: sm8150: Sort dc_noc and gem_noc nodes Nodes should be sorted by address, so move the dc_noc and gem_noc nodes to their correct place. Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210627114616.717101-3-bhupesh.sharma@linaro.org [bjorn: Adjusted order slightly more] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 62b88183174f..6f4cc9dbc80b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2586,20 +2586,6 @@ }; }; - dc_noc: interconnect@9160000 { - compatible = "qcom,sm8150-dc-noc"; - reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sm8150-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - usb_2_qmpphy: phy@88eb000 { compatible = "qcom,sm8150-qmp-usb3-uni-phy"; reg = <0 0x088eb000 0 0x200>; @@ -2631,6 +2617,20 @@ }; }; + dc_noc: interconnect@9160000 { + compatible = "qcom,sm8150-dc-noc"; + reg = <0 0x09160000 0 0x3200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + compatible = "qcom,sm8150-gem-noc"; + reg = <0 0x09680000 0 0x3e200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; -- cgit v1.2.3 From 12dd4ebda47abd5e3907da386b6fe1d8181ad179 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 27 Jun 2021 17:16:16 +0530 Subject: arm64: dts: qcom: Fix usb entries for SA8155p adp board SA8155p adp board has two USB A-type receptacles called USB-portB and USB-portC respectively. While USB-portB is a USB High-Speed connector/interface, the USB-portC one is a USB 3.1 Super-Speed connector/interface. Also the USB-portB is used as the USB emergency download port (for image download purposes). Enable both the ports on the board in USB Host mode (since all the USB interfaces are brought out to USB Type A connectors). Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210627114616.717101-4-bhupesh.sharma@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 60 +++++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 0da7a3b8d1bf..5ae2ddc65f7e 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -307,10 +307,6 @@ status = "okay"; }; -&tlmm { - gpio-reserved-ranges = <0 4>; -}; - &uart2 { status = "okay"; }; @@ -337,6 +333,16 @@ vdda-pll-max-microamp = <18300>; }; +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en1_default>; +}; &usb_1_hsphy { status = "okay"; @@ -346,15 +352,51 @@ }; &usb_1_qmpphy { + status = "disabled"; +}; + +&usb_2 { status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; }; -&usb_1 { +&usb_2_dwc3 { + dr_mode = "host"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en2_default>; +}; + +&usb_2_hsphy { status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; }; -&usb_1_dwc3 { - dr_mode = "peripheral"; +&usb_2_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l8c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; + + usb2phy_ac_en1_default: usb2phy_ac_en1_default { + mux { + pins = "gpio113"; + function = "usb2phy_ac"; + bias-disable; + drive-strength = <2>; + }; + }; + + usb2phy_ac_en2_default: usb2phy_ac_en2_default { + mux { + pins = "gpio123"; + function = "usb2phy_ac"; + bias-disable; + drive-strength = <2>; + }; + }; }; -- cgit v1.2.3 From 298c81a7d44fe01b41d526ddabafcf8515c5f649 Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Tue, 13 Jul 2021 12:36:11 +0530 Subject: arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card Add nodes for eMMC and SD card on sc7280. Signed-off-by: Shaik Sajida Bhanu Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1626159971-22519-1-git-send-email-sbhanu@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 71 ++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 186 ++++++++++++++++++++++++++++++++ 2 files changed, 257 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 3900cfc09562..1be822cef594 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include #include @@ -272,6 +273,34 @@ status = "okay"; }; +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + &uart5 { status = "okay"; }; @@ -291,3 +320,45 @@ bias-pull-up; }; }; + +&sdc1_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + bias-pull-down; + }; +}; + +&sdc2_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a8c274ad74c4..da55adba1f8c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -24,6 +25,11 @@ chosen { }; + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -436,6 +442,60 @@ #mbox-cells = <2>; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + status = "disabled"; + + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>; + reg-names = "hc", "cqhci"; + + iommus = <&apps_smmu 0xc0 0x0>; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + bus-width = <8>; + supports-cqe; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <390000 0>; + }; + }; + + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>; @@ -1035,6 +1095,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + status = "disabled"; + + reg = <0 0x08804000 0 0x1000>; + + iommus = <&apps_smmu 0x100 0x0>; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; + interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + bus-width = <4>; + + qcom,dll-config = <0x0007642c>; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <200000 0>; + }; + }; + + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; @@ -1185,6 +1290,87 @@ pins = "gpio46", "gpio47"; function = "qup13"; }; + + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + }; + + cmd { + pins = "sdc1_cmd"; + }; + + data { + pins = "sdc1_data"; + }; + + rclk { + pins = "sdc1_rclk"; + }; + }; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + rclk { + pins = "sdc1_rclk"; + bias-bus-hold; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + }; + + cmd { + pins = "sdc2_cmd"; + }; + + data { + pins = "sdc2_data"; + }; + + sd-cd { + pins = "gpio91"; + }; + }; + + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd { + pins ="sdc2_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data { + pins ="sdc2_data"; + drive-strength = <2>; + bias-bus-hold; + }; + }; }; apps_smmu: iommu@15000000 { -- cgit v1.2.3 From 1c39e6f9b534f9f609be97890a7a9974cd17e4ab Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Tue, 6 Jul 2021 18:30:12 +0530 Subject: arm64: dts: qcom: sc7280: Add USB related nodes Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1625576413-12324-3-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 164 +++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index da55adba1f8c..1d405c2f234f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1140,6 +1140,125 @@ }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sc7280-qmp-usb3-dp-phy", + "qcom,sm8250-qmp-usb3-dp-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x40>, + <0 0x088ea000 0 0x200>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: usb3-phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + + dp_phy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eac00 0 0x400>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>, + <0 0x088eaa00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_2: usb@8cf8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x08cf8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface","mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>, + <&pdc 12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: usb@8c00000 { + compatible = "snps,dwc3"; + reg = <0 0x08c00000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0xa0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + }; + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; @@ -1168,6 +1287,51 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_1: usb@a6f8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0xe0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + }; + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; reg = <0 0xaaf0000 0 0x10000>; -- cgit v1.2.3 From 820bf3fefa8261b51062d18d5442cb92e913390f Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Tue, 6 Jul 2021 18:30:13 +0530 Subject: arm64: dts: qcom: sc7280: Add USB nodes for IDP board Add USB nodes for sc7280 IDP board. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1625576413-12324-4-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 1be822cef594..73225e3c2f86 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -305,6 +305,45 @@ status = "okay"; }; +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p8>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &qup_uart5_default { -- cgit v1.2.3 From 4f365c75a342c82b431e361631c5004779ebcd2a Mon Sep 17 00:00:00 2001 From: Judy Hsiao Date: Fri, 25 Jun 2021 12:50:10 +0800 Subject: arm64: dts: qcom: sc7180: trogdor: Update audio codec to Max98360A Use max98360a dts node to correctly describe the hardware. Signed-off-by: Judy Hsiao Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20210625045010.2914289-1-judyhsiao@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 43126c56e320..32d129011638 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -247,8 +247,8 @@ }; }; - max98357a: audio-codec-0 { - compatible = "maxim,max98357a"; + max98360a: audio-codec-0 { + compatible = "maxim,max98360a"; pinctrl-names = "default"; pinctrl-0 = <&_en>; sdmode-gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>; @@ -311,7 +311,7 @@ }; sound_multimedia1_codec: codec { - sound-dai = <&max98357a>; + sound-dai = <&max98360a>; }; }; }; -- cgit v1.2.3 From db718417e87f1eb4562d8bc8b02fb108e80d63a1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 8 Jun 2021 22:21:39 +0200 Subject: arm64: dts: qcom: Add PMI8996 DTSI file PMI8996 is *almost* the same hardware as PMI8994, say for some annoyances: - Boards equipped with PMI8996 now have to include pmic-id (which wasn't the case before) - Different qpnp-ibb-discharge-resistor value (will be addressed after LABIBB is introduced) - Different inhibit-derating-ua value (will be addressed after BCL is introduced) - Different ramp_up_step value (will be addressed after [if?] QPNP Flash LED is introduced) This DTSI is supposed to be included >>ON TOP OF<< pmi8994.dtsi, like this: -- msm8996-nice-device.dts -- \#include "pmi8994.dtsi" \#include "pmi8996.dtsi" or more likely like this: -- msm8996-some-phone.dts -- \#include "msm8996.dtsi" ... \#include "pmi8994.dtsi" -- msm8996-pmi8996-some-phone.dts -- \#include "msm8996-some-phone.dts" \#include "pmi8996.dtsi" So that we only have to keep 2 DTs for devices that were shipped with both ones, instead of what would be three (device base + pmi8994 + pmi8996) Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210608202143.247427-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8996.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmi8996.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/pmi8996.dtsi b/arch/arm64/boot/dts/qcom/pmi8996.dtsi new file mode 100644 index 000000000000..31b47209e261 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmi8996.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, Konrad Dybcio + */ + + /* + * PMI8996 is a slight modification of PMI8994 with + * some notable changes, like being the first PMIC + * whose the bootloader has to check to continue booting + * and a change to a LABIBB parameter. + */ + +/ { + qcom,pmic-id = <0x20009 0x10013 0 0>; +}; -- cgit v1.2.3 From a569b10bf74ff9d62d3deb98890ff4a4b75eb81a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 8 Jun 2021 22:21:40 +0200 Subject: arm64: dts: qcom: Add MSM8996v3.0 DTSI file Add an overlay for MSM8996v3.0, which is a pre-final revision of the said SoC. It has some stark differences with regards to GPU, or more specifically its power delivery path. Oh, and of course a different msm-id. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210608202143.247427-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi | 63 ++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi b/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi new file mode 100644 index 000000000000..5728583af41e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "msm8996.dtsi" + +/ { + qcom,msm-id = <246 0x30000>; +}; + + /* + * This revision seems to have differ GPU CPR + * parameters, GPU frequencies and some differences + * when it comes to voltage delivery to.. once again + * the GPU. Funnily enough, it's simpler to make it an + * overlay on top of 3.1 (the final one) than vice versa. + * The differences will show here as more and more + * features get enabled upstream. + */ + +gpu_opp_table_3_0: gpu-opp-table-30 { + compatible = "operating-points-v2"; + + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-level = <7>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-level = <6>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-level = <5>; + }; + + opp-401800000 { + opp-hz = /bits/ 64 <401800000>; + opp-level = <4>; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = <3>; + }; + + opp-214000000 { + opp-hz = /bits/ 64 <214000000>; + opp-level = <3>; + }; + + opp-133000000 { + opp-hz = /bits/ 64 <133000000>; + opp-level = <3>; + }; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table_3_0>; +}; -- cgit v1.2.3 From 08972f34a264a80c5113706fccc1984f87dd2dbf Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 8 Jun 2021 22:21:41 +0200 Subject: arm64: dts: qcom: msm8996-*: Disable HDMI by default Most phones ship without HDMI and leaving it enabled wrecks havoc. Disable it in msm8996.dtsi and re-enable it on the boards that did not disable it previously. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210608202143.247427-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 3 files changed, 20 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 8c7a27e972b7..a57c60070cdc 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -92,6 +92,14 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_phy { + status = "okay"; +}; + &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi index 1e1514e9158c..ac43a91f1104 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi @@ -20,3 +20,11 @@ }; }; }; + +&hdmi { + status = "okay"; +}; + +&hdmi_phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0e1bc4669d7e..ccb98d63c647 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -898,6 +898,8 @@ phy-names = "hdmi_phy"; #sound-dai-cells = <1>; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -931,6 +933,8 @@ <&gcc GCC_HDMI_CLKREF_CLK>; clock-names = "iface", "ref"; + + status = "disabled"; }; }; -- cgit v1.2.3 From 9da65e441d4d7a492ce139e4938ac75fa70f449d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 8 Jun 2021 22:21:42 +0200 Subject: arm64: dts: qcom: Add support for SONY Xperia X Performance / XZ / XZs (msm8996, Tone platform) Add support for following boards: - Xperia X Performance (dora) - Xperia XZ (kagura) - Xperia XZs (keyaki) They are all based on the SONY Tone platform and feature largely similar hardware with the most obvious differences being lack of USB-C and ToF sensor on Dora and different camera sensor on Keyaki. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210608202143.247427-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 6 + .../qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts | 11 + .../msm8996-pmi8996-sony-xperia-tone-kagura.dts | 11 + .../msm8996-pmi8996-sony-xperia-tone-keyaki.dts | 11 + .../dts/qcom/msm8996-sony-xperia-tone-dora.dts | 27 + .../dts/qcom/msm8996-sony-xperia-tone-kagura.dts | 15 + .../dts/qcom/msm8996-sony-xperia-tone-keyaki.dts | 26 + .../boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 956 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 +- 9 files changed, 1069 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index a571bfdddd61..d4a6205ff976 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -27,6 +27,12 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-dora.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-kagura.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts new file mode 100644 index 000000000000..b018693600a5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "msm8996-sony-xperia-tone-dora.dts" +#include "pmi8996.dtsi" + +/ { + model = "Sony Xperia X Performance (PMI8996)"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts new file mode 100644 index 000000000000..842ea3cf557e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "msm8996-sony-xperia-tone-kagura.dts" +#include "pmi8996.dtsi" + +/ { + model = "Sony Xperia XZ (PMI8996)"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts new file mode 100644 index 000000000000..b3f9062da4b0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "msm8996-sony-xperia-tone-keyaki.dts" +#include "pmi8996.dtsi" + +/ { + model = "Sony Xperia XZs (PMI8996)"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts new file mode 100644 index 000000000000..b4cca54dcb68 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8996-sony-xperia-tone.dtsi" + +/ { + model = "Sony Xperia X Performance"; + compatible = "sony,dora-row", "qcom,msm8996"; +}; + +/delete-node/ &tof_sensor; +/delete-node/ &pm8994_l11; +/delete-node/ &pm8994_l14; + +&usb_detect { + pins = "gpio24"; +}; + +&usb3_id { + id-gpio = <&tlmm 24 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dts b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dts new file mode 100644 index 000000000000..be6ea855fcce --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8996-sony-xperia-tone.dtsi" + +/ { + model = "Sony Xperia XZ"; + compatible = "sony,kagura-row", "qcom,msm8996"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dts b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dts new file mode 100644 index 000000000000..1eee7d0fc178 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8996-sony-xperia-tone.dtsi" + +/ { + model = "Sony Xperia XZs"; + compatible = "sony,keyaki-row", "qcom,msm8996"; +}; + +&pm8994_l19 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; + +&pm8994_l30 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-pull-down; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi new file mode 100644 index 000000000000..507396c4d23b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -0,0 +1,956 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "msm8996.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include +#include +#include +#include + +/delete-node/ &slpi_region; +/delete-node/ &venus_region; +/delete-node/ &zap_shader_region; + +/ { + qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */ + qcom,pmic-id = <0x20009 0x2000a 0 0>; /* PM8994 + PMI8994 */ + qcom,board-id = <8 0>; + + chosen { + /* + * Due to an unknown-for-a-few-years regression, + * SDHCI only works on MSM8996 in PIO (lame) mode. + */ + bootargs = "sdhci.debug_quirks=0x40 sdhci.debug_quirks2=0x4 maxcpus=2"; + }; + + reserved-memory { + ramoops@a7f00000 { + compatible = "ramoops"; + reg = <0 0xa7f00000 0 0x100000>; + record-size = <0x20000>; + console-size = <0x40000>; + ftrace-size = <0x20000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + }; + + cont_splash_mem: memory@83401000 { + reg = <0 0x83401000 0 0x23ff000>; + no-map; + }; + + zap_shader_region: gpu@90400000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90400000 0x0 0x2000>; + no-map; + }; + + slpi_region: memory@90500000 { + reg = <0 0x90500000 0 0xa00000>; + no-map; + }; + + venus_region: memory@90f00000 { + reg = <0 0x90f00000 0 0x500000>; + no-map; + }; + }; + + panel_tvdd: tvdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "panel_tvdd"; + gpio = <&tlmm 50 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&tp_vddio_en>; + pinctrl-names = "default"; + }; + + usb3_id: usb3-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_detect>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; + + wlan_en: wlan-en-1-8v { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wl_reg_on>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + clock-frequency = <355000>; + + tof_sensor: vl53l0x@29 { + compatible = "st,vl53l0x"; + reg = <0x29>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + /* FUSB301 USB-C controller */ +}; + +&blsp2_i2c6 { + status = "okay"; + clock-frequency = <355000>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + interrupt-parent = <&tlmm>; + interrupts = <125 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&panel_tvdd>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <220>; + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp2_uart2 { + status = "okay"; +}; + +&camera0_mclk { + drive-strength = <2>; + output-low; +}; + +&camera0_pwdn { + drive-strength = <2>; + output-low; +}; + +&camera0_rst { + pins = "gpio30"; + drive-strength = <2>; + output-low; +}; + +&camera2_mclk { + drive-strength = <2>; + output-low; +}; + +&camera2_rst { + drive-strength = <2>; + output-low; +}; + +&hsusb_phy1 { + status = "okay"; + + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; +}; + +&mmcc { + vdd-gfx-supply = <&vdd_gfx>; +}; + +&pcie0 { + status = "okay"; + perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; + vddpe-3v3-supply = <&wlan_en>; + vdda-supply = <&pm8994_l28>; +}; + +&pcie_phy { + status = "okay"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; +}; + +&pm8994_gpios { + pinctrl-names = "default"; + pinctrl-0 = <&pm8994_gpios_defaults>; + gpio-line-names = + "NC", + "VOL_DOWN_N", + "VOL_UP_N", + "SNAPSHOT_N", + "FOCUS_N", + "NC", + "NFC_VEN", + "NC", + "NC", + "NC", + "NC", + "NC", + "EAR_EN", + "NC", + "PM_DIVCLK1", + "PMI_CLK", + "NC", + "WL_SLEEP_CLK", + "NC", + "PMIC_SPON", + "UIM_BATT_ALARM", + "PMK_SLEEP_CLK"; + + /* + * We don't yet know for sure which GPIOs are of our interest, but what + * we do know is that if a vendor sets the pins to a non-default state, there's + * probably a reason for it, and just to be on the safe side, we follow suit. + */ + pm8994_gpios_defaults: pm8994-gpios-default-state { + pm8994-gpio1-nc { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + bias-high-impedance; + }; + + vol-down-n { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; + }; + + vol-up-n { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + input-enable; + bias-pull-up; + power-source = ; + }; + + camera-snapshot-n { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; + }; + + camera-focus-n { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; + }; + + pm8994-gpio6-nc { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + bias-high-impedance; + power-source = ; + }; + + nfc-download { + pins = "gpio7"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + power-source = ; + }; + + pm8994-gpio8-nc { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + drive-push-pull; + bias-high-impedance; + qcom,drive-strength = ; + power-source = ; + }; + + pm8994-gpio9-nc { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_NORMAL; + output-high; + drive-push-pull; + bias-high-impedance; + qcom,drive-strength = ; + power-source = ; + }; + + nfc-clock { + pins = "gpio10"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + drive-push-pull; + bias-pull-down; + qcom,drive-strength = ; + power-source = ; + }; + + pm8994-gpio11-nc { + pins = "gpio11"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + bias-high-impedance; + power-source = ; + }; + + pm8994-gpio12-nc { + pins = "gpio12"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + bias-high-impedance; + power-source = ; + }; + + ear-enable { + pins = "gpio13"; + function = PMIC_GPIO_FUNC_NORMAL; + output-high; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + power-source = ; + }; + + pm8994-gpio14-nc { + pins = "gpio14"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + input-enable; + bias-high-impedance; + qcom,drive-strength = ; + power-source = ; + }; + + pm-divclk1-gpio { + pins = "gpio15"; + function = "func1"; + output-high; + drive-push-pull; + bias-high-impedance; + qcom,drive-strength = ; + power-source = ; + }; + + pmi-clk-gpio { + pins = "gpio16"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + }; + + pm8994-gpio17-nc { + pins = "gpio17"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + bias-high-impedance; + power-source = ; + }; + + rome-sleep { + pins = "gpio18"; + function = PMIC_GPIO_FUNC_FUNC2; + output-low; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + power-source = ; + }; + + pm8994-gpio19-nc { + pins = "gpio19"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + drive-push-pull; + bias-high-impedance; + qcom,drive-strength = ; + power-source = ; + }; + + pm8994-gpio22-nc { + pins = "gpio22"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + bias-high-impedance; + power-source = ; + }; + }; +}; + +&pm8994_mpps { + pinctrl-names = "default"; + pinctrl-0 = <&pm8994_mpps_defaults>; + + gpio-line-names = + "SDC_UIM_VBIAS", + "LCD_ID_ADC", + "VREF_DACX", + "NC", + "FLASH_THERM", + "NC", + "NC", + "RF_ID"; + + pm8994_mpps_defaults: pm8994-mpps-default-state { + lcd-id_adc-mpp { + pins = "mpp2"; + function = "analog"; + input-enable; + qcom,amux-route = ; + }; + + pm-mpp4-nc { + pins = "mpp4"; + function = "digital"; + bias-high-impedance; + power-source = ; + }; + + flash-therm-mpp { + pins = "mpp5"; + function = "analog"; + input-enable; + qcom,amux-route = ; + }; + + mpp6-nc { + pins = "mpp6"; + function = "digital"; + bias-high-impedance; + }; + + rf-id-mpp { + pins = "mpp8"; + function = "analog"; + input-enable; + qcom,amux-route = ; + }; + }; +}; + +&pm8994_resin { + status = "okay"; + linux,code = ; +}; + +&pmi8994_gpios { + pinctrl-names = "default"; + pinctrl-0 = <&pmi8994_gpios_defaults>; + + gpio-line-names = + "VIB_LDO_EN", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "USB_SWITCH_SEL", + "NC"; + + pmi8994_gpios_defaults: pmi8994-gpios-default-state { + vib-ldo-en-gpio { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + output-low; + bias-disable; + power-source = ; + }; + + pmi-gpio2-nc { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + input-enable; + bias-high-impedance; + qcom,drive-strength = ; + power-source = ; + }; + + pmi-gpio3-nc { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + input-enable; + bias-high-impedance; + qcom,drive-strength = ; + power-source = ; + }; + + pmi-gpio4-nc { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + output-high; + qcom,drive-strength = ; + power-source = ; + }; + + pmi-gpio5-nc { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + output-high; + qcom,drive-strength = ; + power-source = ; + }; + + pmi-gpio6-nc { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + output-high; + qcom,drive-strength = ; + power-source = ; + }; + + pmi-gpio7-nc { + pins = "gpio7"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + output-high; + qcom,drive-strength = ; + power-source = ; + }; + + pmi-gpio8-nc { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + output-high; + qcom,drive-strength = ; + power-source = ; + }; + + usb-switch-sel { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_NORMAL; + drive-push-pull; + }; + + pmi-gpio10-nc { + pins = "gpio10"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + drive-push-pull; + bias-disable; + qcom,drive-strength = ; + power-source = ; + }; + }; +}; + +&pmi8994_spmi_regulators { + qcom,saw-reg = <&saw3>; + + vdd_gfx: + pmi8994_s2: s2 { + /* Pinned to a high value for now to avoid random crashes. */ + regulator-min-microvolt = <1015000>; + regulator-max-microvolt = <1015000>; + regulator-name = "vdd_gfx"; + regulator-always-on; + }; + + pmi8994_s9: s9 { + qcom,saw-slave; + }; + + pmi8994_s10: s10 { + qcom,saw-slave; + }; + + pmi8994_s11: s11 { + qcom,saw-leader; + regulator-always-on; + regulator-min-microvolt = <470000>; + regulator-max-microvolt = <1140000>; + }; +}; + +&pmi8994_wled { + status = "okay"; + default-brightness = <512>; +}; + +&rpm_requests { + pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8994_s3>; + vdd_l2_l26_l28-supply = <&pm8994_s3>; + vdd_l3_l11-supply = <&pm8994_s3>; + vdd_l4_l27_l31-supply = <&pm8994_s3>; + vdd_l5_l7-supply = <&pm8994_s5>; + vdd_l6_l12_l32-supply = <&pm8994_s5>; + vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l14_l15-supply = <&pm8994_s5>; + vdd_l20_l21-supply = <&pm8994_s5>; + vdd_l25-supply = <&pm8994_s3>; + vdd_lvs1_2-supply = <&pm8994_s4>; + + pm8994_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8994_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <325000>; + regulator-always-on; + }; + + pm8994_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pm8994_s7: s7 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + pm8994_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l2: l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + + pm8994_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + pm8994_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + /* L6 and L7 seem unused. */ + + pm8994_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l11: l11 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + pm8994_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + pm8994_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <22000>; + regulator-allow-set-load; + }; + + pm8994_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + pm8994_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l17: l17 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2500000>; + }; + + pm8994_l18: l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l19: l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8994_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + pm8994_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <800000>; + regulator-allow-set-load; + }; + + pm8994_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8994_l23: l23 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-allow-set-load; + }; + + pm8994_l25: l25 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + + pm8994_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l28: l28 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8994_l29: l29 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l30: l30 { }; + + pm8994_l32: l32 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; +}; + +&sdhc1 { + /* eMMC doesn't seem to cooperate even in PIO mode.. */ + status = "disabled"; + + vmmc-supply = <&pm8994_l20>; + vqmmc-supply = <&pm8994_s4>; + mmc-hs400-1_8v; + mmc-hs200-1_8v; +}; + +&sdhc2 { + status = "okay"; + + cd-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm8994_l21>; + vqmmc-supply = <&pm8994_l13>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; + pinctrl-0 = <&sw_service_gpio>; + pinctrl-names = "default"; + + disp_reset_n_gpio: disp-reset-n { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + mdp_vsync_p_gpio: mdp-vsync-p { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; + + sw_service_gpio: sw-service-gpio { + pins = "gpio16"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb_detect: usb-detect { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + uim_detect_en: uim-detect-en { + pins = "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + tray_det_pin: tray-det { + pins = "gpio40"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tp_vddio_en: tp-vddio-en { + pins = "gpio50"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + lcd_vddio_en: lcd-vddio-en { + pins = "gpio51"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + wl_host_wake: wl-host-wake { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-high; + }; + + wl_reg_on: wl-reg-on { + pins = "gpio84"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + ts_reset_n: ts-rst-n { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + }; + + touch_int_n: touch-int-n { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + touch_int_sleep: touch-int-sleep { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +/* + * For reasons that are currently unknown (but probably related to fusb301), USB takes about + * 6 minutes to wake up (nothing interesting in kernel logs), but then it works as it should. + */ +&usb3 { + status = "okay"; + qcom,select-utmi-as-pipe-clk; +}; + +&usb3_dwc3 { + extcon = <&usb3_id>; + dr_mode = "peripheral"; + phys = <&hsusb_phy1>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ccb98d63c647..3fa116e9bbeb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1086,21 +1086,21 @@ camera0_state_on: camera_rear_default: camera-rear-default { - mclk0 { + camera0_mclk: mclk0 { pins = "gpio13"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - rst { + camera0_rst: rst { pins = "gpio25"; function = "gpio"; drive-strength = <16>; bias-disable; }; - pwdn { + camera0_pwdn: pwdn { pins = "gpio26"; function = "gpio"; drive-strength = <16>; @@ -1141,14 +1141,14 @@ camera2_state_on: camera_front_default: camera-front-default { - mclk2 { + camera2_mclk: mclk2 { pins = "gpio15"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - rst { + camera2_rst: rst { pins = "gpio23"; function = "gpio"; drive-strength = <16>; @@ -2570,7 +2570,7 @@ power-domains = <&gcc USB30_GDSC>; status = "disabled"; - usb@6a00000 { + usb3_dwc3: usb@6a00000 { compatible = "snps,dwc3"; reg = <0x06a00000 0xcc00>; interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From b9650a9e9c576ebe6276581fe325e54fc57c717a Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 4 Aug 2021 09:32:23 -0400 Subject: arm64: dts: qcom: sm8150-mtp: Add 8150 compatible string Add "qcom,sm8150" as one of the platform compatible strings. This will be later used by cpufreq-dt-platdev to exclude using cpufreq-dt cpufreq driver. Signed-off-by: Thara Gopinath Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210804133223.2503517-1-thara.gopinath@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 53edf7541169..b484371a6044 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -15,7 +15,7 @@ / { model = "Qualcomm Technologies, Inc. SM8150 MTP"; - compatible = "qcom,sm8150-mtp"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150"; aliases { serial0 = &uart2; -- cgit v1.2.3 From ce3b50cf621c018a8bcbc7720e154926fc736c67 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 4 Aug 2021 09:28:47 -0400 Subject: arm64: dts: qcom: sm8150: Fix incorrect cpu opp table entry CPU0 frequency 768MHz is wrongly modeled as 576000000 hz in cpu0_opp_table. Use the correct value 768000000 hz. Fixes: 2b6187abafea ("arm64: dts: qcom: sm8150: Add CPU opp tables") Signed-off-by: Thara Gopinath Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210804132847.2503269-1-thara.gopinath@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 6f4cc9dbc80b..f8d3725c440e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -319,7 +319,7 @@ }; cpu0_opp6: opp-768000000 { - opp-hz = /bits/ 64 <576000000>; + opp-hz = /bits/ 64 <768000000>; opp-peak-kBps = <1804000 19660800>; }; -- cgit v1.2.3 From 26e02c98a9ad63eb21b9be4ac92002f555130d3b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:04 +0200 Subject: arm64: dts: qcom: sdm630: Rewrite memory map The memory map was wrong. Fix it. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 41 ++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 23 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index f91a928466c3..5ea3884b3ccb 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -343,10 +343,19 @@ }; qhee_code: qhee-code@85800000 { - reg = <0x0 0x85800000 0x0 0x3700000>; + reg = <0x0 0x85800000 0x0 0x600000>; no-map; }; + rmtfs_mem: memory@85e00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x85e00000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + smem_region: smem-mem@86000000 { reg = <0 0x86000000 0 0x200000>; no-map; @@ -357,58 +366,44 @@ no-map; }; - modem_fw_mem: modem-fw-region@8ac00000 { + mpss_region: mpss@8ac00000 { reg = <0x0 0x8ac00000 0x0 0x7e00000>; no-map; }; - adsp_fw_mem: adsp-fw-region@92a00000 { + adsp_region: adsp@92a00000 { reg = <0x0 0x92a00000 0x0 0x1e00000>; no-map; }; - pil_mba_mem: pil-mba-region@94800000 { + mba_region: mba@94800000 { reg = <0x0 0x94800000 0x0 0x200000>; no-map; }; - buffer_mem: buffer-region@94a00000 { + buffer_mem: tzbuffer@94a00000 { reg = <0x0 0x94a00000 0x0 0x100000>; no-map; }; - venus_fw_mem: venus-fw-region@9f800000 { + venus_region: venus@9f800000 { reg = <0x0 0x9f800000 0x0 0x800000>; no-map; }; - secure_region2: secure-region2@f7c00000 { - reg = <0x0 0xf7c00000 0x0 0x5c00000>; - no-map; - }; - adsp_mem: adsp-region@f6000000 { reg = <0x0 0xf6000000 0x0 0x800000>; no-map; }; - qseecom_ta_mem: qseecom-ta-region@fec00000 { - reg = <0x0 0xfec00000 0x0 0x1000000>; - no-map; - }; - qseecom_mem: qseecom-region@f6800000 { reg = <0x0 0xf6800000 0x0 0x1400000>; no-map; }; - secure_display_memory: secure-region@f5c00000 { - reg = <0x0 0xf5c00000 0x0 0x5c00000>; - no-map; - }; - - cont_splash_mem: cont-splash-region@9d400000 { - reg = <0x0 0x9d400000 0x0 0x23ff000>; + zap_shader_region: gpu@fed00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xfed00000 0x0 0xa00000>; no-map; }; }; -- cgit v1.2.3 From 1ce921ae3d30ef86f8313d753e07b67f9bcfc8f8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:05 +0200 Subject: arm64: dts: qcom: sdm630: Add RPMPD nodes Add the rpmpd node on the sdm630 and define the available levels. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 5ea3884b3ccb..0dd838ef5d6e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -423,6 +424,52 @@ compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,sdm660-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + }; + }; }; }; -- cgit v1.2.3 From 01b182d920a8147f185adfc5364952aeed9eb086 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:06 +0200 Subject: arm64: dts: qcom: sdm630: Add MMCC node Add MultiMedia Clock Controller node to allow for accessing and controlling Multimedia Subsystem clocks by their respective users. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 0dd838ef5d6e..e2cbe210048e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -874,6 +874,34 @@ status = "disabled"; }; + mmcc: clock-controller@c8c0000 { + compatible = "qcom,mmcc-sdm630"; + reg = <0x0c8c0000 0x40000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "xo", + "sleep_clk", + "gpll0", + "gpll0_div", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "dp_link_2x_clk_divsel_five", + "dp_vco_divided_clk_src_mux"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&gcc GCC_MMSS_GPLL0_CLK>, + <&gcc GCC_MMSS_GPLL0_DIV_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + }; + blsp1_dma: dma-controller@c144000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c144000 0x1f000>; -- cgit v1.2.3 From 045547a022529d29ad2ddc1981817743d1dac91e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:07 +0200 Subject: arm64: dts: qcom: sdm630: Add interconnect provider nodes Add interconnect provider nodes to allow for NoC bus scaling. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 59 ++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e2cbe210048e..c46b7327afbe 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -516,11 +517,38 @@ clock-names = "core"; }; + bimc: interconnect@1008000 { + compatible = "qcom,sdm660-bimc"; + reg = <0x01008000 0x78000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + restart@10ac000 { compatible = "qcom,pshold"; reg = <0x010ac000 0x4>; }; + cnoc: interconnect@1500000 { + compatible = "qcom,sdm660-cnoc"; + reg = <0x01500000 0x10000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + snoc: interconnect@1626000 { + compatible = "qcom,sdm660-snoc"; + reg = <0x01626000 0x7090>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + anoc2_smmu: iommu@16c0000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x016c0000 0x40000>; @@ -564,6 +592,25 @@ status = "disabled"; }; + a2noc: interconnect@1704000 { + compatible = "qcom,sdm660-a2noc"; + reg = <0x01704000 0xc100>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + }; + + mnoc: interconnect@1745000 { + compatible = "qcom,sdm660-mnoc"; + reg = <0x01745000 0xA010>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a", "iface"; + clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, + <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, + <&mmcc AHB_CLK_SRC>; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x01f40000 0x20000>; @@ -1156,6 +1203,18 @@ status = "disabled"; }; + gnoc: interconnect@17900000 { + compatible = "qcom,sdm660-gnoc"; + reg = <0x17900000 0xe000>; + #interconnect-cells = <1>; + /* + * This one apparently features no clocks, + * so let's not mess with the driver needlessly + */ + clock-names = "bus", "bus_a"; + clocks = <&xo_board>, <&xo_board>; + }; + apcs_glb: mailbox@17911000 { compatible = "qcom,sdm660-apcs-hmss-global"; reg = <0x17911000 0x1000>; -- cgit v1.2.3 From b52555d590d1609ea9577f25f06d366e397afe96 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:08 +0200 Subject: arm64: dts: qcom: sdm630: Add MDSS nodes Add MDSS node along with its children to enable display functionality. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 198 ++++++++++++++++++++++++++++++++++- 1 file changed, 196 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index c46b7327afbe..e0c6099d0810 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -941,14 +941,208 @@ <&sleep_clk>, <&gcc GCC_MMSS_GPLL0_CLK>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <0>, - <0>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, <0>, <0>, <0>, <0>; }; + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-262500000 { + opp-hz = /bits/ 64 <262500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + + mdss: mdss@c900000 { + compatible = "qcom,mdss"; + reg = <0x0c900000 0x1000>, + <0x0c9b0000 0x1040>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + mdp: mdp@c901000 { + compatible = "qcom,mdp5"; + reg = <0x0c901000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + assigned-clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + interconnects = <&mnoc 2 &bimc 5>, + <&mnoc 3 &bimc 5>, + <&gnoc 0 &mnoc 17>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "rotator-mem"; + iommus = <&mmss_smmu 0>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SDM660_VDDCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-peak-kBps = <320000 320000 76800>; + required-opps = <&rpmpd_opp_low_svs>; + }; + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-peak-kBps = <6400000 6400000 160000>; + required-opps = <&rpmpd_opp_svs>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <6400000 6400000 190000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + opp-330000000 { + opp-hz = /bits/ 64 <330000000>; + opp-peak-kBps = <6400000 6400000 240000>; + required-opps = <&rpmpd_opp_nom>; + }; + opp-412500000 { + opp-hz = /bits/ 64 <412500000>; + opp-peak-kBps = <6400000 6400000 320000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + dsi0: dsi@c994000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0c994000 0x400>; + reg-names = "dsi_ctrl"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SDM660_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "byte", + "byte_intf", + "mnoc", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@c994400 { + compatible = "qcom,dsi-phy-14nm-660"; + reg = <0x0c994400 0x100>, + <0x0c994500 0x300>, + <0x0c994800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + }; + }; + blsp1_dma: dma-controller@c144000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c144000 0x1f000>; -- cgit v1.2.3 From 142662f8f43c1725418ff13a2c83fb218d2b0911 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:09 +0200 Subject: arm64: dts: qcom: sdm630: Add qfprom subnodes These will be required for USB and Adreno support. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-7-konrad.dybcio@somainline.org [bjorn: y/_/-/ in gpu_speed_bin] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e0c6099d0810..ae271d697704 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -508,6 +508,16 @@ reg = <0x00780000 0x621c>; #address-cells = <1>; #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@240 { + reg = <0x240 0x1>; + bits = <25 3>; + }; + + gpu_speed_bin: gpu-speed-bin@41a0 { + reg = <0x41a0 0x1>; + bits = <21 7>; + }; }; rng: rng@793000 { -- cgit v1.2.3 From c65a4ed2ea8bca368e8e8822b61f7309aa706171 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:10 +0200 Subject: arm64: dts: qcom: sdm630: Add USB configuration This will let us use USB2 on our devices. The SoC supposedly supports USB3, but there are no known cases of devices that actually have USB3 wired up in hardware. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-8-konrad.dybcio@somainline.org [bjorn: Changes dwc3 node name to "usb"] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 64 ++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index ae271d697704..f2ffe094a8dd 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -904,6 +904,70 @@ cell-index = <0>; }; + usb3: usb@a8f8800 { + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + reg = <0x0a8f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_AGGRE2_USB3_AXI_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "bus", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + assigned-clock-rates = <19200000>, <120000000>, + <19200000>; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB_30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + resets = <&gcc GCC_USB_30_BCR>; + + usb3_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xc8d0>; + interrupts = ; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + /* + * SDM630 technically supports USB3 but I + * haven't seen any devices making use of it. + */ + maximum-speed = "high-speed"; + phys = <&qusb2phy>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; + }; + }; + + qusb2phy: phy@c012000 { + compatible = "qcom,sdm660-qusb2-phy"; + reg = <0x0c012000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; + }; + sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c0c4000 0x1000>, -- cgit v1.2.3 From 36a0d47aee6a8cfd3c6cf4274732d8ef994a25b4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:11 +0200 Subject: arm64: dts: qcom: sdm630: Fix TLMM node and pinctrl configuration Previous pinctrl configuration was wrong. Fix it and clean up how multi-pin states are described. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-9-konrad.dybcio@somainline.org [bjorn: Polished the commit message] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 212 +++++++++++++++++++++++------------ 1 file changed, 139 insertions(+), 73 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index f2ffe094a8dd..a0ee2137a819 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -626,14 +626,18 @@ reg = <0x01f40000 0x20000>; }; - tlmm: pinctrl@3000000 { + tlmm: pinctrl@3100000 { compatible = "qcom,sdm630-pinctrl"; - reg = <0x03000000 0xc00000>; + reg = <0x03100000 0x400000>, + <0x03500000 0x400000>, + <0x03900000 0x400000>; + reg-names = "south", "center", "north"; interrupts = ; gpio-controller; - #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 114>; + #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <0x2>; + #interrupt-cells = <2>; blsp1_uart1_default: blsp1-uart1-default { pins = "gpio0", "gpio1", "gpio2", "gpio3"; @@ -653,40 +657,48 @@ bias-disable; }; - blsp2_uart1_tx_active: blsp2-uart1-tx-active { - pins = "gpio16"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep { - pins = "gpio16"; - drive-strength = <2>; - bias-pull-up; - }; + blsp2_uart1_default: blsp2-uart1-active { + tx-rts { + pins = "gpio16", "gpio19"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-disable; + }; - blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active { - pins = "gpio17", "gpio18"; - drive-strength = <2>; - bias-disable; - }; + rx { + /* + * Avoid garbage data while BT module + * is powered off or not driving signal + */ + pins = "gpio17"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-pull-up; + }; - blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep { - pins = "gpio17", "gpio18"; - drive-strength = <2>; - bias-no-pull; + cts { + /* Match the pull of the BT module */ + pins = "gpio18"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-pull-down; + }; }; - blsp2_uart1_rfr_active: blsp2-uart1-rfr-active { - pins = "gpio19"; - drive-strength = <2>; - bias-disable; - }; + blsp2_uart1_sleep: blsp2-uart1-sleep { + tx { + pins = "gpio16"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; - blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep { - pins = "gpio19"; - drive-strength = <2>; - bias-no-pull; + rx-cts-rts { + pins = "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-no-pull; + }; }; i2c1_default: i2c1-default { @@ -785,50 +797,106 @@ bias-pull-up; }; - sdc1_clk_on: sdc1-clk-on { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; + sdc1_state_on: sdc1-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; - sdc1_clk_off: sdc1-clk-off { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; - sdc1_cmd_on: sdc1-cmd-on { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; - sdc1_cmd_off: sdc1-cmd-off { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; }; - sdc1_data_on: sdc1-data-on { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <8>; - }; + sdc1_state_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; - sdc1_data_off: sdc1-data-off { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; }; - sdc1_rclk_on: sdc1-rclk-on { - pins = "sdc1_rclk"; - bias-pull-down; + sdc2_state_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; }; - sdc1_rclk_off: sdc1-rclk-off { - pins = "sdc1_rclk"; - bias-pull-down; + sdc2_state_off: sdc2-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; }; }; @@ -986,8 +1054,8 @@ clock-names = "core", "iface", "xo", "ice"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; bus-width = <8>; non-removable; @@ -1354,10 +1422,8 @@ dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active - &blsp2_uart1_rfr_active>; - pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep - &blsp2_uart1_rfr_sleep>; + pinctrl-0 = <&blsp2_uart1_default>; + pinctrl-1 = <&blsp2_uart1_sleep>; status = "disabled"; }; -- cgit v1.2.3 From 0b700aa1b3e6240bc9885b18700c95bce6c1d948 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:12 +0200 Subject: arm64: dts: qcom: sdm630: Add SDHCI2 node This will enable usage of (generally) uSD cards. While at it, add accompanying OPP table for DVFS. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-10-konrad.dybcio@somainline.org [bjorn: Dropped "sdhci1-" prefix from opp-table node] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index a0ee2137a819..9baaf86e6a73 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1036,6 +1036,56 @@ status = "disabled"; }; + sdhc_2: sdhci@c084000 { + compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0c084000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + interconnects = <&a2noc 3 &a2noc 10>, + <&gnoc 0 &cnoc 28>; + operating-points-v2 = <&sdhc2_opp_table>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + power-domains = <&rpmpd SDM660_VDDCX>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <200000 140000>; + opp-avg-kBps = <130718 133320>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + opp-peak-kBps = <250000 160000>; + opp-avg-kBps = <196078 150000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <4096000 4096000>; + opp-avg-kBps = <1338562 1338562>; + }; + }; + }; + sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c0c4000 0x1000>, -- cgit v1.2.3 From 738777ab85ea9aced9e6e139be921c5dd89498f3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:13 +0200 Subject: arm64: dts: qcom: sdm630: Add interconnect and opp table to sdhc_1 The SDHC port 1 has interconnects and can make use of DVFS: define the interconnections and the OPP table in order to optimize performance and power consumption. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-11-konrad.dybcio@somainline.org [bjorn: Dropped "sdhc1-" prefix from opp-table node] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 9baaf86e6a73..c8d85e03d0ae 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1103,14 +1103,42 @@ <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "core", "iface", "xo", "ice"; + interconnects = <&a2noc 2 &a2noc 10>, + <&gnoc 0 &cnoc 27>; + interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; + operating-points-v2 = <&sdhc1_opp_table>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; + power-domains = <&rpmpd SDM660_VDDCX>; bus-width = <8>; non-removable; status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <200000 140000>; + opp-avg-kBps = <130718 133320>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + opp-peak-kBps = <250000 160000>; + opp-avg-kBps = <196078 150000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <4096000 4096000>; + opp-avg-kBps = <1338562 1338562>; + }; + }; }; mmcc: clock-controller@c8c0000 { -- cgit v1.2.3 From a64fa0e23b5f712828379319d20b32546e0cfb94 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:14 +0200 Subject: arm64: dts: qcom: sdm630: Add GPU Clock Controller node Add the GPU Clock Controller in SDM630 and keep it disabled by default. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-12-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index c8d85e03d0ae..3c94d892083d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -922,6 +923,22 @@ status = "disabled"; }; + gpucc: clock-controller@5065000 { + compatible = "qcom,gpucc-sdm630"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x05065000 0x9038>; + + clocks = <&xo_board>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names = "xo", + "gcc_gpu_gpll0_clk", + "gcc_gpu_gpll0_div_clk"; + status = "disabled"; + }; + lpass_smmu: iommu@5100000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x05100000 0x40000>; -- cgit v1.2.3 From 6bb717fe56f67218715fd3b8eaf65bb1fe8f8458 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:15 +0200 Subject: arm64: dts: qcom: sdm630: Add clocks and power domains to SMMU nodes Add the required clocks and power domains for the SMMUs to work. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-13-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3c94d892083d..108e9e1ba28e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -563,9 +563,14 @@ anoc2_smmu: iommu@16c0000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x016c0000 0x40000>; - #iommu-cells = <1>; + assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + assigned-clock-rates = <1000>; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + clock-names = "bus"; #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = , , @@ -904,9 +909,22 @@ kgsl_smmu: iommu@5040000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x05040000 0x10000>; - #iommu-cells = <1>; + /* + * GX GDSC parent is CX. We need to bring up CX for SMMU + * but we need both up for Adreno. On the other hand, we + * need to manage the GX rpmpd domain in the adreno driver. + * Enable CX/GX GDSCs here so that we can manage just the GX + * RPM Power Domain in the Adreno driver. + */ + power-domains = <&gpucc GPU_GX_GDSC>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_GPU_BIMC_GFX_CLK>; + clock-names = "iface", "mem", "mem_iface"; #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = , , @@ -1597,9 +1615,16 @@ mmss_smmu: iommu@cd00000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; - #iommu-cells = <1>; + clocks = <&mmcc MNOC_AHB_CLK>, + <&mmcc BIMC_SMMU_AHB_CLK>, + <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, + <&mmcc BIMC_SMMU_AXI_CLK>; + clock-names = "iface-mm", "iface-smmu", + "bus-mm", "bus-smmu"; #global-interrupts = <2>; + #iommu-cells = <1>; + interrupts = , , -- cgit v1.2.3 From 056d4ff8279a1df70eaf2fccb5977508c83627aa Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:16 +0200 Subject: arm64: dts: qcom: sdm630: Add qcom,adreno-smmu compatible The Adreno SMMU in SDM630 needs this compatible string for proper context handling and split pagetables support. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-14-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 108e9e1ba28e..66734649d482 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -907,7 +907,8 @@ }; kgsl_smmu: iommu@5040000 { - compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,sdm630-smmu-v2", + "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0x05040000 0x10000>; /* -- cgit v1.2.3 From 7c54b82b4545386bb576b7c5df5b8d4f95f11a5b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:17 +0200 Subject: arm64: dts: qcom: sdm630: Add TSENS node This will enable temperature reporting for various SoC components. Acked-by: Rob Herring Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-15-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + arch/arm64/boot/dts/qcom/sdm630.dtsi | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 4a2eaf28e3fd..d3b9e9b600a2 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -48,6 +48,7 @@ properties: - qcom,sc7180-tsens - qcom,sc7280-tsens - qcom,sc8180x-tsens + - qcom,sdm630-tsens - qcom,sdm845-tsens - qcom,sm8150-tsens - qcom,sm8250-tsens diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 66734649d482..082fa5c4c46d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -627,6 +627,17 @@ <&mmcc AHB_CLK_SRC>; }; + tsens: thermal-sensor@10ae000 { + compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; + reg = <0x010ae000 0x1000>, /* TM */ + <0x010ad000 0x1000>; /* SROT */ + #qcom,sensors = <12>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x01f40000 0x20000>; -- cgit v1.2.3 From c8236767599afb43d4e274cc56efecfe47c55332 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:18 +0200 Subject: arm64: dts: qcom: sdm630: Add modem/ADSP SMP2P nodes Add SMP2P nodes that are required for ADSP and modem bringup. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-16-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 082fa5c4c46d..d952caf208cf 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -481,6 +481,46 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 3332c59649fea6b00f437c20e294e8b29f07fca7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:19 +0200 Subject: arm64: dts: qcom: sdm630: Add thermal-zones configuration Add a basic thermal-zones configuration to make sure the SoC doesn't overheat itself to death. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-17-konrad.dybcio@somainline.org [bjorn: Sorted thermal-zones below "soc"] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 173 +++++++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index d952caf208cf..e71f799b1e4a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1808,6 +1808,179 @@ #hwlock-cells = <1>; }; + thermal-zones { + aoss-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + /* + * According to what downstream DTS says, + * the entire power efficient cluster has + * only a single thermal sensor. + */ + + pwr-cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + pwr_cluster_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + + pwr_cluster_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + gpu_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- cgit v1.2.3 From 7ca2ebc90a4624b361c9b7291d7cafa2deab2c1a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:20 +0200 Subject: arm64: dts: qcom: sdm630: Add ADSP remoteproc configuration Configure the ADSP remote processor and add a simple sound{} node to make way for future development. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-18-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 83 ++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e71f799b1e4a..97683b16cfd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1709,6 +1710,85 @@ status = "disabled"; }; + adsp_pil: remoteproc@15700000 { + compatible = "qcom,sdm660-adsp-pas"; + reg = <0x15700000 0x4040>; + + interrupts-extended = + <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + power-domains = <&rpmpd SDM660_VDDCX>; + power-domain-names = "cx"; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + + label = "lpass"; + mboxes = <&apcs_glb 9>; + qcom,remote-pid = <2>; + #address-cells = <1>; + #size-cells = <0>; + + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,apr-domain = ; + #address-cells = <1>; + #size-cells = <0>; + + q6core { + reg = ; + compatible = "qcom,q6core"; + }; + + q6afe: apr-service@4 { + compatible = "qcom,q6afe"; + reg = ; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + }; + + q6asm: apr-service@7 { + compatible = "qcom,q6asm"; + reg = ; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&lpass_smmu 1>; + }; + }; + + q6adm: apr-service@8 { + compatible = "qcom,q6adm"; + reg = ; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + }; + }; + gnoc: interconnect@17900000 { compatible = "qcom,sdm660-gnoc"; reg = <0x17900000 0xe000>; @@ -1808,6 +1888,9 @@ #hwlock-cells = <1>; }; + sound: sound { + }; + thermal-zones { aoss-thermal { polling-delay-passive = <250>; -- cgit v1.2.3 From adc57d4a463b59ec7d3adf7125758de5a1db3944 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:21 +0200 Subject: arm64: dts: qcom: sdm630: Raise tcsr_mutex_regs size Enlarge the size to make sure all relevant registers can be reached. This will be required to support the modem. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-19-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 97683b16cfd6..ab2b781cdff0 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -681,7 +681,7 @@ tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; - reg = <0x01f40000 0x20000>; + reg = <0x01f40000 0x40000>; }; tlmm: pinctrl@3100000 { -- cgit v1.2.3 From 5cf69dcbec8bd6620ecef601a6744489d5201e0e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:22 +0200 Subject: arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration The SDM630 SoC features an Adreno 508.0 GPU with a minimum frequency of 160MHz and a maximum of (depending on the speed-bin) 775MHz. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-20-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 84 +++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index ab2b781cdff0..8735cac2fde1 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, AngeloGioacchino Del Regno */ #include @@ -958,6 +959,87 @@ }; }; + adreno_gpu: gpu@5000000 { + compatible = "qcom,adreno-508.0", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x05000000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gpucc GPUCC_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_GPU_BIMC_GFX_CLK>, + <&gpucc GPUCC_RBCPR_CLK>, + <&gpucc GPUCC_GFX3D_CLK>; + + clock-names = "iface", + "rbbmtimer", + "mem", + "mem_iface", + "rbcpr", + "core"; + + power-domains = <&rpmpd SDM660_VDDMX>; + iommus = <&kgsl_smmu 0>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + interconnects = <&gnoc 1 &bimc 5>; + interconnect-names = "gfx-mem"; + + operating-points-v2 = <&gpu_sdm630_opp_table>; + + gpu_sdm630_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-775000000 { + opp-hz = /bits/ 64 <775000000>; + opp-level = ; + opp-peak-kBps = <5412000>; + opp-supported-hw = <0xA2>; + }; + opp-647000000 { + opp-hz = /bits/ 64 <647000000>; + opp-level = ; + opp-peak-kBps = <4068000>; + opp-supported-hw = <0xFF>; + }; + opp-588000000 { + opp-hz = /bits/ 64 <588000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + opp-supported-hw = <0xFF>; + }; + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + opp-level = ; + opp-peak-kBps = <2724000>; + opp-supported-hw = <0xFF>; + }; + opp-370000000 { + opp-hz = /bits/ 64 <370000000>; + opp-level = ; + opp-peak-kBps = <2188000>; + opp-supported-hw = <0xFF>; + }; + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-level = ; + opp-peak-kBps = <1648000>; + opp-supported-hw = <0xFF>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-level = ; + opp-peak-kBps = <1200000>; + opp-supported-hw = <0xFF>; + }; + }; + }; + kgsl_smmu: iommu@5040000 { compatible = "qcom,sdm630-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; -- cgit v1.2.3 From b59b058c623d274919b4cae5e0625f8231cbb474 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:23 +0200 Subject: arm64: dts: qcom: pm660: Support SPMI regulators on PMIC sid 1 The PM660 PMIC has SPMI regulators on the PMIC SID 1: let's declare the second pmic subtree and add the spmi vregs compatible to probe them there. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-21-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index 2e6a6f6c3b66..c6c57fe626e3 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -47,4 +47,15 @@ #interrupt-cells = <2>; }; }; + + pmic@1 { + compatible = "qcom,pm660", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm660_spmi_regulators: pm660-regulators { + compatible = "qcom,pm660-regulators"; + }; + }; }; -- cgit v1.2.3 From 7b56a804e58b1670cb8f17b66543facd21af4dd2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:24 +0200 Subject: arm64: dts: qcom: pm660l: Add WLED support This will enable backlight control on WLED-enabled devices. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-22-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660l.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index edba6de02084..83cc92ba441d 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -31,6 +31,23 @@ reg = <0x3 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm660l_wled: leds@d800 { + compatible = "qcom,pm660l-wled"; + reg = <0xd800 0xd900>; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp"; + label = "backlight"; + + qcom,switching-freq = <800>; + qcom,ovp-millivolt = <29600>; + qcom,current-boost-limit = <970>; + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; + qcom,enabled-strings = <0 1>; + + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 2a1fbb121aa6d87c618f7f345c3c498cb8a65446 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:25 +0200 Subject: arm64: dts: qcom: pm660l: Support SPMI regulators on PMIC sid 3 The PM660L PMIC has SPMI regulators on the PMIC SID 3: let's add the compatible in order to probe them. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-23-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660l.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 83cc92ba441d..64a8e9b9afbe 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -48,6 +48,10 @@ status = "disabled"; }; + + pm660l_spmi_regulators: pm660l-regulators { + compatible = "qcom,pm660l-regulators"; + }; }; }; -- cgit v1.2.3 From 4bf09754050652885bc123454615ef4f74f9586c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:26 +0200 Subject: arm64: dts: qcom: pm660(l): Add VADC and temp alarm nodes Add VADC, temperature alarm and thermal zones for pm660(l) to allow for temperature and voltage readouts and prevent PMIC overheating. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-24-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660.dtsi | 122 +++++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/pm660l.dtsi | 33 ++++++++++ 2 files changed, 155 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index c6c57fe626e3..e847d7209afc 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -3,9 +3,35 @@ * Copyright (c) 2020, Konrad Dybcio */ +#include #include #include #include +#include + +/ { + thermal-zones { + pm660 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm660_temp>; + + trips { + pm660_alert0: pm660-alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + pm660_crit: pm660-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; &spmi_bus { @@ -37,6 +63,102 @@ }; + pm660_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm660_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm660_adc: adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + ref_gnd: ref_gnd@0 { + reg = ; + qcom,decimation = <1024>; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25: vref_1p25@1 { + reg = ; + qcom,decimation = <1024>; + qcom,pre-scaling = <1 1>; + }; + + die_temp: die_temp@6 { + reg = ; + qcom,decimation = <1024>; + qcom,pre-scaling = <1 1>; + }; + + xo_therm: xo_therm@4c { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,decimation = <1024>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + msm_therm: msm_therm@4d { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,decimation = <1024>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + emmc_therm: emmc_therm@4e { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,decimation = <1024>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + pa_therm0: thermistor0@4f { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,decimation = <1024>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + pa_therm1: thermistor1@50 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,decimation = <1024>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + quiet_therm: quiet_therm@51 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,decimation = <1024>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + vadc_vph_pwr: vph_pwr@83 { + reg = ; + qcom,decimation = <1024>; + qcom,pre-scaling = <1 3>; + }; + + vcoin: vcoin@83 { + reg = ; + qcom,decimation = <1024>; + qcom,pre-scaling = <1 3>; + }; + }; + pm660_gpios: gpios@c000 { compatible = "qcom,pm660-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 64a8e9b9afbe..05086cbe573b 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -3,9 +3,35 @@ * Copyright (c) 2020, Konrad Dybcio */ +#include #include #include #include +#include + +/ { + thermal-zones { + pm660l { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm660l_temp>; + + trips { + pm660l_alert0: pm660l-alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + pm660l_crit: pm660l-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; &spmi_bus { @@ -15,6 +41,13 @@ #address-cells = <1>; #size-cells = <0>; + pm660l_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm660l_gpios: gpios@c000 { compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; -- cgit v1.2.3 From 05aa0eb325c98f7e06eeb3f251cbab1b27586c8e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:27 +0200 Subject: arm64: dts: qcom: sdm660: Make the DTS an overlay on top of 630 There is SO MUCH common code between these two SoCs that it makes no sense to keep what is essentially a duplicate of 630.dtsi. Instead, it's better to just change the things that differ. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-25-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 2 - arch/arm64/boot/dts/qcom/sdm660.dtsi | 448 ++++++--------------- 2 files changed, 117 insertions(+), 333 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 76533e8b2092..3e677fb7cfea 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -37,8 +37,6 @@ &blsp1_uart2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 4abbdd03d1e7..13467e2c708a 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -2,371 +2,157 @@ /* * Copyright (c) 2018, Craig Tatlor. * Copyright (c) 2020, Alexey Minnekhanov + * Copyright (c) 2020, AngeloGioacchino Del Regno + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Martin Botka */ -#include -#include +#include "sdm630.dtsi" -/ { - interrupt-parent = <&intc>; +&adreno_gpu { + compatible = "qcom,adreno-512.0", "qcom,adreno"; + operating-points-v2 = <&gpu_sdm660_opp_table>; - #address-cells = <2>; - #size-cells = <2>; + gpu_sdm660_opp_table: opp-table { + compatible = "operating-points-v2"; - chosen { }; + /* + * 775MHz is only available on the highest speed bin + * Though it cannot be used for now due to interconnect + * framework not supporting multiple frequencies + * at the same opp-level - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + opp-peak-kBps = <5412000>; + opp-supported-hw = <0xCHECKME>; }; - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; + * These OPPs are correct, but we are lacking support for the + * GPU regulator. Hence, disable them for now to prevent the + * platform from hanging on high graphics loads. - CPU0: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - L1_I_100: l1-icache { - compatible = "cache"; - }; - L1_D_100: l1-dcache { - compatible = "cache"; - }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + opp-peak-kBps = <5184000>; + opp-supported-hw = <0xFF>; }; - CPU1: cpu@101 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L1_I_101: l1-icache { - compatible = "cache"; - }; - L1_D_101: l1-dcache { - compatible = "cache"; - }; + opp-647000000 { + opp-hz = /bits/ 64 <647000000>; + opp-level = ; + opp-peak-kBps = <4068000>; + opp-supported-hw = <0xFF>; }; - CPU2: cpu@102 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L1_I_102: l1-icache { - compatible = "cache"; - }; - L1_D_102: l1-dcache { - compatible = "cache"; - }; + opp-588000000 { + opp-hz = /bits/ 64 <588000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + opp-supported-hw = <0xFF>; }; - CPU3: cpu@103 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L1_I_103: l1-icache { - compatible = "cache"; - }; - L1_D_103: l1-dcache { - compatible = "cache"; - }; + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + opp-level = ; + opp-peak-kBps = <2724000>; + opp-supported-hw = <0xFF>; }; - CPU4: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - L1_I_0: l1-icache { - compatible = "cache"; - }; - L1_D_0: l1-dcache { - compatible = "cache"; - }; + opp-370000000 { + opp-hz = /bits/ 64 <370000000>; + opp-level = ; + opp-peak-kBps = <2188000>; + opp-supported-hw = <0xFF>; }; + */ - CPU5: cpu@1 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L1_I_1: l1-icache { - compatible = "cache"; - }; - L1_D_1: l1-dcache { - compatible = "cache"; - }; + opp-266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-level = ; + opp-peak-kBps = <1648000>; + opp-supported-hw = <0xFF>; }; - CPU6: cpu@2 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x2>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L1_I_2: l1-icache { - compatible = "cache"; - }; - L1_D_2: l1-dcache { - compatible = "cache"; - }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-level = ; + opp-peak-kBps = <1200000>; + opp-supported-hw = <0xFF>; }; - - CPU7: cpu@3 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x3>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L1_I_3: l1-icache { - compatible = "cache"; - }; - L1_D_3: l1-dcache { - compatible = "cache"; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm"; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; }; +}; - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm660"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00100000 0x94000>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sdm660-pinctrl"; - reg = <0x03100000 0x400000>, - <0x03500000 0x400000>, - <0x03900000 0x400000>; - reg-names = "south", "center", "north"; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 114>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - uart_console_active: uart_console_active { - pinmux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; +&CPU0 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - }; +&CPU1 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; - spmi_bus: spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; +&CPU2 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; - blsp1_uart2: serial@c170000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c170000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; +&CPU3 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; - timer@17920000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17920000 0x1000>; +&CPU4 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; - frame@17921000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17921000 0x1000>, - <0x17922000 0x1000>; - }; +&CPU5 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; - frame@17923000 { - frame-number = <1>; - interrupts = ; - reg = <0x17923000 0x1000>; - status = "disabled"; - }; +&CPU6 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; - frame@17924000 { - frame-number = <2>; - interrupts = ; - reg = <0x17924000 0x1000>; - status = "disabled"; - }; +&CPU7 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; - frame@17925000 { - frame-number = <3>; - interrupts = ; - reg = <0x17925000 0x1000>; - status = "disabled"; - }; +&gcc { + compatible = "qcom,gcc-sdm660"; +}; - frame@17926000 { - frame-number = <4>; - interrupts = ; - reg = <0x17926000 0x1000>; - status = "disabled"; - }; +&gpucc { + compatible = "qcom,gpucc-sdm660"; +}; - frame@17927000 { - frame-number = <5>; - interrupts = ; - reg = <0x17927000 0x1000>; - status = "disabled"; - }; +&mmcc { + compatible = "qcom,mmcc-sdm660"; + /* + * 660 has one more dsi host/phy, which - when implemented + * and tested - should be added to the clocks property. + */ +}; - frame@17928000 { - frame-number = <6>; - interrupts = ; - reg = <0x17928000 0x1000>; - status = "disabled"; - }; - }; +&tlmm { + compatible = "qcom,sdm660-pinctrl"; +}; - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x17a00000 0x10000>, - <0x17b00000 0x100000>; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - interrupts = ; - }; - }; +&tsens { + #qcom,sensors = <14>; }; -- cgit v1.2.3 From 36c7b98f7935110ff5a65b49f03ae3bbf1cbe181 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:28 +0200 Subject: arm64: dts: qcom: Add device tree for SDM636 This SoC is almost identical to its older brother, SDM660, with a few minor exceptions like the different GPU. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-26-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm636.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm636.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm636.dtsi b/arch/arm64/boot/dts/qcom/sdm636.dtsi new file mode 100644 index 000000000000..ae15d81fa3f9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm636.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, AngeloGioacchino Del Regno + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Martin Botka + */ + +#include "sdm660.dtsi" + +/* + * According to the downstream DTS, + * 636 is basically a 660 except for + * different CPU frequencies, Adreno + * 509 instead of 512 and lack of + * turing IP. These differences will + * be addressed when the aforementioned + * peripherals will be enabled upstream. + */ + +&adreno_gpu { + compatible = "qcom,adreno-509.0", "qcom,adreno"; + /* Adreno 509 shares the frequency table with 512 */ +}; -- cgit v1.2.3 From c21512cbfbfdcb72ba3b41e714266149433b11c8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:29 +0200 Subject: arm64: dts: qcom: sdm630: Add IMEM node Add IMEM node and PIL reloc info as its child. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-27-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8735cac2fde1..c2c8396e930a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1747,6 +1747,21 @@ status = "disabled"; }; + imem@146bf000 { + compatible = "simple-mfd"; + reg = <0x146bf000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0x146bf000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + mmss_smmu: iommu@cd00000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; -- cgit v1.2.3 From f3d5d3cc69710344f152c6b65e54ccc8c818b9d4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:30 +0200 Subject: arm64: dts: qcom: sdm630: Configure the camera subsystem Add nodes for camss, cci and its pinctrl in order to bring up camera functionality. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-28-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 215 +++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index c2c8396e930a..15b7cdfb34b6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -856,6 +856,32 @@ bias-pull-up; }; + cci0_default: cci0_default { + pinmux { + pins = "gpio36","gpio37"; + function = "cci_i2c"; + }; + + pinconf { + pins = "gpio36","gpio37"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + cci1_default: cci1_default { + pinmux { + pins = "gpio38","gpio39"; + function = "cci_i2c"; + }; + + pinconf { + pins = "gpio38","gpio39"; + bias-pull-up; + drive-strength = <2>; + }; + }; + sdc1_state_on: sdc1-on { clk { pins = "sdc1_clk"; @@ -1762,6 +1788,195 @@ }; }; + camss: camss@ca00000 { + compatible = "qcom,sdm660-camss"; + reg = <0x0c824000 0x1000>, + <0x0ca00120 0x4>, + <0x0c825000 0x1000>, + <0x0ca00124 0x4>, + <0x0c826000 0x1000>, + <0x0ca00128 0x4>, + <0x0ca30000 0x100>, + <0x0ca30400 0x100>, + <0x0ca30800 0x100>, + <0x0ca30c00 0x100>, + <0x0ca31000 0x500>, + <0x0ca00020 0x10>, + <0x0ca10000 0x1000>, + <0x0ca14000 0x1000>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csiphy2", + "csiphy2_clk_mux", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "csi_clk_mux", + "vfe0", + "vfe1"; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "vfe0", + "vfe1"; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc THROTTLE_CAMSS_AXI_CLK>, + <&mmcc CAMSS_ISPIF_AHB_CLK>, + <&mmcc CAMSS_CSI0PHYTIMER_CLK>, + <&mmcc CAMSS_CSI1PHYTIMER_CLK>, + <&mmcc CAMSS_CSI2PHYTIMER_CLK>, + <&mmcc CAMSS_CSI0_AHB_CLK>, + <&mmcc CAMSS_CSI0_CLK>, + <&mmcc CAMSS_CPHY_CSID0_CLK>, + <&mmcc CAMSS_CSI0PIX_CLK>, + <&mmcc CAMSS_CSI0RDI_CLK>, + <&mmcc CAMSS_CSI1_AHB_CLK>, + <&mmcc CAMSS_CSI1_CLK>, + <&mmcc CAMSS_CPHY_CSID1_CLK>, + <&mmcc CAMSS_CSI1PIX_CLK>, + <&mmcc CAMSS_CSI1RDI_CLK>, + <&mmcc CAMSS_CSI2_AHB_CLK>, + <&mmcc CAMSS_CSI2_CLK>, + <&mmcc CAMSS_CPHY_CSID2_CLK>, + <&mmcc CAMSS_CSI2PIX_CLK>, + <&mmcc CAMSS_CSI2RDI_CLK>, + <&mmcc CAMSS_CSI3_AHB_CLK>, + <&mmcc CAMSS_CSI3_CLK>, + <&mmcc CAMSS_CPHY_CSID3_CLK>, + <&mmcc CAMSS_CSI3PIX_CLK>, + <&mmcc CAMSS_CSI3RDI_CLK>, + <&mmcc CAMSS_AHB_CLK>, + <&mmcc CAMSS_VFE0_CLK>, + <&mmcc CAMSS_CSI_VFE0_CLK>, + <&mmcc CAMSS_VFE0_AHB_CLK>, + <&mmcc CAMSS_VFE0_STREAM_CLK>, + <&mmcc CAMSS_VFE1_CLK>, + <&mmcc CAMSS_CSI_VFE1_CLK>, + <&mmcc CAMSS_VFE1_AHB_CLK>, + <&mmcc CAMSS_VFE1_STREAM_CLK>, + <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, + <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, + <&mmcc CSIPHY_AHB2CRIF_CLK>, + <&mmcc CAMSS_CPHY_CSID0_CLK>, + <&mmcc CAMSS_CPHY_CSID1_CLK>, + <&mmcc CAMSS_CPHY_CSID2_CLK>, + <&mmcc CAMSS_CPHY_CSID3_CLK>; + clock-names = "top_ahb", + "throttle_axi", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csiphy2_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "csi3_ahb", + "csi3", + "csi3_phy", + "csi3_pix", + "csi3_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe0_ahb", + "vfe0_stream", + "vfe1", + "csi_vfe1", + "vfe1_ahb", + "vfe1_stream", + "vfe_ahb", + "vfe_axi", + "csiphy_ahb2crif", + "cphy_csid0", + "cphy_csid1", + "cphy_csid2", + "cphy_csid3"; + interconnects = <&mnoc 5 &bimc 5>; + interconnect-names = "vfe-mem"; + iommus = <&mmss_smmu 0xc00>, + <&mmss_smmu 0xc01>, + <&mmss_smmu 0xc02>, + <&mmss_smmu 0xc03>; + power-domains = <&mmcc CAMSS_VFE0_GDSC>, + <&mmcc CAMSS_VFE1_GDSC>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci: cci@ca0c000 { + compatible = "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0ca0c000 0x1000>; + interrupts = ; + + assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>; + assigned-clock-rates = <80800000>, <37500000>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default &cci1_default>; + power-domains = <&mmcc CAMSS_TOP_GDSC>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mmss_smmu: iommu@cd00000 { compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; -- cgit v1.2.3 From ab290284398d8a33a5e7e9ebe7c7364b481f6dd8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:31 +0200 Subject: arm64: dts: qcom: sdm660: Add required nodes for DSI1 Configure the second DSI host/phy and account for them in the mmcc node. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-29-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 101 +++++++++++++++++++++++++++++++++-- 1 file changed, 97 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 13467e2c708a..eccf6fde16b4 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -141,12 +141,105 @@ compatible = "qcom,gpucc-sdm660"; }; +&mdp { + ports { + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; +}; + +&mdss { + dsi1: dsi@c996000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0c996000 0x400>; + reg-names = "dsi_ctrl"; + + /* DSI1 shares the OPP table with DSI0 */ + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SDM660_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, + <&dsi1_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MISC_AHB_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "byte", + "byte_intf", + "mnoc", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@c996400 { + compatible = "qcom,dsi-phy-14nm-660"; + reg = <0x0c996400 0x100>, + <0x0c996500 0x300>, + <0x0c996800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; +}; + &mmcc { compatible = "qcom,mmcc-sdm660"; - /* - * 660 has one more dsi host/phy, which - when implemented - * and tested - should be added to the clocks property. - */ + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&gcc GCC_MMSS_GPLL0_CLK>, + <&gcc GCC_MMSS_GPLL0_DIV_CLK>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, + <0>, + <0>; }; &tlmm { -- cgit v1.2.3 From 8b36c824b9a77a8816258fdd00997a5f78542814 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 00:25:32 +0200 Subject: arm64: dts: qcom: sdm630-xperia-nile: Add all RPM and fixed regulators Add all of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-30-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 394 ++++++++++++++++++++- 1 file changed, 393 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 9ba359c848d0..db6fcbd75c3b 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, AngeloGioacchino Del Regno + * */ /dts-v1/; @@ -39,6 +41,55 @@ }; }; + board_vbat: vbat-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + regulator-always-on; + regulator-boot-on; + }; + + cam_vdig_imx300_219_vreg: cam_vdig_imx300_219_vreg { + compatible = "regulator-fixed"; + regulator-name = "cam_vdig_imx300_219_vreg"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_vdig_default>; + }; + + cam_vana_front_vreg: cam_vana_front_vreg { + compatible = "regulator-fixed"; + regulator-name = "cam_vana_front_vreg"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&imx219_vana_default>; + }; + + cam_vana_rear_vreg: cam_vana_rear_vreg { + compatible = "regulator-fixed"; + regulator-name = "cam_vana_rear_vreg"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&imx300_vana_default>; + }; + gpio_keys { status = "okay"; compatible = "gpio-keys"; @@ -134,3 +185,344 @@ }; }; }; + +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + /* + * At least on Nile's configuration, S3B/S4B (VDD_CX) and + * S5B (VDD_MX) are managed only through RPM Power Domains. + * Trying to set a voltage on the main supply will create + * havoc and freeze the SoC. + * In any case, reference voltages for these regulators are: + * S3B/S4B: 0.870V + * S5B: 0.915V + */ + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <928000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2b_2p95: l2 { + /* + * This regulator supports 1.648 - 3.104V on this board + * but we set a max voltage of anything less than 2.7V + * to satisfy a condition in sdhci.c that will disable + * 3.3V SDHCI signaling, which happens to be not really + * supported on the Xperia Nile/Ganges platform. + */ + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l3b_3p0: l3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <100000>; + regulator-allow-set-load; + }; + + vreg_l4b_29p5: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_29p5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l6b_3p3: l6 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3128000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* L9B (870mV) is currently unused */ + /* L10B (915mV) is currently unused */ + + vreg_bob: bob { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3624000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1226000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1008000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1008000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1368000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1784000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1904000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* L16A (2.70V) is unused */ + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l18a_1v8: l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <10>; + regulator-min-microamp = <200>; + regulator-max-microamp = <50000>; + regulator-system-load = <10000>; + regulator-allow-set-load; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <8 4>; + + imx300_vana_default: imx300-vana-default { + pins = "gpio50"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + imx219_vana_default: imx219-vana-default { + pins = "gpio51"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cam_vdig_default: cam-vdig-default { + pins = "gpio52"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; +}; -- cgit v1.2.3 From 158f80a68148d7febdbcc3586d2d17e455453563 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:33 +0200 Subject: arm64: dts: qcom: sdm630-nile: Use &labels Refer to nodes by their labels to match the current convention. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-31-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 61 +++++++++++++--------- 1 file changed, 35 insertions(+), 26 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index db6fcbd75c3b..fa7bef49b332 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -5,8 +5,6 @@ * */ -/dts-v1/; - #include "sdm630.dtsi" #include "pm660.dtsi" #include "pm660l.dtsi" @@ -150,40 +148,38 @@ no-map; }; }; +}; - soc { - sdhci@c0c4000 { - status = "okay"; +&blsp_i2c1 { + status = "okay"; - mmc-ddr-1_8v; - /* SoMC Nile platform's eMMC doesn't support HS200 mode */ - mmc-hs400-1_8v; - }; + /* Synaptics touchscreen */ +}; - i2c@c175000 { - status = "okay"; +&blsp_i2c2 { + status = "okay"; - /* Synaptics touchscreen */ - }; + /* SMB1351 charger */ +}; - i2c@c176000 { - status = "okay"; +/* I2C3, 4, 5, 7 and 8 are disabled on this board. */ - /* SMB1351 charger */ - }; +&blsp_i2c6 { + status = "okay"; - serial@c1af000 { - status = "okay"; - }; + /* NXP NFC */ +}; - /* I2C3, 4, 5, 7 and 8 are disabled on this board. */ +&blsp1_uart2 { + status = "okay"; - i2c@c1b6000 { - status = "okay"; + /* MSM serial console */ +}; - /* NXP NFC */ - }; - }; +&blsp2_uart1 { + status = "okay"; + + /* HCI Bluetooth */ }; &rpm_requests { @@ -502,6 +498,19 @@ }; }; +&sdhc_1 { + status = "okay"; + supports-cqe; + + /* SoMC Nile platform's eMMC doesn't support HS200 mode */ + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + vmmc-supply = <&vreg_l4b_29p5>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + &tlmm { gpio-reserved-ranges = <8 4>; -- cgit v1.2.3 From 2c616239f255a66e5989e8fa5cdaefc25eec3d00 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:34 +0200 Subject: arm64: dts: qcom: sdm630-nile: Add USB Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on Nile and Ganges boards. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-32-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index fa7bef49b332..77ee75809e6e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -148,6 +148,15 @@ no-map; }; }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; }; &blsp_i2c1 { @@ -182,6 +191,14 @@ /* HCI Bluetooth */ }; +&qusb2phy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + &rpm_requests { pm660l-regulators { compatible = "qcom,rpm-pm660l-regulators"; @@ -535,3 +552,12 @@ drive-strength = <2>; }; }; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; -- cgit v1.2.3 From fcbcd062a894067f1f622f927ed7c448723d6f06 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:35 +0200 Subject: arm64: dts: qcom: sdm630-nile: Add Volume up key Let's get loud! Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-33-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 77ee75809e6e..38488abbe50e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -191,6 +191,16 @@ /* HCI Bluetooth */ }; +&pon { + volup { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + &qusb2phy { status = "okay"; -- cgit v1.2.3 From 4c1d849ec047dde4e21dca7f20f300575307a660 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:36 +0200 Subject: arm64: dts: qcom: sdm630-xperia: Retire sdm630-sony-xperia-ganges.dtsi After further consideration, it is not worth to keep another separate DTSI, as the differences between Nile and Ganges are very minimal. Instead, let's just address the minimal differences between Kirin and Mermaid. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-34-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm630-sony-xperia-ganges-kirin.dts | 12 ++++++- .../boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi | 40 ---------------------- .../dts/qcom/sdm630-sony-xperia-nile-discovery.dts | 1 + .../dts/qcom/sdm630-sony-xperia-nile-pioneer.dts | 1 + .../dts/qcom/sdm630-sony-xperia-nile-voyager.dts | 1 + .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 1 - .../dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts | 14 +++++--- 7 files changed, 23 insertions(+), 47 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts index 46a7f2b26e6b..aea949265a2d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts @@ -5,9 +5,19 @@ /dts-v1/; -#include "sdm630-sony-xperia-ganges.dtsi" +#include "sdm630.dtsi" +#include "sdm630-sony-xperia-nile.dtsi" / { model = "Sony Xperia 10"; compatible = "sony,kirin-row", "qcom,sdm630"; + + chosen { + framebuffer@9d400000 { + reg = <0 0x9d400000 0 (2520 * 1080 * 4)>; + height = <2520>; + }; + }; }; + +/delete-node/ &vreg_l18a_1v8; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi deleted file mode 100644 index cf2e8b5d60e8..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Martin Botka - */ - -/dts-v1/; - -/* Ganges is very similar to Nile, but - * there are some differences that will need - * to be addresed when more peripherals are - * enabled upstream. Hence the separate DTSI. - */ -#include "sdm630-sony-xperia-nile.dtsi" - -/ { - chosen { - framebuffer@9d400000 { - reg = <0 0x9d400000 0 (2520 * 1080 * 4)>; - height = <2520>; - }; - }; - - /* Yes, this is intentional. - * Ganges devices only use gpio-keys for - * Volume Down, but currently there's an - * issue with it that has to be resolved. - * Until then, let's not make the kernel panic - */ - /delete-node/ gpio-keys; - - soc { - - i2c@c175000 { - status = "okay"; - - /* Novatek touchscreen */ - }; - }; - -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts index 8fca0b69fa01..c574e430ba67 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "sdm630.dtsi" #include "sdm630-sony-xperia-nile.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts index 90dcd4ebaaed..a93ff3ab1b6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "sdm630.dtsi" #include "sdm630-sony-xperia-nile.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts index fae5f1bb6834..59a679c205e0 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "sdm630.dtsi" #include "sdm630-sony-xperia-nile.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 38488abbe50e..7d33a75dca91 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -5,7 +5,6 @@ * */ -#include "sdm630.dtsi" #include "pm660.dtsi" #include "pm660l.dtsi" #include diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index 7c0830e6a48c..bba1c2bce213 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -5,16 +5,20 @@ /dts-v1/; -/* Mermaid uses sdm636, but it's different ever so slightly - * that we can ignore it for the time being. Sony also commonizes - * the Ganges platform as a whole in downstream kernels. - */ -#include "sdm630-sony-xperia-ganges.dtsi" +#include "sdm630-sony-xperia-ganges-kirin.dts" +#include "sdm636.dtsi" / { model = "Sony Xperia 10 Plus"; compatible = "sony,mermaid-row", "qcom,sdm636"; + /* SDM636 v1 */ qcom,msm-id = <345 0>; qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00 0x1001b 0x102001a 0x00 0x00>; }; + +&sdc2_state_on { + pinconf-clk { + drive-strength = <14>; + }; +}; -- cgit v1.2.3 From f8fc1c43c51b4aad8a88d2c968d2a63b5ef7ed13 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:37 +0200 Subject: arm64: dts: qcom: sdm630-nile: Add Synaptics touchscreen. Delete the node on Ganges devices, as they use a different one. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-35-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm630-sony-xperia-ganges-kirin.dts | 2 ++ .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 36 +++++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts index aea949265a2d..a4e1fb8ca52d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts @@ -20,4 +20,6 @@ }; }; +/* Ganges devices feature a Novatek touchscreen instead. */ +/delete-node/ &touchscreen; /delete-node/ &vreg_l18a_1v8; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 7d33a75dca91..73be3d68742f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -161,7 +161,29 @@ &blsp_i2c1 { status = "okay"; - /* Synaptics touchscreen */ + touchscreen: synaptics-rmi4-i2c@70 { + compatible = "syna,rmi4-i2c"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&tlmm 45 0x2008>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_lcd_id_active>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <220>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; }; &blsp_i2c2 { @@ -540,6 +562,18 @@ &tlmm { gpio-reserved-ranges = <8 4>; + ts_int_active: ts-int-active { + pins = "gpio45"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_lcd_id_active: ts-lcd-id-active { + pins = "gpio56"; + drive-strength = <8>; + bias-disable; + }; + imx300_vana_default: imx300-vana-default { pins = "gpio50"; function = "gpio"; -- cgit v1.2.3 From bc81940d8ca568f887d5337ccf97f104a60be955 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:38 +0200 Subject: arm64: dts: qcom: sdm630-nile: Specify ADSP firmware name Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-36-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 73be3d68742f..4c45306b62fa 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -158,6 +158,10 @@ }; }; +&adsp_pil { + firmware-name = "adsp.mdt"; +}; + &blsp_i2c1 { status = "okay"; -- cgit v1.2.3 From e634d8196f7da05b81a4574e1572ef559f1ba85f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:39 +0200 Subject: arm64: dts: qcom: sdm630-nile: Enable uSD card slot Enable the internal uSD slot to let the user have more storage. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-37-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 4c45306b62fa..66e8945fbaf9 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -334,6 +334,7 @@ regulator-enable-ramp-delay = <250>; regulator-ramp-delay = <0>; regulator-allow-set-load; + regulator-system-load = <800000>; }; vreg_l6b_3p3: l6 { @@ -563,6 +564,13 @@ vqmmc-supply = <&vreg_l8a_1p8>; }; +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_29p5>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + &tlmm { gpio-reserved-ranges = <8 4>; -- cgit v1.2.3 From 18abedf7d4e6d069f89ba056223a03ba1e17af3b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:40 +0200 Subject: arm64: dts: qcom: sdm630-nile: Remove gpio-keys autorepeat The autorepeat feature is not needed on gpio-keys. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-38-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 66e8945fbaf9..849900e8b80e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -93,7 +93,6 @@ input-name = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - autorepeat; camera_focus { label = "Camera Focus"; -- cgit v1.2.3 From 536f44285ff618087256f2059d0d6b5581d3748d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:41 +0200 Subject: arm64: dts: qcom: sdm630: Add I2C functions to I2C pins This was overlooked earlier, fix it to ensure the busses can work properly. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-39-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 15b7cdfb34b6..557f81d94130 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -762,96 +762,112 @@ i2c1_default: i2c1-default { pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; i2c1_sleep: i2c1-sleep { pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; drive-strength = <2>; bias-pull-up; }; i2c2_default: i2c2-default { pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; i2c2_sleep: i2c2-sleep { pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; drive-strength = <2>; bias-pull-up; }; i2c3_default: i2c3-default { pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; drive-strength = <2>; bias-disable; }; i2c3_sleep: i2c3-sleep { pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; drive-strength = <2>; bias-pull-up; }; i2c4_default: i2c4-default { pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; i2c4_sleep: i2c4-sleep { pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; drive-strength = <2>; bias-pull-up; }; i2c5_default: i2c5-default { pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; i2c5_sleep: i2c5-sleep { pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; drive-strength = <2>; bias-pull-up; }; i2c6_default: i2c6-default { pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; i2c6_sleep: i2c6-sleep { pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; drive-strength = <2>; bias-pull-up; }; i2c7_default: i2c7-default { pins = "gpio26", "gpio27"; + function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; i2c7_sleep: i2c7-sleep { pins = "gpio26", "gpio27"; + function = "blsp_i2c7"; drive-strength = <2>; bias-pull-up; }; i2c8_default: i2c8-default { pins = "gpio30", "gpio31"; + function = "blsp_i2c8"; drive-strength = <2>; bias-disable; }; i2c8_sleep: i2c8-sleep { pins = "gpio30", "gpio31"; + function = "blsp_i2c8"; drive-strength = <2>; bias-pull-up; }; -- cgit v1.2.3 From 712e245fcbfd92f385ea5bc12af399d97953a298 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 29 Jul 2021 00:25:42 +0200 Subject: arm64: dts: qcom: sdm630: Add DMA to I2C hosts Add DMA properties to I2C hosts to allow for DMA transfers. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210728222542.54269-40-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 557f81d94130..c77d4e4305d6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1626,6 +1626,8 @@ <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_default>; @@ -1644,6 +1646,8 @@ <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_default>; @@ -1662,6 +1666,8 @@ <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c3_default>; @@ -1680,6 +1686,8 @@ <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_default>; @@ -1726,6 +1734,8 @@ <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_default>; @@ -1744,6 +1754,8 @@ <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c6_default>; @@ -1762,6 +1774,8 @@ <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c7_default>; @@ -1780,6 +1794,8 @@ <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; clock-frequency = <400000>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c8_default>; -- cgit v1.2.3 From 2e01e0c2145998ad0b2dfa4a990cc55436194099 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 15 Jun 2021 18:28:16 -0500 Subject: arm64: dts: qcom: sdm850-yoga: Enable IPA Shuffle memory regions to make firmware loading succeed and then enable the ipa device. Tested-by: Steev Klimaszewski Link: https://lore.kernel.org/r/20210615232816.835325-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 ++++++++------------- .../arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 5 +++++ 2 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1796ae8372be..49624eadce84 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -128,28 +128,23 @@ no-map; }; - ipa_fw_mem: memory@8c400000 { - reg = <0 0x8c400000 0 0x10000>; + wlan_msa_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x100000>; no-map; }; - ipa_gsi_mem: memory@8c410000 { - reg = <0 0x8c410000 0 0x5000>; + gpu_mem: memory@8c515000 { + reg = <0 0x8c515000 0 0x2000>; no-map; }; - gpu_mem: memory@8c415000 { - reg = <0 0x8c415000 0 0x2000>; + ipa_fw_mem: memory@8c517000 { + reg = <0 0x8c517000 0 0x5a000>; no-map; }; - adsp_mem: memory@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - - wlan_msa_mem: memory@8df00000 { - reg = <0 0x8df00000 0 0x100000>; + adsp_mem: memory@8c600000 { + reg = <0 0x8c600000 0 0x1a00000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index c2a709a384e9..3eaa42dc3794 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -415,6 +415,11 @@ }; }; +&ipa { + status = "okay"; + memory-region = <&ipa_fw_mem>; +}; + &mdss { status = "okay"; }; -- cgit v1.2.3 From 59983a5c918ed5aad51d866d320c4beb3b952a08 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 15 Jun 2021 16:22:49 +0200 Subject: arm64: dts: qcom: sm8250: Add DMA to I2C/SPI Add dma properties to I2C and SPI nodes to make sure DMA transfers can go through. While at it, fix up the property order in SPI nodes to make #address- and #size-cells go after all the meaningful properties. Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Acked-by: Vinod Koul Link: https://lore.kernel.org/r/20210615142249.170512-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 200 ++++++++++++++++++++++++++++------- 1 file changed, 160 insertions(+), 40 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d4432e357fcf..acd5043e2092 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -561,6 +561,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -572,10 +575,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -587,6 +593,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -598,10 +607,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -613,6 +625,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -624,10 +639,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -639,6 +657,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -650,10 +671,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -678,6 +702,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c18_default>; interrupts = ; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -689,10 +716,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -717,6 +747,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -728,10 +761,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; @@ -779,6 +815,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -790,10 +829,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -805,6 +847,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -816,10 +861,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -831,6 +879,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -842,10 +893,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -870,6 +924,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_default>; interrupts = ; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -881,10 +938,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -896,6 +956,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -907,10 +970,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -922,6 +988,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -933,10 +1002,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -948,6 +1020,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -959,10 +1034,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -987,6 +1065,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -998,10 +1079,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; @@ -1046,6 +1130,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1057,10 +1144,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -1072,6 +1162,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1083,10 +1176,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -1098,6 +1194,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1109,10 +1208,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -1124,6 +1226,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1135,10 +1240,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -1150,6 +1258,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1161,10 +1272,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -1189,6 +1303,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1200,10 +1317,13 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; power-domains = <&rpmhpd SM8250_CX>; operating-points-v2 = <&qup_opp_table>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; -- cgit v1.2.3 From cff4bbaf2a2dee244f852a1c888b281064a9296c Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Mon, 21 Jun 2021 21:53:04 +0200 Subject: arm64: dts: qcom: Add support for SM6125 This commits adds the Device tree file for SM6125 SoC. Signed-off-by: Martin Botka Link: https://lore.kernel.org/r/20210621195308.654587-1-martin.botka@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 566 +++++++++++++++++++++++++++++++++++ 1 file changed, 566 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6125.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi new file mode 100644 index 000000000000..2b37ce6a9f9c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -0,0 +1,566 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Martin Botka + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + next-level-cache = <&L2_1>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + next-level-cache = <&L2_1>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6125", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@40000000 { + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + device_type = "memory"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: memory@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@46000000 { + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + }; + + reserved_mem1: memory@46200000 { + reg = <0x0 0x46200000 0x0 0x2d00000>; + no-map; + }; + + camera_mem: memory@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x500000>; + no-map; + }; + + modem_mem: memory@4b000000 { + reg = <0x0 0x4b000000 0x0 0x7e00000>; + no-map; + }; + + venus_mem: memory@52e00000 { + reg = <0x0 0x52e00000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: memory@53300000 { + reg = <0x0 0x53300000 0x0 0x200000>; + no-map; + }; + + cdsp_mem: memory@53500000 { + reg = <0x0 0x53500000 0x0 0x1e00000>; + no-map; + }; + + adsp_pil_mem: memory@55300000 { + reg = <0x0 0x55300000 0x0 0x1e00000>; + no-map; + }; + + ipa_fw_mem: memory@57100000 { + reg = <0x0 0x57100000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@57110000 { + reg = <0x0 0x57110000 0x0 0x5000>; + no-map; + }; + + gpu_mem: memory@57115000 { + reg = <0x0 0x57115000 0x0 0x2000>; + no-map; + }; + + cont_splash_mem: memory@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_mem: memory@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + cdsp_sec_mem: memory@5f800000 { + reg = <0x0 0x5f800000 0x0 0x1e00000>; + no-map; + }; + + qseecom_mem: memory@5e400000 { + reg = <0x0 0x5e400000 0x0 0x1400000>; + no-map; + }; + + sdsp_mem: memory@f3000000 { + reg = <0x0 0xf3000000 0x0 0x400000>; + no-map; + }; + + adsp_mem: memory@f3400000 { + reg = <0x0 0xf3400000 0x0 0x800000>; + no-map; + }; + + qseecom_ta_mem: memory@13fc00000 { + reg = <0x1 0x3fc00000 0x0 0x400000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6125"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + }; + + smem: smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00 0xffffffff>; + compatible = "simple-bus"; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x00340000 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6125-tlmm"; + reg = <0x00500000 0x400000>, + <0x00900000 0x400000>, + <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc2_state_off: sdc2-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6125"; + reg = <0x01400000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + }; + + hsusb_phy1: phy@1613000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x01613000 0x180>; + #phy-cells = <0>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "ref", "cfg_ahb"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + status = "disabled"; + }; + + rpm_msg_ram: memory@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x045f0000 0x7000>; + }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <4>; + status = "disabled"; + }; + + usb3: usb@4ef8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0x04ef8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + + power-domains = <&gcc USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb3_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x04e00000 0xcd00>; + interrupts = ; + phys = <&hsusb_phy1>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,sm6125-apcs-hmss-global"; + reg = <0x0f111000 0x1000>; + + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0f120000 0x1000>; + clock-frequency = <19200000>; + + frame@0f121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0f121000 0x1000>, + <0x0f122000 0x1000>; + }; + + frame@0f123000 { + frame-number = <1>; + interrupts = ; + reg = <0x0f123000 0x1000>; + status = "disabled"; + }; + + frame@0f124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0f124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = ; + reg = <0x0f125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = ; + reg = <0x0f126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = ; + reg = <0x0f127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = ; + reg = <0x0f128000 0x1000>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0f200000 0x20000>, + <0x0f300000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = ; + clock-frequency = <19200000>; + }; +}; -- cgit v1.2.3 From 82e1783890b773e30705be70db5896ebc67b4f22 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Mon, 21 Jun 2021 21:53:05 +0200 Subject: arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II This commits add support for Sony Xperia 10II based on the SM6125 SoC. Currently working features: - dmesg output to bootloader preconfigured display - USB - eMMC - Volume down button Signed-off-by: Martin Botka Link: https://lore.kernel.org/r/20210621195308.654587-2-martin.botka@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 139 +++++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d4a6205ff976..d4a59978c830 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts new file mode 100644 index 000000000000..58b6b2742d3f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Martin Botka + */ + +/dts-v1/; + +#include "sm6125.dtsi" +#include +#include +#include + +/ { + /* required for bootloader to select correct board */ + qcom,msm-id = <394 0x10000>; /* sm6125 v1 */ + qcom,board-id = <34 0>; + + model = "Sony Xperia 10 II"; + compatible = "sony,pdx201", "qcom,sm6125"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (2520 * 1080 * 4)>; + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + status = "okay"; + compatible = "gpio-keys"; + input-name = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + vol-dn { + label = "Volume Down"; + gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + debug_mem: memory@ffb00000 { + reg = <0x0 0xffb00000 0x0 0xc0000>; + no-map; + }; + + last_log_mem: memory@ffbc0000 { + reg = <0x0 0xffbc0000 0x0 0x80000>; + no-map; + }; + + pstore_mem: ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc40000 0x0 0xc0000>; + record-size = <0x1000>; + console-size = <0x40000>; + msg-size = <0x20000 0x20000>; + }; + + cmdline_mem: memory@ffd00000 { + reg = <0x0 0xffd40000 0x0 0x1000>; + no-map; + }; + }; +}; + +&hsusb_phy1 { + status = "okay"; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio98"; + bias-disable; + drive-strength = <2>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <22 2>, <28 6>; + + sdc2_state_on: sdc2-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio98"; + bias-pull-up; + drive-strength = <2>; + }; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + extcon = <&extcon_usb>; +}; -- cgit v1.2.3 From 184adb500f72d8a65e3cb05d28a0a7de9561734b Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:20 +0530 Subject: arm64: dts: qcom: msm8996: don't use empty memory node We expect bootloader to full memory details but passing empty values can give warning, so add a default value Signed-off-by: Vinod Koul Tested-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210308060826.3074234-13-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 3fa116e9bbeb..139a38e32211 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -368,10 +368,10 @@ #hwlock-cells = <1>; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0x0 0x80000000 0x0 0x0>; }; psci { -- cgit v1.2.3 From d53dc79f9b5699873423b7912d835be4594b3577 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:21 +0530 Subject: arm64: dts: qcom: msm8998: don't use empty memory node We expect bootloader to full memory details but passing empty values can give warning, so add a default value Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-14-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 6f294f9c0cdf..49f04b1c68a3 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -18,10 +18,10 @@ chosen { }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0x0 0x80000000 0x0 0x0>; }; reserved-memory { -- cgit v1.2.3 From cfdf0c27639571d7a99d00fe1ce931daa6726c27 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:22 +0530 Subject: arm64: dts: qcom: sdm630: don't use empty memory node We expect bootloader to full memory details but passing empty values can give warning, so add a default value Signed-off-by: Vinod Koul Tested-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210308060826.3074234-15-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index c77d4e4305d6..e3772fefe03f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -316,10 +316,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0x0 0x80000000 0x0 0x0>; }; pmu { -- cgit v1.2.3 From 52c9887fba71fc8f12d343833fc595c762aac8c7 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:24 +0530 Subject: arm64: dts: qcom: ipq8074: fix pci node reg property reg property should be array of values, here it is a single array, leading to below warning: arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml: soc: pci@10000000:reg:0: [268435456, 3869, 268439328, 168, 557056, 8192, 269484032, 4096] is too long arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml: soc: pci@10000000:ranges: 'oneOf' conditional failed, one must be fixed: arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml: soc: pci@10000000:ranges: 'oneOf' conditional failed, one must be fixed: [[2164260864, 0, 270532608, 270532608, 0, 1048576, 2181038080, 0, 271581184, 271581184, 0, 13631488]] is not of type 'null' [2164260864, 0, 270532608, 270532608, 0, 1048576, 2181038080, 0, 271581184, 271581184, 0, 13631488] is too long arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml: soc: pci@20000000:reg:0: [536870912, 3869, 536874784, 168, 524288, 8192, 537919488, 4096] is too long arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml: soc: pci@20000000:ranges: 'oneOf' conditional failed, one must be fixed: arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml: soc: pci@20000000:ranges: 'oneOf' conditional failed, one must be fixed: [[2164260864, 0, 538968064, 538968064, 0, 1048576, 2181038080, 0, 540016640, 540016640, 0, 13631488]] is not of type 'null' [2164260864, 0, 538968064, 538968064, 0, 1048576, 2181038080, 0, 540016640, 540016640, 0, 13631488] is too long Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-17-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index c1c5d8011a27..0baf17fbafce 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -589,10 +589,10 @@ pcie1: pci@10000000 { compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d - 0x10000f20 0xa8 - 0x00088000 0x2000 - 0x10100000 0x1000>; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x00088000 0x2000>, + <0x10100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <1>; @@ -651,10 +651,10 @@ pcie0: pci@20000000 { compatible = "qcom,pcie-ipq8074"; - reg = <0x20000000 0xf1d - 0x20000f20 0xa8 - 0x00080000 0x2000 - 0x20100000 0x1000>; + reg = <0x20000000 0xf1d>, + <0x20000f20 0xa8>, + <0x00080000 0x2000>, + <0x20100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; -- cgit v1.2.3 From c81210e38966cfa1c784364e4035081c3227cf5b Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:25 +0530 Subject: arm64: dts: qcom: sdm660: use reg value for memory node memory node like other node should be node@reg, which is missing in this case, so fix it up arch/arm64/boot/dts/qcom/ipq8074-hk01.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 1073741824, 0, 536870912]]} Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-18-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index e8c37a1693d3..cc08dc4eb56a 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -20,7 +20,7 @@ stdout-path = "serial0"; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; -- cgit v1.2.3 From 1b91b8ef60e9a67141e66af3cca532c00f4605fe Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:26 +0530 Subject: arm64: dts: qcom: ipq6018: drop '0x' from unit address Nodes need not contain '0x' for the unit address. Drop it to fix the below warning: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: reserved-memory: 'memory@0x60000' does not match any of the regexes Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-19-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 01ca4b8b9d2b..1549c2cf8813 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -151,7 +151,7 @@ #size-cells = <2>; ranges; - rpm_msg_ram: memory@0x60000 { + rpm_msg_ram: memory@60000 { reg = <0x0 0x60000 0x0 0x6000>; no-map; }; -- cgit v1.2.3 From 639dfdbecd88ec05bda87b1d5d419afad50af21c Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:18 +0530 Subject: arm64: dts: qcom: sdm630: don't use underscore in node name We have underscore (_) in node name so fix that up as well. Fix this by changing node name to use dash (-) Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-11-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e3772fefe03f..9153e6616ba4 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -22,14 +22,14 @@ chosen { }; clocks { - xo_board: xo_board { + xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "xo_board"; }; - sleep_clk: sleep_clk { + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32764>; -- cgit v1.2.3 From 8c678beca7ed3fa8a2c6d86f6603bc23400f9ad8 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:16 +0530 Subject: arm64: dts: qcom: msm8994: don't use underscore in node name We have underscore (_) in node name leading to warning: arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dt.yaml: clocks: xo_board: {'type': 'object'} is not allowed for {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[19200000]], 'phandle': [[26]]} arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dt.yaml: clocks: sleep_clk: {'type': 'object'} is not allowed for {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[32768]]} Fix this by changing node name to use dash (-) Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-9-vkoul@kernel.org [bjorn: Added clock-output-names to satisfy parent_names] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 662f2f246b9b..986fe60dec5f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -15,16 +15,18 @@ chosen { }; clocks { - xo_board: xo_board { + xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; + clock-output-names = "xo_board"; }; - sleep_clk: sleep_clk { + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; + clock-output-names = "sleep_clk"; }; }; -- cgit v1.2.3 From 84f3efbe5b4654077608bc2fc027177fe4592321 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:17 +0530 Subject: arm64: dts: qcom: msm8996: don't use underscore in node name We have underscore (_) in node name leading to warning: arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: clocks: xo_board: {'type': 'object'} is not allowed for {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[19200000]], 'clock-output-names': ['xo_board'], 'phandle': [[115]]} Fix this by changing node name to use dash (-) Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-10-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 139a38e32211..491b9b73b092 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -19,14 +19,14 @@ chosen { }; clocks { - xo_board: xo_board { + xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "xo_board"; }; - sleep_clk: sleep_clk { + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32764>; -- cgit v1.2.3 From 39d66a2e7fbfeda9a36ba55a15fd3eaec0e213e4 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 8 Mar 2021 11:38:15 +0530 Subject: dt-bindings: arm: qcom: Drop qcom,mtp qcom,mtp is used msm8916-mtp.dts but not documented, it is a generic mtp compatible and we have specfifc ones for each mtp so drop this arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: /: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,msm8916-mtp', 'qcom,msm8916-mtp/1', 'qcom,msm8916', 'qcom,mtp'] is too long Additional items are not allowed ('qcom,msm8916', 'qcom,mtp' were unexpected) Additional items are not allowed ('qcom,mtp' was unexpected) Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210308060826.3074234-8-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index c3f885923127..d66c15538785 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -9,6 +9,5 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", - "qcom,msm8916", "qcom,mtp"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; }; -- cgit v1.2.3 From 8dc7dba0cc2596a938974fb600db325b248bc1e7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Feb 2021 22:38:42 +0100 Subject: arm64: dts: qcom: pm8004: Enable the PMIC peripherals by default It makes no sense to require one more step to enable the PMIC features. If the PMIC is present, it already has to be explicitly #included anyway. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210225213842.117694-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8004.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/pm8004.dtsi b/arch/arm64/boot/dts/qcom/pm8004.dtsi index 0abd1abe12fc..532b79acf0e8 100644 --- a/arch/arm64/boot/dts/qcom/pm8004.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8004.dtsi @@ -9,7 +9,6 @@ reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; }; pm8004_lsid5: pmic@5 { @@ -17,7 +16,6 @@ reg = <0x5 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; pm8004_spmi_regulators: regulators { compatible = "qcom,pm8004-regulators"; -- cgit v1.2.3 From 589562946f8590bc57eb4e99ed9739d598f0d765 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Wed, 10 Feb 2021 11:40:45 +0000 Subject: arm64: dts: qcom: msm8996: Add gpu cooling support Add cooling-cells property and cooling maps for the GPU. Signed-off-by: Yassine Oudjana Link: https://lore.kernel.org/r/Ku7mRZ_q2mYDZQ048IPlAc8VOVhH8N4uENhMI-JXxjeiZxjbRRs40ZJYwREb_ScgCvtQgtdl1VRjoDd7CR_8vCrbWVe8n3MwyB1S3VbSDis=@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 491b9b73b092..31686950004e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -972,6 +972,8 @@ status = "disabled"; + #cooling-cells = <2>; + gpu_opp_table: opp-table { compatible ="operating-points-v2"; @@ -3209,7 +3211,14 @@ gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -3224,7 +3233,14 @@ gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit v1.2.3 From 77b53d65dc1e54321ec841912f06bcb558a079c0 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 11 Feb 2021 21:36:37 +0200 Subject: arm64: dts: qcom: sm8250: Fix epss_l3 unit address The unit address of the epss_l3 node is incorrect and does not match the address of its "reg" property. Let's fix it. Signed-off-by: Georgi Djakov Reviewed-by: Dmitry Baryshkov Reviewed-by: Sibi Sankar Link: https://lore.kernel.org/r/20210211193637.9737-1-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index acd5043e2092..dc5d0f733aba 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4075,7 +4075,7 @@ }; }; - epss_l3: interconnect@18591000 { + epss_l3: interconnect@18590000 { compatible = "qcom,sm8250-epss-l3"; reg = <0 0x18590000 0 0x1000>; -- cgit v1.2.3 From 437cdef515e29427df9c0d7e5b44b04dd17c3ff8 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Wed, 17 Feb 2021 22:56:32 +0530 Subject: arm64: dts: qcom: sc7180:: modified qfprom CORR size as per RAW size modified QFPROM controller CORRECTED region size as per RAW region size Signed-off-by: Ravi Kumar Bokka Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/1613582792-5225-1-git-send-email-rbokka@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 0d33c671751b..0a7f306dac83 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -668,7 +668,7 @@ qfprom: efuse@784000 { compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; - reg = <0 0x00784000 0 0x8ff>, + reg = <0 0x00784000 0 0x7a0>, <0 0x00780000 0 0x7a0>, <0 0x00782000 0 0x100>, <0 0x00786000 0 0x1fff>; -- cgit v1.2.3 From 67146f0738801d06635942b6faca6dcaafb5e63b Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 11 Mar 2021 19:42:18 -0800 Subject: arm64: dts: qcom: sm8350: Add wakeup-parent to tlmm Now that TLMM has the wakeup table, specify the Power Domain Controller to be the wakeup-parent of TLMM. Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20210312034218.3324410-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a631d58166b1..059cfdad7c19 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -801,6 +801,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 204>; + wakeup-parent = <&pdc>; qup_uart3_default_state: qup-uart3-default-state { rx { -- cgit v1.2.3 From 111c52854102983f2260eb819ab9326084a004d7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 3 Aug 2021 13:16:56 +0300 Subject: arm64: dts: qcom: sdm845: move bus clock to mdp node for sdm845 target Move the bus clock to mdp device node,in order to facilitate bus band width scaling on sdm845 target. The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, move the clock node to mdp device from where the votes are requested. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210803101657.1072358-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 49624eadce84..6bd05f62bb05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4143,9 +4143,8 @@ power-domains = <&dispcc MDSS_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; + clock-names = "iface", "core"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; assigned-clock-rates = <300000000>; @@ -4173,11 +4172,12 @@ <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; -- cgit v1.2.3 From 001ce9785c0674d913531345e86222c965fc8bf4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 3 Aug 2021 13:16:57 +0300 Subject: arm64: dts: qcom: sm8250: remove bus clock from the mdss node for sm8250 target Remove the bus clock from the mdss device node, in order to facilitate bus band width scaling on sm8250 target. The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, and since mdp device node already has the bus clock, remove the clock from the mdss device. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210803101657.1072358-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dc5d0f733aba..c337c32918f6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2590,10 +2590,9 @@ power-domains = <&dispcc MDSS_GDSC>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "nrt_bus", "core"; + clock-names = "iface", "nrt_bus", "core"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; assigned-clock-rates = <460000000>; -- cgit v1.2.3 From 6493367f8031b1e5cf0a217d6520c0d79a5d6659 Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Mon, 2 Aug 2021 10:32:56 +0530 Subject: arm64: dts: qcom: sc7280: Add interconnect properties for USB Add interconnect properties in USB DT nodes for sc7280. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1627880576-22391-1-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 1d405c2f234f..b5a5685193c4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1246,6 +1246,10 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@8c00000 { compatible = "snps,dwc3"; reg = <0 0x08c00000 0 0xe000>; @@ -1319,6 +1323,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; -- cgit v1.2.3 From 7dfb52dcc5a482506e0e1f3cee65a30fddd39a29 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 3 Aug 2021 18:34:12 +0530 Subject: arm64: dts: qcom: sc7280: Remove pm8350 and pmr735b for sc7280-idp Remove pm8350 and pmr735b die temp nodes as these pmics are not present on this board. Correct the tabbing for pmk8350_vadc node. Fixes: fbd5a1d22607 ("arm64: dts: qcom: sc7280: Add ADC channel nodes for PMIC temperatures to sc7280-idp") Signed-off-by: satya priya Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1627995852-24505-1-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 34 ++++++++++----------------------- 1 file changed, 10 insertions(+), 24 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 73225e3c2f86..ee76d96c5dbb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -9,8 +9,6 @@ #include #include -#include -#include #include #include "sc7280.dtsi" #include "pm7325.dtsi" @@ -244,29 +242,17 @@ }; &pmk8350_vadc { - pm8350_die_temp { - reg = ; - label = "pm8350_die_temp"; - qcom,pre-scaling = <1 1>; - }; - - pmk8350_die_temp { - reg = ; - label = "pmk8350_die_temp"; - qcom,pre-scaling = <1 1>; - }; - - pmr735a_die_temp { - reg = ; - label = "pmr735a_die_temp"; - qcom,pre-scaling = <1 1>; - }; + pmk8350_die_temp { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; - pmr735b_die_temp { - reg = ; - label = "pmr735b_die_temp"; - qcom,pre-scaling = <1 1>; - }; + pmr735a_die_temp { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; }; &qupv3_id_0 { -- cgit v1.2.3 From 87f0b434b91860fd6be0c824b596d9f3cb56d69e Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 3 Aug 2021 14:57:56 +0200 Subject: arm64: dts: qcom: sm8350: Rename GENI serial engine DT node In order to conform with downstream and upstream for previous generations of this hardware, rename dt-node 'qupv3_id_1' to 'qupv3_id_0'. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Robert Foss Link: https://lore.kernel.org/r/20210803125756.93824-1-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 2 +- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index f23a0cf3f7b7..56093e260ddf 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -219,7 +219,7 @@ firmware-name = "qcom/sm8350/modem.mbn"; }; -&qupv3_id_1 { +&qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 93740444dd1e..bd95009c1875 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -286,7 +286,7 @@ firmware-name = "qcom/sm8350/modem.mbn"; }; -&qupv3_id_1 { +&qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 059cfdad7c19..15df4a77d6b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -456,7 +456,7 @@ #mbox-cells = <2>; }; - qupv3_id_1: geniqup@9c0000 { + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; clock-names = "m-ahb", "s-ahb"; -- cgit v1.2.3 From 383409806ed6649c8f6c2ec4fecebedba97692b2 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Tue, 20 Jul 2021 15:33:42 +0000 Subject: arm64: dts: qcom: sdm845-oneplus-common: enable debug UART A labelled diagram showing the location of the Rx and Tx testpoints for the OnePlus 6 is available on the postmarketOS wiki: https://wiki.postmarketos.org/wiki/Serial_debugging:Cable_schematics The device uses 1.8v UART at a baud rate of 115200, bootloader output is also available here. Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20210720153125.43389-3-caleb@connolly.tech Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 4d052e39b348..6a32d327078d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -19,9 +19,14 @@ / { aliases { + serial0 = &uart9; hsuart0 = &uart6; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; label = "Volume keys"; @@ -526,6 +531,11 @@ }; }; +&uart9 { + label = "LS-UART1"; + status = "okay"; +}; + &ufs_mem_hc { status = "okay"; -- cgit v1.2.3 From 3440b1becd3c3d91c1418269cc2ef1d5118c9802 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Tue, 20 Jul 2021 15:33:55 +0000 Subject: arm64: dts: qcom: sdm845-oneplus: add ipa firmware names Add the correct patch to the ipa firmware now that custom paths are supported. Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20210720153125.43389-6-caleb@connolly.tech Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 6a32d327078d..150707159590 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -408,6 +408,7 @@ status = "okay"; memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn"; }; &mdss { -- cgit v1.2.3 From 5b01733f4fe60d237f68661fa0e9fc52a8a0dee3 Mon Sep 17 00:00:00 2001 From: V Sujith Kumar Reddy Date: Wed, 21 Jul 2021 13:35:48 +0530 Subject: arm64: dts: qcom: sc7180: Update lpass cpu node for audio over dp Updaate lpass dts node with HDMI reg, interrupt and iommu for supporting audio over dp. Signed-off-by: V Sujith Kumar Reddy Signed-off-by: Srinivasa Rao Mandadapu Reviewed-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20210721080549.28822-2-srivasam@qti.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 0a7f306dac83..b1e8f5073aa9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3532,17 +3532,20 @@ #power-domain-cells = <1>; }; - lpass_cpu: lpass@62f00000 { + lpass_cpu: lpass@62d87000 { compatible = "qcom,sc7180-lpass-cpu"; - reg = <0 0x62f00000 0 0x29000>; - reg-names = "lpass-lpaif"; + reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; + reg-names = "lpass-hdmiif", "lpass-lpaif"; iommus = <&apps_smmu 0x1020 0>, - <&apps_smmu 0x1021 0>; + <&apps_smmu 0x1021 0>, + <&apps_smmu 0x1032 0>; power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + status = "disabled"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, @@ -3559,8 +3562,9 @@ #address-cells = <1>; #size-cells = <0>; - interrupts = ; - interrupt-names = "lpass-irq-lpaif"; + interrupts = , + ; + interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; }; lpass_hm: clock-controller@63000000 { -- cgit v1.2.3 From b22d313e177281e0c87dbc8725704e4952bb910a Mon Sep 17 00:00:00 2001 From: V Sujith Kumar Reddy Date: Wed, 21 Jul 2021 13:35:49 +0530 Subject: arm64: dts: qcom: sc7180-trogdor: Add lpass dai link for HDMI Add dai link in sc7180-trogdor.dtsi for supporting audio over DP Signed-off-by: V Sujith Kumar Reddy Signed-off-by: Srinivasa Rao Mandadapu Reviewed-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20210721080549.28822-3-srivasam@qti.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 32d129011638..1c8c7bcd63df 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -288,6 +288,7 @@ "Headphone Jack", "HPOL", "Headphone Jack", "HPOR"; + #sound-dai-cells = <0>; #address-cells = <1>; #size-cells = <0>; @@ -314,6 +315,18 @@ sound-dai = <&max98360a>; }; }; + + dai-link@2 { + link-name = "MultiMedia2"; + reg = <2>; + cpu { + sound-dai = <&lpass_cpu 2>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; }; }; @@ -768,6 +781,10 @@ hp_i2c: &i2c9 { reg = ; qcom,playback-sd-lines = <0>; }; + + hdmi-primary@0 { + reg = ; + }; }; &mdp { -- cgit v1.2.3 From 53bc6b4170d574e410b2123c37be03ad34e13c09 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 22 Jul 2021 13:01:07 +0300 Subject: arm64: dts: qcom: ipq6018: correct TCSR block area According to Bjorn Andersson[1], &tcsr_q6 base is 0x01937000 with size 0x21000. Adjust qcom,halt-regs offsets (add 0xe000) to match the new syscon base. Also, rename to just &tcsr as Kathiravan T suggested. [1] https://lore.kernel.org/r/YLgO0Aj1d4w9EcPv@yoga Signed-off-by: Baruch Siach Link: https://lore.kernel.org/r/889aae1b88f120cb6281919d27164a959fbe69d0.1626948070.git.baruch@tkos.co.il Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 1549c2cf8813..66da336894eb 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -258,9 +258,9 @@ reg = <0x0 0x01905000 0x0 0x8000>; }; - tcsr_q6: syscon@1945000 { + tcsr: syscon@1937000 { compatible = "syscon"; - reg = <0x0 0x01945000 0x0 0xe000>; + reg = <0x0 0x01937000 0x0 0x21000>; }; blsp_dma: dma-controller@7884000 { @@ -504,7 +504,7 @@ clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "prng"; - qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; + qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; qcom,smem-states = <&wcss_smp2p_out 0>, <&wcss_smp2p_out 1>; -- cgit v1.2.3 From 11e03d692101e484df9322f892a8b6e111a82bfd Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 29 Jul 2021 23:34:44 +0530 Subject: arm64: dts: qcom: sc7280: Fixup the cpufreq node Fixup the register regions used by the cpufreq node on SC7280 SoC to support per core L3 DCVS. Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1627581885-32165-4-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index b5a5685193c4..dbbeb3a94a6d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1795,9 +1795,9 @@ cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; - reg = <0 0x18591000 0 0x1000>, - <0 0x18592000 0 0x1000>, - <0 0x18593000 0 0x1000>; + reg = <0 0x18591100 0 0x900>, + <0 0x18592100 0 0x900>, + <0 0x18593100 0 0x900>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; -- cgit v1.2.3 From c1b2189a19cf2a35b7345f4f94f4d47e452ab8e2 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 30 Jul 2021 12:16:13 +0530 Subject: arm64: dts: qcom: sc7280: Add qfprom node Add the qfprom node and its properties for the sc7280 SoC. Signed-off-by: Rajendra Nayak Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/1627627573-32454-5-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index dbbeb3a94a6d..11c1c20f4c79 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -442,6 +442,19 @@ #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0xa20>, + <0 0x00780000 0 0xa20>, + <0 0x00782000 0 0x120>, + <0 0x00786000 0 0x1fff>; + clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; + clock-names = "core"; + power-domains = <&rpmhpd SC7280_MX>; + #address-cells = <1>; + #size-cells = <1>; + }; + sdhc_1: sdhci@7c4000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; status = "disabled"; -- cgit v1.2.3 From 98b433864c20c7dd98b6da4ce01f1a0cc5c15c03 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Sun, 21 Mar 2021 20:42:12 +0800 Subject: arm64: dts: qcom: msm8916: Enable CoreSight STM component Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, which can benefit the CoreSight development on DB410c. Signed-off-by: Georgi Djakov Signed-off-by: Leo Yan Acked-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210321124212.4253-1-leo.yan@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 6aef0c2e4f0a..f8d8f3e3664e 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -414,6 +414,7 @@ &funnel0 { status = "okay"; }; &funnel1 { status = "okay"; }; &replicator { status = "okay"; }; +&stm { status = "okay"; }; &tpiu { status = "okay"; }; &smd_rpm_regulators { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4f06c0a9c425..3f85e34a8ce6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -489,6 +489,26 @@ <&rpmcc RPM_SMD_SNOC_A_CLK>; }; + stm: stm@802000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x00802000 0x1000>, + <0x09280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + /* System CTIs */ /* CTI 0 - TMC connections */ cti0: cti@810000 { @@ -562,6 +582,13 @@ remote-endpoint = <&funnel1_out>; }; }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; }; out-ports { -- cgit v1.2.3 From 129e1c968457d058d7a8cd21203a3aa42cac7830 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 16 Apr 2021 13:32:24 +0300 Subject: arm64: dts: qcom: sm8150: add SPI nodes Add missing SPI nodes for SM8150. Signed-off-by: Felipe Balbi Reviewed-by: Caleb Connolly Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210416103225.1872145-1-balbi@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 439 +++++++++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f8d3725c440e..d6d50b47e658 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -941,6 +941,21 @@ status = "disabled"; }; + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x880000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; @@ -954,6 +969,21 @@ status = "disabled"; }; + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x884000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; @@ -967,6 +997,21 @@ status = "disabled"; }; + spi2: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x888000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c3: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; @@ -980,6 +1025,21 @@ status = "disabled"; }; + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x88c000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c4: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; @@ -993,6 +1053,21 @@ status = "disabled"; }; + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x890000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c5: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; @@ -1006,6 +1081,21 @@ status = "disabled"; }; + spi5: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x894000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c6: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0 0x00898000 0 0x4000>; @@ -1019,6 +1109,21 @@ status = "disabled"; }; + spi6: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x898000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c7: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0089c000 0 0x4000>; @@ -1032,6 +1137,20 @@ status = "disabled"; }; + spi7: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x89c000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi7_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gpi_dma1: dma-controller@a00000 { @@ -1082,6 +1201,21 @@ status = "disabled"; }; + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0xa80000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; @@ -1095,6 +1229,21 @@ status = "disabled"; }; + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0xa84000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; @@ -1108,6 +1257,21 @@ status = "disabled"; }; + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0xa88000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; @@ -1121,6 +1285,21 @@ status = "disabled"; }; + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0xa8c000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart2: serial@a90000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; @@ -1143,6 +1322,21 @@ status = "disabled"; }; + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0xa90000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c16: i2c@94000 { compatible = "qcom,geni-i2c"; reg = <0 0x0094000 0 0x4000>; @@ -1155,6 +1349,21 @@ #size-cells = <0>; status = "disabled"; }; + + spi16: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0xa94000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi16_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gpi_dma2: dma-controller@c00000 { @@ -1206,6 +1415,21 @@ status = "disabled"; }; + spi17: spi@c80000 { + compatible = "qcom,geni-spi"; + reg = <0 0xc80000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi17_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c18: i2c@c84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c84000 0 0x4000>; @@ -1219,6 +1443,21 @@ status = "disabled"; }; + spi18: spi@c84000 { + compatible = "qcom,geni-spi"; + reg = <0 0xc84000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi18_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c19: i2c@c88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c88000 0 0x4000>; @@ -1232,6 +1471,21 @@ status = "disabled"; }; + spi19: spi@c88000 { + compatible = "qcom,geni-spi"; + reg = <0 0xc88000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi19_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c13: i2c@c8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c8c000 0 0x4000>; @@ -1245,6 +1499,21 @@ status = "disabled"; }; + spi13: spi@c8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0xc8c000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c14: i2c@c90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c90000 0 0x4000>; @@ -1258,6 +1527,21 @@ status = "disabled"; }; + spi14: spi@c90000 { + compatible = "qcom,geni-spi"; + reg = <0 0xc90000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c15: i2c@c94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c94000 0 0x4000>; @@ -1270,6 +1554,21 @@ #size-cells = <0>; status = "disabled"; }; + + spi15: spi@c94000 { + compatible = "qcom,geni-spi"; + reg = <0 0xc94000 0 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; config_noc: interconnect@1500000 { @@ -1616,6 +1915,13 @@ }; }; + qup_spi0_default: qup-spi0-default { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c1_default: qup-i2c1-default { mux { pins = "gpio114", "gpio115"; @@ -1629,6 +1935,13 @@ }; }; + qup_spi1_default: qup-spi1-default { + pins = "gpio114", "gpio115", "gpio116", "gpio117"; + function = "qup1"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c2_default: qup-i2c2-default { mux { pins = "gpio126", "gpio127"; @@ -1642,6 +1955,13 @@ }; }; + qup_spi2_default: qup-spi2-default { + pins = "gpio126", "gpio127", "gpio128", "gpio129"; + function = "qup2"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c3_default: qup-i2c3-default { mux { pins = "gpio144", "gpio145"; @@ -1655,6 +1975,13 @@ }; }; + qup_spi3_default: qup-spi3-default { + pins = "gpio144", "gpio145", "gpio146", "gpio147"; + function = "qup3"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c4_default: qup-i2c4-default { mux { pins = "gpio51", "gpio52"; @@ -1668,6 +1995,13 @@ }; }; + qup_spi4_default: qup-spi4-default { + pins = "gpio51", "gpio52", "gpio53", "gpio54"; + function = "qup4"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c5_default: qup-i2c5-default { mux { pins = "gpio121", "gpio122"; @@ -1681,6 +2015,13 @@ }; }; + qup_spi5_default: qup-spi5-default { + pins = "gpio119", "gpio120", "gpio121", "gpio122"; + function = "qup5"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c6_default: qup-i2c6-default { mux { pins = "gpio6", "gpio7"; @@ -1694,6 +2035,13 @@ }; }; + qup_spi6_default: qup-spi6_default { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "qup6"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c7_default: qup-i2c7-default { mux { pins = "gpio98", "gpio99"; @@ -1707,6 +2055,13 @@ }; }; + qup_spi7_default: qup-spi7_default { + pins = "gpio98", "gpio99", "gpio100", "gpio101"; + function = "qup7"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c8_default: qup-i2c8-default { mux { pins = "gpio88", "gpio89"; @@ -1720,6 +2075,13 @@ }; }; + qup_spi8_default: qup-spi8-default { + pins = "gpio88", "gpio89", "gpio90", "gpio91"; + function = "qup8"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c9_default: qup-i2c9-default { mux { pins = "gpio39", "gpio40"; @@ -1733,6 +2095,13 @@ }; }; + qup_spi9_default: qup-spi9-default { + pins = "gpio39", "gpio40", "gpio41", "gpio42"; + function = "qup9"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c10_default: qup-i2c10-default { mux { pins = "gpio9", "gpio10"; @@ -1746,6 +2115,13 @@ }; }; + qup_spi10_default: qup-spi10-default { + pins = "gpio9", "gpio10", "gpio11", "gpio12"; + function = "qup10"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c11_default: qup-i2c11-default { mux { pins = "gpio94", "gpio95"; @@ -1759,6 +2135,13 @@ }; }; + qup_spi11_default: qup-spi11-default { + pins = "gpio92", "gpio93", "gpio94", "gpio95"; + function = "qup11"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c12_default: qup-i2c12-default { mux { pins = "gpio83", "gpio84"; @@ -1772,6 +2155,13 @@ }; }; + qup_spi12_default: qup-spi12-default { + pins = "gpio83", "gpio84", "gpio85", "gpio86"; + function = "qup12"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c13_default: qup-i2c13-default { mux { pins = "gpio43", "gpio44"; @@ -1785,6 +2175,13 @@ }; }; + qup_spi13_default: qup-spi13-default { + pins = "gpio43", "gpio44", "gpio45", "gpio46"; + function = "qup13"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c14_default: qup-i2c14-default { mux { pins = "gpio47", "gpio48"; @@ -1798,6 +2195,13 @@ }; }; + qup_spi14_default: qup-spi14-default { + pins = "gpio47", "gpio48", "gpio49", "gpio50"; + function = "qup14"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c15_default: qup-i2c15-default { mux { pins = "gpio27", "gpio28"; @@ -1811,6 +2215,13 @@ }; }; + qup_spi15_default: qup-spi15-default { + pins = "gpio27", "gpio28", "gpio29", "gpio30"; + function = "qup15"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c16_default: qup-i2c16-default { mux { pins = "gpio86", "gpio85"; @@ -1824,6 +2235,13 @@ }; }; + qup_spi16_default: qup-spi16-default { + pins = "gpio83", "gpio84", "gpio85", "gpio86"; + function = "qup16"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c17_default: qup-i2c17-default { mux { pins = "gpio55", "gpio56"; @@ -1837,6 +2255,13 @@ }; }; + qup_spi17_default: qup-spi17-default { + pins = "gpio55", "gpio56", "gpio57", "gpio58"; + function = "qup17"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c18_default: qup-i2c18-default { mux { pins = "gpio23", "gpio24"; @@ -1850,6 +2275,13 @@ }; }; + qup_spi18_default: qup-spi18-default { + pins = "gpio23", "gpio24", "gpio25", "gpio26"; + function = "qup18"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c19_default: qup-i2c19-default { mux { pins = "gpio57", "gpio58"; @@ -1862,6 +2294,13 @@ bias-disable; }; }; + + qup_spi19_default: qup-spi19-default { + pins = "gpio55", "gpio56", "gpio57", "gpio58"; + function = "qup19"; + drive-strength = <6>; + bias-disable; + }; }; remoteproc_mpss: remoteproc@4080000 { -- cgit v1.2.3 From f70c6dc013c1842b0ca640926cf74e7b99cec33d Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Tue, 27 Apr 2021 14:07:12 +0100 Subject: arm64: dts: qcom: pm8150b: Add DTS node for PMIC VBUS booster Add the required DTS node for the USB VBUS output regulator, which is available on PM8150B. This will provide the VBUS source to connected peripherals. Cc: Rob Herring Signed-off-by: Wesley Cheng Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20210427130712.2005456-3-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index b21e56a46145..058cc5107c75 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -53,6 +53,12 @@ status = "disabled"; }; + pm8150b_vbus: dcdc@1100 { + compatible = "qcom,pm8150b-vbus-reg"; + status = "disabled"; + reg = <0x1100>; + }; + pm8150b_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; -- cgit v1.2.3 From 095bbdd9a5c302ca4636c8fc92216ac008f46491 Mon Sep 17 00:00:00 2001 From: Selvam Sathappan Periakaruppan Date: Wed, 5 May 2021 12:18:32 +0300 Subject: arm64: dts: qcom: ipq6018: Add pcie support ipq6018 has 1 pcie gen3 port. This patch adds the support for the same. The GICv2m reg property value is a guess based on similar SoCs description in downstream Codeaurora kernel. It appears to work. Signed-off-by: Selvam Sathappan Periakaruppan [baruch: adjust #address-cells/#size-cells; drop unsupported property; increase parf registers size] Signed-off-by: Baruch Siach Link: https://lore.kernel.org/r/0f733656666fa6adaa8e196419ebcfd04677d173.1620203062.git.baruch@tkos.co.il Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 99 +++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 66da336894eb..d2fe58e0eb7a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -384,6 +384,105 @@ interrupts = ; }; + pcie_phy: phy@84000 { + compatible = "qcom,ipq6018-qmp-pcie-phy"; + reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + pcie_phy0: lane@84200 { + reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ + <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ + <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + + pcie0: pci@20000000 { + compatible = "qcom,pcie-ipq6018"; + reg = <0x0 0x20000000 0x0 0xf1d>, + <0x0 0x20000f20 0x0 0xa8>, + <0x0 0x20001000 0x0 0x1000>, + <0x0 0x80000 0x0 0x4000>, + <0x0 0x20100000 0x0 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pcie_phy0>; + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x20200000 0 0x20200000 + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x20220000 0 0x20220000 + 0 0xfde0000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 75 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc PCIE0_RCHNG_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; + + status = "disabled"; + }; + watchdog@b017000 { compatible = "qcom,kpss-wdt"; interrupts = ; -- cgit v1.2.3 From 06bf656eda23affbb7e0117d41733b80bb1bf8f6 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Thu, 13 May 2021 14:13:09 -0400 Subject: arm64: dts: qcom: sm8350: add qupv3_id_1/i2c13 nodes Add the qupv3_id_1 node and the i2c13 child node used for i2c devices connected to gpio0/gpio1. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20210513181309.12491-2-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 15df4a77d6b4..7eb18ff03bd6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -481,6 +481,31 @@ }; }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_default_state>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; @@ -813,6 +838,19 @@ function = "qup3"; }; }; + + qup_i2c13_default_state: qup-i2c13-default-state { + mux { + pins = "gpio0", "gpio1"; + function = "qup13"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; rng: rng@10d3000 { -- cgit v1.2.3 From f9e2df82d2904dd498450784808426b88d2240de Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 18 May 2021 20:16:17 +0200 Subject: arm64: dts: qcom: ipq8074: add crypto nodes IPQ8074 uses Qualcom QCE crypto engine v5.1 which is already supported. So simply add nodes for its DMA and QCE itself. Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20210518181618.3238386-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 0baf17fbafce..b0b0ab68db2b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -204,6 +204,30 @@ status = "disabled"; }; + cryptobam: dma@704000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; + interrupts = ; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely = <1>; + status = "disabled"; + }; + + crypto: crypto@73a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x0073a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq8074-pinctrl"; reg = <0x01000000 0x300000>; -- cgit v1.2.3 From f26f6a5e41dc4bda3329e0bbe7e50f1f027bcea5 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 18 May 2021 20:16:18 +0200 Subject: arm64: dts: qcom: ipq8074: add PRNG node PRNG insinde of IPQ8074 is already supported, so simply add the node for it. Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20210518181618.3238386-2-robimarko@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index b0b0ab68db2b..72b4264d5caa 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -204,6 +204,14 @@ status = "disabled"; }; + prng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + status = "disabled"; + }; + cryptobam: dma@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00704000 0x20000>; -- cgit v1.2.3 From ab428819ee3f8a97c3a2a272029c681896f9508a Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 11 Jun 2021 10:17:47 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: Move panel under the bridge chip Putting the panel under the bridge chip (under the aux-bus node) allows the panel driver to get access to the DP AUX bus, enabling all sorts of fabulous new features. While we're at this, get rid of a level of hierarchy for the panel node. It doesn't need "ports / port" and can just have a "port" child. For Linux, this patch has a hard requirement on the patches adding DP AUX bus support to the ti-sn65dsi86 bridge chip driver. See the patch ("drm/bridge: ti-sn65dsi86: Add support for the DP AUX bus"). Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Acked-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210611101711.v10.11.Ibdb7735fb1844561b902252215a69526a14f9abd@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 30 ++++++++++++++-------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 1c8c7bcd63df..0f2b3c00e434 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -255,21 +255,6 @@ #sound-dai-cells = <0>; }; - panel: panel { - /* Compatible will be filled in per-board */ - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; - - ports { - port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; - pwmleds { compatible = "pwm-leds"; keyboard_backlight: keyboard-backlight { @@ -679,6 +664,21 @@ edp_brij_i2c: &i2c2 { }; }; }; + + aux-bus { + panel: panel { + /* Compatible will be filled in per-board */ + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; }; }; -- cgit v1.2.3 From fc4f0273d4fba2c125141ef45474d253f6c28f3f Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 4 Aug 2021 16:02:11 -0500 Subject: arm64: dts: qcom: sc7280: add IPA information Add IPA-related nodes and definitions to "sc7280.dtsi", including the reserved memory area used for AP-based IPA firmware loading. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210804210214.1891755-2-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 11c1c20f4c79..f70ab3c5d08b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -69,6 +69,11 @@ no-map; reg = <0x0 0x80b00000 0x0 0x100000>; }; + + ipa_fw_mem: memory@8b700000 { + reg = <0 0x8b700000 0 0x10000>; + no-map; + }; }; cpus { @@ -581,6 +586,43 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ipa: ipa@1e40000 { + compatible = "qcom,sc7280-ipa"; + + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x482 0x0>; + reg = <0 0x1e40000 0 0x8000>, + <0 0x1e50000 0 0x4ad0>, + <0 0x1e04000 0 0x23000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, + <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; + interconnect-names = "memory", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex", "syscon"; reg = <0 0x01f40000 0 0x40000>; -- cgit v1.2.3 From 8dc7e3e5fe13c0a94ac6732eedb04db08418f4cc Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 4 Aug 2021 16:02:12 -0500 Subject: arm64: dts: qcom: sc7280: enable IPA for sc7280-idp Enable IPA for the SC7280 IDP, with the modem performing early initialization. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210804210214.1891755-3-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index ee76d96c5dbb..292c02877133 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -241,6 +241,11 @@ }; }; +&ipa { + status = "okay"; + modem-init; +}; + &pmk8350_vadc { pmk8350_die_temp { reg = ; -- cgit v1.2.3 From 310b266655a341e753a44a9f31836195b00f24c2 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 4 Aug 2021 16:02:13 -0500 Subject: arm64: dts: qcom: sc7180: define ipa_fw_mem node Define the reserved memory space used for IPA firmware for the Qualcomm SC7180 SoC. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210804210214.1891755-4-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index b1e8f5073aa9..88d2ecbb6a22 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -110,6 +110,11 @@ no-map; }; + ipa_fw_mem: memory@8b700000 { + reg = <0 0x8b700000 0 0x10000>; + no-map; + }; + rmtfs_mem: memory@94600000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x94600000 0x0 0x200000>; -- cgit v1.2.3 From 84173ca359787abd720d150d3d0d7edabf9db46c Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 4 Aug 2021 16:02:14 -0500 Subject: arm64: dts: qcom: sm8350: fix IPA interconnects There should only be two interconnects defined for IPA on the QUalcomm SM8350 SoC. The names should also match those specified by the IPA Device Tree binding. Fixes: f11d3e7da32e ("arm64: dts: qcom: sm8350: add IPA information") Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210804210214.1891755-5-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7eb18ff03bd6..e91cd8a5e535 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -691,12 +691,10 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>, - <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; - interconnect-names = "ipa_to_llcc", - "llcc_to_ebi1", - "appss_to_ipa"; + interconnect-names = "memory", + "config"; qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; -- cgit v1.2.3 From 97a5b73b7058206425e7ba465f4c7f6a81fb4888 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 4 Aug 2021 18:33:19 +0530 Subject: arm64: dts: qcom: sc7280-idp: Add device tree files for IDP2 Move all the common device tree bits for both sc7280 IDPs into a sc7280-idp.dtsi and create 2 different dts files (sc7280-idp.dts and sc7280-idp2.dts) in order to manage differences across the IDP SKU1 and SKU2 Boards. PMR735A is present on IDP board only and is not present on IDP2. Signed-off-by: Rajendra Nayak Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1628082199-17002-3-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dts | 328 +---------------------------- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 341 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 23 +++ 4 files changed, 367 insertions(+), 326 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp2.dts (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d4a59978c830..70516508be56 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -67,6 +67,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 292c02877133..64fc22aff33d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -7,17 +7,12 @@ /dts-v1/; -#include #include -#include -#include "sc7280.dtsi" -#include "pm7325.dtsi" +#include "sc7280-idp.dtsi" #include "pmr735a.dtsi" -#include "pm8350c.dtsi" -#include "pmk8350.dtsi" / { - model = "Qualcomm Technologies, Inc. sc7280 IDP platform"; + model = "Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform"; compatible = "qcom,sc7280-idp", "google,senor", "qcom,sc7280"; aliases { @@ -30,186 +25,6 @@ }; &apps_rsc { - pm7325-regulators { - compatible = "qcom,pm7325-rpmh-regulators"; - qcom,pmic-id = "b"; - - vreg_s1b_1p8: smps1 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_s7b_0p9: smps7 { - regulator-min-microvolt = <535000>; - regulator-max-microvolt = <1120000>; - }; - - vreg_s8b_1p2: smps8 { - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1500000>; - }; - - vreg_l1b_0p8: ldo1 { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <925000>; - }; - - vreg_l2b_3p0: ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - }; - - vreg_l6b_1p2: ldo6 { - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1260000>; - }; - - vreg_l7b_2p9: ldo7 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - }; - - vreg_l8b_0p9: ldo8 { - regulator-min-microvolt = <870000>; - regulator-max-microvolt = <970000>; - }; - - vreg_l9b_1p2: ldo9 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1304000>; - }; - - vreg_l11b_1p7: ldo11 { - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_l12b_0p8: ldo12 { - regulator-min-microvolt = <751000>; - regulator-max-microvolt = <824000>; - }; - - vreg_l13b_0p8: ldo13 { - regulator-min-microvolt = <530000>; - regulator-max-microvolt = <824000>; - }; - - vreg_l14b_1p2: ldo14 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1304000>; - }; - - vreg_l15b_0p8: ldo15 { - regulator-min-microvolt = <765000>; - regulator-max-microvolt = <1020000>; - }; - - vreg_l16b_1p2: ldo16 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - }; - - vreg_l17b_1p8: ldo17 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - }; - - vreg_l18b_1p8: ldo18 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_l19b_1p8: ldo19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - pm8350c-regulators { - compatible = "qcom,pm8350c-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_s1c_2p2: smps1 { - regulator-min-microvolt = <2190000>; - regulator-max-microvolt = <2210000>; - }; - - vreg_s9c_1p0: smps9 { - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - }; - - vreg_l1c_1p8: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1980000>; - }; - - vreg_l2c_1p8: ldo2 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - }; - - vreg_l3c_3p0: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3540000>; - }; - - vreg_l4c_1p8: ldo4 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_l5c_1p8: ldo5 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_l6c_2p9: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - vreg_l7c_3p0: ldo7 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3544000>; - }; - - vreg_l8c_1p8: ldo8 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_l9c_2p9: ldo9 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - }; - - vreg_l10c_0p8: ldo10 { - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1050000>; - }; - - vreg_l11c_2p8: ldo11 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3544000>; - }; - - vreg_l12c_1p8: ldo12 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_l13c_3p0: ldo13 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - }; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - }; - }; - pmr735a-regulators { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; @@ -247,148 +62,9 @@ }; &pmk8350_vadc { - pmk8350_die_temp { - reg = ; - label = "pmk8350_die_temp"; - qcom,pre-scaling = <1 1>; - }; - pmr735a_die_temp { reg = ; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; }; }; - -&qupv3_id_0 { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - - non-removable; - no-sd; - no-sdio; - - vmmc-supply = <&vreg_l7b_2p9>; - vqmmc-supply = <&vreg_l19b_1p8>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - - vmmc-supply = <&vreg_l9c_2p9>; - vqmmc-supply = <&vreg_l6c_2p9>; - - cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; -}; - -&uart5 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l10c_0p8>; - vdda33-supply = <&vreg_l2b_3p0>; - vdda18-supply = <&vreg_l1c_1p8>; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p8>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l10c_0p8>; - vdda33-supply = <&vreg_l2b_3p0>; - vdda18-supply = <&vreg_l1c_1p8>; -}; - -/* PINCTRL - additions to nodes defined in sc7280.dtsi */ - -&qup_uart5_default { - tx { - pins = "gpio46"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio47"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&sdc1_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - rclk { - bias-pull-down; - }; -}; - -&sdc2_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi new file mode 100644 index 000000000000..371a2a9dcf7a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 IDP board device tree source (common between SKU1 and SKU2) + * + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "sc7280.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +&apps_rsc { + pm7325-regulators { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_s1b_1p8: smps1 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p9: smps7 { + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p2: smps8 { + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1500000>; + }; + + vreg_l1b_0p8: ldo1 { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l6b_1p2: ldo6 { + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + vreg_l7b_2p9: ldo7 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l8b_0p9: ldo8 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + vreg_l9b_1p2: ldo9 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l11b_1p7: ldo11 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l12b_0p8: ldo12 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + vreg_l13b_0p8: ldo13 { + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + }; + + vreg_l14b_1p2: ldo14 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l15b_0p8: ldo15 { + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + }; + + vreg_l16b_1p2: ldo16 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + vreg_l17b_1p8: ldo17 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + vreg_l18b_1p8: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l19b_1p8: ldo19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pm8350c-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s1c_2p2: smps1 { + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_1p0: smps9 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + }; + + vreg_l2c_1p8: ldo2 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + vreg_l3c_3p0: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10c_0p8: ldo10 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + vreg_l11c_2p8: ldo11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l12c_1p8: ldo12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l13c_3p0: ldo13 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&ipa { + status = "okay"; + modem-init; +}; + +&pmk8350_vadc { + pmk8350_die_temp { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p9>; + vqmmc-supply = <&vreg_l19b_1p8>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + +&uart5 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p8>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ + +&qup_uart5_default { + tx { + pins = "gpio46"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio47"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&sdc1_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + bias-pull-down; + }; +}; + +&sdc2_on { + clk { + bias-disable; + drive-strength = <16>; + }; + + cmd { + bias-pull-up; + drive-strength = <10>; + }; + + data { + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts new file mode 100644 index 000000000000..1fc2addc8ab6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 IDP2 board device tree source + * + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sc7280-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform"; + compatible = "qcom,sc7280-idp2", "google,piglin", "qcom,sc7280"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; -- cgit v1.2.3 From b547b216228fde064e196838f695c2b0d6c110ae Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 10 Jul 2021 00:07:23 +0300 Subject: arm64: dts: qcom: sc7180: assign DSI clock source parents Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Link: https://lore.kernel.org/r/20210709210729.953114-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 88d2ecbb6a22..47b20ba69057 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2989,6 +2989,9 @@ "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7180_CX>; -- cgit v1.2.3 From 3289022b32985871cdb5e82d3473eafac6033869 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 10 Jul 2021 00:07:24 +0300 Subject: arm64: dts: qcom: sdm845: assign DSI clock source parents Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Link: https://lore.kernel.org/r/20210709210729.953114-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6bd05f62bb05..ff6bda15ae04 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4255,6 +4255,9 @@ "core", "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; @@ -4321,6 +4324,9 @@ "core", "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; -- cgit v1.2.3 From 77246d45d28f32fee3f92421aaca0e24c97ce6d1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 10 Jul 2021 00:07:25 +0300 Subject: arm64: dts: qcom: sdm845-mtp: assign DSI clock source parents Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Link: https://lore.kernel.org/r/20210709210729.953114-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 91ede9296aff..52dd7a858231 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -413,6 +413,9 @@ qcom,dual-dsi-mode; + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + ports { port@1 { endpoint { -- cgit v1.2.3 From 97ec669dfcfa22f8a595356ceb6ce46e7b4a82e9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 10 Jul 2021 00:07:26 +0300 Subject: arm64: dts: qcom: sm8250: assign DSI clock source parents Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Link: https://lore.kernel.org/r/20210709210729.953114-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c337c32918f6..8c15d9fed08f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2697,6 +2697,9 @@ "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; @@ -2767,6 +2770,9 @@ "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; -- cgit v1.2.3