From 72ea48610d43c59507d9ad39083d40085400ba12 Mon Sep 17 00:00:00 2001 From: Bintian Wang Date: Fri, 29 May 2015 10:08:38 +0800 Subject: clk: hi6220: Clock driver support for Hisilicon hi6220 SoC Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Bintian Wang Acked-by: Haojian Zhuang Reviewed-by: Zhangfei Gao Tested-by: Will Deacon Tested-by: Tyler Baker Tested-by: Kevin Hilman Signed-off-by: Michael Turquette --- drivers/clk/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/Kconfig') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9897f353bf1a..8ec04156717b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -150,6 +150,7 @@ config COMMON_CLK_CDCE706 ---help--- This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. +source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/qcom/Kconfig" endmenu -- cgit v1.2.3