From 7ebaa41047738d46fca6376b3f1765ef69c463c5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 30 Jun 2021 16:50:42 +0200 Subject: pinctrl: renesas: rcar: Avoid changing PUDn when disabling bias MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When disabling pin bias, there is no need to touch the LSI pin pull-up/down control register (PUDn), which selects between pull-up and pull-down. Just disabling the pull-up/down function through the LSI pin pull-enable register (PUENn) is sufficient. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/071ec644de2555da593a4531ef5d3e4d79cf997d.1625064076.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index bb488af29862..85cb78cfcfa6 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -898,17 +898,17 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, if (reg->puen) { enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) + if (bias != PIN_CONFIG_BIAS_DISABLE) { enable |= BIT(bit); - if (reg->pud) { - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); + if (reg->pud) { + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); - sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->pud, updown); + } } - sh_pfc_write(pfc, reg->puen, enable); } else { enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); -- cgit v1.2.3 From e9d66bdbc5abecaf705bf5a2f4f6279b9e313b0c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 30 Jun 2021 16:50:43 +0200 Subject: pinctrl: renesas: r8a77995: Add bias pinconf support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77995.c | 320 ++++++++++++++++++++++++++++++++- drivers/pinctrl/renesas/pinctrl.c | 2 +- drivers/pinctrl/renesas/sh_pfc.h | 3 + 3 files changed, 316 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index b479f87a3b23..c56e1e4c13b3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -14,16 +14,27 @@ #include #include +#include "core.h" #include "sh_pfc.h" -#define CPU_ALL_GP(fn, sfx) \ - PORT_GP_9(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_21(5, fn, sfx), \ - PORT_GP_14(6, fn, sfx) +#define CPU_ALL_GP(fn, sfx) \ + PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) /* * F_() : just information @@ -930,8 +941,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------- */ @@ -2834,6 +2854,214 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po return bit; } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */ + [ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */ + [ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */ + [ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */ + [ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */ + [ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */ + [ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */ + [ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */ + [ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */ + [ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */ + [10] = PIN_MLB_REF, /* MLB_REF */ + [11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */ + [12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */ + [13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */ + [14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */ + [15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */ + [16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */ + [17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */ + [18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */ + [19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */ + [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [22] = PIN_FSCLKST_N, /* FSCLKST# */ + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = PIN_TDI, /* TDI */ + [29] = PIN_TMS, /* TMS */ + [30] = PIN_TCK, /* TCK */ + [31] = PIN_TRST_N, /* TRST# */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */ + [ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */ + [ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */ + [ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */ + [ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */ + [ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */ + [ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */ + [ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */ + [ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */ + [ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */ + [10] = RCAR_GP_PIN(1, 31), /* QPOLB */ + [11] = RCAR_GP_PIN(1, 30), /* QPOLA */ + [12] = RCAR_GP_PIN(1, 29), /* DU_CDE */ + [13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */ + [14] = RCAR_GP_PIN(1, 27), /* DU_DISP */ + [15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */ + [16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */ + [17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */ + [18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */ + [19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */ + [20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */ + [21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */ + [22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */ + [23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */ + [24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */ + [25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */ + [26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */ + [27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */ + [28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */ + [29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */ + [30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */ + [31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */ + [ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */ + [ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */ + [ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */ + [ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */ + [ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */ + [ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */ + [ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */ + [ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */ + [ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */ + [10] = RCAR_GP_PIN(2, 31), /* NFCE# */ + [11] = RCAR_GP_PIN(2, 30), /* NFCLE */ + [12] = RCAR_GP_PIN(2, 29), /* NFALE */ + [13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */ + [14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */ + [15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */ + [16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */ + [17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */ + [18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */ + [19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */ + [20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */ + [21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */ + [22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */ + [23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */ + [24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */ + [25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */ + [26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */ + [27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */ + [28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */ + [29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */ + [30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */ + [31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */ + [ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */ + [ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */ + [ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */ + [ 4] = RCAR_GP_PIN(4, 27), /* TX2 */ + [ 5] = RCAR_GP_PIN(4, 26), /* RX2 */ + [ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */ + [ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */ + [ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */ + [ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */ + [10] = RCAR_GP_PIN(4, 21), /* TX0_A */ + [11] = RCAR_GP_PIN(4, 20), /* RX0_A */ + [12] = RCAR_GP_PIN(4, 19), /* SCK0_A */ + [13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */ + [14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */ + [15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */ + [16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */ + [17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */ + [18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */ + [19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */ + [20] = RCAR_GP_PIN(4, 11), /* SDA1 */ + [21] = RCAR_GP_PIN(4, 10), /* SCL1 */ + [22] = RCAR_GP_PIN(4, 9), /* SDA0 */ + [23] = RCAR_GP_PIN(4, 8), /* SCL0 */ + [24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */ + [25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */ + [26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */ + [27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */ + [28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */ + [29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */ + [30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */ + [31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */ + [ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */ + [ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */ + [ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */ + [ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */ + [ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */ + [ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */ + [ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */ + [ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */ + [ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */ + [10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */ + [11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */ + [12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */ + [13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */ + [14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */ + [15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */ + [16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */ + [17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */ + [18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */ + [19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */ + [20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */ + [21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */ + [22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */ + [23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */ + [24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */ + [25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */ + [26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */ + [27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */ + [28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */ + [29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */ + [30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */ + [31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) { + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */ + [30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */ + [31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */ + } }, + { /* sentinel */ } +}; + enum ioctrl_regs { TDSELCTRL, }; @@ -2843,8 +3071,83 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; +static const struct pinmux_bias_reg * +r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *puen_bit, unsigned int *pud_bit) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = rcar_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return reg; + + *puen_bit = bit; + + /* NFWE# and NFRE# use different bit positions in PUD2 */ + switch (pin) { + case RCAR_GP_PIN(3, 0): /* NFRE# */ + *pud_bit = 7; + break; + + case RCAR_GP_PIN(3, 1): /* NFWE# */ + *pud_bit = 8; + break; + + default: + *pud_bit = bit; + break; + } + + return reg; +} + +static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int puen_bit, pud_bit; + + reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + unsigned int puen_bit, pud_bit; + u32 enable, updown; + + reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit); + if (!reg) + return; + + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) { + enable |= BIT(puen_bit); + + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(pud_bit); + + sh_pfc_write(pfc, reg->pud, updown); + } + sh_pfc_write(pfc, reg->puen, enable); +} + static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, + .get_bias = r8a77995_pinmux_get_bias, + .set_bias = r8a77995_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77995_pinmux_info = { @@ -2862,6 +3165,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 85cb78cfcfa6..f3eecb20c086 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -841,7 +841,7 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) return pinctrl_enable(pmx->pctl); } -static const struct pinmux_bias_reg * +const struct pinmux_bias_reg * rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, unsigned int *bit) { diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 320898861c4b..bf9822ef7e8c 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -781,6 +781,9 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; /* * Bias helpers */ +const struct pinmux_bias_reg * +rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *bit); unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); -- cgit v1.2.3 From 41353ae7a17ba63118ef364896309df3e3824390 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 24 Jun 2021 21:17:41 +0200 Subject: pinctrl: qcom: Add MDM9607 pinctrl driver Add a pinctrl driver to allow for managing SoC pins. Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210624191743.617073-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-mdm9607.c | 1087 ++++++++++++++++++++++++++++++++ 3 files changed, 1096 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-mdm9607.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2f51b4f99393..6a151f3c1e3b 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -88,6 +88,14 @@ config PINCTRL_MSM8960 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8960 platform. +config PINCTRL_MDM9607 + tristate "Qualcomm 9607 pin controller driver" + depends on GPIOLIB && OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 9607 platform. + config PINCTRL_MDM9615 tristate "Qualcomm 9615 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index d696fe2789bb..3337860b4860 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o +obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c new file mode 100644 index 000000000000..d622b3df0fe7 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -0,0 +1,1087 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Konrad Dybcio + * + * based on pinctrl-msm8916.c + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc mdm9607_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "SDC1_CLK"), + PINCTRL_PIN(81, "SDC1_CMD"), + PINCTRL_PIN(82, "SDC1_DATA"), + PINCTRL_PIN(83, "SDC2_CLK"), + PINCTRL_PIN(84, "SDC2_CMD"), + PINCTRL_PIN(85, "SDC2_DATA"), + PINCTRL_PIN(86, "QDSD_CLK"), + PINCTRL_PIN(87, "QDSD_CMD"), + PINCTRL_PIN(88, "QDSD_DATA0"), + PINCTRL_PIN(89, "QDSD_DATA1"), + PINCTRL_PIN(90, "QDSD_DATA2"), + PINCTRL_PIN(91, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } + +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); + +static const unsigned int sdc1_clk_pins[] = { 80 }; +static const unsigned int sdc1_cmd_pins[] = { 81 }; +static const unsigned int sdc1_data_pins[] = { 82 }; +static const unsigned int sdc2_clk_pins[] = { 83 }; +static const unsigned int sdc2_cmd_pins[] = { 84 }; +static const unsigned int sdc2_data_pins[] = { 85 }; +static const unsigned int qdsd_clk_pins[] = { 86 }; +static const unsigned int qdsd_cmd_pins[] = { 87 }; +static const unsigned int qdsd_data0_pins[] = { 88 }; +static const unsigned int qdsd_data1_pins[] = { 89 }; +static const unsigned int qdsd_data2_pins[] = { 90 }; +static const unsigned int qdsd_data3_pins[] = { 91 }; + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum mdm9607_functions { + msm_mux_adsp_ext, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_combodac_to_gpio_native, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_atest_tsens, + msm_mux_backlight_en_b, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp1_spi, + msm_mux_blsp2_spi, + msm_mux_blsp3_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_codec_int, + msm_mux_codec_rst, + msm_mux_coex_uart, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_a_d_8_b, + msm_mux_ebi2_lcd, + msm_mux_ebi2_lcd_cs_n_b, + msm_mux_ebi2_lcd_te_b, + msm_mux_eth_irq, + msm_mux_eth_rst, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gmac_mdio, + msm_mux_gpio, + msm_mux_gsm0_tx, + msm_mux_lcd_rst, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_modem_tsync, + msm_mux_nav_ptp_pps_in_a, + msm_mux_nav_ptp_pps_in_b, + msm_mux_nav_tsync_out_a, + msm_mux_nav_tsync_out_b, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pri_mi2s_data0_a, + msm_mux_pri_mi2s_data1_a, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pri_mi2s_sck_a, + msm_mux_pri_mi2s_ws_a, + msm_mux_prng_rosc, + msm_mux_ptp_pps_out_a, + msm_mux_ptp_pps_out_b, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_rcm_marker1, + msm_mux_rcm_marker2, + msm_mux_sd_write, + msm_mux_sec_mi2s, + msm_mux_sensor_en, + msm_mux_sensor_int2, + msm_mux_sensor_int3, + msm_mux_sensor_rst, + msm_mux_ssbi1, + msm_mux_ssbi2, + msm_mux_touch_rst, + msm_mux_ts_int, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_wlan_en1, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; +static const char * const blsp_spi3_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_uart3_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; +static const char * const bimc_dte1_groups[] = { + "gpio1", "gpio24", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio2", "gpio3", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio2", +}; +static const char * const bimc_dte0_groups[] = { + "gpio2", "gpio15", +}; +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio6", +}; +static const char * const sensor_int2_groups[] = { + "gpio8", +}; +static const char * const blsp_spi5_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uart5_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ebi2_lcd_groups[] = { + "gpio8", "gpio11", "gpio74", "gpio78", +}; +static const char * const m_voc_groups[] = { + "gpio8", "gpio78", +}; +static const char * const sensor_int3_groups[] = { + "gpio9", +}; +static const char * const sensor_en_groups[] = { + "gpio10", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio10", "gpio11", +}; +static const char * const ebi2_a_groups[] = { + "gpio10", +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio46", + "gpio47", "gpio48", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio58", "gpio59", +}; +static const char * const sensor_rst_groups[] = { + "gpio11", +}; +static const char * const blsp2_spi_groups[] = { + "gpio11", "gpio13", "gpio77", +}; +static const char * const blsp_spi1_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const blsp_uart1_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const blsp_uim1_groups[] = { + "gpio12", "gpio13", +}; +static const char * const blsp3_spi_groups[] = { + "gpio12", "gpio26", "gpio76", +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio12", +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio14", "gpio15", +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio14", +}; +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const rcm_marker1_groups[] = { + "gpio18", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", +}; +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio18", +}; +static const char * const rcm_marker2_groups[] = { + "gpio19", +}; +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio19", +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const blsp_uart6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const pri_mi2s_ws_a_groups[] = { + "gpio20", +}; +static const char * const ebi2_lcd_te_b_groups[] = { + "gpio20", +}; +static const char * const blsp1_spi_groups[] = { + "gpio20", "gpio21", "gpio78", +}; +static const char * const backlight_en_b_groups[] = { + "gpio21", +}; +static const char * const pri_mi2s_data0_a_groups[] = { + "gpio21", +}; +static const char * const pri_mi2s_data1_a_groups[] = { + "gpio22", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const ebi2_a_d_8_b_groups[] = { + "gpio22", +}; +static const char * const pri_mi2s_sck_a_groups[] = { + "gpio23", +}; +static const char * const ebi2_lcd_cs_n_b_groups[] = { + "gpio23", +}; +static const char * const touch_rst_groups[] = { + "gpio24", +}; +static const char * const pri_mi2s_mclk_a_groups[] = { + "gpio24", +}; +static const char * const pwr_nav_enabled_a_groups[] = { + "gpio24", +}; +static const char * const ts_int_groups[] = { + "gpio25", +}; +static const char * const sd_write_groups[] = { + "gpio25", +}; +static const char * const pwr_crypto_enabled_a_groups[] = { + "gpio25", +}; +static const char * const codec_rst_groups[] = { + "gpio26", +}; +static const char * const adsp_ext_groups[] = { + "gpio26", +}; +static const char * const atest_combodac_to_gpio_native_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio41", "gpio45", "gpio49", "gpio50", + "gpio51", "gpio52", "gpio54", "gpio55", "gpio57", "gpio59", +}; +static const char * const uim2_data_groups[] = { + "gpio27", +}; +static const char * const gmac_mdio_groups[] = { + "gpio27", "gpio28", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio27", +}; +static const char * const uim2_clk_groups[] = { + "gpio28", +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio28", +}; +static const char * const eth_irq_groups[] = { + "gpio29", +}; +static const char * const uim2_reset_groups[] = { + "gpio29", +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio29", +}; +static const char * const eth_rst_groups[] = { + "gpio30", +}; +static const char * const uim2_present_groups[] = { + "gpio30", +}; +static const char * const prng_rosc_groups[] = { + "gpio30", +}; +static const char * const uim1_data_groups[] = { + "gpio31", +}; +static const char * const uim1_clk_groups[] = { + "gpio32", +}; +static const char * const uim1_reset_groups[] = { + "gpio33", +}; +static const char * const uim1_present_groups[] = { + "gpio34", +}; +static const char * const gcc_plltest_groups[] = { + "gpio34", "gpio35", +}; +static const char * const uim_batt_groups[] = { + "gpio35", +}; +static const char * const coex_uart_groups[] = { + "gpio36", "gpio37", +}; +static const char * const codec_int_groups[] = { + "gpio38", +}; +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio38", +}; +static const char * const atest_bbrx1_groups[] = { + "gpio39", +}; +static const char * const cri_trng0_groups[] = { + "gpio40", +}; +static const char * const atest_bbrx0_groups[] = { + "gpio40", +}; +static const char * const cri_trng_groups[] = { + "gpio42", +}; +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio44", +}; +static const char * const atest_gpsadc_dtest0_native_groups[] = { + "gpio44", +}; +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio45", +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio49", +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio50", +}; +static const char * const pa_indicator_groups[] = { + "gpio51", +}; +static const char * const modem_tsync_groups[] = { + "gpio53", +}; +static const char * const nav_tsync_out_a_groups[] = { + "gpio53", +}; +static const char * const nav_ptp_pps_in_a_groups[] = { + "gpio53", +}; +static const char * const ptp_pps_out_a_groups[] = { + "gpio53", +}; +static const char * const gsm0_tx_groups[] = { + "gpio55", +}; +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio56", +}; +static const char * const cri_trng1_groups[] = { + "gpio57", +}; +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio57", +}; +static const char * const ssbi1_groups[] = { + "gpio58", +}; +static const char * const atest_gpsadc_dtest1_native_groups[] = { + "gpio58", +}; +static const char * const ssbi2_groups[] = { + "gpio59", +}; +static const char * const atest_char3_groups[] = { + "gpio60", +}; +static const char * const atest_char2_groups[] = { + "gpio61", +}; +static const char * const atest_char1_groups[] = { + "gpio62", +}; +static const char * const atest_char0_groups[] = { + "gpio63", +}; +static const char * const atest_char_groups[] = { + "gpio64", +}; +static const char * const ebi0_wrcdc_groups[] = { + "gpio70", +}; +static const char * const ldo_update_groups[] = { + "gpio72", +}; +static const char * const gcc_tlmm_groups[] = { + "gpio72", +}; +static const char * const ldo_en_groups[] = { + "gpio73", +}; +static const char * const dbg_out_groups[] = { + "gpio73", +}; +static const char * const atest_tsens_groups[] = { + "gpio73", +}; +static const char * const lcd_rst_groups[] = { + "gpio74", +}; +static const char * const wlan_en1_groups[] = { + "gpio75", +}; +static const char * const nav_tsync_out_b_groups[] = { + "gpio75", +}; +static const char * const nav_ptp_pps_in_b_groups[] = { + "gpio75", +}; +static const char * const ptp_pps_out_b_groups[] = { + "gpio75", +}; +static const char * const pbs0_groups[] = { + "gpio76", +}; +static const char * const sec_mi2s_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; +static const char * const pwr_modem_enabled_a_groups[] = { + "gpio76", +}; +static const char * const pbs1_groups[] = { + "gpio77", +}; +static const char * const pwr_modem_enabled_b_groups[] = { + "gpio77", +}; +static const char * const pbs2_groups[] = { + "gpio78", +}; +static const char * const pwr_nav_enabled_b_groups[] = { + "gpio78", +}; +static const char * const pwr_crypto_enabled_b_groups[] = { + "gpio79", +}; + +static const struct msm_function mdm9607_functions[] = { + FUNCTION(adsp_ext), + FUNCTION(atest_bbrx0), + FUNCTION(atest_bbrx1), + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_combodac_to_gpio_native), + FUNCTION(atest_gpsadc_dtest0_native), + FUNCTION(atest_gpsadc_dtest1_native), + FUNCTION(atest_tsens), + FUNCTION(backlight_en_b), + FUNCTION(bimc_dte0), + FUNCTION(bimc_dte1), + FUNCTION(blsp1_spi), + FUNCTION(blsp2_spi), + FUNCTION(blsp3_spi), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(codec_int), + FUNCTION(codec_rst), + FUNCTION(coex_uart), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ebi0_wrcdc), + FUNCTION(ebi2_a), + FUNCTION(ebi2_a_d_8_b), + FUNCTION(ebi2_lcd), + FUNCTION(ebi2_lcd_cs_n_b), + FUNCTION(ebi2_lcd_te_b), + FUNCTION(eth_irq), + FUNCTION(eth_rst), + FUNCTION(gcc_gp1_clk_a), + FUNCTION(gcc_gp1_clk_b), + FUNCTION(gcc_gp2_clk_a), + FUNCTION(gcc_gp2_clk_b), + FUNCTION(gcc_gp3_clk_a), + FUNCTION(gcc_gp3_clk_b), + FUNCTION(gcc_plltest), + FUNCTION(gcc_tlmm), + FUNCTION(gmac_mdio), + FUNCTION(gpio), + FUNCTION(gsm0_tx), + FUNCTION(lcd_rst), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(m_voc), + FUNCTION(modem_tsync), + FUNCTION(nav_ptp_pps_in_a), + FUNCTION(nav_ptp_pps_in_b), + FUNCTION(nav_tsync_out_a), + FUNCTION(nav_tsync_out_b), + FUNCTION(pa_indicator), + FUNCTION(pbs0), + FUNCTION(pbs1), + FUNCTION(pbs2), + FUNCTION(pri_mi2s_data0_a), + FUNCTION(pri_mi2s_data1_a), + FUNCTION(pri_mi2s_mclk_a), + FUNCTION(pri_mi2s_sck_a), + FUNCTION(pri_mi2s_ws_a), + FUNCTION(prng_rosc), + FUNCTION(ptp_pps_out_a), + FUNCTION(ptp_pps_out_b), + FUNCTION(pwr_crypto_enabled_a), + FUNCTION(pwr_crypto_enabled_b), + FUNCTION(pwr_modem_enabled_a), + FUNCTION(pwr_modem_enabled_b), + FUNCTION(pwr_nav_enabled_a), + FUNCTION(pwr_nav_enabled_b), + FUNCTION(qdss_cti_trig_in_a0), + FUNCTION(qdss_cti_trig_in_a1), + FUNCTION(qdss_cti_trig_in_b0), + FUNCTION(qdss_cti_trig_in_b1), + FUNCTION(qdss_cti_trig_out_a0), + FUNCTION(qdss_cti_trig_out_a1), + FUNCTION(qdss_cti_trig_out_b0), + FUNCTION(qdss_cti_trig_out_b1), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_tracedata_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(rcm_marker1), + FUNCTION(rcm_marker2), + FUNCTION(sd_write), + FUNCTION(sec_mi2s), + FUNCTION(sensor_en), + FUNCTION(sensor_int2), + FUNCTION(sensor_int3), + FUNCTION(sensor_rst), + FUNCTION(ssbi1), + FUNCTION(ssbi2), + FUNCTION(touch_rst), + FUNCTION(ts_int), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(uim_batt), + FUNCTION(wlan_en1) +}; + +static const struct msm_pingroup mdm9607_groups[] = { + PINGROUP(0, blsp_uart3, blsp_spi3, _, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(1, blsp_uart3, blsp_spi3, _, _, _, _, _, qdss_tracedata_a, bimc_dte1), + PINGROUP(2, blsp_uart3, blsp_i2c3, blsp_spi3, _, _, _, _, _, qdss_traceclk_a), + PINGROUP(3, blsp_uart3, blsp_i2c3, blsp_spi3, _, _, _, _, _, _), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _), + PINGROUP(8, blsp_spi5, blsp_uart5, ebi2_lcd, m_voc, _, _, _, _, _), + PINGROUP(9, blsp_spi5, blsp_uart5, _, _, _, _, _, _, _), + PINGROUP(10, blsp_spi5, blsp_i2c5, blsp_uart5, ebi2_a, _, _, qdss_tracedata_b, _, _), + PINGROUP(11, blsp_spi5, blsp_i2c5, blsp_uart5, blsp2_spi, ebi2_lcd, _, _, _, _), + PINGROUP(12, blsp_spi1, blsp_uart1, blsp_uim1, blsp3_spi, gcc_gp2_clk_b, _, _, _, _), + PINGROUP(13, blsp_spi1, blsp_uart1, blsp_uim1, blsp2_spi, gcc_gp3_clk_b, _, _, _, _), + PINGROUP(14, blsp_spi1, blsp_uart1, blsp_i2c1, gcc_gp1_clk_b, _, _, _, _, _), + PINGROUP(15, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), + PINGROUP(16, blsp_spi4, blsp_uart4, _, _, _, _, _, _, _), + PINGROUP(17, blsp_spi4, blsp_uart4, _, _, _, _, _, _, _), + PINGROUP(18, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(19, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(20, blsp_spi6, blsp_uart6, pri_mi2s_ws_a, ebi2_lcd_te_b, blsp1_spi, _, _, _, + qdss_tracedata_a), + PINGROUP(21, blsp_spi6, blsp_uart6, pri_mi2s_data0_a, blsp1_spi, _, _, _, _, _), + PINGROUP(22, blsp_spi6, blsp_uart6, pri_mi2s_data1_a, blsp_i2c6, ebi2_a_d_8_b, _, _, _, _), + PINGROUP(23, blsp_spi6, blsp_uart6, pri_mi2s_sck_a, blsp_i2c6, ebi2_lcd_cs_n_b, _, _, _, _), + PINGROUP(24, pri_mi2s_mclk_a, _, pwr_nav_enabled_a, _, _, _, _, qdss_tracedata_a, + bimc_dte1), + PINGROUP(25, sd_write, _, pwr_crypto_enabled_a, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(26, blsp3_spi, adsp_ext, _, qdss_tracedata_a, _, atest_combodac_to_gpio_native, _, + _, _), + PINGROUP(27, uim2_data, gmac_mdio, gcc_gp1_clk_a, _, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(28, uim2_clk, gmac_mdio, gcc_gp2_clk_a, _, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(29, uim2_reset, gcc_gp3_clk_a, _, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(30, uim2_present, prng_rosc, _, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(31, uim1_data, _, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(32, uim1_clk, _, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(33, uim1_reset, _, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(34, uim1_present, gcc_plltest, _, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(35, uim_batt, gcc_plltest, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(36, coex_uart, _, _, _, _, _, _, _, _), + PINGROUP(37, coex_uart, _, _, _, _, _, _, _, _), + PINGROUP(38, _, _, _, qdss_cti_trig_in_a0, _, _, _, _, _), + PINGROUP(39, _, _, _, qdss_tracedata_b, _, atest_bbrx1, _, _, _), + PINGROUP(40, _, cri_trng0, _, _, _, _, qdss_tracedata_b, _, atest_bbrx0), + PINGROUP(41, _, _, _, _, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _), + PINGROUP(42, _, cri_trng, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(43, _, _, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(44, _, _, qdss_cti_trig_in_b0, _, atest_gpsadc_dtest0_native, _, _, _, _), + PINGROUP(45, _, _, qdss_cti_trig_out_b0, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(46, _, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(47, _, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(48, _, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(49, _, _, qdss_tracectl_b, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(50, _, _, qdss_traceclk_b, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(51, _, pa_indicator, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(52, _, _, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _), + PINGROUP(53, _, modem_tsync, nav_tsync_out_a, nav_ptp_pps_in_a, ptp_pps_out_a, + qdss_tracedata_b, _, _, _), + PINGROUP(54, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(55, gsm0_tx, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(56, _, _, qdss_cti_trig_in_b1, _, _, _, _, _, _), + PINGROUP(57, _, cri_trng1, _, qdss_cti_trig_out_b1, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(58, _, ssbi1, _, qdss_tracedata_b, _, atest_gpsadc_dtest1_native, _, _, _), + PINGROUP(59, _, ssbi2, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _), + PINGROUP(60, atest_char3, _, _, _, _, _, _, _, _), + PINGROUP(61, atest_char2, _, _, _, _, _, _, _, _), + PINGROUP(62, atest_char1, _, _, _, _, _, _, _, _), + PINGROUP(63, atest_char0, _, _, _, _, _, _, _, _), + PINGROUP(64, atest_char, _, _, _, _, _, _, _, _), + PINGROUP(65, _, _, _, _, _, _, _, _, _), + PINGROUP(66, _, _, _, _, _, _, _, _, _), + PINGROUP(67, _, _, _, _, _, _, _, _, _), + PINGROUP(68, _, _, _, _, _, _, _, _, _), + PINGROUP(69, _, _, _, _, _, _, _, _, _), + PINGROUP(70, _, _, ebi0_wrcdc, _, _, _, _, _, _), + PINGROUP(71, _, _, _, _, _, _, _, _, _), + PINGROUP(72, ldo_update, _, gcc_tlmm, _, _, _, _, _, _), + PINGROUP(73, ldo_en, dbg_out, _, _, _, atest_tsens, _, _, _), + PINGROUP(74, ebi2_lcd, _, _, _, _, _, _, _, _), + PINGROUP(75, nav_tsync_out_b, nav_ptp_pps_in_b, ptp_pps_out_b, _, qdss_tracedata_a, _, _, _, + _), + PINGROUP(76, pbs0, sec_mi2s, blsp3_spi, pwr_modem_enabled_a, _, qdss_tracedata_a, _, _, _), + PINGROUP(77, pbs1, sec_mi2s, blsp2_spi, pwr_modem_enabled_b, _, qdss_tracedata_a, _, _, _), + PINGROUP(78, pbs2, sec_mi2s, blsp1_spi, ebi2_lcd, m_voc, pwr_nav_enabled_b, _, + qdss_tracedata_a, _), + PINGROUP(79, sec_mi2s, _, pwr_crypto_enabled_b, _, qdss_tracedata_a, _, _, _, _), + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_pinctrl_soc_data mdm9607_pinctrl = { + .pins = mdm9607_pins, + .npins = ARRAY_SIZE(mdm9607_pins), + .functions = mdm9607_functions, + .nfunctions = ARRAY_SIZE(mdm9607_functions), + .groups = mdm9607_groups, + .ngroups = ARRAY_SIZE(mdm9607_groups), + .ngpios = 80, +}; + +static int mdm9607_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &mdm9607_pinctrl); +} + +static const struct of_device_id mdm9607_pinctrl_of_match[] = { + { .compatible = "qcom,mdm9607-tlmm", }, + { } +}; + +static struct platform_driver mdm9607_pinctrl_driver = { + .driver = { + .name = "mdm9607-pinctrl", + .of_match_table = mdm9607_pinctrl_of_match, + }, + .probe = mdm9607_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init mdm9607_pinctrl_init(void) +{ + return platform_driver_register(&mdm9607_pinctrl_driver); +} +arch_initcall(mdm9607_pinctrl_init); + +static void __exit mdm9607_pinctrl_exit(void) +{ + platform_driver_unregister(&mdm9607_pinctrl_driver); +} +module_exit(mdm9607_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm mdm9607 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match); -- cgit v1.2.3 From 29d45a642d4ea8de7e89b57f856046df7c3b219f Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 24 Jun 2021 14:49:13 +0800 Subject: pinctrl: bcm2835: Replace BUG with BUG_ON The if condition followed by BUG can be replaced to BUG_ON which is more compact and formal in linux source. Signed-off-by: Jason Wang Acked-by: Florian Fainelli Link: https://lore.kernel.org/r/20210624064913.41788-1-wangborong@cdjrlc.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 2c87af1180c4..8440c722f6f8 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -416,8 +416,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc) } } /* This should not happen, every IRQ has a bank */ - if (i == BCM2835_NUM_IRQS) - BUG(); + BUG_ON(i == BCM2835_NUM_IRQS); chained_irq_enter(host_chip, desc); -- cgit v1.2.3 From baf8d6899b1e8906dc076ef26cc633e96a8bb0c3 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 19 Jul 2021 13:29:38 +0200 Subject: pinctrl: armada-37xx: Correct PWM pins definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Fixes: b835d6953009 ("pinctrl: armada-37xx: swap polarity on LED group") Signed-off-by: Marek Behún Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210719112938.27594-1-kabel@kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt index 38dc56a57760..ecec514b3155 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt @@ -43,19 +43,19 @@ group emmc_nb group pwm0 - pin 11 (GPIO1-11) - - functions pwm, gpio + - functions pwm, led, gpio group pwm1 - pin 12 - - functions pwm, gpio + - functions pwm, led, gpio group pwm2 - pin 13 - - functions pwm, gpio + - functions pwm, led, gpio group pwm3 - pin 14 - - functions pwm, gpio + - functions pwm, led, gpio group pmic1 - pin 7 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 5a68e242f6b3..5cb018f98800 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -167,10 +167,14 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), - PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"), - PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"), - PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"), - PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"), + PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3), + "pwm", "led"), + PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4), + "pwm", "led"), + PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5), + "pwm", "led"), + PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6), + "pwm", "led"), PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), @@ -184,10 +188,6 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 18, 2, "gpio", "uart"), - PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"), - PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"), - PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"), - PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"), }; static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { -- cgit v1.2.3 From 16b343e8e0ef7de5ce451427fafc9e2ea42f548f Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 7 Jun 2021 14:10:41 +0800 Subject: pinctrl: imx8ulp: Add pinctrl driver support Add i.MX8ULP pinctrl driver support. Signed-off-by: Anson Huang Signed-off-by: Jacky Bai Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/20210607061041.2654568-2-ping.bai@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx8ulp.c | 274 ++++++++++++++++++++++++++++ 3 files changed, 282 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8ulp.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index f294336430cc..21fa21c6547b 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -166,6 +166,13 @@ config PINCTRL_IMX8DXL help Say Y here to enable the imx8dxl pinctrl driver +config PINCTRL_IMX8ULP + tristate "IMX8ULP pinctrl driver" + depends on ARCH_MXC + select PINCTRL_IMX + help + Say Y here to enable the imx8ulp pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index e476cb671037..c44930b1b362 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o +obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c new file mode 100644 index 000000000000..c5db5dfcfcce --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx8ulp_pads { + IMX8ULP_PAD_PTD0 = 0, + IMX8ULP_PAD_PTD1, + IMX8ULP_PAD_PTD2, + IMX8ULP_PAD_PTD3, + IMX8ULP_PAD_PTD4, + IMX8ULP_PAD_PTD5, + IMX8ULP_PAD_PTD6, + IMX8ULP_PAD_PTD7, + IMX8ULP_PAD_PTD8, + IMX8ULP_PAD_PTD9, + IMX8ULP_PAD_PTD10, + IMX8ULP_PAD_PTD11, + IMX8ULP_PAD_PTD12, + IMX8ULP_PAD_PTD13, + IMX8ULP_PAD_PTD14, + IMX8ULP_PAD_PTD15, + IMX8ULP_PAD_PTD16, + IMX8ULP_PAD_PTD17, + IMX8ULP_PAD_PTD18, + IMX8ULP_PAD_PTD19, + IMX8ULP_PAD_PTD20, + IMX8ULP_PAD_PTD21, + IMX8ULP_PAD_PTD22, + IMX8ULP_PAD_PTD23, + IMX8ULP_PAD_RESERVE0, + IMX8ULP_PAD_RESERVE1, + IMX8ULP_PAD_RESERVE2, + IMX8ULP_PAD_RESERVE3, + IMX8ULP_PAD_RESERVE4, + IMX8ULP_PAD_RESERVE5, + IMX8ULP_PAD_RESERVE6, + IMX8ULP_PAD_RESERVE7, + IMX8ULP_PAD_PTE0, + IMX8ULP_PAD_PTE1, + IMX8ULP_PAD_PTE2, + IMX8ULP_PAD_PTE3, + IMX8ULP_PAD_PTE4, + IMX8ULP_PAD_PTE5, + IMX8ULP_PAD_PTE6, + IMX8ULP_PAD_PTE7, + IMX8ULP_PAD_PTE8, + IMX8ULP_PAD_PTE9, + IMX8ULP_PAD_PTE10, + IMX8ULP_PAD_PTE11, + IMX8ULP_PAD_PTE12, + IMX8ULP_PAD_PTE13, + IMX8ULP_PAD_PTE14, + IMX8ULP_PAD_PTE15, + IMX8ULP_PAD_PTE16, + IMX8ULP_PAD_PTE17, + IMX8ULP_PAD_PTE18, + IMX8ULP_PAD_PTE19, + IMX8ULP_PAD_PTE20, + IMX8ULP_PAD_PTE21, + IMX8ULP_PAD_PTE22, + IMX8ULP_PAD_PTE23, + IMX8ULP_PAD_RESERVE8, + IMX8ULP_PAD_RESERVE9, + IMX8ULP_PAD_RESERVE10, + IMX8ULP_PAD_RESERVE11, + IMX8ULP_PAD_RESERVE12, + IMX8ULP_PAD_RESERVE13, + IMX8ULP_PAD_RESERVE14, + IMX8ULP_PAD_RESERVE15, + IMX8ULP_PAD_PTF0, + IMX8ULP_PAD_PTF1, + IMX8ULP_PAD_PTF2, + IMX8ULP_PAD_PTF3, + IMX8ULP_PAD_PTF4, + IMX8ULP_PAD_PTF5, + IMX8ULP_PAD_PTF6, + IMX8ULP_PAD_PTF7, + IMX8ULP_PAD_PTF8, + IMX8ULP_PAD_PTF9, + IMX8ULP_PAD_PTF10, + IMX8ULP_PAD_PTF11, + IMX8ULP_PAD_PTF12, + IMX8ULP_PAD_PTF13, + IMX8ULP_PAD_PTF14, + IMX8ULP_PAD_PTF15, + IMX8ULP_PAD_PTF16, + IMX8ULP_PAD_PTF17, + IMX8ULP_PAD_PTF18, + IMX8ULP_PAD_PTF19, + IMX8ULP_PAD_PTF20, + IMX8ULP_PAD_PTF21, + IMX8ULP_PAD_PTF22, + IMX8ULP_PAD_PTF23, + IMX8ULP_PAD_PTF24, + IMX8ULP_PAD_PTF25, + IMX8ULP_PAD_PTF26, + IMX8ULP_PAD_PTF27, + IMX8ULP_PAD_PTF28, + IMX8ULP_PAD_PTF29, + IMX8ULP_PAD_PTF30, + IMX8ULP_PAD_PTF31, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx8ulp_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14), + IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30), + IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31), +}; + +#define BM_OBE_ENABLED BIT(17) +#define BM_IBE_ENABLED BIT(16) +#define BM_MUX_MODE 0xf00 +#define BP_MUX_MODE 8 + +static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, bool input) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pin_reg *pin_reg; + u32 reg; + + reg = readl(ipctl->base + pin_reg->mux_reg); + if (input) + reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED; + else + reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED; + writel(reg, ipctl->base + pin_reg->mux_reg); + + return 0; +} + +static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = { + .pins = imx8ulp_pinctrl_pads, + .npins = ARRAY_SIZE(imx8ulp_pinctrl_pads), + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, + .gpio_set_direction = imx8ulp_pmx_gpio_set_direction, + .mux_mask = BM_MUX_MODE, + .mux_shift = BP_MUX_MODE, +}; + +static const struct of_device_id imx8ulp_pinctrl_of_match[] = { + { .compatible = "fsl,imx8ulp-iomuxc1", }, + { /* sentinel */ } +}; + +static int imx8ulp_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info); +} + +static struct platform_driver imx8ulp_pinctrl_driver = { + .driver = { + .name = "imx8ulp-pinctrl", + .of_match_table = imx8ulp_pinctrl_of_match, + .suppress_bind_attrs = true, + }, + .probe = imx8ulp_pinctrl_probe, +}; + +static int __init imx8ulp_pinctrl_init(void) +{ + return platform_driver_register(&imx8ulp_pinctrl_driver); +} +arch_initcall(imx8ulp_pinctrl_init); + +MODULE_AUTHOR("Jacky Bai "); +MODULE_DESCRIPTION("NXP i.MX8ULP pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 1ac1f6459d1e4bddd541949019b871ccfb3f4e6e Mon Sep 17 00:00:00 2001 From: kernel test robot Date: Sat, 26 Jun 2021 13:15:50 +0800 Subject: pinctrl: mediatek: fix platform_no_drv_owner.cocci warnings drivers/pinctrl/mediatek/pinctrl-mt8365.c:488:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC") CC: Fabien Parent Reported-by: kernel test robot Signed-off-by: kernel test robot Link: https://lore.kernel.org/r/20210626051550.GA37544@d0c207d51ce8 Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 22c33c3cb581..79b1fee5a1eb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -485,7 +485,6 @@ static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pinctrl_probe, .driver = { .name = "mediatek-mt8365-pinctrl", - .owner = THIS_MODULE, .of_match_table = mt8365_pctrl_match, .pm = &mtk_eint_pm_ops, }, -- cgit v1.2.3 From 4afc2a0c62a372a923cfb06182af387425489b7c Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 29 Jun 2021 18:04:06 +0530 Subject: pinctrl: qcom/pinctrl-spmi-gpio: Arrange compatibles alphabetically Arrange the compatibles inside qcom pinctrl-spmi gpio driver alphabetically. Cc: Linus Walleij Cc: Bjorn Andersson Reviewed-by: Bjorn Andersson Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210629123407.82561-4-bhupesh.sharma@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 34 ++++++++++++++++---------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index a89d24a040af..5246ea09c295 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1104,23 +1104,15 @@ static int pmic_gpio_remove(struct platform_device *pdev) } static const struct of_device_id pmic_gpio_of_match[] = { - { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, - { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, - { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, - /* pm8950 has 8 GPIOs with holes on 3 */ - { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 }, - { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 }, - { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, - { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, - { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, - { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, - { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, - /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ - { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ { .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, /* pm8150b has 12 GPIOs with holes on 3, r and 7 */ @@ -1130,13 +1122,21 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, + { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, + /* pm8950 has 8 GPIOs with holes on 3 */ + { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, + { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, + { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, + { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 }, + { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, - { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, - { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, - { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, - { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, + /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ + { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, { }, -- cgit v1.2.3 From 79e2311c876c276566e3fb84ba33682eb540874b Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 29 Jun 2021 18:04:07 +0530 Subject: pinctrl: qcom/pinctrl-spmi-gpio: Add compatible for pmic-gpio on SA8155p-adp SA8155p-adp PMIC (PMM8155AU) exposes 10 GPIOs. Add support for the same in the pinctrl driver. Cc: Linus Walleij Cc: Bjorn Andersson Reviewed-by: Bjorn Andersson Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210629123407.82561-5-bhupesh.sharma@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 5246ea09c295..bbea3499178e 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1133,6 +1133,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ -- cgit v1.2.3 From af0ca06f8781499bd889658b47df75ee2da8ca8f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 23 Jul 2021 17:32:42 -0300 Subject: pinctrl: imx8ulp: Initialize pin_reg The initialization of pin_reg is missing, causing the following build warning: drivers/pinctrl/freescale/pinctrl-imx8ulp.c:228:35: warning: 'pin_reg' is used uninitialized in this function [-Wuninitialized] Initialize pin_reg the same way as it is done on vf610 and imx7ulp to fix the problem. Fixes: 16b343e8e0ef ("pinctrl: imx8ulp: Add pinctrl driver support") Reported-by: kernel test robot Signed-off-by: Fabio Estevam Link: https://lore.kernel.org/r/20210723203242.88845-1-festevam@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx8ulp.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c index c5db5dfcfcce..f8572597a54e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c @@ -225,6 +225,10 @@ static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, const struct imx_pin_reg *pin_reg; u32 reg; + pin_reg = &ipctl->pin_regs[offset]; + if (pin_reg->mux_reg == -1) + return -EINVAL; + reg = readl(ipctl->base + pin_reg->mux_reg); if (input) reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED; -- cgit v1.2.3 From 91d1be9fb7d667ae136f05cc645276eb2c9fa40e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 19 Jul 2021 17:17:00 +0200 Subject: pinctrl: renesas: Fix pin control matching on R-Car H3e-2G As R-Car H3 ES1.x (R8A77950) and R-Car ES2.0+ (R8A77951) use the same compatible value, the pin control driver relies on soc_device_match() with soc_id = "r8a7795" and the (non)matching of revision = "ES1.*" to match with and distinguish between the two SoC variants. The corresponding entries in the normal of_match_table are present only to make the optional sanity checks work. The R-Car H3e-2G (R8A779M1) SoC is a different grading of the R-Car H3 ES3.0 (R8A77951) SoC. It uses the same compatible values for individual devices, but has an additional compatible value for the root node. When running on an R-Car H3e-2G SoC, soc_device_match() with soc_id = "r8a7795" does not return a match. Hence the pin control driver falls back to the normal of_match_table, and, as the R8A77950 entry is listed first, incorrectly uses the sub-driver for R-Car H3 ES1.x. Fix this by moving the entry for R8A77951 before the entry for R8A77950. Simplify sh_pfc_quirk_match() to only handle R-Car H3 ES1,x, as R-Car H3 ES2.0+ can now be matched using the normal of_match_table as well. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/6cdc5bfa424461105779b56f455387e03560cf66.1626707688.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 29 ++++++++++++----------------- drivers/pinctrl/renesas/sh_pfc.h | 4 ++-- 2 files changed, 14 insertions(+), 19 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 5ccc49b387f1..f2ab02225837 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -571,17 +571,21 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7794_pinmux_info, }, #endif -/* Both r8a7795 entries must be present to make sanity checks work */ -#ifdef CONFIG_PINCTRL_PFC_R8A77950 +/* + * Both r8a7795 entries must be present to make sanity checks work, but only + * the first entry is actually used. + * R-Car H3 ES1.x is matched using soc_device_match() instead. + */ +#ifdef CONFIG_PINCTRL_PFC_R8A77951 { .compatible = "renesas,pfc-r8a7795", - .data = &r8a77950_pinmux_info, + .data = &r8a77951_pinmux_info, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77951 +#ifdef CONFIG_PINCTRL_PFC_R8A77950 { .compatible = "renesas,pfc-r8a7795", - .data = &r8a77951_pinmux_info, + .data = &r8a77950_pinmux_info, }, #endif #ifdef CONFIG_PINCTRL_PFC_R8A77960 @@ -1085,26 +1089,20 @@ static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} #ifdef CONFIG_OF static const void *sh_pfc_quirk_match(void) { -#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \ - defined(CONFIG_PINCTRL_PFC_R8A77951) +#ifdef CONFIG_PINCTRL_PFC_R8A77950 const struct soc_device_attribute *match; static const struct soc_device_attribute quirks[] = { { .soc_id = "r8a7795", .revision = "ES1.*", .data = &r8a77950_pinmux_info, }, - { - .soc_id = "r8a7795", - .data = &r8a77951_pinmux_info, - }, - { /* sentinel */ } }; match = soc_device_match(quirks); if (match) - return match->data ?: ERR_PTR(-ENODEV); -#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */ + return match->data; +#endif /* CONFIG_PINCTRL_PFC_R8A77950 */ return NULL; } @@ -1119,9 +1117,6 @@ static int sh_pfc_probe(struct platform_device *pdev) #ifdef CONFIG_OF if (pdev->dev.of_node) { info = sh_pfc_quirk_match(); - if (IS_ERR(info)) - return PTR_ERR(info); - if (!info) info = of_device_get_match_data(&pdev->dev); } else diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index bf9822ef7e8c..2479b4fb9cf9 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -332,8 +332,8 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; -extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak; -extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak; +extern const struct sh_pfc_soc_info r8a77950_pinmux_info; +extern const struct sh_pfc_soc_info r8a77951_pinmux_info; extern const struct sh_pfc_soc_info r8a77960_pinmux_info; extern const struct sh_pfc_soc_info r8a77961_pinmux_info; extern const struct sh_pfc_soc_info r8a77965_pinmux_info; -- cgit v1.2.3 From ff128cdb7f3ddf237989c4ff925b42c9def33f7e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 13 Jul 2021 09:25:12 -0300 Subject: pinctrl: imx8mn: Constify imx_pinctrl_soc_info The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Signed-off-by: Fabio Estevam Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/20210713122513.3112941-1-festevam@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx8mn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mn.c b/drivers/pinctrl/freescale/pinctrl-imx8mn.c index 448a79eb4568..dbf89cfba477 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mn.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mn.c @@ -317,7 +317,7 @@ static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD), }; -static struct imx_pinctrl_soc_info imx8mn_pinctrl_info = { +static const struct imx_pinctrl_soc_info imx8mn_pinctrl_info = { .pins = imx8mn_pinctrl_pads, .npins = ARRAY_SIZE(imx8mn_pinctrl_pads), .gpr_compatible = "fsl,imx8mn-iomuxc-gpr", -- cgit v1.2.3 From b013dc8a02d9a604767d589feb6549e2da6a9133 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 13 Jul 2021 09:25:13 -0300 Subject: pinctrl: imx8qxp: Constify imx_pinctrl_soc_info The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Signed-off-by: Fabio Estevam Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/20210713122513.3112941-2-festevam@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c index 4f97813ba8b7..0a0acc0038d0 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -194,7 +194,7 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B), }; -static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = { +static const struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = { .pins = imx8qxp_pinctrl_pads, .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads), .flags = IMX_USE_SCU, -- cgit v1.2.3 From 2fefcf2400659f3f2d2c5ed87a4ceebde3dad7a8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Jul 2021 10:13:41 -0300 Subject: pinctrl: imx8dxl: Constify imx_pinctrl_soc_info The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Reported-by: Dong Aisheng Signed-off-by: Fabio Estevam Link: https://lore.kernel.org/r/20210716131341.3370620-1-festevam@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx8dxl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c index 041455c13d0d..f947b1d0d1aa 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -155,7 +155,7 @@ static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = { }; -static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = { +static const struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = { .pins = imx8dxl_pinctrl_pads, .npins = ARRAY_SIZE(imx8dxl_pinctrl_pads), .flags = IMX_USE_SCU, -- cgit v1.2.3 From 6ceb3c64063cd7b7155709f5ff67b85aa8a0e20b Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 21 Jul 2021 11:01:31 +0800 Subject: pinctrl: pistachio: Make it as an option So it will be avilable for generic MIPS kernel. -- Signed-off-by: Jiaxun Yang v3: Depend on OF as well Link: https://lore.kernel.org/r/20210721030134.10562-7-jiaxun.yang@flygoat.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f38f12801f18..eb981713b40d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -248,12 +248,15 @@ config PINCTRL_SX150X - 16 bits: sx1509q, sx1506q config PINCTRL_PISTACHIO - def_bool y if MACH_PISTACHIO + bool "IMG Pistachio SoC pinctrl driver" + depends on OF && (MIPS || COMPILE_TEST) depends on GPIOLIB select PINMUX select GENERIC_PINCONF select GPIOLIB_IRQCHIP select OF_GPIO + help + This support pinctrl and gpio driver for IMG Pistachio SoC. config PINCTRL_ST bool -- cgit v1.2.3 From cdd57325548af9803f0602914de16a8ddcb5bec0 Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Wed, 21 Jul 2021 17:22:32 +0530 Subject: pinctrl: pinctrl-zynq: Add support for 'power-source' parameter Add support for generic pin parameter 'power-source'. To maintain the backward compatibility, 'io-standard' parameter is still supported in the driver. Signed-off-by: Sai Krishna Potthuri Link: https://lore.kernel.org/r/1626868353-96475-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-zynq.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 5fb924a2eedd..a96af8a76a7a 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -1028,6 +1028,7 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, break; } case PIN_CONFIG_IOSTANDARD: + case PIN_CONFIG_POWER_SOURCE: arg = zynq_pinconf_iostd_get(reg); break; default: @@ -1078,6 +1079,7 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_IOSTANDARD: + case PIN_CONFIG_POWER_SOURCE: if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) { dev_warn(pctldev->dev, "unsupported IO standard '%u'\n", -- cgit v1.2.3 From 4b77f1dff5a67bbae9ec44ab97c1e354d893d975 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Fri, 23 Jul 2021 22:23:52 +0300 Subject: drivers: qcom: pinctrl: Add pinctrl driver for sm6115 Based on CAF implementation with egpio/wake_reg support removed. Similar function names were merged to reduce total number of functions. Signed-off-by: Iskren Chernev Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210723192352.546902-3-iskren.chernev@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6115.c | 923 ++++++++++++++++++++++++++++++++++ 3 files changed, 933 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm6115.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 6a151f3c1e3b..2bc620655550 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -264,6 +264,15 @@ config PINCTRL_SDX55 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX55 platform. +config PINCTRL_SM6115 + tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver" + depends on GPIOLIB && OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM6115 and SM4250 platforms. + config PINCTRL_SM6125 tristate "Qualcomm Technologies Inc SM6125 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 3337860b4860..7a12e8cd2fba 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o +obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c new file mode 100644 index 000000000000..b3a0161ca377 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -0,0 +1,923 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const char * const sm6115_tiles[] = { + "south", + "east", + "west" +}; + +enum { + SOUTH, + EAST, + WEST +}; + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = _tile, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = WEST, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sm6115_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "UFS_RESET"), + PINCTRL_PIN(114, "SDC1_RCLK"), + PINCTRL_PIN(115, "SDC1_CLK"), + PINCTRL_PIN(116, "SDC1_CMD"), + PINCTRL_PIN(117, "SDC1_DATA"), + PINCTRL_PIN(118, "SDC2_CLK"), + PINCTRL_PIN(119, "SDC2_CMD"), + PINCTRL_PIN(120, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); + +static const unsigned int ufs_reset_pins[] = { 113 }; +static const unsigned int sdc1_rclk_pins[] = { 114 }; +static const unsigned int sdc1_clk_pins[] = { 115 }; +static const unsigned int sdc1_cmd_pins[] = { 116 }; +static const unsigned int sdc1_data_pins[] = { 117 }; +static const unsigned int sdc2_clk_pins[] = { 118 }; +static const unsigned int sdc2_cmd_pins[] = { 119 }; +static const unsigned int sdc2_data_pins[] = { 120 }; + +enum sm6115_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer, + msm_mux_cri_trng, + msm_mux_dac_calib, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gsm0_tx, + msm_mux_gsm1_tx, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_out_0, + msm_mux_mdp_vsync_out_1, + msm_mux_mpm_pwr, + msm_mux_mss_lte, + msm_mux_m_voc, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pbs, + msm_mux_pbs_out, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb, + msm_mux_sd_write, + msm_mux_ssbi_wtr1, + msm_mux_tgu, + msm_mux_tsense_pwm, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux__, +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", +}; +static const char * const ddr_bist_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", + "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", + "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64", + "gpio102", "gpio103", "gpio104", "gpio105", +}; +static const char * const qdss_gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10", + "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91", + "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio109", "gpio110", +}; +static const char * const atest_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio100", "gpio101", +}; +static const char * const mpm_pwr_groups[] = { + "gpio1", +}; +static const char * const m_voc_groups[] = { + "gpio0", +}; +static const char * const dac_calib_groups[] = { + "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio80", "gpio81", + "gpio82", "gpio102", "gpio103", "gpio104", "gpio105" +}; +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio69", "gpio70", +}; +static const char * const cri_trng_groups[] = { + "gpio4", "gpio5", "gpio18", +}; +static const char * const qup2_groups[] = { + "gpio6", "gpio7", "gpio71", "gpio80", +}; +static const char * const qup3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const pbs_out_groups[] = { + "gpio8", "gpio9", "gpio52", +}; +static const char * const pll_bist_groups[] = { + "gpio8", "gpio9", +}; +static const char * const tsense_pwm_groups[] = { + "gpio8", +}; +static const char * const agera_pll_groups[] = { + "gpio10", "gpio11", +}; +static const char * const pbs_groups[] = { + "gpio10", "gpio11", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio47", "gpio48", "gpio87", + "gpio90", "gpio91", +}; +static const char * const qup4_groups[] = { + "gpio12", "gpio13", "gpio96", "gpio97", +}; +static const char * const tgu_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup5_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const sdc2_tb_groups[] = { + "gpio18", +}; +static const char * const sdc1_tb_groups[] = { + "gpio19", +}; +static const char * const cam_mclk_groups[] = { + "gpio20", "gpio21", "gpio27", "gpio28", +}; +static const char * const adsp_ext_groups[] = { + "gpio21", +}; +static const char * const cci_i2c_groups[] = { + "gpio22", "gpio23", "gpio29", "gpio30", +}; +static const char * const prng_rosc_groups[] = { + "gpio22", "gpio23", +}; +static const char * const cci_timer_groups[] = { + "gpio24", "gpio25", "gpio28", "gpio32", +}; +static const char * const gcc_gp1_groups[] = { + "gpio24", "gpio86", +}; +static const char * const cci_async_groups[] = { + "gpio25", +}; +static const char * const vsense_trigger_groups[] = { + "gpio26", +}; +static const char * const qdss_cti_groups[] = { + "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97", +}; +static const char * const gp_pdm0_groups[] = { + "gpio31", "gpio95", +}; +static const char * const gp_pdm1_groups[] = { + "gpio32", "gpio96", +}; +static const char * const gp_pdm2_groups[] = { + "gpio33", "gpio97", +}; +static const char * const nav_gpio_groups[] = { + "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106", + "gpio107", "gpio108", +}; +static const char * const vfr_1_groups[] = { + "gpio48", +}; +static const char * const pa_indicator_groups[] = { + "gpio49", +}; +static const char * const gsm1_tx_groups[] = { + "gpio53", +}; +static const char * const ssbi_wtr1_groups[] = { + "gpio59", "gpio60", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio62", +}; +static const char * const pll_reset_groups[] = { + "gpio63", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio63", "gpio64", +}; +static const char * const gsm0_tx_groups[] = { + "gpio64", +}; +static const char * const gcc_gp2_groups[] = { + "gpio69", "gpio107", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio69", "gpio70", +}; +static const char * const gcc_gp3_groups[] = { + "gpio70", "gpio106", +}; +static const char * const dbg_out_groups[] = { + "gpio71", +}; +static const char * const uim2_data_groups[] = { + "gpio72", +}; +static const char * const uim2_clk_groups[] = { + "gpio73", +}; +static const char * const uim2_reset_groups[] = { + "gpio74", +}; +static const char * const uim2_present_groups[] = { + "gpio75", +}; +static const char * const uim1_data_groups[] = { + "gpio76", +}; +static const char * const uim1_clk_groups[] = { + "gpio77", +}; +static const char * const uim1_reset_groups[] = { + "gpio78", +}; +static const char * const uim1_present_groups[] = { + "gpio79", +}; +static const char * const mdp_vsync_groups[] = { + "gpio81", "gpio96", "gpio97", +}; +static const char * const mdp_vsync_out_0_groups[] = { + "gpio81", +}; +static const char * const mdp_vsync_out_1_groups[] = { + "gpio81", +}; +static const char * const usb_phy_groups[] = { + "gpio89", +}; +static const char * const mss_lte_groups[] = { + "gpio90", "gpio91", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio94", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio95", +}; +static const char * const sd_write_groups[] = { + "gpio96", +}; +static const char * const jitter_bist_groups[] = { + "gpio96", "gpio97", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio102", "gpio103", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio104", "gpio105", +}; + +static const struct msm_function sm6115_functions[] = { + FUNCTION(adsp_ext), + FUNCTION(agera_pll), + FUNCTION(atest), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer), + FUNCTION(cri_trng), + FUNCTION(dac_calib), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gpio), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gsm0_tx), + FUNCTION(gsm1_tx), + FUNCTION(jitter_bist), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync_out_0), + FUNCTION(mdp_vsync_out_1), + FUNCTION(mpm_pwr), + FUNCTION(mss_lte), + FUNCTION(m_voc), + FUNCTION(nav_gpio), + FUNCTION(pa_indicator), + FUNCTION(pbs), + FUNCTION(pbs_out), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_reset), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(sdc1_tb), + FUNCTION(sdc2_tb), + FUNCTION(sd_write), + FUNCTION(ssbi_wtr1), + FUNCTION(tgu), + FUNCTION(tsense_pwm), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(usb_phy), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger), + FUNCTION(wlan1_adc0), + FUNCTION(wlan1_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm6115_groups[] = { + [0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), + [1] = PINGROUP(1, WEST, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), + [2] = PINGROUP(2, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), + [3] = PINGROUP(3, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), + [4] = PINGROUP(4, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), + [5] = PINGROUP(5, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), + [6] = PINGROUP(6, WEST, qup2, _, phase_flag, dac_calib, atest, _, _, _, _), + [7] = PINGROUP(7, WEST, qup2, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _), + [9] = PINGROUP(9, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _), + [10] = PINGROUP(10, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), + [11] = PINGROUP(11, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), + [12] = PINGROUP(12, WEST, qup4, tgu, _, _, _, _, _, _, _), + [13] = PINGROUP(13, WEST, qup4, tgu, _, _, _, _, _, _, _), + [14] = PINGROUP(14, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), + [15] = PINGROUP(15, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), + [16] = PINGROUP(16, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), + [17] = PINGROUP(17, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), + [18] = PINGROUP(18, EAST, sdc2_tb, cri_trng, pbs, qdss_gpio, _, _, _, _, _), + [19] = PINGROUP(19, EAST, sdc1_tb, pbs, qdss_gpio, _, _, _, _, _, _), + [20] = PINGROUP(20, EAST, cam_mclk, pbs, qdss_gpio, _, _, _, _, _, _), + [21] = PINGROUP(21, EAST, cam_mclk, adsp_ext, pbs, qdss_gpio, _, _, _, _, _), + [22] = PINGROUP(22, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [23] = PINGROUP(23, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [24] = PINGROUP(24, EAST, cci_timer, gcc_gp1, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [25] = PINGROUP(25, EAST, cci_async, cci_timer, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [26] = PINGROUP(26, EAST, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _), + [27] = PINGROUP(27, EAST, cam_mclk, qdss_cti, _, _, _, _, _, _, _), + [28] = PINGROUP(28, EAST, cam_mclk, cci_timer, qdss_cti, _, _, _, _, _, _), + [29] = PINGROUP(29, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), + [30] = PINGROUP(30, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), + [31] = PINGROUP(31, EAST, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _), + [32] = PINGROUP(32, EAST, cci_timer, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _), + [33] = PINGROUP(33, EAST, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _), + [34] = PINGROUP(34, EAST, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, EAST, _, phase_flag, _, _, _, _, _, _, _), + [36] = PINGROUP(36, EAST, _, phase_flag, _, _, _, _, _, _, _), + [37] = PINGROUP(37, EAST, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, EAST, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, EAST, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, EAST, _, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, EAST, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, EAST, _, nav_gpio, _, _, _, _, _, _, _), + [43] = PINGROUP(43, EAST, _, _, phase_flag, _, _, _, _, _, _), + [44] = PINGROUP(44, EAST, _, _, phase_flag, _, _, _, _, _, _), + [45] = PINGROUP(45, EAST, _, _, phase_flag, _, _, _, _, _, _), + [46] = PINGROUP(46, EAST, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, EAST, _, nav_gpio, pbs, qdss_gpio, _, _, _, _, _), + [48] = PINGROUP(48, EAST, _, vfr_1, _, pbs, qdss_gpio, _, _, _, _), + [49] = PINGROUP(49, EAST, _, pa_indicator, _, _, _, _, _, _, _), + [50] = PINGROUP(50, EAST, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, EAST, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, EAST, _, nav_gpio, pbs_out, _, _, _, _, _, _), + [53] = PINGROUP(53, EAST, _, gsm1_tx, _, _, _, _, _, _, _), + [54] = PINGROUP(54, EAST, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, EAST, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, EAST, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, EAST, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, EAST, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), + [60] = PINGROUP(60, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), + [61] = PINGROUP(61, EAST, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, EAST, _, pll_bypassnl, _, _, _, _, _, _, _), + [63] = PINGROUP(63, EAST, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _), + [64] = PINGROUP(64, EAST, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _), + [65] = PINGROUP(65, WEST, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, WEST, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, WEST, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, WEST, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, WEST, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _), + [70] = PINGROUP(70, WEST, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _), + [71] = PINGROUP(71, WEST, qup2, dbg_out, _, _, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, uim2_data, qdss_cti, _, _, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, uim2_clk, _, qdss_cti, _, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, uim2_reset, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, uim2_present, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, uim1_data, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, SOUTH, uim1_reset, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, WEST, qup2, dac_calib, _, _, _, _, _, _, _), + [81] = PINGROUP(81, WEST, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _), + [82] = PINGROUP(82, WEST, qup0, dac_calib, _, _, _, _, _, _, _), + [83] = PINGROUP(83, WEST, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, WEST, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, WEST, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, WEST, qup0, gcc_gp1, atest, _, _, _, _, _, _), + [87] = PINGROUP(87, EAST, pbs, qdss_gpio, _, _, _, _, _, _, _), + [88] = PINGROUP(88, EAST, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, WEST, usb_phy, atest, _, _, _, _, _, _, _), + [90] = PINGROUP(90, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), + [91] = PINGROUP(91, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), + [92] = PINGROUP(92, WEST, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, WEST, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, WEST, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _), + [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), + [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), + [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), + [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), + [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), + [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), + [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), + [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), + [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _), + [113] = UFS_RESET(ufs_reset, 0x78000), + [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0), + [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6), + [116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3), + [117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0), + [118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6), + [119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3), + [120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm6115_tlmm = { + .pins = sm6115_pins, + .npins = ARRAY_SIZE(sm6115_pins), + .functions = sm6115_functions, + .nfunctions = ARRAY_SIZE(sm6115_functions), + .groups = sm6115_groups, + .ngroups = ARRAY_SIZE(sm6115_groups), + .ngpios = 114, + .tiles = sm6115_tiles, + .ntiles = ARRAY_SIZE(sm6115_tiles), +}; + +static int sm6115_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm6115_tlmm); +} + +static const struct of_device_id sm6115_tlmm_of_match[] = { + { .compatible = "qcom,sm6115-tlmm", }, + { } +}; + +static struct platform_driver sm6115_tlmm_driver = { + .driver = { + .name = "sm6115-tlmm", + .of_match_table = sm6115_tlmm_of_match, + }, + .probe = sm6115_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm6115_tlmm_init(void) +{ + return platform_driver_register(&sm6115_tlmm_driver); +} +arch_initcall(sm6115_tlmm_init); + +static void __exit sm6115_tlmm_exit(void) +{ + platform_driver_unregister(&sm6115_tlmm_driver); +} +module_exit(sm6115_tlmm_exit); + +MODULE_DESCRIPTION("QTI sm6115 tlmm driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); -- cgit v1.2.3 From 70115558ab02fe8d28a6634350b3491a542aaa02 Mon Sep 17 00:00:00 2001 From: Jaehyoung Choi Date: Fri, 30 Jul 2021 22:29:05 +0300 Subject: pinctrl: samsung: Fix pinctrl bank pin count Commit 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") changes the order of GPIO and pinctrl registration: now pinctrl is registered before GPIO. That means gpio_chip->ngpio is not set when samsung_pinctrl_register() called, and one cannot rely on that value anymore. Use `pin_bank->nr_pins' instead of `pin_bank->gpio_chip.ngpio' to fix mentioned inconsistency. Fixes: 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") Signed-off-by: Jaehyoung Choi Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20210730192905.7173-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 376876bd6605..2975b4369f32 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -918,7 +918,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev, pin_bank->grange.pin_base = drvdata->pin_base + pin_bank->pin_base; pin_bank->grange.base = pin_bank->grange.pin_base; - pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; + pin_bank->grange.npins = pin_bank->nr_pins; pin_bank->grange.gc = &pin_bank->gpio_chip; pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); } -- cgit v1.2.3 From 182700f258531c75846cb0f070e847e8b4c457b2 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 28 Jun 2021 17:38:51 -0700 Subject: pinctrl: qcom: spmi-gpio: Add pmc8180 & pmc8180c The SC8180x platform comes with PMC8180 and PMC8180c, add support for the GPIO controller in these PMICs. Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210629003851.1787673-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 4 ++++ drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++ 2 files changed, 6 insertions(+) (limited to 'drivers/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 261a1d114253..48cc82d075e2 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -30,6 +30,8 @@ PMIC's from Qualcomm. "qcom,pm8994-gpio" "qcom,pm8998-gpio" "qcom,pma8084-gpio" + "qcom,pmc8180-gpio" + "qcom,pmc8180c-gpio" "qcom,pmi8950-gpio" "qcom,pmi8994-gpio" "qcom,pmi8998-gpio" @@ -122,6 +124,8 @@ to specify in a pin configuration subnode: gpio1-gpio22 for pm8994 gpio1-gpio26 for pm8998 gpio1-gpio22 for pma8084 + gpio1-gpio10 for pmc8180 + gpio1-gpio12 for pmc8180c gpio1-gpio2 for pmi8950 gpio1-gpio10 for pmi8994 gpio1-gpio4 for pmk8350 diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index bbea3499178e..98bf0e2a2a8d 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1115,10 +1115,12 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 }, /* pm8150b has 12 GPIOs with holes on 3, r and 7 */ { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, /* pm8150l has 12 GPIOs with holes on 7 */ { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, -- cgit v1.2.3 From d789a490d32fdf0465275e3607f8a3bc87d3f3ba Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Thu, 22 Jul 2021 11:39:29 +0800 Subject: pinctrl: single: Fix error return code in pcs_parse_bits_in_pinctrl_entry() Fix to return -ENOTSUPP instead of 0 when PCS_HAS_PINCONF is true, which is the same as that returned in pcs_parse_pinconf(). Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Reported-by: Hulk Robot Signed-off-by: Zhen Lei Link: https://lore.kernel.org/r/20210722033930.4034-2-thunder.leizhen@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index e3aa64798f7d..4fcae8458359 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1224,6 +1224,7 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, if (PCS_HAS_PINCONF) { dev_err(pcs->dev, "pinconf not supported\n"); + res = -ENOTSUPP; goto free_pingroups; } -- cgit v1.2.3 From 2ac48d0d486d9dbdcca2e6d945031541d880df3b Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Thu, 22 Jul 2021 11:39:30 +0800 Subject: pinctrl: single: Move test PCS_HAS_PINCONF in pcs_parse_bits_in_pinctrl_entry() to the beginning The value of pcs->flags is not overwritten in function pcs_parse_bits_in_pinctrl_entry() and its subfunctions, so moving this check to the beginning of the function eliminates unnecessary rollback operations. Signed-off-by: Zhen Lei Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20210722033930.4034-3-thunder.leizhen@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 4fcae8458359..d8b4dc40f3c6 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1115,7 +1115,7 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, { const char *name = "pinctrl-single,bits"; struct pcs_func_vals *vals; - int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; + int rows, *pins, found = 0, res = -ENOMEM, i, fsel; int npins_in_row; struct pcs_function *function = NULL; @@ -1125,6 +1125,11 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, return -EINVAL; } + if (PCS_HAS_PINCONF) { + dev_err(pcs->dev, "pinconf not supported\n"); + return -ENOTSUPP; + } + npins_in_row = pcs->width / pcs->bits_per_pin; vals = devm_kzalloc(pcs->dev, @@ -1212,30 +1217,19 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, goto free_pins; } - gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); - if (gsel < 0) { - res = gsel; + res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); + if (res < 0) goto free_function; - } (*map)->type = PIN_MAP_TYPE_MUX_GROUP; (*map)->data.mux.group = np->name; (*map)->data.mux.function = np->name; - if (PCS_HAS_PINCONF) { - dev_err(pcs->dev, "pinconf not supported\n"); - res = -ENOTSUPP; - goto free_pingroups; - } - *num_maps = 1; mutex_unlock(&pcs->mutex); return 0; -free_pingroups: - pinctrl_generic_remove_group(pcs->pctl, gsel); - *num_maps = 1; free_function: pinmux_generic_remove_function(pcs->pctl, fsel); free_pins: -- cgit v1.2.3 From a022135a19a1b2f8ee1f9e90d5d9de419543904c Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 23 Jul 2021 15:28:05 +0200 Subject: pinctrl: stm32: Add STM32MP135 SoC support STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO banks contain same features as STM32MP157 GPIO banks except that each GPIO line of the STM32MP135 can be secured. Signed-off-by: Alexandre Torgue Acked-by: Arnd Bergmann --- drivers/pinctrl/stm32/Kconfig | 6 + drivers/pinctrl/stm32/Makefile | 1 + drivers/pinctrl/stm32/pinctrl-stm32mp135.c | 1679 ++++++++++++++++++++++++++++ 3 files changed, 1686 insertions(+) create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp135.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index f36f29113370..d532f3c6f670 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -40,6 +40,12 @@ config PINCTRL_STM32H743 default MACH_STM32H743 select PINCTRL_STM32 +config PINCTRL_STM32MP135 + bool "STMicroelectronics STM32MP135 pin control" if COMPILE_TEST && !MACH_STM32MP13 + depends on OF && HAS_IOMEM + default MACH_STM32MP13 + select PINCTRL_STM32 + config PINCTRL_STM32MP157 bool "STMicroelectronics STM32MP157 pin control" if COMPILE_TEST && !MACH_STM32MP157 depends on OF && HAS_IOMEM diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index f7c56d4b941c..619629ee9944 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_STM32F469) += pinctrl-stm32f469.o obj-$(CONFIG_PINCTRL_STM32F746) += pinctrl-stm32f746.o obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o +obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp135.c b/drivers/pinctrl/stm32/pinctrl-stm32mp135.c new file mode 100644 index 000000000000..4ab03520c407 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32mp135.c @@ -0,0 +1,1679 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32mp135_pins[] = { + STM32_PIN( + PINCTRL_PIN(0, "PA0"), + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "TIM2_CH1"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(5, "TIM15_BKIN"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(9, "UART5_TX"), + STM32_FUNCTION(12, "ETH1_MII_CRS"), + STM32_FUNCTION(13, "ETH2_MII_CRS"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(1, "PA1"), + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(4, "LPTIM3_OUT"), + STM32_FUNCTION(5, "TIM15_CH1N"), + STM32_FUNCTION(7, "DFSDM1_CKIN0"), + STM32_FUNCTION(8, "USART2_RTS USART2_DE"), + STM32_FUNCTION(12, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(2, "PA2"), + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(4, "LPTIM4_OUT"), + STM32_FUNCTION(5, "TIM15_CH1"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(12, "ETH1_MDIO"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(3, "PA3"), + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(4, "LPTIM5_OUT"), + STM32_FUNCTION(5, "TIM15_CH2"), + STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(7, "SAI1_FS_B"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(12, "ETH1_MII_COL"), + STM32_FUNCTION(13, "ETH2_MII_COL"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(4, "PA4"), + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(3, "TIM5_ETR"), + STM32_FUNCTION(4, "USART2_CK"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "DFSDM1_CKIN1"), + STM32_FUNCTION(11, "ETH1_PPS_OUT"), + STM32_FUNCTION(12, "ETH2_PPS_OUT"), + STM32_FUNCTION(13, "SAI1_SCK_A"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(5, "PA5"), + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(3, "USART2_CK"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(5, "SAI1_D1"), + STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(11, "ETH1_PPS_OUT"), + STM32_FUNCTION(12, "ETH2_PPS_OUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(6, "PA6"), + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(5, "SAI2_CK2"), + STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(8, "USART1_CK"), + STM32_FUNCTION(9, "UART4_RTS UART4_DE"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(13, "SAI2_SCK_A"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(7, "PA7"), + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(5, "SAI2_D1"), + STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(8, "USART1_CTS USART1_NSS"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(12, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"), + STM32_FUNCTION(13, "SAI2_SD_A"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(8, "PA8"), + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(1, "MCO1"), + STM32_FUNCTION(3, "SAI2_MCLK_A"), + STM32_FUNCTION(4, "TIM8_BKIN2"), + STM32_FUNCTION(5, "I2C4_SDA"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(7, "SAI2_CK1"), + STM32_FUNCTION(8, "USART1_CK"), + STM32_FUNCTION(9, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(11, "OTG_HS_SOF"), + STM32_FUNCTION(12, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(9, "PA9"), + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(7, "DFSDM1_DATIN0"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(11, "FMC_NWAIT"), + STM32_FUNCTION(14, "DCMIPP_D0"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(10, "PA10"), + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(11, "PA11"), + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(5, "I2C5_SCL"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(8, "USART1_CTS USART1_NSS"), + STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"), + STM32_FUNCTION(12, "ETH1_CLK"), + STM32_FUNCTION(14, "ETH2_CLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(12, "PA12"), + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(3, "SAI2_MCLK_A"), + STM32_FUNCTION(8, "USART1_RTS USART1_DE"), + STM32_FUNCTION(11, "TSC_G1_IO2"), + STM32_FUNCTION(12, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(14, "DCMIPP_D1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(13, "PA13"), + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(1, "DBTRGO"), + STM32_FUNCTION(2, "DBTRGI"), + STM32_FUNCTION(3, "MCO1"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(14, "PA14"), + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(1, "DBTRGO"), + STM32_FUNCTION(2, "DBTRGI"), + STM32_FUNCTION(3, "MCO2"), + STM32_FUNCTION(11, "OTG_HS_SOF"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(15, "PA15"), + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(1, "TRACED5"), + STM32_FUNCTION(2, "TIM2_CH1"), + STM32_FUNCTION(6, "I2S4_MCK"), + STM32_FUNCTION(8, "UART4_RTS UART4_DE"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(10, "LCD_R0"), + STM32_FUNCTION(11, "TSC_G3_IO1"), + STM32_FUNCTION(12, "LCD_G7"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(14, "DCMIPP_D14"), + STM32_FUNCTION(15, "DCMIPP_D5"), + STM32_FUNCTION(16, "HDP5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(16, "PB0"), + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(5, "USART1_RX"), + STM32_FUNCTION(6, "I2S1_MCK"), + STM32_FUNCTION(7, "SAI2_FS_A"), + STM32_FUNCTION(8, "USART1_CK"), + STM32_FUNCTION(9, "UART4_CTS"), + STM32_FUNCTION(11, "SAI2_D2"), + STM32_FUNCTION(12, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(17, "PB1"), + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(7, "DFSDM1_DATIN1"), + STM32_FUNCTION(8, "UART4_RX"), + STM32_FUNCTION(12, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(18, "PB2"), + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(2, "RTC_OUT2"), + STM32_FUNCTION(3, "SAI1_D1"), + STM32_FUNCTION(6, "I2S_CKIN"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(10, "QUADSPI_BK1_NCS"), + STM32_FUNCTION(12, "ETH2_MDIO"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(19, "PB3"), + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(5, "SAI2_CK1"), + STM32_FUNCTION(6, "SPI4_NSS I2S4_WS"), + STM32_FUNCTION(9, "SDMMC1_D123DIR"), + STM32_FUNCTION(11, "SDMMC2_D2"), + STM32_FUNCTION(12, "LCD_R6"), + STM32_FUNCTION(13, "SAI2_MCLK_A"), + STM32_FUNCTION(14, "UART7_RX"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(20, "PB4"), + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(1, "TRACED14"), + STM32_FUNCTION(2, "TIM16_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(5, "SAI2_CK2"), + STM32_FUNCTION(6, "SPI4_SCK I2S4_CK"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(11, "SDMMC2_D3"), + STM32_FUNCTION(12, "LCD_G1"), + STM32_FUNCTION(13, "SAI2_SCK_A"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(21, "PB5"), + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(2, "TIM17_BKIN"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(7, "I2C4_SMBA"), + STM32_FUNCTION(9, "SDMMC1_CKIN"), + STM32_FUNCTION(10, "FDCAN2_RX"), + STM32_FUNCTION(12, "UART5_RX"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(22, "PB6"), + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(1, "TRACED6"), + STM32_FUNCTION(2, "TIM16_CH1N"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(5, "USART1_TX"), + STM32_FUNCTION(7, "SAI1_CK2"), + STM32_FUNCTION(8, "LCD_B6"), + STM32_FUNCTION(10, "QUADSPI_BK1_NCS"), + STM32_FUNCTION(11, "TSC_G1_IO4"), + STM32_FUNCTION(12, "ETH2_MDIO"), + STM32_FUNCTION(13, "FMC_NE3"), + STM32_FUNCTION(14, "DCMIPP_D5"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "HDP6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(23, "PB7"), + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(2, "TIM17_CH1N"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(4, "TSC_SYNC"), + STM32_FUNCTION(6, "I2S4_CK"), + STM32_FUNCTION(7, "I2C4_SDA"), + STM32_FUNCTION(11, "FMC_NCE2"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(14, "DCMIPP_D13"), + STM32_FUNCTION(15, "DCMIPP_PIXCLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(24, "PB8"), + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(2, "TIM16_CH1"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(6, "I2C3_SCL"), + STM32_FUNCTION(7, "DFSDM1_DATIN1"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(11, "SAI1_D1"), + STM32_FUNCTION(13, "FMC_D13 FMC_AD13"), + STM32_FUNCTION(14, "DCMIPP_D6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(25, "PB9"), + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(7, "I2C4_SDA"), + STM32_FUNCTION(10, "FDCAN1_TX"), + STM32_FUNCTION(11, "SDMMC2_D5"), + STM32_FUNCTION(12, "UART5_TX"), + STM32_FUNCTION(13, "SDMMC1_CDIR"), + STM32_FUNCTION(14, "LCD_DE"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(26, "PB10"), + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(4, "LPTIM2_IN1"), + STM32_FUNCTION(5, "I2C5_SMBA"), + STM32_FUNCTION(6, "SPI4_NSS I2S4_WS"), + STM32_FUNCTION(7, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(27, "PB11"), + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(4, "LPTIM1_OUT"), + STM32_FUNCTION(5, "I2C5_SMBA"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(12, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(28, "PB12"), + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(1, "TRACED10"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(7, "DFSDM1_DATIN1"), + STM32_FUNCTION(8, "UART7_RTS UART7_DE"), + STM32_FUNCTION(9, "USART3_RX"), + STM32_FUNCTION(12, "UART5_RX"), + STM32_FUNCTION(13, "SDMMC1_D5"), + STM32_FUNCTION(14, "LCD_R3"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(29, "PB13"), + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(5, "LPTIM2_OUT"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(7, "I2C4_SCL"), + STM32_FUNCTION(9, "SDMMC1_D123DIR"), + STM32_FUNCTION(10, "FDCAN2_TX"), + STM32_FUNCTION(12, "UART5_TX"), + STM32_FUNCTION(14, "LCD_CLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(30, "PB14"), + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM12_CH1"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(5, "USART1_TX"), + STM32_FUNCTION(11, "SDMMC2_D0"), + STM32_FUNCTION(12, "SDMMC1_D4"), + STM32_FUNCTION(14, "LCD_R0"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(31, "PB15"), + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(1, "RTC_REFIN"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM12_CH2"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(5, "SAI2_D2"), + STM32_FUNCTION(6, "SPI4_MOSI I2S4_SDO"), + STM32_FUNCTION(7, "DFSDM1_CKIN2"), + STM32_FUNCTION(8, "UART7_CTS"), + STM32_FUNCTION(9, "SDMMC1_CKIN"), + STM32_FUNCTION(11, "SDMMC2_D1"), + STM32_FUNCTION(13, "SAI2_FS_A"), + STM32_FUNCTION(14, "LCD_CLK"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(32, "PC0"), + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(3, "SAI1_SCK_A"), + STM32_FUNCTION(5, "SAI1_CK2"), + STM32_FUNCTION(6, "I2S1_MCK"), + STM32_FUNCTION(7, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(33, "PC1"), + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(4, "DFSDM1_DATIN0"), + STM32_FUNCTION(7, "SAI1_D3"), + STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RMII_CRS_DV"), + STM32_FUNCTION(12, "ETH1_RGMII_GTX_CLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(34, "PC2"), + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(2, "SPI5_NSS"), + STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "SAI2_MCLK_A"), + STM32_FUNCTION(8, "USART1_RTS USART1_DE"), + STM32_FUNCTION(11, "SAI2_CK1"), + STM32_FUNCTION(12, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(35, "PC3"), + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(3, "SAI1_CK1"), + STM32_FUNCTION(4, "DFSDM1_CKOUT"), + STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(7, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(9, "UART5_CTS"), + STM32_FUNCTION(11, "SAI1_MCLK_A"), + STM32_FUNCTION(12, "ETH1_MII_TX_CLK"), + STM32_FUNCTION(13, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(36, "PC4"), + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(3, "TIM3_ETR"), + STM32_FUNCTION(4, "DFSDM1_CKIN2"), + STM32_FUNCTION(5, "SAI1_D3"), + STM32_FUNCTION(6, "I2S1_MCK"), + STM32_FUNCTION(9, "UART5_RTS UART5_DE"), + STM32_FUNCTION(10, "SPDIFRX_IN2"), + STM32_FUNCTION(12, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"), + STM32_FUNCTION(13, "SAI2_D3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(37, "PC5"), + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(4, "DFSDM1_DATIN2"), + STM32_FUNCTION(5, "SAI2_D4"), + STM32_FUNCTION(6, "I2S_CKIN"), + STM32_FUNCTION(7, "SAI1_D4"), + STM32_FUNCTION(8, "USART2_CTS USART2_NSS"), + STM32_FUNCTION(10, "SPDIFRX_IN3"), + STM32_FUNCTION(12, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(38, "PC6"), + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(5, "DFSDM1_DATIN0"), + STM32_FUNCTION(6, "I2S3_MCK"), + STM32_FUNCTION(8, "USART6_TX"), + STM32_FUNCTION(9, "SDMMC1_D6"), + STM32_FUNCTION(10, "SDMMC2_D0DIR"), + STM32_FUNCTION(11, "SDMMC2_D6"), + STM32_FUNCTION(12, "LCD_B1"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "HDP2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(39, "PC7"), + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(7, "I2S2_MCK"), + STM32_FUNCTION(8, "USART6_RX"), + STM32_FUNCTION(9, "USART3_CTS"), + STM32_FUNCTION(10, "SDMMC2_CDIR"), + STM32_FUNCTION(11, "SDMMC2_D7"), + STM32_FUNCTION(12, "LCD_R1"), + STM32_FUNCTION(13, "SDMMC1_D7"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "HDP4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(40, "PC8"), + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(8, "USART6_CK"), + STM32_FUNCTION(9, "USART3_CTS"), + STM32_FUNCTION(11, "SAI2_FS_B"), + STM32_FUNCTION(12, "UART5_RTS UART5_DE"), + STM32_FUNCTION(13, "SDMMC1_D0"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(41, "PC9"), + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(9, "UART5_CTS"), + STM32_FUNCTION(10, "FDCAN1_TX"), + STM32_FUNCTION(13, "SDMMC1_D1"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(42, "PC10"), + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(6, "I2C1_SCL"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(11, "SAI2_MCLK_B"), + STM32_FUNCTION(13, "SDMMC1_D2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(43, "PC11"), + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(9, "UART5_RX"), + STM32_FUNCTION(11, "SAI2_SCK_B"), + STM32_FUNCTION(13, "SDMMC1_D3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(44, "PC12"), + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(11, "SAI2_SD_B"), + STM32_FUNCTION(13, "SDMMC1_CK"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(45, "PC13"), + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(46, "PC14"), + STM32_FUNCTION(0, "GPIOC14"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(47, "PC15"), + STM32_FUNCTION(0, "GPIOC15"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(48, "PD0"), + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(3, "SAI1_MCLK_A"), + STM32_FUNCTION(7, "SAI1_CK1"), + STM32_FUNCTION(10, "FDCAN1_RX"), + STM32_FUNCTION(13, "FMC_D2 FMC_AD2"), + STM32_FUNCTION(14, "DCMIPP_D1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(49, "PD1"), + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(5, "I2C5_SCL"), + STM32_FUNCTION(6, "SPI4_MOSI I2S4_SDO"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(10, "QUADSPI_BK1_NCS"), + STM32_FUNCTION(12, "LCD_B6"), + STM32_FUNCTION(13, "FMC_D3 FMC_AD3"), + STM32_FUNCTION(14, "DCMIPP_D13"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(50, "PD2"), + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(3, "TIM3_ETR"), + STM32_FUNCTION(5, "I2C1_SMBA"), + STM32_FUNCTION(6, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(7, "SAI2_D1"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(13, "SDMMC1_CMD"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(51, "PD3"), + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(3, "TIM2_CH1"), + STM32_FUNCTION(4, "USART2_CTS USART2_NSS"), + STM32_FUNCTION(5, "DFSDM1_CKOUT"), + STM32_FUNCTION(6, "I2C1_SDA"), + STM32_FUNCTION(7, "SAI1_D3"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "DCMIPP_D5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(52, "PD4"), + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(4, "USART2_RTS USART2_DE"), + STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(7, "DFSDM1_CKIN0"), + STM32_FUNCTION(10, "QUADSPI_CLK"), + STM32_FUNCTION(12, "LCD_R1"), + STM32_FUNCTION(13, "FMC_NOE"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(53, "PD5"), + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO0"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(14, "LCD_B0"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(54, "PD6"), + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(2, "TIM16_CH1N"), + STM32_FUNCTION(3, "SAI1_D1"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(12, "TSC_G2_IO1"), + STM32_FUNCTION(14, "DCMIPP_D4"), + STM32_FUNCTION(15, "DCMIPP_D0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(55, "PD7"), + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(1, "MCO1"), + STM32_FUNCTION(4, "USART2_CK"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(6, "I2C3_SDA"), + STM32_FUNCTION(10, "SPDIFRX_IN0"), + STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"), + STM32_FUNCTION(12, "QUADSPI_BK1_IO2"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(56, "PD8"), + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(4, "USART2_TX"), + STM32_FUNCTION(6, "I2S4_WS"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(11, "TSC_G1_IO3"), + STM32_FUNCTION(14, "DCMIPP_D9"), + STM32_FUNCTION(15, "DCMIPP_D3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(57, "PD9"), + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(4, "DFSDM1_DATIN3"), + STM32_FUNCTION(11, "SDMMC2_CDIR"), + STM32_FUNCTION(12, "LCD_B5"), + STM32_FUNCTION(13, "FMC_D14 FMC_AD14"), + STM32_FUNCTION(14, "LCD_CLK"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(58, "PD10"), + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(1, "RTC_REFIN"), + STM32_FUNCTION(5, "I2C5_SMBA"), + STM32_FUNCTION(6, "SPI4_NSS I2S4_WS"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(10, "LCD_G5"), + STM32_FUNCTION(11, "TSC_G2_IO2"), + STM32_FUNCTION(12, "LCD_B7"), + STM32_FUNCTION(13, "FMC_D15 FMC_AD15"), + STM32_FUNCTION(14, "DCMIPP_VSYNC"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(59, "PD11"), + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(4, "LPTIM2_IN2"), + STM32_FUNCTION(5, "I2C4_SMBA"), + STM32_FUNCTION(8, "USART3_CTS USART3_NSS"), + STM32_FUNCTION(9, "SPDIFRX_IN0"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO2"), + STM32_FUNCTION(11, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(12, "LCD_R7"), + STM32_FUNCTION(13, "FMC_CLE FMC_A16"), + STM32_FUNCTION(14, "UART7_RX"), + STM32_FUNCTION(15, "DCMIPP_D4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(60, "PD12"), + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(6, "I2C1_SCL"), + STM32_FUNCTION(8, "USART3_RTS USART3_DE"), + STM32_FUNCTION(13, "FMC_ALE FMC_A17"), + STM32_FUNCTION(14, "DCMIPP_D6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(61, "PD13"), + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(2, "LPTIM2_ETR"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(5, "SAI1_CK1"), + STM32_FUNCTION(7, "SAI1_MCLK_A"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO3"), + STM32_FUNCTION(11, "TSC_G2_IO4"), + STM32_FUNCTION(12, "QUADSPI_BK2_IO2"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(62, "PD14"), + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(9, "UART8_CTS"), + STM32_FUNCTION(13, "FMC_D0 FMC_AD0"), + STM32_FUNCTION(14, "DCMIPP_D8"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(63, "PD15"), + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(2, "USART2_RX"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(4, "DFSDM1_DATIN2"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO3"), + STM32_FUNCTION(13, "FMC_D1 FMC_AD1"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(64, "PE0"), + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(7, "DCMIPP_D12"), + STM32_FUNCTION(9, "UART8_RX"), + STM32_FUNCTION(10, "FDCAN2_RX"), + STM32_FUNCTION(11, "TSC_G4_IO1"), + STM32_FUNCTION(12, "LCD_B1"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(14, "DCMIPP_D1"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(65, "PE1"), + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(4, "TSC_G2_IO3"), + STM32_FUNCTION(9, "UART8_TX"), + STM32_FUNCTION(10, "LCD_HSYNC"), + STM32_FUNCTION(12, "LCD_R4"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "DCMIPP_D3"), + STM32_FUNCTION(15, "DCMIPP_D12"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(66, "PE2"), + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(2, "TIM2_ETR"), + STM32_FUNCTION(4, "TSC_G5_IO1"), + STM32_FUNCTION(5, "I2C4_SCL"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(7, "SAI1_FS_B"), + STM32_FUNCTION(8, "USART6_RTS USART6_DE"), + STM32_FUNCTION(10, "SPDIFRX_IN1"), + STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(67, "PE3"), + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACED11"), + STM32_FUNCTION(3, "SAI2_D4"), + STM32_FUNCTION(5, "TIM15_BKIN"), + STM32_FUNCTION(6, "SPI4_MISO I2S4_SDI"), + STM32_FUNCTION(9, "USART3_RTS USART3_DE"), + STM32_FUNCTION(10, "FDCAN1_RX"), + STM32_FUNCTION(11, "SDMMC2_CK"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(68, "PE4"), + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(2, "SPI5_MISO"), + STM32_FUNCTION(3, "SAI1_D2"), + STM32_FUNCTION(4, "DFSDM1_DATIN3"), + STM32_FUNCTION(5, "TIM15_CH1N"), + STM32_FUNCTION(6, "I2S_CKIN"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(8, "UART7_RTS UART7_DE"), + STM32_FUNCTION(9, "UART8_TX"), + STM32_FUNCTION(10, "QUADSPI_BK2_NCS"), + STM32_FUNCTION(11, "FMC_NCE2"), + STM32_FUNCTION(12, "TSC_G1_IO1"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(14, "DCMIPP_D3"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(69, "PE5"), + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(3, "SAI2_SCK_B"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(5, "TIM15_CH1"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(70, "PE6"), + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(1, "MCO2"), + STM32_FUNCTION(2, "TIM1_BKIN2"), + STM32_FUNCTION(3, "SAI2_SCK_B"), + STM32_FUNCTION(5, "TIM15_CH2"), + STM32_FUNCTION(6, "I2C3_SMBA"), + STM32_FUNCTION(7, "SAI1_SCK_B"), + STM32_FUNCTION(9, "UART4_RTS UART4_DE"), + STM32_FUNCTION(12, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "DCMIPP_D7"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(71, "PE7"), + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(5, "LPTIM2_IN1"), + STM32_FUNCTION(9, "UART5_TX"), + STM32_FUNCTION(13, "FMC_D4 FMC_AD4"), + STM32_FUNCTION(14, "LCD_B3"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(72, "PE8"), + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(4, "DFSDM1_CKIN2"), + STM32_FUNCTION(6, "I2C1_SDA"), + STM32_FUNCTION(8, "UART7_TX"), + STM32_FUNCTION(13, "FMC_D5 FMC_AD5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(73, "PE9"), + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO1"), + STM32_FUNCTION(12, "LCD_HSYNC"), + STM32_FUNCTION(13, "FMC_D6 FMC_AD6"), + STM32_FUNCTION(14, "DCMIPP_D7"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "HDP3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(74, "PE10"), + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(8, "UART7_RX"), + STM32_FUNCTION(10, "FDCAN1_TX"), + STM32_FUNCTION(13, "FMC_D7 FMC_AD7"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(75, "PE11"), + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(3, "USART2_CTS USART2_NSS"), + STM32_FUNCTION(5, "SAI1_D2"), + STM32_FUNCTION(6, "SPI4_MOSI I2S4_SDO"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(8, "USART6_CK"), + STM32_FUNCTION(10, "LCD_R0"), + STM32_FUNCTION(11, "ETH2_MII_TX_ER"), + STM32_FUNCTION(12, "ETH1_MII_TX_ER"), + STM32_FUNCTION(13, "FMC_D8 FMC_AD8"), + STM32_FUNCTION(14, "DCMIPP_D10"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(76, "PE12"), + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(6, "SPI4_SCK I2S4_CK"), + STM32_FUNCTION(9, "UART8_RTS UART8_DE"), + STM32_FUNCTION(10, "LCD_VSYNC"), + STM32_FUNCTION(11, "TSC_G3_IO2"), + STM32_FUNCTION(12, "LCD_G4"), + STM32_FUNCTION(13, "FMC_D9 FMC_AD9"), + STM32_FUNCTION(14, "DCMIPP_D11"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "HDP4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(77, "PE13"), + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(5, "I2C5_SDA"), + STM32_FUNCTION(6, "SPI4_MISO I2S4_SDI"), + STM32_FUNCTION(12, "LCD_B1"), + STM32_FUNCTION(13, "FMC_D10 FMC_AD10"), + STM32_FUNCTION(14, "DCMIPP_D4"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(78, "PE14"), + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(5, "SAI1_D4"), + STM32_FUNCTION(9, "UART8_RTS UART8_DE"), + STM32_FUNCTION(10, "QUADSPI_BK1_NCS"), + STM32_FUNCTION(11, "QUADSPI_BK2_IO2"), + STM32_FUNCTION(13, "FMC_D11 FMC_AD11"), + STM32_FUNCTION(14, "DCMIPP_D7"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(79, "PE15"), + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(2, "TIM2_ETR"), + STM32_FUNCTION(3, "TIM1_BKIN"), + STM32_FUNCTION(4, "USART2_CTS USART2_NSS"), + STM32_FUNCTION(7, "I2C4_SCL"), + STM32_FUNCTION(13, "FMC_D12 FMC_AD12"), + STM32_FUNCTION(14, "DCMIPP_D10"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "HDP7"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(80, "PF0"), + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(1, "TRACED13"), + STM32_FUNCTION(4, "DFSDM1_CKOUT"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(11, "SDMMC2_D4"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(81, "PF1"), + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(14, "LCD_B7"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "HDP7"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(82, "PF2"), + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(7, "DFSDM1_CKIN1"), + STM32_FUNCTION(8, "USART6_CK"), + STM32_FUNCTION(10, "SDMMC2_D0DIR"), + STM32_FUNCTION(12, "SDMMC1_D0DIR"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(14, "LCD_G4"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(83, "PF3"), + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(4, "LPTIM2_IN2"), + STM32_FUNCTION(5, "I2C5_SDA"), + STM32_FUNCTION(6, "SPI4_MISO I2S4_SDI"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(84, "PF4"), + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(4, "USART2_RX"), + STM32_FUNCTION(11, "TSC_G3_IO3"), + STM32_FUNCTION(12, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(14, "DCMIPP_D4"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(85, "PF5"), + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(1, "TRACED12"), + STM32_FUNCTION(5, "DFSDM1_CKIN0"), + STM32_FUNCTION(6, "I2C1_SMBA"), + STM32_FUNCTION(10, "LCD_G0"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(14, "DCMIPP_D11"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(86, "PF6"), + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(2, "TIM16_CH1"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(8, "UART7_RX"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO2"), + STM32_FUNCTION(12, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"), + STM32_FUNCTION(14, "LCD_R7"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(87, "PF7"), + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(2, "TIM17_CH1"), + STM32_FUNCTION(8, "UART7_TX"), + STM32_FUNCTION(9, "UART4_CTS"), + STM32_FUNCTION(11, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(12, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(88, "PF8"), + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(2, "TIM16_CH1N"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(7, "SAI1_SCK_B"), + STM32_FUNCTION(8, "USART6_TX"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(11, "QUADSPI_BK1_IO0"), + STM32_FUNCTION(14, "DCMIPP_D15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(89, "PF9"), + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(2, "TIM17_CH1N"), + STM32_FUNCTION(3, "TIM1_CH1"), + STM32_FUNCTION(4, "DFSDM1_CKIN3"), + STM32_FUNCTION(7, "SAI1_D4"), + STM32_FUNCTION(8, "UART7_CTS"), + STM32_FUNCTION(9, "UART8_RX"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(11, "QUADSPI_BK1_IO1"), + STM32_FUNCTION(12, "QUADSPI_BK2_IO3"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(90, "PF10"), + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(2, "TIM16_BKIN"), + STM32_FUNCTION(3, "SAI1_D3"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(8, "USART6_RTS USART6_DE"), + STM32_FUNCTION(9, "UART7_RTS UART7_DE"), + STM32_FUNCTION(10, "QUADSPI_CLK"), + STM32_FUNCTION(14, "DCMIPP_HSYNC"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(91, "PF11"), + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(2, "USART2_TX"), + STM32_FUNCTION(3, "SAI1_D2"), + STM32_FUNCTION(4, "DFSDM1_CKIN3"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(13, "ETH2_MII_RX_ER"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(92, "PF12"), + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(11, "ETH1_MII_TX_ER"), + STM32_FUNCTION(12, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(93, "PF13"), + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(2, "TIM2_ETR"), + STM32_FUNCTION(3, "SAI1_MCLK_B"), + STM32_FUNCTION(7, "DFSDM1_DATIN3"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(9, "UART5_RX"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(94, "PF14"), + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(1, "JTCK SWCLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(95, "PF15"), + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(1, "JTMS SWDIO"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(96, "PG0"), + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(10, "FDCAN2_TX"), + STM32_FUNCTION(11, "TSC_G4_IO2"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(14, "DCMIPP_PIXCLK"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(97, "PG1"), + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(3, "TIM4_ETR"), + STM32_FUNCTION(4, "SAI2_FS_A"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(7, "SAI2_D2"), + STM32_FUNCTION(10, "FDCAN2_TX"), + STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(98, "PG2"), + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(2, "MCO2"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(11, "SAI2_MCLK_B"), + STM32_FUNCTION(12, "ETH1_MDC"), + STM32_FUNCTION(14, "DCMIPP_D1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(99, "PG3"), + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(4, "TIM8_BKIN2"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(7, "SAI2_SD_B"), + STM32_FUNCTION(10, "FDCAN2_RX"), + STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"), + STM32_FUNCTION(12, "ETH1_MDIO"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(14, "DCMIPP_D15"), + STM32_FUNCTION(15, "DCMIPP_D12"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(100, "PG4"), + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "TIM1_BKIN2"), + STM32_FUNCTION(5, "DFSDM1_CKIN3"), + STM32_FUNCTION(9, "USART3_RX"), + STM32_FUNCTION(11, "SDMMC2_D123DIR"), + STM32_FUNCTION(12, "LCD_VSYNC"), + STM32_FUNCTION(13, "FMC_A14"), + STM32_FUNCTION(14, "DCMIPP_D8"), + STM32_FUNCTION(15, "DCMIPP_D13"), + STM32_FUNCTION(16, "HDP1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(101, "PG5"), + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(2, "TIM17_CH1"), + STM32_FUNCTION(11, "ETH2_MDC"), + STM32_FUNCTION(12, "LCD_G4"), + STM32_FUNCTION(13, "FMC_A15"), + STM32_FUNCTION(14, "DCMIPP_VSYNC"), + STM32_FUNCTION(15, "DCMIPP_D3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(102, "PG6"), + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "TIM17_BKIN"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(4, "SAI2_D1"), + STM32_FUNCTION(5, "USART1_RX"), + STM32_FUNCTION(7, "SAI2_SD_A"), + STM32_FUNCTION(11, "SDMMC2_CMD"), + STM32_FUNCTION(12, "LCD_G0"), + STM32_FUNCTION(14, "LCD_DE"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "HDP3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(103, "PG7"), + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(1, "TRACED8"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(9, "UART7_CTS"), + STM32_FUNCTION(11, "SDMMC2_CKIN"), + STM32_FUNCTION(12, "LCD_R1"), + STM32_FUNCTION(14, "LCD_R5"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(104, "PG8"), + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(2, "TIM2_CH1"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(7, "SAI1_MCLK_B"), + STM32_FUNCTION(8, "LCD_B1"), + STM32_FUNCTION(9, "USART3_RTS USART3_DE"), + STM32_FUNCTION(10, "SPDIFRX_IN2"), + STM32_FUNCTION(11, "QUADSPI_BK2_IO2"), + STM32_FUNCTION(12, "QUADSPI_BK1_IO3"), + STM32_FUNCTION(13, "FMC_NE2"), + STM32_FUNCTION(14, "ETH2_CLK"), + STM32_FUNCTION(15, "DCMIPP_D6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(105, "PG9"), + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(1, "DBTRGO"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(8, "USART6_RX"), + STM32_FUNCTION(9, "SPDIFRX_IN3"), + STM32_FUNCTION(10, "FDCAN1_RX"), + STM32_FUNCTION(11, "FMC_NE2"), + STM32_FUNCTION(13, "FMC_NCE"), + STM32_FUNCTION(14, "DCMIPP_VSYNC"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(106, "PG10"), + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(9, "UART8_CTS"), + STM32_FUNCTION(10, "FDCAN1_TX"), + STM32_FUNCTION(11, "QUADSPI_BK2_IO1"), + STM32_FUNCTION(13, "FMC_NE3"), + STM32_FUNCTION(14, "DCMIPP_D2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(107, "PG11"), + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(5, "SAI2_D3"), + STM32_FUNCTION(6, "I2S2_MCK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(14, "DCMIPP_D14"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(108, "PG12"), + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(4, "TSC_G5_IO2"), + STM32_FUNCTION(5, "SAI2_SCK_A"), + STM32_FUNCTION(7, "SAI2_CK2"), + STM32_FUNCTION(8, "USART6_RTS USART6_DE"), + STM32_FUNCTION(9, "USART3_CTS"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(12, "ETH1_PHY_INTN"), + STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(109, "PG13"), + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(2, "LPTIM1_OUT"), + STM32_FUNCTION(8, "USART6_CTS USART6_NSS"), + STM32_FUNCTION(12, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(110, "PG14"), + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(7, "SAI2_D1"), + STM32_FUNCTION(8, "USART6_TX"), + STM32_FUNCTION(11, "SAI2_SD_A"), + STM32_FUNCTION(12, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(111, "PG15"), + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(8, "USART6_CTS USART6_NSS"), + STM32_FUNCTION(9, "UART7_CTS"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO1"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(12, "LCD_B4"), + STM32_FUNCTION(14, "DCMIPP_D10"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(112, "PH0"), + STM32_FUNCTION(0, "GPIOH0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(113, "PH1"), + STM32_FUNCTION(0, "GPIOH1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(114, "PH2"), + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(4, "TSC_G4_IO3"), + STM32_FUNCTION(7, "DCMIPP_D9"), + STM32_FUNCTION(8, "LCD_G1"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO0"), + STM32_FUNCTION(11, "ETH2_MII_CRS"), + STM32_FUNCTION(12, "ETH1_MII_CRS"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(14, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(115, "PH3"), + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO1"), + STM32_FUNCTION(11, "ETH1_MII_COL"), + STM32_FUNCTION(12, "LCD_R5"), + STM32_FUNCTION(13, "ETH2_MII_COL"), + STM32_FUNCTION(14, "QUADSPI_BK1_IO0"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(116, "PH4"), + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(1, "JTDI"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(117, "PH5"), + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(1, "JTDO"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(118, "PH6"), + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(3, "TIM12_CH1"), + STM32_FUNCTION(4, "USART2_CK"), + STM32_FUNCTION(5, "I2C5_SDA"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(10, "QUADSPI_BK1_IO2"), + STM32_FUNCTION(11, "ETH1_PHY_INTN"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(13, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"), + STM32_FUNCTION(14, "QUADSPI_BK1_NCS"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(119, "PH7"), + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(3, "SAI2_FS_B"), + STM32_FUNCTION(6, "I2C3_SDA"), + STM32_FUNCTION(7, "SPI5_SCK"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO3"), + STM32_FUNCTION(11, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(12, "ETH1_MII_TX_CLK"), + STM32_FUNCTION(14, "QUADSPI_BK1_IO3"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(120, "PH8"), + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(1, "TRACED9"), + STM32_FUNCTION(3, "TIM5_ETR"), + STM32_FUNCTION(4, "USART2_RX"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(12, "LCD_R6"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(14, "DCMIPP_HSYNC"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "HDP2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(121, "PH9"), + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(3, "TIM12_CH2"), + STM32_FUNCTION(4, "TSC_SYNC"), + STM32_FUNCTION(6, "SPI4_SCK I2S4_CK"), + STM32_FUNCTION(7, "DCMIPP_D13"), + STM32_FUNCTION(10, "LCD_B5"), + STM32_FUNCTION(12, "LCD_DE"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "DCMIPP_D9"), + STM32_FUNCTION(15, "DCMIPP_D8"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(122, "PH10"), + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(4, "SAI2_D3"), + STM32_FUNCTION(5, "DFSDM1_DATIN2"), + STM32_FUNCTION(6, "I2S3_MCK"), + STM32_FUNCTION(7, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(8, "USART3_CTS USART3_NSS"), + STM32_FUNCTION(9, "SDMMC1_D4"), + STM32_FUNCTION(14, "LCD_HSYNC"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "HDP0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(123, "PH11"), + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(2, "SPI5_NSS"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(4, "SAI2_SD_A"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(7, "I2C4_SCL"), + STM32_FUNCTION(8, "USART6_RX"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO0"), + STM32_FUNCTION(12, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(124, "PH12"), + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(2, "USART2_TX"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(4, "DFSDM1_CKIN1"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(7, "SAI1_SCK_A"), + STM32_FUNCTION(10, "QUADSPI_BK2_IO2"), + STM32_FUNCTION(11, "SAI1_CK2"), + STM32_FUNCTION(12, "ETH1_MII_CRS"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(14, "DCMIPP_D3"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(125, "PH13"), + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(1, "TRACED15"), + STM32_FUNCTION(3, "USART2_CK"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(5, "I2C5_SCL"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(14, "LCD_G3"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(126, "PH14"), + STM32_FUNCTION(0, "GPIOH14"), + STM32_FUNCTION(4, "DFSDM1_DATIN2"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(7, "DCMIPP_D8"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(12, "LCD_B4"), + STM32_FUNCTION(14, "DCMIPP_D2"), + STM32_FUNCTION(15, "DCMIPP_PIXCLK"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(128, "PI0"), + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(9, "SPDIFRX_IN0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(129, "PI1"), + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(9, "SPDIFRX_IN1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(130, "PI2"), + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(9, "SPDIFRX_IN2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(131, "PI3"), + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(9, "SPDIFRX_IN3"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(132, "PI4"), + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(1, "BOOT0"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(133, "PI5"), + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(1, "BOOT1"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(134, "PI6"), + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(1, "BOOT2"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(135, "PI7"), + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32mp135_match_data = { + .pins = stm32mp135_pins, + .npins = ARRAY_SIZE(stm32mp135_pins), +}; + +static const struct of_device_id stm32mp135_pctrl_match[] = { + { + .compatible = "st,stm32mp135-pinctrl", + .data = &stm32mp135_match_data, + }, + { } +}; + +static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume) +}; + +static struct platform_driver stm32mp135_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32mp135-pinctrl", + .of_match_table = stm32mp135_pctrl_match, + .pm = &stm32_pinctrl_dev_pm_ops, + }, +}; + +static int __init stm32mp135_pinctrl_init(void) +{ + return platform_driver_register(&stm32mp135_pinctrl_driver); +} +arch_initcall(stm32mp135_pinctrl_init); -- cgit v1.2.3 From 1b73e588f47397dee6e4bdfd953e0306c60b5fe5 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sun, 25 Jul 2021 19:08:30 +0100 Subject: pinctrl: stmfx: Fix hazardous u8[] to unsigned long cast Casting a small array of u8 to an unsigned long is *never* OK: - it does funny thing when the array size is less than that of a long, as it accesses random places in the stack - it makes everything even more fun with a BE kernel Fix this by building the unsigned long used as a bitmap byte by byte, in a way that works across endianess and has no undefined behaviours. An extra BUILD_BUG_ON() catches the unlikely case where the array would be larger than a single unsigned long. Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Signed-off-by: Marc Zyngier Cc: stable@vger.kernel.org Cc: Amelie Delaunay Cc: Linus Walleij Cc: Maxime Coquelin Cc: Alexandre Torgue Link: https://lore.kernel.org/r/20210725180830.250218-1-maz@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-stmfx.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 008c83107a3c..5fa2488fae87 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -566,7 +566,7 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) u8 pending[NR_GPIO_REGS]; u8 src[NR_GPIO_REGS] = {0, 0, 0}; unsigned long n, status; - int ret; + int i, ret; ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, &pending, NR_GPIO_REGS); @@ -576,7 +576,9 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, src, NR_GPIO_REGS); - status = *(unsigned long *)pending; + BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status)); + for (i = 0, status = 0; i < NR_GPIO_REGS; i++) + status |= (unsigned long)pending[i] << (i * 8); for_each_set_bit(n, &status, gc->ngpio) { handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); stmfx_pinctrl_irq_toggle_trigger(pctl, n); -- cgit v1.2.3 From 5fa9d19b3fb640e3616de2a7615236c0cc45e702 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 22 Jul 2021 20:48:40 -0700 Subject: pinctrl: aspeed: placate kernel-doc warnings Eliminate kernel-doc warnings in drivers/pinctrl/aspeed by using proper kernel-doc notation. Fixes these kernel-doc warnings: drivers/pinctrl/aspeed/pinmux-aspeed.c:61: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Query the enabled or disabled state for a mux function's signal on a pin drivers/pinctrl/aspeed/pinctrl-aspeed.c:135: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Search for the signal expression needed to enable the pin's signal for the Signed-off-by: Randy Dunlap Reported-by: kernel test robot Cc: Aditya Srivastava Cc: Andrew Jeffery Cc: linux-aspeed@lists.ozlabs.org Cc: openbmc@lists.ozlabs.org Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210723034840.8752-1-rdunlap@infradead.org Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 4 ++-- drivers/pinctrl/aspeed/pinmux-aspeed.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 9bbfe5c14b36..c94e24aadf92 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -133,8 +133,8 @@ static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx, } /** - * Search for the signal expression needed to enable the pin's signal for the - * requested function. + * aspeed_find_expr_by_name - Search for the signal expression needed to + * enable the pin's signal for the requested function. * * @exprs: List of signal expressions (haystack) * @name: The name of the requested function (needle) diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.c b/drivers/pinctrl/aspeed/pinmux-aspeed.c index 894e2efd3be7..4aa46383c2c5 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.c +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.c @@ -59,7 +59,8 @@ int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, } /** - * Query the enabled or disabled state for a mux function's signal on a pin + * aspeed_sig_expr_eval - Query the enabled or disabled state for a + * mux function's signal on a pin * * @ctx: The driver context for the pinctrl IP * @expr: An expression controlling the signal for a mux function on a pin -- cgit v1.2.3 From 28c1caaf492ed941d9dc7ce643515831f4e98117 Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Sat, 24 Jul 2021 14:36:41 +0800 Subject: pinctrl: Ingenic: Improve the code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.Rename the original "dmicx" ABIs to "dmic-ifx", since these devices have only one DMIC module which has multiple input interfaces. The original naming is easy to make users mistakenly think that the device has multiple dmic modules. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 2.Rename the original "ssix-ce0" ABIs to "ssix-ce", since the X2000 have only one ce pin. The original naming is easy to make users mistakenly think that the device has multiple ce pins. Currently, in the mainline, no other devicetree out there is using the "ssix-ce0" ABIs, so we should be able to replace it safely. 3.Split the original "sfc" ABI into "sfc-data", "sfc-ce", "sfc-clk" to increase the flexibility when configuring the pins. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 4.There is more than one compatible string in the match table, so renaming "ingenic_xxxx_of_match[]" to "ingenic_xxxx_of_matches" is more reasonable, and remove the unnecessary commas in "ingenic_gpio_of_matches[]" to reduce code size as much as possible. Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/1627108604-91304-2-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 155 ++++++++++++++++++++++---------------- 1 file changed, 89 insertions(+), 66 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 983ba9865f77..1ec05ee4f0c7 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1827,7 +1827,9 @@ static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; -static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; +static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, }; +static int x1000_sfc_clk_pins[] = { 0x1a, }; +static int x1000_sfc_ce_pins[] = { 0x1b, }; static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; static int x1000_ssi_dt_d_pins[] = { 0x62, }; @@ -1871,8 +1873,8 @@ static int x1000_i2s_data_tx_pins[] = { 0x24, }; static int x1000_i2s_data_rx_pins[] = { 0x23, }; static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; static int x1000_i2s_sysclk_pins[] = { 0x20, }; -static int x1000_dmic0_pins[] = { 0x35, 0x36, }; -static int x1000_dmic1_pins[] = { 0x25, }; +static int x1000_dmic_if0_pins[] = { 0x35, 0x36, }; +static int x1000_dmic_if1_pins[] = { 0x25, }; static int x1000_cim_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, @@ -1901,7 +1903,9 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), - INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), + INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), + INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), + INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), @@ -1938,8 +1942,8 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), - INGENIC_PIN_GROUP("dmic0", x1000_dmic0, 0), - INGENIC_PIN_GROUP("dmic1", x1000_dmic1, 1), + INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0), + INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1), INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), @@ -1956,7 +1960,7 @@ static const char *x1000_uart1_groups[] = { "uart1-data-a", "uart1-data-d", "uart1-hwflow", }; static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; -static const char *x1000_sfc_groups[] = { "sfc", }; +static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; static const char *x1000_ssi_groups[] = { "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", @@ -1983,7 +1987,7 @@ static const char *x1000_i2c2_groups[] = { "i2c2-data", }; static const char *x1000_i2s_groups[] = { "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", }; -static const char *x1000_dmic_groups[] = { "dmic0", "dmic1", }; +static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", }; static const char *x1000_cim_groups[] = { "cim-data", }; static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; static const char *x1000_pwm0_groups[] = { "pwm0", }; @@ -2048,8 +2052,8 @@ static int x1500_i2s_data_tx_pins[] = { 0x24, }; static int x1500_i2s_data_rx_pins[] = { 0x23, }; static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; static int x1500_i2s_sysclk_pins[] = { 0x20, }; -static int x1500_dmic0_pins[] = { 0x35, 0x36, }; -static int x1500_dmic1_pins[] = { 0x25, }; +static int x1500_dmic_if0_pins[] = { 0x35, 0x36, }; +static int x1500_dmic_if1_pins[] = { 0x25, }; static int x1500_cim_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, @@ -2068,7 +2072,9 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), - INGENIC_PIN_GROUP("sfc", x1000_sfc, 1), + INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), + INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), + INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), @@ -2079,8 +2085,8 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), - INGENIC_PIN_GROUP("dmic0", x1500_dmic0, 0), - INGENIC_PIN_GROUP("dmic1", x1500_dmic1, 1), + INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0), + INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1), INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), @@ -2101,7 +2107,7 @@ static const char *x1500_i2c2_groups[] = { "i2c2-data", }; static const char *x1500_i2s_groups[] = { "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", }; -static const char *x1500_dmic_groups[] = { "dmic0", "dmic1", }; +static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", }; static const char *x1500_cim_groups[] = { "cim-data", }; static const char *x1500_pwm0_groups[] = { "pwm0", }; static const char *x1500_pwm1_groups[] = { "pwm1", }; @@ -2151,7 +2157,9 @@ static const u32 x1830_pull_downs[4] = { static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; -static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; +static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, }; +static int x1830_sfc_clk_pins[] = { 0x1b, }; +static int x1830_sfc_ce_pins[] = { 0x1c, }; static int x1830_ssi0_dt_pins[] = { 0x4c, }; static int x1830_ssi0_dr_pins[] = { 0x4b, }; static int x1830_ssi0_clk_pins[] = { 0x4f, }; @@ -2182,8 +2190,8 @@ static int x1830_i2s_data_rx_pins[] = { 0x54, }; static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; static int x1830_i2s_sysclk_pins[] = { 0x57, }; -static int x1830_dmic0_pins[] = { 0x48, 0x59, }; -static int x1830_dmic1_pins[] = { 0x5a, }; +static int x1830_dmic_if0_pins[] = { 0x48, 0x59, }; +static int x1830_dmic_if1_pins[] = { 0x5a, }; static int x1830_lcd_tft_8bit_pins[] = { 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x73, 0x72, 0x69, @@ -2223,7 +2231,9 @@ static const struct group_desc x1830_groups[] = { INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), - INGENIC_PIN_GROUP("sfc", x1830_sfc, 1), + INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1), + INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1), + INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1), INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), @@ -2254,8 +2264,8 @@ static const struct group_desc x1830_groups[] = { INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), - INGENIC_PIN_GROUP("dmic0", x1830_dmic0, 2), - INGENIC_PIN_GROUP("dmic1", x1830_dmic1, 2), + INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2), + INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2), INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), @@ -2281,7 +2291,7 @@ static const struct group_desc x1830_groups[] = { static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *x1830_uart1_groups[] = { "uart1-data", }; -static const char *x1830_sfc_groups[] = { "sfc", }; +static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; static const char *x1830_ssi0_groups[] = { "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", }; @@ -2301,7 +2311,7 @@ static const char *x1830_i2c2_groups[] = { "i2c2-data", }; static const char *x1830_i2s_groups[] = { "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", }; -static const char *x1830_dmic_groups[] = { "dmic0", "dmic1", }; +static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", }; static const char *x1830_lcd_groups[] = { "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", }; @@ -2381,17 +2391,21 @@ static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; -static int x2000_sfc0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, 0x71, 0x72, }; -static int x2000_sfc0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, 0x90, 0x91, }; -static int x2000_sfc1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; +static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, }; +static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, }; +static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; +static int x2000_sfc_clk_d_pins[] = { 0x71, }; +static int x2000_sfc_clk_e_pins[] = { 0x90, }; +static int x2000_sfc_ce_d_pins[] = { 0x72, }; +static int x2000_sfc_ce_e_pins[] = { 0x91, }; static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; static int x2000_ssi0_dt_d_pins[] = { 0x69, }; static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; static int x2000_ssi0_clk_d_pins[] = { 0x68, }; -static int x2000_ssi0_ce0_b_pins[] = { 0x3c, }; -static int x2000_ssi0_ce0_d_pins[] = { 0x6d, }; +static int x2000_ssi0_ce_b_pins[] = { 0x3c, }; +static int x2000_ssi0_ce_d_pins[] = { 0x6d, }; static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; static int x2000_ssi1_dt_d_pins[] = { 0x72, }; static int x2000_ssi1_dt_e_pins[] = { 0x91, }; @@ -2401,9 +2415,9 @@ static int x2000_ssi1_dr_e_pins[] = { 0x92, }; static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; static int x2000_ssi1_clk_d_pins[] = { 0x71, }; static int x2000_ssi1_clk_e_pins[] = { 0x90, }; -static int x2000_ssi1_ce0_c_pins[] = { 0x49, }; -static int x2000_ssi1_ce0_d_pins[] = { 0x76, }; -static int x2000_ssi1_ce0_e_pins[] = { 0x95, }; +static int x2000_ssi1_ce_c_pins[] = { 0x49, }; +static int x2000_ssi1_ce_d_pins[] = { 0x76, }; +static int x2000_ssi1_ce_e_pins[] = { 0x95, }; static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; @@ -2455,10 +2469,10 @@ static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; -static int x2000_dmic0_pins[] = { 0x54, 0x55, }; -static int x2000_dmic1_pins[] = { 0x56, }; -static int x2000_dmic2_pins[] = { 0x57, }; -static int x2000_dmic3_pins[] = { 0x58, }; +static int x2000_dmic_if0_pins[] = { 0x54, 0x55, }; +static int x2000_dmic_if1_pins[] = { 0x56, }; +static int x2000_dmic_if2_pins[] = { 0x57, }; +static int x2000_dmic_if3_pins[] = { 0x58, }; static int x2000_cim_8bit_pins[] = { 0x0e, 0x0c, 0x0d, 0x4f, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, @@ -2545,17 +2559,21 @@ static const struct group_desc x2000_groups[] = { INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), - INGENIC_PIN_GROUP("sfc0-d", x2000_sfc0_d, 1), - INGENIC_PIN_GROUP("sfc0-e", x2000_sfc0_e, 0), - INGENIC_PIN_GROUP("sfc1", x2000_sfc1, 1), + INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), + INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), + INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), + INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), + INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), + INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), + INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), - INGENIC_PIN_GROUP("ssi0-ce0-b", x2000_ssi0_ce0_b, 1), - INGENIC_PIN_GROUP("ssi0-ce0-d", x2000_ssi0_ce0_d, 1), + INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), + INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), @@ -2565,9 +2583,9 @@ static const struct group_desc x2000_groups[] = { INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), - INGENIC_PIN_GROUP("ssi1-ce0-c", x2000_ssi1_ce0_c, 2), - INGENIC_PIN_GROUP("ssi1-ce0-d", x2000_ssi1_ce0_d, 2), - INGENIC_PIN_GROUP("ssi1-ce0-e", x2000_ssi1_ce0_e, 1), + INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), + INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), + INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), @@ -2612,10 +2630,10 @@ static const struct group_desc x2000_groups[] = { INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), - INGENIC_PIN_GROUP("dmic0", x2000_dmic0, 0), - INGENIC_PIN_GROUP("dmic1", x2000_dmic1, 0), - INGENIC_PIN_GROUP("dmic2", x2000_dmic2, 0), - INGENIC_PIN_GROUP("dmic3", x2000_dmic3, 0), + INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), + INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), + INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), + INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, x2000_cim_8bit_funcs), INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), @@ -2670,18 +2688,21 @@ static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; static const char *x2000_uart8_groups[] = { "uart8-data", }; static const char *x2000_uart9_groups[] = { "uart9-data", }; -static const char *x2000_sfc_groups[] = { "sfc0-d", "sfc0-e", "sfc1", }; +static const char *x2000_sfc_groups[] = { + "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1", + "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e", +}; static const char *x2000_ssi0_groups[] = { "ssi0-dt-b", "ssi0-dt-d", "ssi0-dr-b", "ssi0-dr-d", "ssi0-clk-b", "ssi0-clk-d", - "ssi0-ce0-b", "ssi0-ce0-d", + "ssi0-ce-b", "ssi0-ce-d", }; static const char *x2000_ssi1_groups[] = { "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", - "ssi1-ce0-c", "ssi1-ce0-d", "ssi1-ce0-e", + "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e", }; static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; @@ -2711,7 +2732,9 @@ static const char *x2000_i2s3_groups[] = { "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", "i2s3-clk-tx", "i2s3-sysclk-tx", }; -static const char *x2000_dmic_groups[] = { "dmic0", "dmic1", "dmic2", "dmic3", }; +static const char *x2000_dmic_groups[] = { + "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3", +}; static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; static const char *x2000_lcd_groups[] = { "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", @@ -3654,19 +3677,19 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = { .reg_stride = 4, }; -static const struct of_device_id ingenic_gpio_of_match[] __initconst = { - { .compatible = "ingenic,jz4730-gpio", }, - { .compatible = "ingenic,jz4740-gpio", }, - { .compatible = "ingenic,jz4725b-gpio", }, - { .compatible = "ingenic,jz4750-gpio", }, - { .compatible = "ingenic,jz4755-gpio", }, - { .compatible = "ingenic,jz4760-gpio", }, - { .compatible = "ingenic,jz4770-gpio", }, - { .compatible = "ingenic,jz4775-gpio", }, - { .compatible = "ingenic,jz4780-gpio", }, - { .compatible = "ingenic,x1000-gpio", }, - { .compatible = "ingenic,x1830-gpio", }, - { .compatible = "ingenic,x2000-gpio", }, +static const struct of_device_id ingenic_gpio_of_matches[] __initconst = { + { .compatible = "ingenic,jz4730-gpio" }, + { .compatible = "ingenic,jz4740-gpio" }, + { .compatible = "ingenic,jz4725b-gpio" }, + { .compatible = "ingenic,jz4750-gpio" }, + { .compatible = "ingenic,jz4755-gpio" }, + { .compatible = "ingenic,jz4760-gpio" }, + { .compatible = "ingenic,jz4770-gpio" }, + { .compatible = "ingenic,jz4775-gpio" }, + { .compatible = "ingenic,jz4780-gpio" }, + { .compatible = "ingenic,x1000-gpio" }, + { .compatible = "ingenic,x1830-gpio" }, + { .compatible = "ingenic,x2000-gpio" }, {}, }; @@ -3843,7 +3866,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) dev_set_drvdata(dev, jzpc->map); for_each_child_of_node(dev->of_node, node) { - if (of_match_node(ingenic_gpio_of_match, node)) { + if (of_match_node(ingenic_gpio_of_matches, node)) { err = ingenic_gpio_probe(jzpc, node); if (err) { of_node_put(node); @@ -3857,7 +3880,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr)) -static const struct of_device_id ingenic_pinctrl_of_match[] = { +static const struct of_device_id ingenic_pinctrl_of_matches[] = { { .compatible = "ingenic,jz4730-pinctrl", .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) @@ -3928,7 +3951,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { static struct platform_driver ingenic_pinctrl_driver = { .driver = { .name = "pinctrl-ingenic", - .of_match_table = ingenic_pinctrl_of_match, + .of_match_table = ingenic_pinctrl_of_matches, }, }; -- cgit v1.2.3 From b638e0f18dea6f51a8f822a03028676ba2f7cf5b Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Sat, 24 Jul 2021 14:36:42 +0800 Subject: pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SSI pins support for the JZ4755 SoC and the JZ4760 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/1627108604-91304-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 155 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 1ec05ee4f0c7..f88bccfb2ff6 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -589,6 +589,18 @@ static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; static int jz4755_uart2_data_pins[] = { 0x9f, }; +static int jz4755_ssi_dt_b_pins[] = { 0x3b, }; +static int jz4755_ssi_dt_f_pins[] = { 0xa1, }; +static int jz4755_ssi_dr_b_pins[] = { 0x3c, }; +static int jz4755_ssi_dr_f_pins[] = { 0xa2, }; +static int jz4755_ssi_clk_b_pins[] = { 0x3a, }; +static int jz4755_ssi_clk_f_pins[] = { 0xa0, }; +static int jz4755_ssi_gpc_b_pins[] = { 0x3e, }; +static int jz4755_ssi_gpc_f_pins[] = { 0xa4, }; +static int jz4755_ssi_ce0_b_pins[] = { 0x3d, }; +static int jz4755_ssi_ce0_f_pins[] = { 0xa3, }; +static int jz4755_ssi_ce1_b_pins[] = { 0x3f, }; +static int jz4755_ssi_ce1_f_pins[] = { 0xa5, }; static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; @@ -630,6 +642,18 @@ static const struct group_desc jz4755_groups[] = { INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0), INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), + INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0), + INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0), + INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0), + INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0), + INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0), + INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0), + INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0), + INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0), + INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0), + INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0), + INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0), + INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0), INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, jz4755_mmc0_1bit_funcs), INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, @@ -661,6 +685,14 @@ static const struct group_desc jz4755_groups[] = { static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *jz4755_uart1_groups[] = { "uart1-data", }; static const char *jz4755_uart2_groups[] = { "uart2-data", }; +static const char *jz4755_ssi_groups[] = { + "ssi-dt-b", "ssi-dt-f", + "ssi-dr-b", "ssi-dr-f", + "ssi-clk-b", "ssi-clk-f", + "ssi-gpc-b", "ssi-gpc-f", + "ssi-ce0-b", "ssi-ce0-f", + "ssi-ce1-b", "ssi-ce1-f", +}; static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; static const char *jz4755_i2c_groups[] = { "i2c-data", }; @@ -683,6 +715,7 @@ static const struct function_desc jz4755_functions[] = { { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), }, { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), }, { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), }, + { "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), }, { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), }, { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), }, { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), }, @@ -725,6 +758,58 @@ static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; +static int jz4760_ssi0_dt_a_pins[] = { 0x15, }; +static int jz4760_ssi0_dt_b_pins[] = { 0x35, }; +static int jz4760_ssi0_dt_d_pins[] = { 0x75, }; +static int jz4760_ssi0_dt_e_pins[] = { 0x91, }; +static int jz4760_ssi0_dr_a_pins[] = { 0x14, }; +static int jz4760_ssi0_dr_b_pins[] = { 0x34, }; +static int jz4760_ssi0_dr_d_pins[] = { 0x74, }; +static int jz4760_ssi0_dr_e_pins[] = { 0x8e, }; +static int jz4760_ssi0_clk_a_pins[] = { 0x12, }; +static int jz4760_ssi0_clk_b_pins[] = { 0x3c, }; +static int jz4760_ssi0_clk_d_pins[] = { 0x78, }; +static int jz4760_ssi0_clk_e_pins[] = { 0x8f, }; +static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, }; +static int jz4760_ssi0_gpc_d_pins[] = { 0x76, }; +static int jz4760_ssi0_gpc_e_pins[] = { 0x93, }; +static int jz4760_ssi0_ce0_a_pins[] = { 0x13, }; +static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, }; +static int jz4760_ssi0_ce0_d_pins[] = { 0x79, }; +static int jz4760_ssi0_ce0_e_pins[] = { 0x90, }; +static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, }; +static int jz4760_ssi0_ce1_d_pins[] = { 0x77, }; +static int jz4760_ssi0_ce1_e_pins[] = { 0x92, }; +static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, }; +static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, }; +static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, }; +static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, }; +static int jz4760_ssi1_dt_e_pins[] = { 0x91, }; +static int jz4760_ssi1_dt_f_pins[] = { 0xa3, }; +static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, }; +static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, }; +static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, }; +static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, }; +static int jz4760_ssi1_dr_e_pins[] = { 0x8e, }; +static int jz4760_ssi1_dr_f_pins[] = { 0xa0, }; +static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, }; +static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, }; +static int jz4760_ssi1_clk_d_pins[] = { 0x78, }; +static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, }; +static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, }; +static int jz4760_ssi1_clk_f_pins[] = { 0xa2, }; +static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, }; +static int jz4760_ssi1_gpc_d_pins[] = { 0x76, }; +static int jz4760_ssi1_gpc_e_pins[] = { 0x93, }; +static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, }; +static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, }; +static int jz4760_ssi1_ce0_d_pins[] = { 0x79, }; +static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, }; +static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, }; +static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, }; +static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, }; +static int jz4760_ssi1_ce1_d_pins[] = { 0x77, }; +static int jz4760_ssi1_ce1_e_pins[] = { 0x92, }; static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; @@ -801,6 +886,58 @@ static const struct group_desc jz4760_groups[] = { INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, jz4760_uart3_data_funcs), INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), + INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2), + INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1), + INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1), + INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0), + INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1), + INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1), + INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1), + INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0), + INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2), + INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1), + INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1), + INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0), + INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1), + INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1), + INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0), + INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2), + INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1), + INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1), + INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0), + INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1), + INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1), + INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0), + INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2), + INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2), + INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2), + INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2), + INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1), + INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2), + INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2), + INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2), + INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2), + INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2), + INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1), + INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2), + INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2), + INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2), + INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2), + INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2), + INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1), + INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2), + INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2), + INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2), + INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1), + INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2), + INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2), + INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2), + INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2), + INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1), + INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2), + INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2), + INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2), + INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1), INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, jz4760_mmc0_1bit_a_funcs), INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), @@ -854,6 +991,22 @@ static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; +static const char *jz4760_ssi0_groups[] = { + "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", + "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", + "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", + "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", + "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", + "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", +}; +static const char *jz4760_ssi1_groups[] = { + "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f", + "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f", + "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f", + "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", + "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f", + "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", +}; static const char *jz4760_mmc0_groups[] = { "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", @@ -898,6 +1051,8 @@ static const struct function_desc jz4760_functions[] = { { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, + { "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), }, + { "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), }, { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, -- cgit v1.2.3 From 2a18211b8ccfa316d1cb68d00d4ceba0e81653f8 Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Sat, 24 Jul 2021 14:36:44 +0800 Subject: pinctrl: Ingenic: Add pinctrl driver for X2100. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for probing the pinctrl-ingenic driver on the X2100 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/1627108604-91304-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 216 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 216 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index f88bccfb2ff6..cd296d98548d 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -104,6 +104,7 @@ enum jz_version { ID_X1500, ID_X1830, ID_X2000, + ID_X2100, }; struct ingenic_chip_info { @@ -2980,6 +2981,216 @@ static const struct ingenic_chip_info x2000_chip_info = { .pull_downs = x2000_pull_downs, }; +static const u32 x2100_pull_ups[5] = { + 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f, +}; + +static const u32 x2100_pull_downs[5] = { + 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f, +}; + +static int x2100_mac_pins[] = { + 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41, +}; + +static const struct group_desc x2100_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), + INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), + INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), + INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), + INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), + INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), + INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), + INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), + INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), + INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), + INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), + INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), + INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), + INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), + INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), + INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), + INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), + INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), + INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), + INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), + INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), + INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), + INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), + INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), + INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), + INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), + INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), + INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), + INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), + INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), + INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), + INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), + INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), + INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), + INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), + INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), + INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), + INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), + INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), + INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), + INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), + INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), + INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), + INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), + INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), + INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), + INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), + INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), + INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), + INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), + INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), + INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), + INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), + INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), + INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), + INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), + INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), + INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), + INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), + INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), + INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), + INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), + INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), + INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), + INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), + INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), + INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), + INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), + INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), + INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), + INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), + INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), + INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), + INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), + INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), + INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), + INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), + INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), + INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), + INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), + INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), + INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), + INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), + INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), + INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), + INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), + INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), + INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), + INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), + INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), + INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), + INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), + INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), + INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), + INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), + INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), + INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, + x2000_cim_8bit_funcs), + INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), + INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), + INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), + INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), + INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), + INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), + INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), + INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), + INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), + INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), + INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), + INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), + INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), + INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), + INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), + INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), + INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), + INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), + INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), + INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), + INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), + INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), + INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), + INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), + INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), + INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), + INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), + INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), + INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), + INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), + INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), + INGENIC_PIN_GROUP("mac", x2100_mac, 1), +}; + +static const char *x2100_mac_groups[] = { "mac", }; + +static const struct function_desc x2100_functions[] = { + { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, + { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, + { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, + { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, + { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, + { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, + { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, + { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, + { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, + { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, + { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, + { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, + { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, + { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, + { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, + { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, + { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, + { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, + { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, + { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, + { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, + { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, + { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, + { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, + { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, + { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, + { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, + { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, + { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, + { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, + { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, + { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, + { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, + { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, + { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, + { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, + { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, + { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, + { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, + { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, + { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, + { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, + { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, + { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, + { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, + { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, + { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, + { "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), }, +}; + +static const struct ingenic_chip_info x2100_chip_info = { + .num_chips = 5, + .reg_offset = 0x100, + .version = ID_X2100, + .groups = x2100_groups, + .num_groups = ARRAY_SIZE(x2100_groups), + .functions = x2100_functions, + .num_functions = ARRAY_SIZE(x2100_functions), + .pull_ups = x2100_pull_ups, + .pull_downs = x2100_pull_downs, +}; + static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -3845,6 +4056,7 @@ static const struct of_device_id ingenic_gpio_of_matches[] __initconst = { { .compatible = "ingenic,x1000-gpio" }, { .compatible = "ingenic,x1830-gpio" }, { .compatible = "ingenic,x2000-gpio" }, + { .compatible = "ingenic,x2100-gpio" }, {}, }; @@ -4100,6 +4312,10 @@ static const struct of_device_id ingenic_pinctrl_of_matches[] = { .compatible = "ingenic,x2000e-pinctrl", .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) }, + { + .compatible = "ingenic,x2100-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info) + }, { /* sentinel */ }, }; -- cgit v1.2.3 From d5e931403942b3af39212960c2592b5ba741b2bf Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sat, 17 Jul 2021 18:48:34 +0100 Subject: pinctrl: ingenic: Fix incorrect pull up/down info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the pull up/down info for both the JZ4760 and JZ4770 SoCs, as the previous values sometimes contradicted what's written in the programming manual. Fixes: b5c23aa46537 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Cc: # v4.12 Signed-off-by: Paul Cercueil Tested-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20210717174836.14776-1-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index cd296d98548d..5a602e6479b9 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -744,7 +744,7 @@ static const struct ingenic_chip_info jz4755_chip_info = { }; static const u32 jz4760_pull_ups[6] = { - 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, + 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f, }; static const u32 jz4760_pull_downs[6] = { @@ -1092,11 +1092,11 @@ static const struct ingenic_chip_info jz4760_chip_info = { }; static const u32 jz4770_pull_ups[6] = { - 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, + 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f, }; static const u32 jz4770_pull_downs[6] = { - 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, + 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0, }; static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; -- cgit v1.2.3 From 7261851e938f4b0fe8c0f5a8e627ae90e1ba9875 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sat, 17 Jul 2021 18:48:35 +0100 Subject: pinctrl: ingenic: Fix bias config for X2000(E) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ingenic_set_bias() function's "bias" argument is not a "enum pin_config_param", so its value should not be compared against values of that enum. This should fix the bias config not working on the X2000(E) SoCs. Fixes: 943e0da15370 ("pinctrl: Ingenic: Add pinctrl driver for X2000.") Cc: # v5.12 Signed-off-by: Paul Cercueil Tested-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20210717174836.14776-2-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 5a602e6479b9..2b894db1029b 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3830,17 +3830,17 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, { if (jzpc->info->version >= ID_X2000) { switch (bias) { - case PIN_CONFIG_BIAS_PULL_UP: + case GPIO_PULL_UP: ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); break; - case PIN_CONFIG_BIAS_PULL_DOWN: + case GPIO_PULL_DOWN: ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); break; - case PIN_CONFIG_BIAS_DISABLE: + case GPIO_PULL_DIS: default: ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); -- cgit v1.2.3 From 6626a76ef857c937ba7b96f0ea8bb5451c1419eb Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sat, 17 Jul 2021 18:48:36 +0100 Subject: pinctrl: ingenic: Add .max_register in regmap_config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Compute the max register from the GPIO chip offset and number of GPIO chips. This permits to read all registers from debugfs. Signed-off-by: Paul Cercueil Tested-by: 周琰杰 (Zhou Yanjie) Link: https://lore.kernel.org/r/20210717174836.14776-3-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 2b894db1029b..cf4cc8f129f4 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -4149,6 +4149,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) void __iomem *base; const struct ingenic_chip_info *chip_info; struct device_node *node; + struct regmap_config regmap_config; unsigned int i; int err; @@ -4166,8 +4167,10 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - jzpc->map = devm_regmap_init_mmio(dev, base, - &ingenic_pinctrl_regmap_config); + regmap_config = ingenic_pinctrl_regmap_config; + regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset; + + jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); if (IS_ERR(jzpc->map)) { dev_err(dev, "Failed to create regmap\n"); return PTR_ERR(jzpc->map); -- cgit v1.2.3 From 3fb5c90452e41d3536106789a532edfa7e7a032f Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 29 Jul 2021 15:19:05 +0800 Subject: pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device It's not necessary to unregister pin controller device registered with devm_pinctrl_register() and using pinctrl_unregister() leads to a double free. Fixes: fa99e7013827 ("pinctrl: zynqmp: some code cleanups") Signed-off-by: Yang Yingliang Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20210729071905.3235953-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-zynqmp.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index bbde676b7313..e14012209992 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -866,15 +866,6 @@ static int zynqmp_pinctrl_probe(struct platform_device *pdev) return ret; } -static int zynqmp_pinctrl_remove(struct platform_device *pdev) -{ - struct zynqmp_pinctrl *pctrl = platform_get_drvdata(pdev); - - pinctrl_unregister(pctrl->pctrl); - - return 0; -} - static const struct of_device_id zynqmp_pinctrl_of_match[] = { { .compatible = "xlnx,zynqmp-pinctrl" }, { } @@ -887,7 +878,6 @@ static struct platform_driver zynqmp_pinctrl_driver = { .of_match_table = zynqmp_pinctrl_of_match, }, .probe = zynqmp_pinctrl_probe, - .remove = zynqmp_pinctrl_remove, }; module_platform_driver(zynqmp_pinctrl_driver); -- cgit v1.2.3 From ffd4e739358be036377563a0c6c33702c700e3ee Mon Sep 17 00:00:00 2001 From: Lakshmi Sowjanya D Date: Fri, 6 Aug 2021 19:55:27 +0530 Subject: pinctrl: Add Intel Keem Bay pinctrl driver About Intel Keem Bay: ------------------- Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU. Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Keem Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC. Co-developed-by: Vineetha G. Jaya Kumaran Signed-off-by: Vineetha G. Jaya Kumaran Co-developed-by: Vijayakannan Ayyathurai Signed-off-by: Vijayakannan Ayyathurai Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Mark Gross Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 19 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-keembay.c | 1731 +++++++++++++++++++++++++++++++++++++ 3 files changed, 1751 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-keembay.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index eb981713b40d..31921108e456 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -407,6 +407,25 @@ config PINCTRL_K210 Add support for the Canaan Kendryte K210 RISC-V SOC Field Programmable IO Array (FPIOA) controller. +config PINCTRL_KEEMBAY + tristate "Pinctrl driver for Intel Keem Bay SoC" + depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST) + depends on HAS_IOMEM + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select GPIO_GENERIC + help + This selects pin control driver for the Intel Keembay SoC. + It provides pin config functions such as pullup, pulldown, + interrupt, drive strength, sec lock, schmitt trigger, slew + rate control and direction control. This module will be + called as pinctrl-keembay. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 5ef5334a797f..200073bcc2c1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o +obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o obj-y += actions/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ diff --git a/drivers/pinctrl/pinctrl-keembay.c b/drivers/pinctrl/pinctrl-keembay.c new file mode 100644 index 000000000000..2bce563d5b8b --- /dev/null +++ b/drivers/pinctrl/pinctrl-keembay.c @@ -0,0 +1,1731 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2020 Intel Corporation */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "core.h" +#include "pinmux.h" + +/* GPIO data registers' offsets */ +#define KEEMBAY_GPIO_DATA_OUT 0x000 +#define KEEMBAY_GPIO_DATA_IN 0x020 +#define KEEMBAY_GPIO_DATA_IN_RAW 0x040 +#define KEEMBAY_GPIO_DATA_HIGH 0x060 +#define KEEMBAY_GPIO_DATA_LOW 0x080 + +/* GPIO Interrupt and mode registers' offsets */ +#define KEEMBAY_GPIO_INT_CFG 0x000 +#define KEEMBAY_GPIO_MODE 0x070 + +/* GPIO mode register bit fields */ +#define KEEMBAY_GPIO_MODE_PULLUP_MASK GENMASK(13, 12) +#define KEEMBAY_GPIO_MODE_DRIVE_MASK GENMASK(8, 7) +#define KEEMBAY_GPIO_MODE_INV_MASK GENMASK(5, 4) +#define KEEMBAY_GPIO_MODE_SELECT_MASK GENMASK(2, 0) +#define KEEMBAY_GPIO_MODE_DIR_OVR BIT(15) +#define KEEMBAY_GPIO_MODE_REN BIT(11) +#define KEEMBAY_GPIO_MODE_SCHMITT_EN BIT(10) +#define KEEMBAY_GPIO_MODE_SLEW_RATE BIT(9) +#define KEEMBAY_GPIO_IRQ_ENABLE BIT(7) +#define KEEMBAY_GPIO_MODE_DIR BIT(3) +#define KEEMBAY_GPIO_MODE_DEFAULT 0x7 +#define KEEMBAY_GPIO_MODE_INV_VAL 0x3 + +#define KEEMBAY_GPIO_DISABLE 0 +#define KEEMBAY_GPIO_PULL_UP 1 +#define KEEMBAY_GPIO_PULL_DOWN 2 +#define KEEMBAY_GPIO_BUS_HOLD 3 +#define KEEMBAY_GPIO_NUM_IRQ 8 +#define KEEMBAY_GPIO_MAX_PER_IRQ 4 +#define KEEMBAY_GPIO_MAX_PER_REG 32 +#define KEEMBAY_GPIO_MIN_STRENGTH 2 +#define KEEMBAY_GPIO_MAX_STRENGTH 12 +#define KEEMBAY_GPIO_SENSE_LOW (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING) + +/* GPIO reg address calculation */ +#define KEEMBAY_GPIO_REG_OFFSET(pin) ((pin) * 4) + +/** + * struct keembay_mux_desc - Mux properties of each GPIO pin + * @mode: Pin mode when operating in this function + * @name: Pin function name + */ +struct keembay_mux_desc { + u8 mode; + const char *name; +}; + +#define KEEMBAY_PIN_DESC(pin_number, pin_name, ...) { \ + .number = pin_number, \ + .name = pin_name, \ + .drv_data = &(struct keembay_mux_desc[]) { \ + __VA_ARGS__, { } }, \ +} \ + +#define KEEMBAY_MUX(pin_mode, pin_function) { \ + .mode = pin_mode, \ + .name = pin_function, \ +} \ + +/** + * struct keembay_gpio_irq - Config of each GPIO Interrupt sources + * @source: Interrupt source number (0 - 7) + * @line: Actual Interrupt line number + * @pins: Array of GPIO pins using this Interrupt line + * @trigger: Interrupt trigger type for this line + * @num_share: Number of pins currently using this Interrupt line + */ +struct keembay_gpio_irq { + unsigned int source; + unsigned int line; + unsigned int pins[KEEMBAY_GPIO_MAX_PER_IRQ]; + unsigned int trigger; + unsigned int num_share; +}; + +/** + * struct keembay_pinctrl - Intel Keembay pinctrl structure + * @pctrl: Pointer to the pin controller device + * @base0: First register base address + * @base1: Second register base address + * @dev: Pointer to the device structure + * @chip: GPIO chip used by this pin controller + * @soc: Pin control configuration data based on SoC + * @lock: Spinlock to protect various gpio config register access + * @ngroups: Number of pin groups available + * @nfuncs: Number of pin functions available + * @npins: Number of GPIO pins available + * @irq: Store Interrupt source + * @max_gpios_level_type: Store max level trigger type + * @max_gpios_edge_type: Store max edge trigger type + */ +struct keembay_pinctrl { + struct pinctrl_dev *pctrl; + void __iomem *base0; + void __iomem *base1; + struct device *dev; + struct gpio_chip chip; + const struct keembay_pin_soc *soc; + raw_spinlock_t lock; + unsigned int ngroups; + unsigned int nfuncs; + unsigned int npins; + struct keembay_gpio_irq irq[KEEMBAY_GPIO_NUM_IRQ]; + int max_gpios_level_type; + int max_gpios_edge_type; +}; + +/** + * struct keembay_pin_soc - Pin control config data based on SoC + * @pins: Pin description structure + */ +struct keembay_pin_soc { + const struct pinctrl_pin_desc *pins; +}; + +static const struct pinctrl_pin_desc keembay_pins[] = { + KEEMBAY_PIN_DESC(0, "GPIO0", + KEEMBAY_MUX(0x0, "I2S0_M0"), + KEEMBAY_MUX(0x1, "SD0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(1, "GPIO1", + KEEMBAY_MUX(0x0, "I2S0_M0"), + KEEMBAY_MUX(0x1, "SD0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(2, "GPIO2", + KEEMBAY_MUX(0x0, "I2S0_M0"), + KEEMBAY_MUX(0x1, "I2S0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(3, "GPIO3", + KEEMBAY_MUX(0x0, "I2S0_M0"), + KEEMBAY_MUX(0x1, "I2S0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(4, "GPIO4", + KEEMBAY_MUX(0x0, "I2S0_M0"), + KEEMBAY_MUX(0x1, "I2S0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C2_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(5, "GPIO5", + KEEMBAY_MUX(0x0, "I2S0_M0"), + KEEMBAY_MUX(0x1, "I2S0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C2_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(6, "GPIO6", + KEEMBAY_MUX(0x0, "I2S1_M0"), + KEEMBAY_MUX(0x1, "SD0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C3_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(7, "GPIO7", + KEEMBAY_MUX(0x0, "I2S1_M0"), + KEEMBAY_MUX(0x1, "SD0_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "I2C3_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(8, "GPIO8", + KEEMBAY_MUX(0x0, "I2S1_M0"), + KEEMBAY_MUX(0x1, "I2S1_M1"), + KEEMBAY_MUX(0x2, "SLVDS0_M2"), + KEEMBAY_MUX(0x3, "UART0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(9, "GPIO9", + KEEMBAY_MUX(0x0, "I2S1_M0"), + KEEMBAY_MUX(0x1, "I2S1_M1"), + KEEMBAY_MUX(0x2, "PWM_M2"), + KEEMBAY_MUX(0x3, "UART0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(10, "GPIO10", + KEEMBAY_MUX(0x0, "I2S2_M0"), + KEEMBAY_MUX(0x1, "SD0_M1"), + KEEMBAY_MUX(0x2, "PWM_M2"), + KEEMBAY_MUX(0x3, "UART0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(11, "GPIO11", + KEEMBAY_MUX(0x0, "I2S2_M0"), + KEEMBAY_MUX(0x1, "SD0_M1"), + KEEMBAY_MUX(0x2, "PWM_M2"), + KEEMBAY_MUX(0x3, "UART0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(12, "GPIO12", + KEEMBAY_MUX(0x0, "I2S2_M0"), + KEEMBAY_MUX(0x1, "I2S2_M1"), + KEEMBAY_MUX(0x2, "PWM_M2"), + KEEMBAY_MUX(0x3, "SPI0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(13, "GPIO13", + KEEMBAY_MUX(0x0, "I2S2_M0"), + KEEMBAY_MUX(0x1, "I2S2_M1"), + KEEMBAY_MUX(0x2, "PWM_M2"), + KEEMBAY_MUX(0x3, "SPI0_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(14, "GPIO14", + KEEMBAY_MUX(0x0, "UART0_M0"), + KEEMBAY_MUX(0x1, "I2S3_M1"), + KEEMBAY_MUX(0x2, "PWM_M2"), + KEEMBAY_MUX(0x3, "SD1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "ETH_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(15, "GPIO15", + KEEMBAY_MUX(0x0, "UART0_M0"), + KEEMBAY_MUX(0x1, "I2S3_M1"), + KEEMBAY_MUX(0x2, "UART0_M2"), + KEEMBAY_MUX(0x3, "SD1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "SPI1_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(16, "GPIO16", + KEEMBAY_MUX(0x0, "UART0_M0"), + KEEMBAY_MUX(0x1, "I2S3_M1"), + KEEMBAY_MUX(0x2, "UART0_M2"), + KEEMBAY_MUX(0x3, "SD1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "SPI1_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(17, "GPIO17", + KEEMBAY_MUX(0x0, "UART0_M0"), + KEEMBAY_MUX(0x1, "I2S3_M1"), + KEEMBAY_MUX(0x2, "I2S3_M2"), + KEEMBAY_MUX(0x3, "SD1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "SPI1_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(18, "GPIO18", + KEEMBAY_MUX(0x0, "UART1_M0"), + KEEMBAY_MUX(0x1, "SPI0_M1"), + KEEMBAY_MUX(0x2, "I2S3_M2"), + KEEMBAY_MUX(0x3, "SD1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "SPI1_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(19, "GPIO19", + KEEMBAY_MUX(0x0, "UART1_M0"), + KEEMBAY_MUX(0x1, "LCD_M1"), + KEEMBAY_MUX(0x2, "DEBUG_M2"), + KEEMBAY_MUX(0x3, "SD1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "SPI1_M5"), + KEEMBAY_MUX(0x6, "LCD_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(20, "GPIO20", + KEEMBAY_MUX(0x0, "UART1_M0"), + KEEMBAY_MUX(0x1, "LCD_M1"), + KEEMBAY_MUX(0x2, "DEBUG_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "SPI1_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(21, "GPIO21", + KEEMBAY_MUX(0x0, "UART1_M0"), + KEEMBAY_MUX(0x1, "LCD_M1"), + KEEMBAY_MUX(0x2, "DEBUG_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C0_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(22, "GPIO22", + KEEMBAY_MUX(0x0, "I2C0_M0"), + KEEMBAY_MUX(0x1, "UART2_M1"), + KEEMBAY_MUX(0x2, "DEBUG_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C0_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(23, "GPIO23", + KEEMBAY_MUX(0x0, "I2C0_M0"), + KEEMBAY_MUX(0x1, "UART2_M1"), + KEEMBAY_MUX(0x2, "DEBUG_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C1_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(24, "GPIO24", + KEEMBAY_MUX(0x0, "I2C1_M0"), + KEEMBAY_MUX(0x1, "UART2_M1"), + KEEMBAY_MUX(0x2, "DEBUG_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C1_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(25, "GPIO25", + KEEMBAY_MUX(0x0, "I2C1_M0"), + KEEMBAY_MUX(0x1, "UART2_M1"), + KEEMBAY_MUX(0x2, "SPI0_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C2_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(26, "GPIO26", + KEEMBAY_MUX(0x0, "SPI0_M0"), + KEEMBAY_MUX(0x1, "I2C2_M1"), + KEEMBAY_MUX(0x2, "UART0_M2"), + KEEMBAY_MUX(0x3, "DSU_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C2_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(27, "GPIO27", + KEEMBAY_MUX(0x0, "SPI0_M0"), + KEEMBAY_MUX(0x1, "I2C2_M1"), + KEEMBAY_MUX(0x2, "UART0_M2"), + KEEMBAY_MUX(0x3, "DSU_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C0_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(28, "GPIO28", + KEEMBAY_MUX(0x0, "SPI0_M0"), + KEEMBAY_MUX(0x1, "I2C3_M1"), + KEEMBAY_MUX(0x2, "UART0_M2"), + KEEMBAY_MUX(0x3, "PWM_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C1_M5"), + KEEMBAY_MUX(0x6, "SLVDS0_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(29, "GPIO29", + KEEMBAY_MUX(0x0, "SPI0_M0"), + KEEMBAY_MUX(0x1, "I2C3_M1"), + KEEMBAY_MUX(0x2, "UART0_M2"), + KEEMBAY_MUX(0x3, "PWM_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I3C2_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(30, "GPIO30", + KEEMBAY_MUX(0x0, "SPI0_M0"), + KEEMBAY_MUX(0x1, "I2S0_M1"), + KEEMBAY_MUX(0x2, "I2C4_M2"), + KEEMBAY_MUX(0x3, "PWM_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(31, "GPIO31", + KEEMBAY_MUX(0x0, "SPI0_M0"), + KEEMBAY_MUX(0x1, "I2S0_M1"), + KEEMBAY_MUX(0x2, "I2C4_M2"), + KEEMBAY_MUX(0x3, "PWM_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "UART1_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(32, "GPIO32", + KEEMBAY_MUX(0x0, "SD0_M0"), + KEEMBAY_MUX(0x1, "SPI0_M1"), + KEEMBAY_MUX(0x2, "UART1_M2"), + KEEMBAY_MUX(0x3, "PWM_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "PCIE_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(33, "GPIO33", + KEEMBAY_MUX(0x0, "SD0_M0"), + KEEMBAY_MUX(0x1, "SPI0_M1"), + KEEMBAY_MUX(0x2, "UART1_M2"), + KEEMBAY_MUX(0x3, "PWM_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "PCIE_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(34, "GPIO34", + KEEMBAY_MUX(0x0, "SD0_M0"), + KEEMBAY_MUX(0x1, "SPI0_M1"), + KEEMBAY_MUX(0x2, "I2C0_M2"), + KEEMBAY_MUX(0x3, "UART1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I2S0_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(35, "GPIO35", + KEEMBAY_MUX(0x0, "SD0_M0"), + KEEMBAY_MUX(0x1, "PCIE_M1"), + KEEMBAY_MUX(0x2, "I2C0_M2"), + KEEMBAY_MUX(0x3, "UART1_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I2S0_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(36, "GPIO36", + KEEMBAY_MUX(0x0, "SD0_M0"), + KEEMBAY_MUX(0x1, "SPI3_M1"), + KEEMBAY_MUX(0x2, "I2C1_M2"), + KEEMBAY_MUX(0x3, "DEBUG_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I2S0_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(37, "GPIO37", + KEEMBAY_MUX(0x0, "SD0_M0"), + KEEMBAY_MUX(0x1, "SPI3_M1"), + KEEMBAY_MUX(0x2, "I2C1_M2"), + KEEMBAY_MUX(0x3, "DEBUG_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "I2S0_M5"), + KEEMBAY_MUX(0x6, "SLVDS1_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(38, "GPIO38", + KEEMBAY_MUX(0x0, "I3C1_M0"), + KEEMBAY_MUX(0x1, "SPI3_M1"), + KEEMBAY_MUX(0x2, "UART3_M2"), + KEEMBAY_MUX(0x3, "DEBUG_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2C2_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(39, "GPIO39", + KEEMBAY_MUX(0x0, "I3C1_M0"), + KEEMBAY_MUX(0x1, "SPI3_M1"), + KEEMBAY_MUX(0x2, "UART3_M2"), + KEEMBAY_MUX(0x3, "DEBUG_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2C2_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(40, "GPIO40", + KEEMBAY_MUX(0x0, "I2S2_M0"), + KEEMBAY_MUX(0x1, "SPI3_M1"), + KEEMBAY_MUX(0x2, "UART3_M2"), + KEEMBAY_MUX(0x3, "DEBUG_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2C3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(41, "GPIO41", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI3_M1"), + KEEMBAY_MUX(0x2, "SPI3_M2"), + KEEMBAY_MUX(0x3, "DEBUG_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2C3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(42, "GPIO42", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SD1_M1"), + KEEMBAY_MUX(0x2, "SPI3_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "CAM_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2C4_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(43, "GPIO43", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SD1_M1"), + KEEMBAY_MUX(0x2, "SPI3_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "I2S0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2C4_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(44, "GPIO44", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SD1_M1"), + KEEMBAY_MUX(0x2, "SPI0_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "I2S0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(45, "GPIO45", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SD1_M1"), + KEEMBAY_MUX(0x2, "SPI0_M2"), + KEEMBAY_MUX(0x3, "CPR_M3"), + KEEMBAY_MUX(0x4, "I2S0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(46, "GPIO46", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SD1_M1"), + KEEMBAY_MUX(0x2, "SPI0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(47, "GPIO47", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SD1_M1"), + KEEMBAY_MUX(0x2, "SPI0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(48, "GPIO48", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "UART2_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(49, "GPIO49", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "UART2_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(50, "GPIO50", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "UART2_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(51, "GPIO51", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "UART2_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(52, "GPIO52", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "SD0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(53, "GPIO53", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "SD0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S2_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(54, "GPIO54", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "SD0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S2_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(55, "GPIO55", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "SD1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S2_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(56, "GPIO56", + KEEMBAY_MUX(0x0, "ETH_M0"), + KEEMBAY_MUX(0x1, "SPI2_M1"), + KEEMBAY_MUX(0x2, "SD1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I2S2_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(57, "GPIO57", + KEEMBAY_MUX(0x0, "SPI1_M0"), + KEEMBAY_MUX(0x1, "I2S1_M1"), + KEEMBAY_MUX(0x2, "SD1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(58, "GPIO58", + KEEMBAY_MUX(0x0, "SPI1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SD0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(59, "GPIO59", + KEEMBAY_MUX(0x0, "SPI1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SD0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(60, "GPIO60", + KEEMBAY_MUX(0x0, "SPI1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "I3C1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(61, "GPIO61", + KEEMBAY_MUX(0x0, "SPI1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SD0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(62, "GPIO62", + KEEMBAY_MUX(0x0, "SPI1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SD1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(63, "GPIO63", + KEEMBAY_MUX(0x0, "I2S1_M0"), + KEEMBAY_MUX(0x1, "SPI1_M1"), + KEEMBAY_MUX(0x2, "SD1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(64, "GPIO64", + KEEMBAY_MUX(0x0, "I2S2_M0"), + KEEMBAY_MUX(0x1, "SPI1_M1"), + KEEMBAY_MUX(0x2, "ETH_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "UART1_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(65, "GPIO65", + KEEMBAY_MUX(0x0, "I3C0_M0"), + KEEMBAY_MUX(0x1, "SPI1_M1"), + KEEMBAY_MUX(0x2, "SD1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SPI0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(66, "GPIO66", + KEEMBAY_MUX(0x0, "I3C0_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "I2C0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SPI0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "CAM_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(67, "GPIO67", + KEEMBAY_MUX(0x0, "I3C1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "I2C0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SPI0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2S3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(68, "GPIO68", + KEEMBAY_MUX(0x0, "I3C1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "I2C1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SPI0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2S3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(69, "GPIO69", + KEEMBAY_MUX(0x0, "I3C2_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "I2C1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SPI0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2S3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(70, "GPIO70", + KEEMBAY_MUX(0x0, "I3C2_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SPI0_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SD0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2S3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(71, "GPIO71", + KEEMBAY_MUX(0x0, "I3C0_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SD0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "I2S3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(72, "GPIO72", + KEEMBAY_MUX(0x0, "I3C1_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SD0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART2_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(73, "GPIO73", + KEEMBAY_MUX(0x0, "I3C2_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SD0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART2_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(74, "GPIO74", + KEEMBAY_MUX(0x0, "I3C0_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SD0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART2_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(75, "GPIO75", + KEEMBAY_MUX(0x0, "I3C0_M0"), + KEEMBAY_MUX(0x1, "ETH_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "SD0_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART2_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(76, "GPIO76", + KEEMBAY_MUX(0x0, "I2C2_M0"), + KEEMBAY_MUX(0x1, "I3C0_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "ETH_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(77, "GPIO77", + KEEMBAY_MUX(0x0, "PCIE_M0"), + KEEMBAY_MUX(0x1, "I3C1_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I3C2_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(78, "GPIO78", + KEEMBAY_MUX(0x0, "PCIE_M0"), + KEEMBAY_MUX(0x1, "I3C2_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I3C2_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), + KEEMBAY_PIN_DESC(79, "GPIO79", + KEEMBAY_MUX(0x0, "PCIE_M0"), + KEEMBAY_MUX(0x1, "I2C2_M1"), + KEEMBAY_MUX(0x2, "SLVDS1_M2"), + KEEMBAY_MUX(0x3, "TPIU_M3"), + KEEMBAY_MUX(0x4, "I3C2_M4"), + KEEMBAY_MUX(0x5, "LCD_M5"), + KEEMBAY_MUX(0x6, "UART3_M6"), + KEEMBAY_MUX(0x7, "GPIO_M7")), +}; + +static inline u32 keembay_read_reg(void __iomem *base, unsigned int pin) +{ + return readl(base + KEEMBAY_GPIO_REG_OFFSET(pin)); +} + +static inline u32 keembay_read_gpio_reg(void __iomem *base, unsigned int pin) +{ + return keembay_read_reg(base, pin / KEEMBAY_GPIO_MAX_PER_REG); +} + +static inline u32 keembay_read_pin(void __iomem *base, unsigned int pin) +{ + u32 val = keembay_read_gpio_reg(base, pin); + + return !!(val & BIT(pin % KEEMBAY_GPIO_MAX_PER_REG)); +} + +static inline void keembay_write_reg(u32 val, void __iomem *base, unsigned int pin) +{ + writel(val, base + KEEMBAY_GPIO_REG_OFFSET(pin)); +} + +static inline void keembay_write_gpio_reg(u32 val, void __iomem *base, unsigned int pin) +{ + keembay_write_reg(val, base, pin / KEEMBAY_GPIO_MAX_PER_REG); +} + +static void keembay_gpio_invert(struct keembay_pinctrl *kpc, unsigned int pin) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + /* + * This IP doesn't support the falling edge and low level interrupt + * trigger. Invert API is used to mimic the falling edge and low + * level support + */ + + val |= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, KEEMBAY_GPIO_MODE_INV_VAL); + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); +} + +static void keembay_gpio_restore_default(struct keembay_pinctrl *kpc, unsigned int pin) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + val &= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, 0); + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); +} + +static int keembay_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int pin) +{ + struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); + unsigned int val; + + if (pin >= kpc->npins) + return -EINVAL; + + val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + val = FIELD_GET(KEEMBAY_GPIO_MODE_SELECT_MASK, val); + + /* As per Pin Mux Map, Modes 0 to 6 are for peripherals */ + if (val != KEEMBAY_GPIO_MODE_DEFAULT) + return -EBUSY; + + return 0; +} + +static int keembay_set_mux(struct pinctrl_dev *pctldev, unsigned int fun_sel, + unsigned int grp_sel) +{ + struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); + struct function_desc *func; + struct group_desc *grp; + unsigned int val; + u8 pin_mode; + int pin; + + grp = pinctrl_generic_get_group(pctldev, grp_sel); + if (!grp) + return -EINVAL; + + func = pinmux_generic_get_function(pctldev, fun_sel); + if (!func) + return -EINVAL; + + /* Change modes for pins in the selected group */ + pin = *grp->pins; + pin_mode = *(u8 *)(func->data); + + val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + val = u32_replace_bits(val, pin_mode, KEEMBAY_GPIO_MODE_SELECT_MASK); + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return 0; +} + +static u32 keembay_pinconf_get_pull(struct keembay_pinctrl *kpc, unsigned int pin) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return FIELD_GET(KEEMBAY_GPIO_MODE_PULLUP_MASK, val); +} + +static int keembay_pinconf_set_pull(struct keembay_pinctrl *kpc, unsigned int pin, + unsigned int pull) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + val = u32_replace_bits(val, pull, KEEMBAY_GPIO_MODE_PULLUP_MASK); + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return 0; +} + +static int keembay_pinconf_get_drive(struct keembay_pinctrl *kpc, unsigned int pin) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + val = FIELD_GET(KEEMBAY_GPIO_MODE_DRIVE_MASK, val) * 4; + if (val) + return val; + + return KEEMBAY_GPIO_MIN_STRENGTH; +} + +static int keembay_pinconf_set_drive(struct keembay_pinctrl *kpc, unsigned int pin, + unsigned int drive) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + unsigned int strength = clamp_val(drive, KEEMBAY_GPIO_MIN_STRENGTH, + KEEMBAY_GPIO_MAX_STRENGTH) / 4; + + val = u32_replace_bits(val, strength, KEEMBAY_GPIO_MODE_DRIVE_MASK); + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return 0; +} + +static int keembay_pinconf_get_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return !!(val & KEEMBAY_GPIO_MODE_SLEW_RATE); +} + +static int keembay_pinconf_set_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin, + unsigned int slew_rate) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + if (slew_rate) + val |= KEEMBAY_GPIO_MODE_SLEW_RATE; + else + val &= ~KEEMBAY_GPIO_MODE_SLEW_RATE; + + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return 0; +} + +static int keembay_pinconf_get_schmitt(struct keembay_pinctrl *kpc, unsigned int pin) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return !!(val & KEEMBAY_GPIO_MODE_SCHMITT_EN); +} + +static int keembay_pinconf_set_schmitt(struct keembay_pinctrl *kpc, unsigned int pin, + unsigned int schmitt_en) +{ + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + if (schmitt_en) + val |= KEEMBAY_GPIO_MODE_SCHMITT_EN; + else + val &= ~KEEMBAY_GPIO_MODE_SCHMITT_EN; + + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return 0; +} + +static int keembay_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *cfg) +{ + struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*cfg); + unsigned int val; + + if (pin >= kpc->npins) + return -EINVAL; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_DISABLE) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_UP) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_DOWN) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_BUS_HOLD: + if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_BUS_HOLD) + return -EINVAL; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!keembay_pinconf_get_schmitt(kpc, pin)) + return -EINVAL; + break; + + case PIN_CONFIG_SLEW_RATE: + val = keembay_pinconf_get_slew_rate(kpc, pin); + *cfg = pinconf_to_config_packed(param, val); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + val = keembay_pinconf_get_drive(kpc, pin); + *cfg = pinconf_to_config_packed(param, val); + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + +static int keembay_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *cfg, unsigned int num_configs) +{ + struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + unsigned int arg, i; + int ret = 0; + + if (pin >= kpc->npins) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(cfg[i]); + arg = pinconf_to_config_argument(cfg[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_DISABLE); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_UP); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_DOWN); + break; + + case PIN_CONFIG_BIAS_BUS_HOLD: + ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_BUS_HOLD); + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + ret = keembay_pinconf_set_schmitt(kpc, pin, arg); + break; + + case PIN_CONFIG_SLEW_RATE: + ret = keembay_pinconf_set_slew_rate(kpc, pin, arg); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = keembay_pinconf_set_drive(kpc, pin, arg); + break; + + default: + return -ENOTSUPP; + } + if (ret) + return ret; + } + return ret; +} + +static const struct pinctrl_ops keembay_pctlops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static const struct pinmux_ops keembay_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .gpio_request_enable = keembay_request_gpio, + .set_mux = keembay_set_mux, +}; + +static const struct pinconf_ops keembay_confops = { + .is_generic = true, + .pin_config_get = keembay_pinconf_get, + .pin_config_set = keembay_pinconf_set, +}; + +static struct pinctrl_desc keembay_pinctrl_desc = { + .name = "keembay-pinmux", + .pctlops = &keembay_pctlops, + .pmxops = &keembay_pmxops, + .confops = &keembay_confops, + .owner = THIS_MODULE, +}; + +static int keembay_gpio_get(struct gpio_chip *gc, unsigned int pin) +{ + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + unsigned int val, offset; + + val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + offset = (val & KEEMBAY_GPIO_MODE_DIR) ? KEEMBAY_GPIO_DATA_IN : KEEMBAY_GPIO_DATA_OUT; + + return keembay_read_pin(kpc->base0 + offset, pin); +} + +static void keembay_gpio_set(struct gpio_chip *gc, unsigned int pin, int val) +{ + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + unsigned int reg_val; + + reg_val = keembay_read_gpio_reg(kpc->base0 + KEEMBAY_GPIO_DATA_OUT, pin); + if (val) + keembay_write_gpio_reg(reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG), + kpc->base0 + KEEMBAY_GPIO_DATA_HIGH, pin); + else + keembay_write_gpio_reg(~reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG), + kpc->base0 + KEEMBAY_GPIO_DATA_LOW, pin); +} + +static int keembay_gpio_get_direction(struct gpio_chip *gc, unsigned int pin) +{ + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return !!(val & KEEMBAY_GPIO_MODE_DIR); +} + +static int keembay_gpio_set_direction_in(struct gpio_chip *gc, unsigned int pin) +{ + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + unsigned int val; + + val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + val |= KEEMBAY_GPIO_MODE_DIR; + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); + + return 0; +} + +static int keembay_gpio_set_direction_out(struct gpio_chip *gc, + unsigned int pin, int value) +{ + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + unsigned int val; + + val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); + val &= ~KEEMBAY_GPIO_MODE_DIR; + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); + keembay_gpio_set(gc, pin, value); + + return 0; +} + +static void keembay_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + unsigned int kmb_irq = irq_desc_get_irq(desc); + unsigned long reg, clump = 0, bit = 0; + struct irq_chip *parent_chip; + struct keembay_pinctrl *kpc; + unsigned int src, pin, val; + + /* Identify GPIO interrupt number from GIC interrupt number */ + for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) { + if (kmb_irq == gc->irq.parents[src]) + break; + } + + if (src == KEEMBAY_GPIO_NUM_IRQ) + return; + + parent_chip = irq_desc_get_chip(desc); + kpc = gpiochip_get_data(gc); + + chained_irq_enter(parent_chip, desc); + reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); + + /* + * Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit + * and input values were checked to identify the source of the + * Interrupt. The checked enable bit positions are 7, 15, 23 and 31. + */ + for_each_set_clump8(bit, clump, ®, BITS_PER_TYPE(typeof(reg))) { + pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE; + val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin); + kmb_irq = irq_linear_revmap(gc->irq.domain, pin); + + /* Checks if the interrupt is enabled */ + if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE)) + generic_handle_irq(kmb_irq); + } + chained_irq_exit(parent_chip, desc); +} + +static void keembay_gpio_clear_irq(struct irq_data *data, unsigned long pos, + u32 src, irq_hw_number_t pin) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + unsigned long trig = irqd_get_trigger_type(data); + struct keembay_gpio_irq *irq = &kpc->irq[src]; + unsigned long val; + + /* Check if the value of pos/KEEMBAY_GPIO_NUM_IRQ is in valid range. */ + if ((pos / KEEMBAY_GPIO_NUM_IRQ) >= KEEMBAY_GPIO_MAX_PER_IRQ) + return; + + /* Retains val register as it handles other interrupts as well. */ + val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); + + bitmap_set_value8(&val, 0, pos); + keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); + + irq->num_share--; + irq->pins[pos / KEEMBAY_GPIO_NUM_IRQ] = 0; + + if (trig & IRQ_TYPE_LEVEL_MASK) + keembay_gpio_restore_default(kpc, pin); + + if (irq->trigger == IRQ_TYPE_LEVEL_HIGH) + kpc->max_gpios_level_type++; + else if (irq->trigger == IRQ_TYPE_EDGE_RISING) + kpc->max_gpios_edge_type++; +} + +static int keembay_find_free_slot(struct keembay_pinctrl *kpc, unsigned int src) +{ + unsigned long val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); + + return bitmap_find_free_region(&val, KEEMBAY_GPIO_MAX_PER_REG, 3) / KEEMBAY_GPIO_NUM_IRQ; +} + +static int keembay_find_free_src(struct keembay_pinctrl *kpc, unsigned int trig) +{ + int src, type = 0; + + if (trig & IRQ_TYPE_LEVEL_MASK) + type = IRQ_TYPE_LEVEL_HIGH; + else if (trig & IRQ_TYPE_EDGE_BOTH) + type = IRQ_TYPE_EDGE_RISING; + + for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) { + if (kpc->irq[src].trigger != type) + continue; + + if (!keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src) || + kpc->irq[src].num_share < KEEMBAY_GPIO_MAX_PER_IRQ) + return src; + } + + return -EBUSY; +} + +static void keembay_gpio_set_irq(struct keembay_pinctrl *kpc, int src, + int slot, irq_hw_number_t pin) +{ + unsigned long val = pin | KEEMBAY_GPIO_IRQ_ENABLE; + struct keembay_gpio_irq *irq = &kpc->irq[src]; + unsigned long flags, reg; + + raw_spin_lock_irqsave(&kpc->lock, flags); + reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); + bitmap_set_value8(®, val, slot * 8); + keembay_write_reg(reg, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); + raw_spin_unlock_irqrestore(&kpc->lock, flags); + + if (irq->trigger == IRQ_TYPE_LEVEL_HIGH) + kpc->max_gpios_level_type--; + else if (irq->trigger == IRQ_TYPE_EDGE_RISING) + kpc->max_gpios_edge_type--; + + irq->source = src; + irq->pins[slot] = pin; + irq->num_share++; +} + +static void keembay_gpio_irq_enable(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + unsigned int trig = irqd_get_trigger_type(data); + irq_hw_number_t pin = irqd_to_hwirq(data); + int src, slot; + + /* Check which Interrupt source and slot is available */ + src = keembay_find_free_src(kpc, trig); + slot = keembay_find_free_slot(kpc, src); + + if (src < 0 || slot < 0) + return; + + if (trig & KEEMBAY_GPIO_SENSE_LOW) + keembay_gpio_invert(kpc, pin); + + keembay_gpio_set_irq(kpc, src, slot, pin); +} + +static void keembay_gpio_irq_ack(struct irq_data *data) +{ + /* + * The keembay_gpio_irq_ack function is needed to handle_edge_irq. + * IRQ ack is not possible from the SOC perspective. The IP by itself + * is used for handling interrupts which do not come in short-time and + * not used as protocol or communication interrupts. All the interrupts + * are threaded IRQ interrupts. But this function is expected to be + * present as the gpio IP is registered with irq framework. Otherwise + * handle_edge_irq() fails. + */ +} + +static void keembay_gpio_irq_disable(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + irq_hw_number_t pin = irqd_to_hwirq(data); + unsigned long reg, clump = 0, pos = 0; + unsigned int src; + + for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) { + reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); + for_each_set_clump8(pos, clump, ®, BITS_PER_TYPE(typeof(reg))) { + if ((clump & ~KEEMBAY_GPIO_IRQ_ENABLE) == pin) { + keembay_gpio_clear_irq(data, pos, src, pin); + return; + } + } + } +} + +static int keembay_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct keembay_pinctrl *kpc = gpiochip_get_data(gc); + + /* Change EDGE_BOTH as EDGE_RISING in order to claim the IRQ for power button */ + if (!kpc->max_gpios_edge_type && (type & IRQ_TYPE_EDGE_BOTH)) + type = IRQ_TYPE_EDGE_RISING; + + if (!kpc->max_gpios_level_type && (type & IRQ_TYPE_LEVEL_MASK)) + type = IRQ_TYPE_NONE; + + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(data, handle_edge_irq); + else if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(data, handle_level_irq); + else + return -EINVAL; + + return 0; +} + +static int keembay_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + struct keembay_pinctrl *kpc = gpiochip_get_data(chip); + int ret; + + ret = gpiochip_add_pin_range(chip, dev_name(kpc->dev), 0, 0, chip->ngpio); + if (ret) + dev_err_probe(kpc->dev, ret, "failed to add GPIO pin range\n"); + return ret; +} + +static struct irq_chip keembay_gpio_irqchip = { + .name = "keembay-gpio", + .irq_enable = keembay_gpio_irq_enable, + .irq_disable = keembay_gpio_irq_disable, + .irq_set_type = keembay_gpio_irq_set_type, + .irq_ack = keembay_gpio_irq_ack, +}; + +static int keembay_gpiochip_probe(struct keembay_pinctrl *kpc, + struct platform_device *pdev) +{ + unsigned int i, level_line = 0, edge_line = 0; + struct gpio_chip *gc = &kpc->chip; + struct gpio_irq_chip *girq; + + /* Setup GPIO IRQ chip */ + girq = &kpc->chip.irq; + girq->chip = &keembay_gpio_irqchip; + girq->parent_handler = keembay_gpio_irq_handler; + girq->num_parents = KEEMBAY_GPIO_NUM_IRQ; + girq->parents = devm_kcalloc(kpc->dev, girq->num_parents, + sizeof(*girq->parents), GFP_KERNEL); + + if (!girq->parents) + return -ENOMEM; + + /* Setup GPIO chip */ + gc->label = dev_name(kpc->dev); + gc->parent = kpc->dev; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->get_direction = keembay_gpio_get_direction; + gc->direction_input = keembay_gpio_set_direction_in; + gc->direction_output = keembay_gpio_set_direction_out; + gc->get = keembay_gpio_get; + gc->set = keembay_gpio_set; + gc->set_config = gpiochip_generic_config; + gc->base = -1; + gc->ngpio = kpc->npins; + gc->add_pin_ranges = keembay_gpio_add_pin_ranges; + + for (i = 0; i < KEEMBAY_GPIO_NUM_IRQ; i++) { + struct keembay_gpio_irq *kmb_irq = &kpc->irq[i]; + int irq; + + irq = platform_get_irq_optional(pdev, i); + if (irq <= 0) + continue; + + girq->parents[i] = irq; + kmb_irq->line = girq->parents[i]; + kmb_irq->source = i; + kmb_irq->trigger = irq_get_trigger_type(girq->parents[i]); + kmb_irq->num_share = 0; + + if (kmb_irq->trigger == IRQ_TYPE_LEVEL_HIGH) + level_line++; + else + edge_line++; + } + + kpc->max_gpios_level_type = level_line * KEEMBAY_GPIO_MAX_PER_IRQ; + kpc->max_gpios_edge_type = edge_line * KEEMBAY_GPIO_MAX_PER_IRQ; + + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + return devm_gpiochip_add_data(kpc->dev, gc, kpc); +} + +static int keembay_build_groups(struct keembay_pinctrl *kpc) +{ + struct group_desc *grp; + unsigned int i; + + kpc->ngroups = kpc->npins; + grp = devm_kcalloc(kpc->dev, kpc->ngroups, sizeof(*grp), GFP_KERNEL); + if (!grp) + return -ENOMEM; + + /* Each pin is categorised as one group */ + for (i = 0; i < kpc->ngroups; i++) { + const struct pinctrl_pin_desc *pdesc = keembay_pins + i; + struct group_desc *kmb_grp = grp + i; + + kmb_grp->name = pdesc->name; + kmb_grp->pins = (int *)&pdesc->number; + pinctrl_generic_add_group(kpc->pctrl, kmb_grp->name, + kmb_grp->pins, 1, NULL); + } + + return 0; +} + +static int keembay_pinctrl_reg(struct keembay_pinctrl *kpc, struct device *dev) +{ + int ret; + + keembay_pinctrl_desc.pins = keembay_pins; + ret = of_property_read_u32(dev->of_node, "ngpios", &kpc->npins); + if (ret < 0) + return ret; + keembay_pinctrl_desc.npins = kpc->npins; + + kpc->pctrl = devm_pinctrl_register(kpc->dev, &keembay_pinctrl_desc, kpc); + + return PTR_ERR_OR_ZERO(kpc->pctrl); +} + +static int keembay_add_functions(struct keembay_pinctrl *kpc, + struct function_desc *function) +{ + unsigned int i; + + /* Assign the groups for each function */ + for (i = 0; i < kpc->npins; i++) { + const struct pinctrl_pin_desc *pdesc = keembay_pins + i; + struct keembay_mux_desc *mux = pdesc->drv_data; + + while (mux->name) { + struct function_desc *func; + const char **grp; + size_t grp_size; + u32 j, grp_num; + + for (j = 0; j < kpc->nfuncs; j++) { + if (!strcmp(mux->name, function[j].name)) + break; + } + + if (j == kpc->nfuncs) + return -EINVAL; + + func = function + j; + grp_num = func->num_group_names; + grp_size = sizeof(*func->group_names); + + if (!func->group_names) { + func->group_names = devm_kcalloc(kpc->dev, + grp_num, + grp_size, + GFP_KERNEL); + if (!func->group_names) + return -ENOMEM; + } + + grp = func->group_names; + while (*grp) + grp++; + + *grp = pdesc->name; + mux++; + } + } + + /* Add all functions */ + for (i = 0; i < kpc->nfuncs; i++) { + pinmux_generic_add_function(kpc->pctrl, + function[i].name, + function[i].group_names, + function[i].num_group_names, + function[i].data); + } + + return 0; +} + +static int keembay_build_functions(struct keembay_pinctrl *kpc) +{ + struct function_desc *keembay_funcs, *new_funcs; + int i; + + /* Allocate total number of functions */ + kpc->nfuncs = 0; + keembay_funcs = kcalloc(kpc->npins * 8, sizeof(*keembay_funcs), GFP_KERNEL); + if (!keembay_funcs) + return -ENOMEM; + + /* Find total number of functions and each's properties */ + for (i = 0; i < kpc->npins; i++) { + const struct pinctrl_pin_desc *pdesc = keembay_pins + i; + struct keembay_mux_desc *mux = pdesc->drv_data; + + while (mux->name) { + struct function_desc *fdesc = keembay_funcs; + + while (fdesc->name) { + if (!strcmp(mux->name, fdesc->name)) { + fdesc->num_group_names++; + break; + } + + fdesc++; + } + + if (!fdesc->name) { + fdesc->name = mux->name; + fdesc->num_group_names = 1; + fdesc->data = &mux->mode; + kpc->nfuncs++; + } + + mux++; + } + } + + /* Reallocate memory based on actual number of functions */ + new_funcs = krealloc(keembay_funcs, kpc->nfuncs * sizeof(*new_funcs), GFP_KERNEL); + if (!new_funcs) { + kfree(keembay_funcs); + return -ENOMEM; + } + + return keembay_add_functions(kpc, new_funcs); +} + +static const struct keembay_pin_soc keembay_data = { + .pins = keembay_pins, +}; + +static const struct of_device_id keembay_pinctrl_match[] = { + { .compatible = "intel,keembay-pinctrl", .data = &keembay_data }, + { } +}; +MODULE_DEVICE_TABLE(of, keembay_pinctrl_match); + +static int keembay_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct keembay_pinctrl *kpc; + int ret; + + kpc = devm_kzalloc(dev, sizeof(*kpc), GFP_KERNEL); + if (!kpc) + return -ENOMEM; + + kpc->dev = dev; + kpc->soc = device_get_match_data(dev); + + kpc->base0 = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(kpc->base0)) + return PTR_ERR(kpc->base0); + + kpc->base1 = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(kpc->base1)) + return PTR_ERR(kpc->base1); + + raw_spin_lock_init(&kpc->lock); + + ret = keembay_pinctrl_reg(kpc, dev); + if (ret) + return ret; + + ret = keembay_build_groups(kpc); + if (ret) + return ret; + + ret = keembay_build_functions(kpc); + if (ret) + return ret; + + ret = keembay_gpiochip_probe(kpc, pdev); + if (ret) + return ret; + + platform_set_drvdata(pdev, kpc); + + return 0; +} + +static struct platform_driver keembay_pinctrl_driver = { + .probe = keembay_pinctrl_probe, + .driver = { + .name = "keembay-pinctrl", + .of_match_table = keembay_pinctrl_match, + }, +}; +module_platform_driver(keembay_pinctrl_driver); + +MODULE_AUTHOR("Muhammad Husaini Zulkifli "); +MODULE_AUTHOR("Vijayakannan Ayyathurai "); +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_DESCRIPTION("Intel Keem Bay SoC pinctrl/GPIO driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From cdd3d945dcec0d0dab845175dc9400ab54512aa6 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 11 Aug 2021 14:48:22 +0300 Subject: pinctrl: samsung: Add Exynos850 SoC specific data Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20210811114827.27322-3-semen.protsenko@linaro.org [krzysztof: lower-case the hex-numbers] Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 116 +++++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 29 +++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 148 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b6e56422a700..fe5f6046fbd5 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), + EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), + EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), + EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), + EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { + .ctrl = exynos850_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index da1ec13697e7..bfad1ced8017 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -108,6 +108,35 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2975b4369f32..2a0fc63516f1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos850-pinctrl", + .data = &exynos850_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index de44f8ec330b..4c2149e9c544 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; -- cgit v1.2.3 From c4c4637eb57f2a25c445421aadeb689a2538b20b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 27 Jul 2021 12:23:26 +0100 Subject: pinctrl: renesas: Add RZ/G2L pin and gpio controller driver Add support for pin and gpio controller driver for RZ/G2L SoC. Based on a patch in the BSP by Hien Huynh . Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210727112328.18809-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/Kconfig | 11 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1175 +++++++++++++++++++++++++++++++ 3 files changed, 1187 insertions(+) create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 4b84a744ae87..9a72999084b3 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -37,6 +37,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77990 if ARCH_R8A77990 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 + select PINCTRL_RZG2L if ARCH_R9A07G044 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 @@ -176,6 +177,16 @@ config PINCTRL_RZA2 help This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. +config PINCTRL_RZG2L + bool "pin control support for RZ/G2L" if COMPILE_TEST + depends on OF + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms. + config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST select PINCTRL_SH_PFC diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 353563228dc2..7d9238a9ef57 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o +obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o ifeq ($(CONFIG_COMPILE_TEST),y) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c new file mode 100644 index 000000000000..dbf2f521bb27 --- /dev/null +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -0,0 +1,1175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L Pin Control and GPIO driver core + * + * Copyright (C) 2021 Renesas Electronics Corporation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#define DRV_NAME "pinctrl-rzg2l" + +/* + * Use 16 lower bits [15:0] for pin identifier + * Use 16 higher bits [31:16] for pin mux function + */ +#define MUX_PIN_ID_MASK GENMASK(15, 0) +#define MUX_FUNC_MASK GENMASK(31, 16) +#define MUX_FUNC_OFFS 16 +#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) + +/* PIN capabilities */ +#define PIN_CFG_IOLH BIT(0) +#define PIN_CFG_SR BIT(1) +#define PIN_CFG_IEN BIT(2) +#define PIN_CFG_PUPD BIT(3) +#define PIN_CFG_IOLH_SD0 BIT(4) +#define PIN_CFG_IOLH_SD1 BIT(5) +#define PIN_CFG_IOLH_QSPI BIT(6) +#define PIN_CFG_IOLH_ETH0 BIT(7) +#define PIN_CFG_IOLH_ETH1 BIT(8) +#define PIN_CFG_FILONOFF BIT(9) +#define PIN_CFG_FILNUM BIT(10) +#define PIN_CFG_FILCLKSEL BIT(11) + +#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \ + PIN_CFG_SR | \ + PIN_CFG_PUPD | \ + PIN_CFG_FILONOFF | \ + PIN_CFG_FILNUM | \ + PIN_CFG_FILCLKSEL) + +#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ + PIN_CFG_FILONOFF | \ + PIN_CFG_FILNUM | \ + PIN_CFG_FILCLKSEL) + +/* + * n indicates number of pins in the port, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) +#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) +#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) + +/* + * BIT(31) indicates dedicated pin, p is the register index while + * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits + * (b * 8) and f is the pin configuration capabilities supported. + */ +#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ + ((p) << 24) | ((b) << 20) | (f)) +#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) & GENMASK(30, 24)) >> 24) +#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) +#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) + +#define P(n) (0x0000 + 0x10 + (n)) +#define PM(n) (0x0100 + 0x20 + (n) * 2) +#define PMC(n) (0x0200 + 0x10 + (n)) +#define PFC(n) (0x0400 + 0x40 + (n) * 4) +#define PIN(n) (0x0800 + 0x10 + (n)) +#define IEN(n) (0x1800 + (n) * 8) +#define PWPR (0x3014) +#define SD_CH(n) (0x3000 + (n) * 4) +#define QSPI (0x3008) + +#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ + +#define PWPR_B0WI BIT(7) /* Bit Write Disable */ +#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ + +#define PM_MASK 0x03 +#define PVDD_MASK 0x01 +#define PFC_MASK 0x07 +#define IEN_MASK 0x01 + +#define PM_INPUT 0x1 +#define PM_OUTPUT 0x2 + +#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) +#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) + +struct rzg2l_dedicated_configs { + const char *name; + u32 config; +}; + +struct rzg2l_pinctrl_data { + const char * const *port_pins; + const u32 *port_pin_configs; + struct rzg2l_dedicated_configs *dedicated_pins; + unsigned int n_port_pins; + unsigned int n_dedicated_pins; +}; + +struct rzg2l_pinctrl { + struct pinctrl_dev *pctl; + struct pinctrl_desc desc; + struct pinctrl_pin_desc *pins; + + const struct rzg2l_pinctrl_data *data; + void __iomem *base; + struct device *dev; + struct clk *clk; + + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range gpio_range; + + spinlock_t lock; +}; + +static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, + u8 port, u8 pin, u8 func) +{ + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* Set pin to 'Non-use (Hi-Z input protection)' */ + reg = readw(pctrl->base + PM(port)); + reg &= ~(PM_MASK << (pin * 2)); + writew(reg, pctrl->base + PM(port)); + + /* Temporarily switch to GPIO mode with PMC register */ + reg = readb(pctrl->base + PMC(port)); + writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); + + /* Set the PWPR register to allow PFC register to write */ + writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ + writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ + + /* Select Pin function mode with PFC register */ + reg = readl(pctrl->base + PFC(port)); + reg &= ~(PFC_MASK << (pin * 4)); + writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); + + /* Set the PWPR register to be write-protected */ + writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ + writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ + + /* Switch to Peripheral pin function with PMC register */ + reg = readb(pctrl->base + PMC(port)); + writeb(reg | BIT(pin), pctrl->base + PMC(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); +}; + +static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct function_desc *func; + unsigned int i, *psel_val; + struct group_desc *group; + int *pins; + + func = pinmux_generic_get_function(pctldev, func_selector); + if (!func) + return -EINVAL; + group = pinctrl_generic_get_group(pctldev, group_selector); + if (!group) + return -EINVAL; + + psel_val = func->data; + pins = group->pins; + + for (i = 0; i < group->num_pins; i++) { + dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", + RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), + psel_val[i]); + rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), + RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); + } + + return 0; +}; + +static int rzg2l_map_add_config(struct pinctrl_map *map, + const char *group_or_pin, + enum pinctrl_map_type type, + unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *cfgs; + + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), + GFP_KERNEL); + if (!cfgs) + return -ENOMEM; + + map->type = type; + map->data.configs.group_or_pin = group_or_pin; + map->data.configs.configs = cfgs; + map->data.configs.num_configs = num_configs; + + return 0; +} + +static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps, + unsigned int *index) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pinctrl_map *maps = *map; + unsigned int nmaps = *num_maps; + unsigned long *configs = NULL; + unsigned int *pins, *psel_val; + unsigned int num_pinmux = 0; + unsigned int idx = *index; + unsigned int num_pins, i; + unsigned int num_configs; + struct property *pinmux; + struct property *prop; + int ret, gsel, fsel; + const char **pin_fn; + const char *pin; + + pinmux = of_find_property(np, "pinmux", NULL); + if (pinmux) + num_pinmux = pinmux->length / sizeof(u32); + + ret = of_property_count_strings(np, "pins"); + if (ret == -EINVAL) { + num_pins = 0; + } else if (ret < 0) { + dev_err(pctrl->dev, "Invalid pins list in DT\n"); + return ret; + } else { + num_pins = ret; + } + + if (!num_pinmux && !num_pins) + return 0; + + if (num_pinmux && num_pins) { + dev_err(pctrl->dev, + "DT node must contain either a pinmux or pins and not both\n"); + return -EINVAL; + } + + ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); + if (ret < 0) + return ret; + + if (num_pins && !num_configs) { + dev_err(pctrl->dev, "DT node must contain a config\n"); + ret = -ENODEV; + goto done; + } + + if (num_pinmux) + nmaps += 1; + + if (num_pins) + nmaps += num_pins; + + maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); + if (!maps) { + ret = -ENOMEM; + goto done; + } + + *map = maps; + *num_maps = nmaps; + if (num_pins) { + of_property_for_each_string(np, "pins", prop, pin) { + ret = rzg2l_map_add_config(&maps[idx], pin, + PIN_MAP_TYPE_CONFIGS_PIN, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + ret = 0; + goto done; + } + + pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); + psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), + GFP_KERNEL); + pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); + if (!pins || !psel_val || !pin_fn) { + ret = -ENOMEM; + goto done; + } + + /* Collect pin locations and mux settings from DT properties */ + for (i = 0; i < num_pinmux; ++i) { + u32 value; + + ret = of_property_read_u32_index(np, "pinmux", i, &value); + if (ret) + goto done; + pins[i] = value & MUX_PIN_ID_MASK; + psel_val[i] = MUX_FUNC(value); + } + + /* Register a single pin group listing all the pins we read from DT */ + gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); + if (gsel < 0) { + ret = gsel; + goto done; + } + + /* + * Register a single group function where the 'data' is an array PSEL + * register values read from DT. + */ + pin_fn[0] = np->name; + fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, + psel_val); + if (fsel < 0) { + ret = fsel; + goto remove_group; + } + + maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; + maps[idx].data.mux.group = np->name; + maps[idx].data.mux.function = np->name; + idx++; + + dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); + ret = 0; + goto done; + +remove_group: + pinctrl_generic_remove_group(pctldev, gsel); +done: + *index = idx; + kfree(configs); + return ret; +} + +static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + unsigned int i; + + if (!map) + return; + + for (i = 0; i < num_maps; ++i) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || + map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + } + kfree(map); +} + +static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device_node *child; + unsigned int index; + int ret; + + *map = NULL; + *num_maps = 0; + index = 0; + + for_each_child_of_node(np, child) { + ret = rzg2l_dt_subnode_to_map(pctldev, child, map, + num_maps, &index); + if (ret < 0) { + of_node_put(child); + goto done; + } + } + + if (*num_maps == 0) { + ret = rzg2l_dt_subnode_to_map(pctldev, np, map, + num_maps, &index); + if (ret < 0) + goto done; + } + + if (*num_maps) + return 0; + + dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); + ret = -EINVAL; + +done: + if (ret < 0) + rzg2l_dt_free_map(pctldev, *map, *num_maps); + + return ret; +} + +static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int _pin, + unsigned long *config) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; + unsigned int *pin_data = pin->drv_data; + unsigned int arg = 0; + unsigned long flags; + void __iomem *addr; + u32 port = 0, reg; + u32 cfg = 0; + u8 bit = 0; + + if (!pin_data) + return -EINVAL; + + if (*pin_data & RZG2L_SINGLE_PIN) { + port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); + bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + } + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: + if (!(cfg & PIN_CFG_IEN)) + return -EINVAL; + spin_lock_irqsave(&pctrl->lock, flags); + /* handle _L/_H for 32-bit register read/write */ + addr = pctrl->base + IEN(port); + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + reg = readl(addr) & (IEN_MASK << (bit * 8)); + arg = (reg >> (bit * 8)) & 0x1; + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + + case PIN_CONFIG_POWER_SOURCE: { + u32 pwr_reg = 0x0; + + if (cfg & PIN_CFG_IOLH_SD0) + pwr_reg = SD_CH(0); + else if (cfg & PIN_CFG_IOLH_SD1) + pwr_reg = SD_CH(1); + else if (cfg & PIN_CFG_IOLH_QSPI) + pwr_reg = QSPI; + else + return -EINVAL; + + spin_lock_irqsave(&pctrl->lock, flags); + addr = pctrl->base + pwr_reg; + arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + } + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +}; + +static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int _pin, + unsigned long *_configs, + unsigned int num_configs) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; + unsigned int *pin_data = pin->drv_data; + enum pin_config_param param; + unsigned long flags; + void __iomem *addr; + u32 port = 0, reg; + unsigned int i; + u32 cfg = 0; + u8 bit = 0; + + if (!pin_data) + return -EINVAL; + + if (*pin_data & RZG2L_SINGLE_PIN) { + port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); + bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + } + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(_configs[i]); + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: { + unsigned int arg = + pinconf_to_config_argument(_configs[i]); + + if (!(cfg & PIN_CFG_IEN)) + return -EINVAL; + + /* handle _L/_H for 32-bit register read/write */ + addr = pctrl->base + IEN(port); + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + spin_lock_irqsave(&pctrl->lock, flags); + reg = readl(addr) & ~(IEN_MASK << (bit * 8)); + writel(reg | (arg << (bit * 8)), addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + } + + case PIN_CONFIG_POWER_SOURCE: { + unsigned int mV = pinconf_to_config_argument(_configs[i]); + u32 pwr_reg = 0x0; + + if (mV != 1800 && mV != 3300) + return -EINVAL; + + if (cfg & PIN_CFG_IOLH_SD0) + pwr_reg = SD_CH(0); + else if (cfg & PIN_CFG_IOLH_SD1) + pwr_reg = SD_CH(1); + else if (cfg & PIN_CFG_IOLH_QSPI) + pwr_reg = QSPI; + else + return -EINVAL; + + addr = pctrl->base + pwr_reg; + spin_lock_irqsave(&pctrl->lock, flags); + writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + } + default: + return -EOPNOTSUPP; + } + } + + return 0; +} + +static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int i, npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +}; + +static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + const unsigned int *pins; + unsigned int i, npins, prev_config = 0; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); + if (ret) + return ret; + + /* Check config matching between to pin */ + if (i && prev_config != *config) + return -EOPNOTSUPP; + + prev_config = *config; + } + + return 0; +}; + +static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = rzg2l_dt_node_to_map, + .dt_free_map = rzg2l_dt_free_map, +}; + +static const struct pinmux_ops rzg2l_pinctrl_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = rzg2l_pinctrl_set_mux, + .strict = true, +}; + +static const struct pinconf_ops rzg2l_pinctrl_confops = { + .is_generic = true, + .pin_config_get = rzg2l_pinctrl_pinconf_get, + .pin_config_set = rzg2l_pinctrl_pinconf_set, + .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, + .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + unsigned long flags; + u8 reg8; + int ret; + + ret = pinctrl_gpio_request(chip->base + offset); + if (ret) + return ret; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* Select GPIO mode in PMC Register */ + reg8 = readb(pctrl->base + PMC(port)); + reg8 &= ~BIT(bit); + writeb(reg8, pctrl->base + PMC(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, + u8 bit, bool output) +{ + unsigned long flags; + u16 reg16; + + spin_lock_irqsave(&pctrl->lock, flags); + + reg16 = readw(pctrl->base + PM(port)); + reg16 &= ~(PM_MASK << (bit * 2)); + + reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); + writew(reg16, pctrl->base + PM(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + + if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { + u16 reg16; + + reg16 = readw(pctrl->base + PM(port)); + reg16 = (reg16 >> (bit * 2)) & PM_MASK; + if (reg16 == PM_OUTPUT) + return GPIO_LINE_DIRECTION_OUT; + } + + return GPIO_LINE_DIRECTION_IN; +} + +static int rzg2l_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + + rzg2l_gpio_set_direction(pctrl, port, bit, false); + + return 0; +} + +static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + unsigned long flags; + u8 reg8; + + spin_lock_irqsave(&pctrl->lock, flags); + + reg8 = readb(pctrl->base + P(port)); + + if (value) + writeb(reg8 | BIT(bit), pctrl->base + P(port)); + else + writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int rzg2l_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + + rzg2l_gpio_set(chip, offset, value); + rzg2l_gpio_set_direction(pctrl, port, bit, true); + + return 0; +} + +static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + u16 reg16; + + reg16 = readw(pctrl->base + PM(port)); + reg16 = (reg16 >> (bit * 2)) & PM_MASK; + + if (reg16 == PM_INPUT) + return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); + else if (reg16 == PM_OUTPUT) + return !!(readb(pctrl->base + P(port)) & BIT(bit)); + else + return -EINVAL; +} + +static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + pinctrl_gpio_free(chip->base + offset); + + /* + * Set the GPIO as an input to ensure that the next GPIO request won't + * drive the GPIO pin as an output. + */ + rzg2l_gpio_direction_input(chip, offset); +} + +static const char * const rzg2l_gpio_names[] = { + "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", + "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", + "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", + "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", + "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", + "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", + "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", + "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", + "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", + "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", + "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", + "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", + "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", + "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", + "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", + "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", + "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", + "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", + "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", + "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", + "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", + "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", + "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", + "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", + "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", + "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", + "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", + "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", + "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", + "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", + "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", + "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", + "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", + "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", + "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", + "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", + "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", + "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", + "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", + "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", + "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", + "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", + "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", + "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", + "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", + "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", + "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", + "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", + "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", +}; + +static const u32 rzg2l_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), +}; + +static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, + (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, + (PIN_CFG_SR | PIN_CFG_IOLH | PIN_CFG_IEN)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN)) }, + { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, + { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD1))}, + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) }, + { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, + { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, + { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, + { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, +}; + +static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) +{ + struct device_node *np = pctrl->dev->of_node; + struct gpio_chip *chip = &pctrl->gpio_chip; + const char *name = dev_name(pctrl->dev); + struct of_phandle_args of_args; + int ret; + + ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); + if (ret) { + dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); + return ret; + } + + if (of_args.args[0] != 0 || of_args.args[1] != 0 || + of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) { + dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); + return -EINVAL; + } + + chip->names = rzg2l_gpio_names; + chip->request = rzg2l_gpio_request; + chip->free = rzg2l_gpio_free; + chip->get_direction = rzg2l_gpio_get_direction; + chip->direction_input = rzg2l_gpio_direction_input; + chip->direction_output = rzg2l_gpio_direction_output; + chip->get = rzg2l_gpio_get; + chip->set = rzg2l_gpio_set; + chip->label = name; + chip->parent = pctrl->dev; + chip->owner = THIS_MODULE; + chip->base = -1; + chip->ngpio = of_args.args[2]; + + pctrl->gpio_range.id = 0; + pctrl->gpio_range.pin_base = 0; + pctrl->gpio_range.base = 0; + pctrl->gpio_range.npins = chip->ngpio; + pctrl->gpio_range.name = chip->label; + pctrl->gpio_range.gc = chip; + ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "failed to add GPIO controller\n"); + return ret; + } + + dev_dbg(pctrl->dev, "Registered gpio controller\n"); + + return 0; +} + +static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) +{ + struct pinctrl_pin_desc *pins; + unsigned int i, j; + u32 *pin_data; + int ret; + + pctrl->desc.name = DRV_NAME; + pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; + pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; + pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; + pctrl->desc.confops = &rzg2l_pinctrl_confops; + pctrl->desc.owner = THIS_MODULE; + + pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, + sizeof(*pin_data), GFP_KERNEL); + if (!pin_data) + return -ENOMEM; + + pctrl->pins = pins; + pctrl->desc.pins = pins; + + for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { + pins[i].number = i; + pins[i].name = pctrl->data->port_pins[i]; + if (i && !(i % RZG2L_PINS_PER_PORT)) + j++; + pin_data[i] = pctrl->data->port_pin_configs[j]; + pins[i].drv_data = &pin_data[i]; + } + + for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { + unsigned int index = pctrl->data->n_port_pins + i; + + pins[index].number = index; + pins[index].name = pctrl->data->dedicated_pins[i].name; + pin_data[index] = pctrl->data->dedicated_pins[i].config; + pins[index].drv_data = &pin_data[index]; + } + + ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, + &pctrl->pctl); + if (ret) { + dev_err(pctrl->dev, "pinctrl registration failed\n"); + return ret; + } + + ret = pinctrl_enable(pctrl->pctl); + if (ret) { + dev_err(pctrl->dev, "pinctrl enable failed\n"); + return ret; + } + + ret = rzg2l_gpio_register(pctrl); + if (ret) { + dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); + return ret; + } + + return 0; +} + +static void rzg2l_pinctrl_clk_disable(void *data) +{ + clk_disable_unprepare(data); +} + +static int rzg2l_pinctrl_probe(struct platform_device *pdev) +{ + struct rzg2l_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + + pctrl->data = of_device_get_match_data(&pdev->dev); + if (!pctrl->data) + return -EINVAL; + + pctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->base)) + return PTR_ERR(pctrl->base); + + pctrl->clk = devm_clk_get(pctrl->dev, NULL); + if (IS_ERR(pctrl->clk)) { + ret = PTR_ERR(pctrl->clk); + dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); + return ret; + } + + spin_lock_init(&pctrl->lock); + + platform_set_drvdata(pdev, pctrl); + + ret = clk_prepare_enable(pctrl->clk); + if (ret) { + dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); + return ret; + } + + ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, + pctrl->clk); + if (ret) { + dev_err(pctrl->dev, + "failed to register GPIO clk disable action, %i\n", + ret); + return ret; + } + + ret = rzg2l_pinctrl_register(pctrl); + if (ret) + return ret; + + dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); + return 0; +} + +static struct rzg2l_pinctrl_data r9a07g044_data = { + .port_pins = rzg2l_gpio_names, + .port_pin_configs = rzg2l_gpio_configs, + .dedicated_pins = rzg2l_dedicated_pins, + .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), + .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins), +}; + +static const struct of_device_id rzg2l_pinctrl_of_table[] = { + { + .compatible = "renesas,r9a07g044-pinctrl", + .data = &r9a07g044_data, + }, + { /* sentinel */ } +}; + +static struct platform_driver rzg2l_pinctrl_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), + }, + .probe = rzg2l_pinctrl_probe, +}; + +static int __init rzg2l_pinctrl_init(void) +{ + return platform_driver_register(&rzg2l_pinctrl_driver); +} +core_initcall(rzg2l_pinctrl_init); + +MODULE_AUTHOR("Lad Prabhakar "); +MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3