From f7c05e837df794d2aaf19174269a270c93a52eca Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Feb 2014 15:43:00 +0100 Subject: spi: sh-msiof: Fix SPI bus population from DT DT doesn't instantiate SPI children if spi_master.dev.of_node is not set up properly. Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 81cc02f5f9b0..21ac8f668682 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -711,6 +711,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; master->flags = 0; master->bus_num = pdev->id; + master->dev.of_node = pdev->dev.of_node; master->num_chipselect = p->info->num_chipselect; master->setup = spi_bitbang_setup; master->cleanup = spi_bitbang_cleanup; -- cgit v1.2.3 From a669c11a0df07477afbfeb53bc9d8fc989d1ed59 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Feb 2014 15:43:01 +0100 Subject: spi: sh-msiof: Typo in comment s/tx/rx/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 21ac8f668682..5eded247fce4 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -487,7 +487,7 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, /* clear status bits */ sh_msiof_reset_str(p); - /* shut down frame, tx/tx and clock signals */ + /* shut down frame, rx/tx and clock signals */ ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); if (rx_buf) -- cgit v1.2.3 From 6a85fc5af1f09982e50abe56efc70eda9ad24632 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Feb 2014 15:43:02 +0100 Subject: spi: sh-msiof: Change hz from unsigned long to u32 Both spi_transfer.speed_hz and spi_master.max_speed_hz are u32 Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 5eded247fce4..d0af05e96a2d 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -145,8 +145,7 @@ static struct { }; static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, - unsigned long parent_rate, - unsigned long spi_hz) + unsigned long parent_rate, u32 spi_hz) { unsigned long div = 1024; size_t k; @@ -373,10 +372,9 @@ static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) return bits; } -static unsigned long sh_msiof_spi_hz(struct spi_device *spi, - struct spi_transfer *t) +static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t) { - unsigned long hz; + u32 hz; hz = t ? t->speed_hz : 0; if (!hz) -- cgit v1.2.3 From 01cfef57efe9c8ef445d4a5ad3bf26770fd5942a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Feb 2014 15:43:03 +0100 Subject: spi: sh-msiof: Add more register documentation Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 152 +++++++++++++++++++++++++++++---------------- 1 file changed, 100 insertions(+), 52 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index d0af05e96a2d..7acbc4052757 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -42,32 +42,80 @@ struct sh_msiof_spi_priv { int rx_fifo_size; }; -#define TMDR1 0x00 -#define TMDR2 0x04 -#define TMDR3 0x08 -#define RMDR1 0x10 -#define RMDR2 0x14 -#define RMDR3 0x18 -#define TSCR 0x20 -#define RSCR 0x22 -#define CTR 0x28 -#define FCTR 0x30 -#define STR 0x40 -#define IER 0x44 -#define TDR1 0x48 -#define TDR2 0x4c -#define TFDR 0x50 -#define RDR1 0x58 -#define RDR2 0x5c -#define RFDR 0x60 - -#define CTR_TSCKE (1 << 15) -#define CTR_TFSE (1 << 14) -#define CTR_TXE (1 << 9) -#define CTR_RXE (1 << 8) - -#define STR_TEOF (1 << 23) -#define STR_REOF (1 << 7) +#define TMDR1 0x00 /* Transmit Mode Register 1 */ +#define TMDR2 0x04 /* Transmit Mode Register 2 */ +#define TMDR3 0x08 /* Transmit Mode Register 3 */ +#define RMDR1 0x10 /* Receive Mode Register 1 */ +#define RMDR2 0x14 /* Receive Mode Register 2 */ +#define RMDR3 0x18 /* Receive Mode Register 3 */ +#define TSCR 0x20 /* Transmit Clock Select Register */ +#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ +#define CTR 0x28 /* Control Register */ +#define FCTR 0x30 /* FIFO Control Register */ +#define STR 0x40 /* Status Register */ +#define IER 0x44 /* Interrupt Enable Register */ +#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ +#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ +#define TFDR 0x50 /* Transmit FIFO Data Register */ +#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ +#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ +#define RFDR 0x60 /* Receive FIFO Data Register */ + +/* TMDR1 and RMDR1 */ +#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ +#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ +#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ +#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ +#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ +#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ +#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ +#define MDR1_FLD_SHIFT 2 +#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ +/* TMDR1 */ +#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ + +/* TMDR2 and RMDR2 */ +#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ +#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ +#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ + +/* TSCR and RSCR */ +#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ +#define SCR_BRPS(i) (((i) - 1) << 8) +#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ +#define SCR_BRDV_DIV_2 0x0000 +#define SCR_BRDV_DIV_4 0x0001 +#define SCR_BRDV_DIV_8 0x0002 +#define SCR_BRDV_DIV_16 0x0003 +#define SCR_BRDV_DIV_32 0x0004 +#define SCR_BRDV_DIV_1 0x0007 + +/* CTR */ +#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ +#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ +#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ +#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ +#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ +#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ +#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ +#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ +#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ +#define CTR_TXDIZ_LOW 0x00000000 /* 0 */ +#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ +#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ +#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ +#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ +#define CTR_TXE 0x00000200 /* Transmit Enable */ +#define CTR_RXE 0x00000100 /* Receive Enable */ + +/* STR and IER */ +#define STR_TEOF 0x00800000 /* Frame Transmission End */ +#define STR_REOF 0x00000080 /* Frame Reception End */ + + +#define DEFAULT_TX_FIFO_SIZE 64 +#define DEFAULT_RX_FIFO_SIZE 64 + static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) { @@ -131,17 +179,17 @@ static struct { unsigned short div; unsigned short scr; } const sh_msiof_spi_clk_table[] = { - { 1, 0x0007 }, - { 2, 0x0000 }, - { 4, 0x0001 }, - { 8, 0x0002 }, - { 16, 0x0003 }, - { 32, 0x0004 }, - { 64, 0x1f00 }, - { 128, 0x1f01 }, - { 256, 0x1f02 }, - { 512, 0x1f03 }, - { 1024, 0x1f04 }, + { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, + { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, + { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, + { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, + { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, + { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, + { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, + { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, + { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, + { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, + { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, }; static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, @@ -182,21 +230,21 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, */ sh_msiof_write(p, FCTR, 0); - tmp = 0; - tmp |= !cs_high << 25; - tmp |= lsb_first << 24; - sh_msiof_write(p, TMDR1, 0xe0000005 | tmp); - sh_msiof_write(p, RMDR1, 0x20000005 | tmp); + tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; + tmp |= !cs_high << MDR1_SYNCAC_SHIFT; + tmp |= lsb_first << MDR1_BITLSB_SHIFT; + sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); + sh_msiof_write(p, RMDR1, tmp); - tmp = 0xa0000000; - tmp |= cpol << 30; /* TSCKIZ */ - tmp |= cpol << 28; /* RSCKIZ */ + tmp = 0; + tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; + tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; edge = cpol ^ !cpha; - tmp |= edge << 27; /* TEDG */ - tmp |= edge << 26; /* REDG */ - tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */ + tmp |= edge << CTR_TEDG_SHIFT; + tmp |= edge << CTR_REDG_SHIFT; + tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; sh_msiof_write(p, CTR, tmp); } @@ -204,12 +252,12 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, const void *tx_buf, void *rx_buf, u32 bits, u32 words) { - u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16); + u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); if (tx_buf) sh_msiof_write(p, TMDR2, dr2); else - sh_msiof_write(p, TMDR2, dr2 | 1); + sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); if (rx_buf) sh_msiof_write(p, RMDR2, dr2); @@ -695,8 +743,8 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); /* The standard version of MSIOF use 64 word FIFOs */ - p->tx_fifo_size = 64; - p->rx_fifo_size = 64; + p->tx_fifo_size = DEFAULT_TX_FIFO_SIZE; + p->rx_fifo_size = DEFAULT_RX_FIFO_SIZE; /* Platform data may override FIFO sizes */ if (p->info->tx_fifo_override) -- cgit v1.2.3 From 8d19534a8d539bb2e598e56e017a423f205e909e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Feb 2014 15:43:04 +0100 Subject: spi: sh-msiof: Use the core cs_gpio field, and make it optional In current implementation, CS is controlled by GPIO, which is passed through spi->controller_data. However, the MSIOF HW module has a function to output CS by itself, which is already enabled and actual switch will be done by pinmux. Store the GPIO number in the core cs_gpio field, and ignore it if it is an invalid (negative) GPIO number. Loosely based on a patch from Takashi Yoshii . Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 7acbc4052757..6e2ba62ceb63 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -446,6 +446,21 @@ static int sh_msiof_spi_setup_transfer(struct spi_device *spi, return spi_bitbang_setup_transfer(spi, t); } +static int sh_msiof_spi_setup(struct spi_device *spi) +{ + struct device_node *np = spi->master->dev.of_node; + + if (!np) { + /* + * Use spi->controller_data for CS (same strategy as spi_gpio), + * if any. otherwise let HW control CS + */ + spi->cs_gpio = (uintptr_t)spi->controller_data; + } + + return spi_bitbang_setup(spi); +} + static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) { struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); @@ -471,8 +486,8 @@ static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) !!(spi->mode & SPI_CS_HIGH)); } - /* use spi->controller data for CS (same strategy as spi_gpio) */ - gpio_set_value((uintptr_t)spi->controller_data, value); + if (spi->cs_gpio >= 0) + gpio_set_value(spi->cs_gpio, value); if (is_on == BITBANG_CS_INACTIVE) { if (test_and_clear_bit(0, &p->flags)) { @@ -759,7 +774,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) master->bus_num = pdev->id; master->dev.of_node = pdev->dev.of_node; master->num_chipselect = p->info->num_chipselect; - master->setup = spi_bitbang_setup; + master->setup = sh_msiof_spi_setup; master->cleanup = spi_bitbang_cleanup; p->bitbang.master = master; -- cgit v1.2.3 From 32d3b2d1ddeafe105ab6f738fba427242141194e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:21:08 +0100 Subject: spi: sh-msiof: Improve bindings Documentation: - Add missing "interrupt-parent", "#address-cells", "#size-cells", and "clocks" properties, - Add missing default values for "num-cs", "renesas,tx-fifo-size" and "renesas,rx-fifo-size", - Add a reference to the pinctrl documentation. Implementation: - As "num-cs" is marked optional, provide a sensible default. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 24 +++++++++++++++------- drivers/spi/spi-sh-msiof.c | 2 +- 2 files changed, 18 insertions(+), 8 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index e6222106ca36..eae3c8c9300e 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -1,12 +1,22 @@ Renesas MSIOF spi controller Required properties: -- compatible : "renesas,sh-msiof" for SuperH or - "renesas,sh-mobile-msiof" for SH Mobile series -- reg : Offset and length of the register set for the device -- interrupts : interrupt line used by MSIOF +- compatible : "renesas,sh-msiof" for SuperH, or + "renesas,sh-mobile-msiof" for SH Mobile series. +- reg : Offset and length of the register set for the device +- interrupt-parent : The phandle for the interrupt controller that + services interrupts for this device +- interrupts : Interrupt specifier +- #address-cells : Must be <1> +- #size-cells : Must be <0> Optional properties: -- num-cs : total number of chip-selects -- renesas,tx-fifo-size : Overrides the default tx fifo size given in words -- renesas,rx-fifo-size : Overrides the default rx fifo size given in words +- clocks : Must contain a reference to the functional clock. +- num-cs : Total number of chip-selects (default is 1) +- renesas,tx-fifo-size : Overrides the default tx fifo size given in words + (default is 64) +- renesas,rx-fifo-size : Overrides the default rx fifo size given in words + (default is 64) + +Pinctrl properties might be needed, too. See +Documentation/devicetree/bindings/pinctrl/renesas,*. diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 6e2ba62ceb63..181efd049d12 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -664,7 +664,7 @@ static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) { struct sh_msiof_spi_info *info; struct device_node *np = dev->of_node; - u32 num_cs = 0; + u32 num_cs = 1; info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); if (!info) { -- cgit v1.2.3 From 50a7e23f53677918bf521b09ce9bb20fb87cd175 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:21:09 +0100 Subject: spi: sh-msiof: Move default FIFO sizes to device ID data As different variants of MSIOF have different FIFO sizes, move the default FIFO sizes to a new struct sh_msiof_chipdata, pointed to from the device ID data. [Moved ifdef to fix build -- broonie] Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 50 +++++++++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 16 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 181efd049d12..38d6b70e9be2 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -30,11 +31,18 @@ #include + +struct sh_msiof_chipdata { + u16 tx_fifo_size; + u16 rx_fifo_size; +}; + struct sh_msiof_spi_priv { struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ void __iomem *mapbase; struct clk *clk; struct platform_device *pdev; + const struct sh_msiof_chipdata *chipdata; struct sh_msiof_spi_info *info; struct completion done; unsigned long flags; @@ -113,10 +121,6 @@ struct sh_msiof_spi_priv { #define STR_REOF 0x00000080 /* Frame Reception End */ -#define DEFAULT_TX_FIFO_SIZE 64 -#define DEFAULT_RX_FIFO_SIZE 64 - - static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) { switch (reg_offs) { @@ -659,6 +663,18 @@ static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, return 0; } +static const struct sh_msiof_chipdata sh_data = { + .tx_fifo_size = 64, + .rx_fifo_size = 64, +}; + +static const struct of_device_id sh_msiof_match[] = { + { .compatible = "renesas,sh-msiof", .data = &sh_data }, + { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, sh_msiof_match); + #ifdef CONFIG_OF static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) { @@ -694,6 +710,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) { struct resource *r; struct spi_master *master; + const struct of_device_id *of_id; struct sh_msiof_spi_priv *p; int i; int ret; @@ -707,10 +724,15 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) p = spi_master_get_devdata(master); platform_set_drvdata(pdev, p); - if (pdev->dev.of_node) + + of_id = of_match_device(sh_msiof_match, &pdev->dev); + if (of_id) { + p->chipdata = of_id->data; p->info = sh_msiof_spi_parse_dt(&pdev->dev); - else + } else { + p->chipdata = (const void *)pdev->id_entry->driver_data; p->info = dev_get_platdata(&pdev->dev); + } if (!p->info) { dev_err(&pdev->dev, "failed to obtain device info\n"); @@ -757,11 +779,9 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) p->pdev = pdev; pm_runtime_enable(&pdev->dev); - /* The standard version of MSIOF use 64 word FIFOs */ - p->tx_fifo_size = DEFAULT_TX_FIFO_SIZE; - p->rx_fifo_size = DEFAULT_RX_FIFO_SIZE; - /* Platform data may override FIFO sizes */ + p->tx_fifo_size = p->chipdata->tx_fifo_size; + p->rx_fifo_size = p->chipdata->rx_fifo_size; if (p->info->tx_fifo_override) p->tx_fifo_size = p->info->tx_fifo_override; if (p->info->rx_fifo_override) @@ -811,18 +831,16 @@ static int sh_msiof_spi_remove(struct platform_device *pdev) return ret; } -#ifdef CONFIG_OF -static const struct of_device_id sh_msiof_match[] = { - { .compatible = "renesas,sh-msiof", }, - { .compatible = "renesas,sh-mobile-msiof", }, +static struct platform_device_id spi_driver_ids[] = { + { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, {}, }; -MODULE_DEVICE_TABLE(of, sh_msiof_match); -#endif +MODULE_DEVICE_TABLE(platform, spi_driver_ids); static struct platform_driver sh_msiof_spi_drv = { .probe = sh_msiof_spi_probe, .remove = sh_msiof_spi_remove, + .id_table = spi_driver_ids, .driver = { .name = "spi_sh_msiof", .owner = THIS_MODULE, -- cgit v1.2.3 From beb74bb0875579c409778d853b8a050c124b3c79 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:21:10 +0100 Subject: spi: sh-msiof: Add support for R-Car H2 and M2 Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2 (r8a7791) SoCs. Binding documentation: - Add future-proof "renesas,msiof-" compatible values, - The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2, - "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for soctype-specific bindings, - Add example bindings. Implementation: - MSIOF on R-Car H2 and M2 requires the transmission of dummy data if data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write dummy transmission data to SITFDR" in paragraph "Transmit and Receive Procedures" of the Hardware User's Manual). - As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR register (Receive Clock Select Register), and some bits in the RMDR1 (Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2) registers. - Use the recently introduced SPI_MASTER_MUST_TX flag to enable support for dummy transmission in the SPI core, and to differentiate from other MSIOF implementations in code paths that need this. - New DT compatible values ("renesas,msiof-r8a7790" and "renesas,msiof-r8a7791") are added, as well as new platform device names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof"). - The default RX FIFO size is 256 words on R-Car H2 and M2. This is loosely based on a set of patches from Takashi Yoshii . Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 23 ++++++++++++++++++++-- drivers/spi/spi-sh-msiof.c | 23 +++++++++++++++++++--- 2 files changed, 41 insertions(+), 5 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index eae3c8c9300e..1f0cb33763a1 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -1,8 +1,13 @@ Renesas MSIOF spi controller Required properties: -- compatible : "renesas,sh-msiof" for SuperH, or +- compatible : "renesas,msiof-" for SoCs, + "renesas,sh-msiof" for SuperH, or "renesas,sh-mobile-msiof" for SH Mobile series. + Examples with soctypes are: + "renesas,msiof-sh7724" (SH) + "renesas,msiof-r8a7790" (R-Car H2) + "renesas,msiof-r8a7791" (R-Car M2) - reg : Offset and length of the register set for the device - interrupt-parent : The phandle for the interrupt controller that services interrupts for this device @@ -13,10 +18,24 @@ Required properties: Optional properties: - clocks : Must contain a reference to the functional clock. - num-cs : Total number of chip-selects (default is 1) + +Optional properties, deprecated for soctype-specific bindings: - renesas,tx-fifo-size : Overrides the default tx fifo size given in words (default is 64) - renesas,rx-fifo-size : Overrides the default rx fifo size given in words - (default is 64) + (default is 64, or 256 on R-Car H2 and M2) Pinctrl properties might be needed, too. See Documentation/devicetree/bindings/pinctrl/renesas,*. + +Example: + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7791"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 38d6b70e9be2..e7f4797fa59d 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -35,6 +35,7 @@ struct sh_msiof_chipdata { u16 tx_fifo_size; u16 rx_fifo_size; + u16 master_flags; }; struct sh_msiof_spi_priv { @@ -215,7 +216,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); - sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); + if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) + sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); } static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, @@ -238,6 +240,10 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, tmp |= !cs_high << MDR1_SYNCAC_SHIFT; tmp |= lsb_first << MDR1_BITLSB_SHIFT; sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); + if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { + /* These bits are reserved if RX needs TX */ + tmp &= ~0x0000ffff; + } sh_msiof_write(p, RMDR1, tmp); tmp = 0; @@ -258,7 +264,7 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, { u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); - if (tx_buf) + if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) sh_msiof_write(p, TMDR2, dr2); else sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); @@ -666,11 +672,20 @@ static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, static const struct sh_msiof_chipdata sh_data = { .tx_fifo_size = 64, .rx_fifo_size = 64, + .master_flags = 0, +}; + +static const struct sh_msiof_chipdata r8a779x_data = { + .tx_fifo_size = 64, + .rx_fifo_size = 256, + .master_flags = SPI_MASTER_MUST_TX, }; static const struct of_device_id sh_msiof_match[] = { { .compatible = "renesas,sh-msiof", .data = &sh_data }, { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, + { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, + { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, {}, }; MODULE_DEVICE_TABLE(of, sh_msiof_match); @@ -790,7 +805,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) /* init master and bitbang code */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; - master->flags = 0; + master->flags = p->chipdata->master_flags; master->bus_num = pdev->id; master->dev.of_node = pdev->dev.of_node; master->num_chipselect = p->info->num_chipselect; @@ -833,6 +848,8 @@ static int sh_msiof_spi_remove(struct platform_device *pdev) static struct platform_device_id spi_driver_ids[] = { { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, + { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, + { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, {}, }; MODULE_DEVICE_TABLE(platform, spi_driver_ids); -- cgit v1.2.3 From c833ff7304511805ce5a3378d1637e39e00e00ea Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:21:11 +0100 Subject: spi: sh-msiof: Move clock management to (un)prepare_message() Move clock management and pin configuration from the bitbang chipselect() method to the SPI core prepare_message() and unprepare_message() methods. As spi_master.{,un}prepare_message() is guaranteed to be called in matching pairs, the clock management synchronization is no longer needed. As sh_msiof_spi_set_pin_regs() is no longer called at spi_master.setup() time (through spi_bitbang_setup() and the spi_bitbang.chipselect() callback), we now have to take care of that ourselves. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 61 +++++++++++++++++++++++++++++----------------- 1 file changed, 38 insertions(+), 23 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index e7f4797fa59d..efeda03bbace 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -46,7 +46,6 @@ struct sh_msiof_spi_priv { const struct sh_msiof_chipdata *chipdata; struct sh_msiof_spi_info *info; struct completion done; - unsigned long flags; int tx_fifo_size; int rx_fifo_size; }; @@ -459,6 +458,7 @@ static int sh_msiof_spi_setup_transfer(struct spi_device *spi, static int sh_msiof_spi_setup(struct spi_device *spi) { struct device_node *np = spi->master->dev.of_node; + struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); if (!np) { /* @@ -468,12 +468,46 @@ static int sh_msiof_spi_setup(struct spi_device *spi) spi->cs_gpio = (uintptr_t)spi->controller_data; } + /* Configure pins before deasserting CS */ + sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), + !!(spi->mode & SPI_CPHA), + !!(spi->mode & SPI_3WIRE), + !!(spi->mode & SPI_LSB_FIRST), + !!(spi->mode & SPI_CS_HIGH)); + return spi_bitbang_setup(spi); } +static int sh_msiof_prepare_message(struct spi_master *master, + struct spi_message *msg) +{ + struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); + const struct spi_device *spi = msg->spi; + + pm_runtime_get_sync(&p->pdev->dev); + clk_enable(p->clk); + + /* Configure pins before asserting CS */ + sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), + !!(spi->mode & SPI_CPHA), + !!(spi->mode & SPI_3WIRE), + !!(spi->mode & SPI_LSB_FIRST), + !!(spi->mode & SPI_CS_HIGH)); + return 0; +} + +static int sh_msiof_unprepare_message(struct spi_master *master, + struct spi_message *msg) +{ + struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); + + clk_disable(p->clk); + pm_runtime_put(&p->pdev->dev); + return 0; +} + static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) { - struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); int value; /* chip select is active low unless SPI_CS_HIGH is set */ @@ -482,29 +516,8 @@ static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) else value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; - if (is_on == BITBANG_CS_ACTIVE) { - if (!test_and_set_bit(0, &p->flags)) { - pm_runtime_get_sync(&p->pdev->dev); - clk_enable(p->clk); - } - - /* Configure pins before asserting CS */ - sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), - !!(spi->mode & SPI_CPHA), - !!(spi->mode & SPI_3WIRE), - !!(spi->mode & SPI_LSB_FIRST), - !!(spi->mode & SPI_CS_HIGH)); - } - if (spi->cs_gpio >= 0) gpio_set_value(spi->cs_gpio, value); - - if (is_on == BITBANG_CS_INACTIVE) { - if (test_and_clear_bit(0, &p->flags)) { - clk_disable(p->clk); - pm_runtime_put(&p->pdev->dev); - } - } } static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, @@ -811,6 +824,8 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) master->num_chipselect = p->info->num_chipselect; master->setup = sh_msiof_spi_setup; master->cleanup = spi_bitbang_cleanup; + master->prepare_message = sh_msiof_prepare_message; + master->unprepare_message = sh_msiof_unprepare_message; p->bitbang.master = master; p->bitbang.chipselect = sh_msiof_spi_chipselect; -- cgit v1.2.3 From 2416289c714343ea855e725d59d42668a9ab3cf6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:21:12 +0100 Subject: spi: sh-msiof: Convert to let spi core validate xfer->bits_per_word Set bits_per_word_mask so the spi core will reject transfers that attempt to use an unsupported bits_per_word value. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index efeda03bbace..a0380b7c977f 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -439,22 +439,6 @@ static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t) return hz; } -static int sh_msiof_spi_setup_transfer(struct spi_device *spi, - struct spi_transfer *t) -{ - int bits; - - /* noting to check hz values against since parent clock is disabled */ - - bits = sh_msiof_spi_bits(spi, t); - if (bits < 8) - return -EINVAL; - if (bits > 32) - return -EINVAL; - - return spi_bitbang_setup_transfer(spi, t); -} - static int sh_msiof_spi_setup(struct spi_device *spi) { struct device_node *np = spi->master->dev.of_node; @@ -826,10 +810,11 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) master->cleanup = spi_bitbang_cleanup; master->prepare_message = sh_msiof_prepare_message; master->unprepare_message = sh_msiof_unprepare_message; + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); p->bitbang.master = master; p->bitbang.chipselect = sh_msiof_spi_chipselect; - p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; + p->bitbang.setup_transfer = spi_bitbang_setup_transfer; p->bitbang.txrx_bufs = sh_msiof_spi_txrx; p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; -- cgit v1.2.3 From 1bd6363bc0c69ff6120b53daa35cf9459c3628ad Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:21:13 +0100 Subject: spi: sh-msiof: Use core message handling instead of spi-bitbang The only remaining feature of spi-bitbang used by this driver is the chipselect() callback, which just does conditional GPIO. This is handled fine by the SPI core's spi_set_cs(), hence switch the driver to use the core message handling through our own transfer_one() method. As the (optional) GPIO CS is no longer deasserted at spi_master.setup() time (through spi_bitbang_setup() and the spi_bitbang.chipselect() callback), we now have to take care of that ourselves. Remove the call to spi_master_put() in sh_msiof_spi_remove(), as our SPI master is now registered using devm_spi_register_master() (spi_bitbang_start() uses the non-managed version). Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 1 - drivers/spi/spi-sh-msiof.c | 67 ++++++++++++++-------------------------------- 2 files changed, 20 insertions(+), 48 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ba9310bc9acb..16f2987c29dc 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -416,7 +416,6 @@ config SPI_SH_MSIOF tristate "SuperH MSIOF SPI controller" depends on HAVE_CLK depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST - select SPI_BITBANG help SPI driver for SuperH and SH Mobile MSIOF blocks. diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index a0380b7c977f..db687011dc4f 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -27,7 +27,6 @@ #include #include -#include #include @@ -39,7 +38,6 @@ struct sh_msiof_chipdata { }; struct sh_msiof_spi_priv { - struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ void __iomem *mapbase; struct clk *clk; struct platform_device *pdev; @@ -459,7 +457,10 @@ static int sh_msiof_spi_setup(struct spi_device *spi) !!(spi->mode & SPI_LSB_FIRST), !!(spi->mode & SPI_CS_HIGH)); - return spi_bitbang_setup(spi); + if (spi->cs_gpio >= 0) + gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); + + return 0; } static int sh_msiof_prepare_message(struct spi_master *master, @@ -490,20 +491,6 @@ static int sh_msiof_unprepare_message(struct spi_master *master, return 0; } -static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) -{ - int value; - - /* chip select is active low unless SPI_CS_HIGH is set */ - if (spi->mode & SPI_CS_HIGH) - value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0; - else - value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; - - if (spi->cs_gpio >= 0) - gpio_set_value(spi->cs_gpio, value); -} - static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int), @@ -573,9 +560,11 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, return ret; } -static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) +static int sh_msiof_transfer_one(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *t) { - struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); + struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); int bits; @@ -656,13 +645,6 @@ static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) words -= n; } - return bytes_done; -} - -static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, - u32 word, u8 bits) -{ - BUG(); /* unused but needed by bitbang code */ return 0; } @@ -799,7 +781,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) if (p->info->rx_fifo_override) p->rx_fifo_size = p->info->rx_fifo_override; - /* init master and bitbang code */ + /* init master code */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; master->flags = p->chipdata->master_flags; @@ -807,24 +789,20 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) master->dev.of_node = pdev->dev.of_node; master->num_chipselect = p->info->num_chipselect; master->setup = sh_msiof_spi_setup; - master->cleanup = spi_bitbang_cleanup; master->prepare_message = sh_msiof_prepare_message; master->unprepare_message = sh_msiof_unprepare_message; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); + master->transfer_one = sh_msiof_transfer_one; - p->bitbang.master = master; - p->bitbang.chipselect = sh_msiof_spi_chipselect; - p->bitbang.setup_transfer = spi_bitbang_setup_transfer; - p->bitbang.txrx_bufs = sh_msiof_spi_txrx; - p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; - p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; - p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; - p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; + ret = devm_spi_register_master(&pdev->dev, master); + if (ret < 0) { + dev_err(&pdev->dev, "spi_register_master error.\n"); + goto err2; + } - ret = spi_bitbang_start(&p->bitbang); - if (ret == 0) - return 0; + return 0; + err2: pm_runtime_disable(&pdev->dev); clk_unprepare(p->clk); err1: @@ -835,15 +813,10 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) static int sh_msiof_spi_remove(struct platform_device *pdev) { struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); - int ret; - ret = spi_bitbang_stop(&p->bitbang); - if (!ret) { - pm_runtime_disable(&pdev->dev); - clk_unprepare(p->clk); - spi_master_put(p->bitbang.master); - } - return ret; + pm_runtime_disable(&pdev->dev); + clk_unprepare(p->clk); + return 0; } static struct platform_device_id spi_driver_ids[] = { -- cgit v1.2.3 From b14158603288b9d898716b41f2f0acb7d49dad2c Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Sun, 2 Mar 2014 22:30:32 +0800 Subject: spi: sh-msiof: Kill sh_msiof_spi_bits and sh_msiof_spi_hz functions In the implementation of __spi_validate(), spi core will set transfer bits_per_word and max speed as spi device default if it is not set for this transfer. So we can remove the same implementation in this driver. Signed-off-by: Axel Lin Acked-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index db687011dc4f..3ffb8eed5ac5 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -417,26 +417,6 @@ static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); } -static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) -{ - int bits; - - bits = t ? t->bits_per_word : 0; - if (!bits) - bits = spi->bits_per_word; - return bits; -} - -static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t) -{ - u32 hz; - - hz = t ? t->speed_hz : 0; - if (!hz) - hz = spi->max_speed_hz; - return hz; -} - static int sh_msiof_spi_setup(struct spi_device *spi) { struct device_node *np = spi->master->dev.of_node; @@ -574,7 +554,7 @@ static int sh_msiof_transfer_one(struct spi_master *master, int n; bool swab; - bits = sh_msiof_spi_bits(spi, t); + bits = t->bits_per_word; if (bits <= 8 && t->len > 15 && !(t->len & 3)) { bits = 32; @@ -624,8 +604,7 @@ static int sh_msiof_transfer_one(struct spi_master *master, } /* setup clocks (clock already enabled in chipselect()) */ - sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), - sh_msiof_spi_hz(spi, t)); + sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); /* transfer in fifo sized chunks */ words = t->len / bytes_per_word; -- cgit v1.2.3 From e2a0ba547ba31cd7b217cc948d93e4edc78cbcb1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 11 Mar 2014 10:59:11 +0100 Subject: spi: sh-msiof: Convert to spi core auto_runtime_pm framework Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) (limited to 'drivers/spi/spi-sh-msiof.c') diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 3ffb8eed5ac5..b6b013a2f397 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -449,9 +449,6 @@ static int sh_msiof_prepare_message(struct spi_master *master, struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); const struct spi_device *spi = msg->spi; - pm_runtime_get_sync(&p->pdev->dev); - clk_enable(p->clk); - /* Configure pins before asserting CS */ sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), !!(spi->mode & SPI_CPHA), @@ -461,16 +458,6 @@ static int sh_msiof_prepare_message(struct spi_master *master, return 0; } -static int sh_msiof_unprepare_message(struct spi_master *master, - struct spi_message *msg) -{ - struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); - - clk_disable(p->clk); - pm_runtime_put(&p->pdev->dev); - return 0; -} - static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int), @@ -743,12 +730,6 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) goto err1; } - ret = clk_prepare(p->clk); - if (ret < 0) { - dev_err(&pdev->dev, "unable to prepare clock\n"); - goto err1; - } - p->pdev = pdev; pm_runtime_enable(&pdev->dev); @@ -769,8 +750,8 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) master->num_chipselect = p->info->num_chipselect; master->setup = sh_msiof_spi_setup; master->prepare_message = sh_msiof_prepare_message; - master->unprepare_message = sh_msiof_unprepare_message; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); + master->auto_runtime_pm = true; master->transfer_one = sh_msiof_transfer_one; ret = devm_spi_register_master(&pdev->dev, master); @@ -783,7 +764,6 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) err2: pm_runtime_disable(&pdev->dev); - clk_unprepare(p->clk); err1: spi_master_put(master); return ret; @@ -791,10 +771,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) static int sh_msiof_spi_remove(struct platform_device *pdev) { - struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); - pm_runtime_disable(&pdev->dev); - clk_unprepare(p->clk); return 0; } -- cgit v1.2.3