From 1526c704b3c32640b5e6cdc1662b0698603e9d4f Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 14 Aug 2017 06:22:14 -0400 Subject: media: v4l: fwnode: The clock lane is the first lane in lane_polarities The clock lane is the first lane in the lane_polarities array. Reflect this consistently by putting the number of data lanes after the number of clock lanes. Fixes: 4ee236219f6d ("media: v4l2-fwnode: suppress a warning at OF parsing logic") Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- include/media/v4l2-fwnode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/media') diff --git a/include/media/v4l2-fwnode.h b/include/media/v4l2-fwnode.h index cb34dcb0bb65..08e743fb7944 100644 --- a/include/media/v4l2-fwnode.h +++ b/include/media/v4l2-fwnode.h @@ -42,7 +42,7 @@ struct v4l2_fwnode_bus_mipi_csi2 { unsigned char data_lanes[MAX_DATA_LANES]; unsigned char clock_lane; unsigned short num_data_lanes; - bool lane_polarities[MAX_DATA_LANES + 1]; + bool lane_polarities[1 + MAX_DATA_LANES]; }; /** -- cgit v1.2.3