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Bindings for Synopsys DesignWare I3C master block
=================================================
Required properties:
--------------------
- compatible: shall be "snps,dw-i3c-master-1.00a"
- clocks: shall reference the core_clk
- interrupts: the interrupt line connected to this I3C master
- reg: Offset and length of I3C master registers
Mandatory properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- #address-cells: shall be set to 3
- #size-cells: shall be set to 0
Optional properties defined by the generic binding (see
Documentation/devicetree/bindings/i3c/i3c.yaml for more details):
- i2c-scl-hz
- i3c-scl-hz
Optional properties specific for this driver:
- i3c-od-scl-low-ns: SCL low period for Open-Drain phase. Expressed in
nanoseconds. It is validated by the driver. Minimum value is 200.
- i3c-od-scl-high-ns: SCL high period for Open-Drain phase. Expressed in
nanoseconds. It is validated by the driver. Minimum value is 25.
- i3c-pp-scl-low-ns: SCL low period for Push-Pull phase. Expressed in
nanoseconds. It is validated by the driver. Minimum value is 25.
- i3c-pp-scl-high-ns: SCL high period for Push-Pull phase. It is expressed in
nanoseconds. It is validated by the driver. Minimum value is 25.
- sda-tx-hold-ns: SDA Hold Time (Thd_dat). Expressed in nanoseconds. It is not
validated by driver. Minimum value is 5. Maximum value is 35. Other
values will be trimmed to the range. This parameter is not supported by
old IP versions.
I3C device connected on the bus follow the generic description (see
Documentation/devicetree/bindings/i3c/i3c.yaml for more details).
Example:
i3c-master@2000 {
compatible = "snps,dw-i3c-master-1.00a";
#address-cells = <3>;
#size-cells = <0>;
reg = <0x02000 0x1000>;
interrupts = <0>;
clocks = <&i3cclk>;
eeprom@57{
compatible = "atmel,24c01";
reg = <0x57 0x0 0x10>;
pagesize = <0x8>;
};
};
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