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author | Jason M. Bills <jason.m.bills@intel.com> | 2022-01-06 23:59:39 +0300 |
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committer | Jason M. Bills <jason.m.bills@intel.com> | 2022-01-06 23:59:39 +0300 |
commit | 32777eec25d2c527a62e5ffab90a3dfef35855aa (patch) | |
tree | 588a90a6fe9fb0b35c7ce23ea3bd79fa5151ccde /meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch | |
parent | 61f1ca1b31a9a1108e9e7f71e47fdc19beb0490b (diff) | |
parent | 5cc2f81c5b66da00cad24e18b0d23442af060c3f (diff) | |
download | openbmc-32777eec25d2c527a62e5ffab90a3dfef35855aa.tar.xz |
Merge tag '0.86' of firmware.bmc.openbmc.yocto.openbmc into update
Diffstat (limited to 'meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch')
-rw-r--r-- | meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch deleted file mode 100644 index 249d4398f..000000000 --- a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch +++ /dev/null @@ -1,45 +0,0 @@ -From c6e0470d82417b79b23f218c6db1099eb6e160af Mon Sep 17 00:00:00 2001 -From: "Thang Q. Nguyen" <thang@os.amperecomputing.com> -Date: Wed, 23 Dec 2020 04:42:21 +0000 -Subject: [PATCH] aspeed: Disable internal PD resistors for GPIOs - -Configure SCU8C - Multi-function pin control 4 to disable internal pull -down resistors for GPIOJ, GPIOG/GPIOAB, GPIOD/GPIOY, GPIOC/GPIOS as -external resistors are already installed. - -Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> ---- - board/aspeed/ast-g5/ast-g5.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index fba22a728e..9bf6c905fe 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -27,9 +27,23 @@ int board_init(void) - #ifdef CONFIG_BOARD_LATE_INIT - int board_late_init(void) - { -+ u32 val; -+ - /* Switch PWM to GPIO mode to make FAN run in max speed */ - ast_scu_switch_pwm_to_gpio_mode(); - -+ /* -+ * Disable internal pull down resistor for GPIOJ, -+ * GPIOG/GPIOAB, GPIOD/GPIOY, GPIOC/GPIOS as external pull up/down -+ * resistors are installed already. Unlock SCU regs before writing. -+ */ -+ writel(SCU_PROTECT_UNLOCK, AST_SCU_BASE); -+ val = readl(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL4) | 0x024C0000; -+ writel(val, AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL4); -+#ifdef CONFIG_AST_SCU_LOCK -+ writel(0xaa, AST_SCU_BASE); -+#endif -+ - return 0; - } - #endif --- -2.25.1 - |