diff options
| author | Thang Q. Nguyen <thang@os.amperecomputing.com> | 2020-12-23 07:45:53 +0300 |
|---|---|---|
| committer | Brad Bishop <bradleyb@fuzziesquirrel.com> | 2021-02-01 16:44:46 +0300 |
| commit | d76c413d1c8430cb26a5365988521815112e45f5 (patch) | |
| tree | ef4b820a43fbd8b29c3016456c2d4ce228940244 /meta-ampere | |
| parent | 8f221bfb0979fa018f6c16b5af153c1549448e7d (diff) | |
| download | openbmc-d76c413d1c8430cb26a5365988521815112e45f5.tar.xz | |
meta-ampere: u-boot: Disable internal PD resistors for GPIOs
Configure SCU8C - Multi-function pin control 4 to disable internal pull
down resistors for GPIOJ, GPIOG/GPIOAB, GPIOD/GPIOY, GPIOC/GPIOS as
external resistors are already installed.
Tested: scan I2C4 and check devices on the bus are detected
Signed-off-by: Thinh Pham <thinh.pham@amperecomputing.com>
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Change-Id: I5a4b682310b5243830bd9c7a66889b0a52c4770c
Diffstat (limited to 'meta-ampere')
2 files changed, 46 insertions, 0 deletions
diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch new file mode 100644 index 000000000..249d4398f --- /dev/null +++ b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch @@ -0,0 +1,45 @@ +From c6e0470d82417b79b23f218c6db1099eb6e160af Mon Sep 17 00:00:00 2001 +From: "Thang Q. Nguyen" <thang@os.amperecomputing.com> +Date: Wed, 23 Dec 2020 04:42:21 +0000 +Subject: [PATCH] aspeed: Disable internal PD resistors for GPIOs + +Configure SCU8C - Multi-function pin control 4 to disable internal pull +down resistors for GPIOJ, GPIOG/GPIOAB, GPIOD/GPIOY, GPIOC/GPIOS as +external resistors are already installed. + +Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> +--- + board/aspeed/ast-g5/ast-g5.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index fba22a728e..9bf6c905fe 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -27,9 +27,23 @@ int board_init(void) + #ifdef CONFIG_BOARD_LATE_INIT + int board_late_init(void) + { ++ u32 val; ++ + /* Switch PWM to GPIO mode to make FAN run in max speed */ + ast_scu_switch_pwm_to_gpio_mode(); + ++ /* ++ * Disable internal pull down resistor for GPIOJ, ++ * GPIOG/GPIOAB, GPIOD/GPIOY, GPIOC/GPIOS as external pull up/down ++ * resistors are installed already. Unlock SCU regs before writing. ++ */ ++ writel(SCU_PROTECT_UNLOCK, AST_SCU_BASE); ++ val = readl(AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL4) | 0x024C0000; ++ writel(val, AST_SCU_BASE + AST_SCU_FUN_PIN_CTRL4); ++#ifdef CONFIG_AST_SCU_LOCK ++ writel(0xaa, AST_SCU_BASE); ++#endif ++ + return 0; + } + #endif +-- +2.25.1 + diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend index 983dc2400..c40bfcd02 100644 --- a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend @@ -2,4 +2,5 @@ FILESEXTRAPATHS_append_mtjade := "${THISDIR}/${PN}:" SRC_URI += " \ file://0001-aspeed-scu-Switch-PWM-pin-to-GPIO-input-mode.patch \ + file://0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch \ " |