diff options
author | Dave Cobbley <david.j.cobbley@linux.intel.com> | 2018-08-23 04:40:54 +0300 |
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committer | Brad Bishop <bradleyb@fuzziesquirrel.com> | 2018-08-23 19:39:42 +0300 |
commit | 194ff4f1f5d44b12e9cb06ddafa6adb20174a13c (patch) | |
tree | 823835cd29daf8901a31ac14c7e6534abf199be3 /meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed | |
parent | 4feb727cd6b77a68bdaca63e121b378d814f5eaf (diff) | |
download | openbmc-194ff4f1f5d44b12e9cb06ddafa6adb20174a13c.tar.xz |
[Subtree] Bring openbmc machines to top level
The new subtree model brings the subtrees up from the openbmc-machines
layer.
Change-Id: I58a03ae1be374bc79ae1438e65e888375d12d0c0
Signed-off-by: Dave Cobbley <david.j.cobbley@linux.intel.com>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Diffstat (limited to 'meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed')
2 files changed, 103 insertions, 0 deletions
diff --git a/meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed/0001-board-aspeed-Add-reset_phy-for-Zaius.patch b/meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed/0001-board-aspeed-Add-reset_phy-for-Zaius.patch new file mode 100644 index 000000000..3b621e37e --- /dev/null +++ b/meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed/0001-board-aspeed-Add-reset_phy-for-Zaius.patch @@ -0,0 +1,60 @@ +From 3cd9aa92ab8ddd230cf6a9a68a27a18705b6f57c Mon Sep 17 00:00:00 2001 +From: Xo Wang <xow@google.com> +Date: Thu, 20 Oct 2016 16:26:29 -0700 +Subject: [PATCH 1/2] board/aspeed: Add reset_phy() for Zaius + +The Broadcom PHY for the Zaius BMC requires a hard reset after RGMII +clocks are enabled. Add reset_phy() implementation and configure it to +be called. + +Signed-off-by: Xo Wang <xow@google.com> +--- + board/aspeed/ast-g5/ast-g5.c | 19 +++++++++++++++++++ + include/configs/ast-common.h | 3 +++ + 2 files changed, 22 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index da79d7b..433ad18 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -33,6 +33,25 @@ int dram_init(void) + return 0; + } + ++void reset_phy(void) ++{ ++ unsigned long reg; ++ /* D3 in GPIOA/B/C/D direction and data registers */ ++ unsigned long phy_reset_mask = BIT(27); ++ ++ /* Assert MAC2 PHY hardware reset */ ++ /* Set pin low */ ++ reg = readl(AST_GPIO_BASE | 0x00); ++ writel(reg & ~phy_reset_mask, AST_GPIO_BASE | 0x00); ++ /* Enable pin for output */ ++ reg = readl(AST_GPIO_BASE | 0x04); ++ writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x04); ++ udelay(3); ++ /* Set pin high */ ++ reg = readl(AST_GPIO_BASE | 0x00); ++ writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x00); ++} ++ + #ifdef CONFIG_FTGMAC100 + int board_eth_init(bd_t *bd) + { +diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h +index b39ea33..3566f73 100644 +--- a/include/configs/ast-common.h ++++ b/include/configs/ast-common.h +@@ -104,4 +104,7 @@ + "spi_dma=yes\0" \ + "" + ++/* Call reset_phy() */ ++#define CONFIG_RESET_PHY_R 1 ++ + #endif /* __AST_COMMON_CONFIG_H */ +-- +2.8.0.rc3.226.g39d4020 + diff --git a/meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed/0002-board-aspeed-aspeednic-Use-MAC2-for-networking.patch b/meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed/0002-board-aspeed-aspeednic-Use-MAC2-for-networking.patch new file mode 100644 index 000000000..2de2d8234 --- /dev/null +++ b/meta-ingrasys/meta-zaius/recipes-bsp/u-boot/u-boot-aspeed/0002-board-aspeed-aspeednic-Use-MAC2-for-networking.patch @@ -0,0 +1,43 @@ +From cbb09e400a5283e5b543e2b01b8c0038890a5260 Mon Sep 17 00:00:00 2001 +From: Xo Wang <xow@google.com> +Date: Thu, 20 Oct 2016 17:42:13 -0700 +Subject: [PATCH 2/2] board/aspeed, aspeednic: Use MAC2 for networking + +Enable and select MAC2 for aspeednic. + +Signed-off-by: Xo Wang <xow@google.com> +--- + drivers/net/aspeednic.c | 4 ++-- + include/configs/ast-g5-ncsi.h | 1 + + 2 files changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/aspeednic.c b/drivers/net/aspeednic.c +index 8b85893..cff8370 100644 +--- a/drivers/net/aspeednic.c ++++ b/drivers/net/aspeednic.c +@@ -18,8 +18,8 @@ + /* From the board config file */ + #define CONFIG_MAC1_PHY_SETTING 2 + #define CONFIG_MAC2_PHY_SETTING 0 +-#define CONFIG_ASPEED_MAC_NUMBER 1 +-#define CONFIG_ASPEED_MAC_CONFIG 1 // config MAC1 ++#define CONFIG_ASPEED_MAC_NUMBER 2 ++#define CONFIG_ASPEED_MAC_CONFIG 2 // config MAC2 + #define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING + #define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac) + #define CONFIG_ASPEED_MAC_PHY_SETTING \ +diff --git a/include/configs/ast-g5-ncsi.h b/include/configs/ast-g5-ncsi.h +index f73a8f1..1408618 100644 +--- a/include/configs/ast-g5-ncsi.h ++++ b/include/configs/ast-g5-ncsi.h +@@ -22,6 +22,7 @@ + /* Ethernet */ + #define CONFIG_LIB_RAND + #define CONFIG_ASPEEDNIC ++#define CONFIG_MAC2_ENABLE + + /* platform.S settings */ + #define CONFIG_DRAM_ECC_SIZE 0x10000000 +-- +2.8.0.rc3.226.g39d4020 + |