Update to internal 0.26

Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

9 files changed, 508 insertions, 14 deletions

diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch
new file mode 100644
index 000000000..2d2b906b5
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch
@@ -0,0 +1,272 @@
+From 367c6c2734e54ff37eac2ace4691f55b0e3d6096 Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Mon, 14 Sep 2020 17:38:28 -0700
+Subject: [PATCH] Add WDT to u-boot to cover booting failures
+
+This commit enables WDT1 in early booting phase in u-boot to make BMC
+reset to cover booting failures. If BMC meet any failure or if
+systemd can't initiate watchdog timer service properly, BMC will
+be reset by this watchdog. This watchdog will get feeding by
+WATCHDOG_RESET macro calls from several points in u-boot loop
+code. The early u-boot WD timeout is 5 seconds and kernel booting WD
+timeout is 100 seconds.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ arch/arm/mach-aspeed/flash.c       |  7 +++
+ arch/arm/mach-aspeed/platform_g5.S | 78 ++++++++++++++++++++++++++++++
+ board/aspeed/ast-g5/ast-g5-intel.c |  3 ++
+ board/aspeed/ast-g5/ast-g5.c       | 30 +++++++++++-
+ common/bootm_os.c                  |  5 ++
+ 5 files changed, 121 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c
+index d33fb9e0fe78..31bbf77e9e67 100644
+--- a/arch/arm/mach-aspeed/flash.c
++++ b/arch/arm/mach-aspeed/flash.c
+@@ -30,6 +30,7 @@
+ #include <asm/byteorder.h>
+ #include <asm/io.h>
+ #include <environment.h>
++#include <watchdog.h>
+ 
+ #include <asm/arch/ast_scu.h>
+ #include <asm/arch/aspeed.h>
+@@ -610,6 +611,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
+                         }
+ 
+ 			putc ('.');
++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
++			WATCHDOG_RESET();
++#endif
+ 		}
+ 	}
+ 	puts (" done\n");
+@@ -679,6 +683,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+ 		src += count;
+ 		cnt -= count;
+ 		printf("%c\b", pat[(patcnt++) & 0x03]);
++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
++		WATCHDOG_RESET();
++#endif
+ 	}
+ 
+ 	reset_flash(info);
+diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S
+index f221c97b19dc..e468ed68d687 100644
+--- a/arch/arm/mach-aspeed/platform_g5.S
++++ b/arch/arm/mach-aspeed/platform_g5.S
+@@ -582,6 +582,31 @@ espi_early_init_done:
+     mov   r1, #0xAE
+     str   r1, [r0]
+ 
++#ifdef CONFIG_HW_WATCHDOG
++    /* Enable WDT1 to recover u-boot hang */
++    ldr   r0, =0x1e785004
++    ldr   r1, =0x00500000             @ ~5 seconds
++    str   r1, [r0]
++    ldr   r0, =0x1e785008
++    ldr   r1, =0x00004755
++    str   r1, [r0]
++    ldr   r0, =0x1e78500c
++    ldr   r1, =0x00000033
++    str   r1, [r0]
++
++    /* Clear Scratch register Bit 6 to do DDR training again on WDT1 reset */
++    ldr   r0, =0x1e6e203c
++    ldr   r1, [r0]
++    tst   r1, #(1<<2)
++    beq   bypass_scratch_reg_clear
++    ldr   r0, =0x1e6e2040
++    ldr   r1, [r0]
++    and   r1, r1, #0xFFFFFFBF
++    str   r1, [r0]
++
++bypass_scratch_reg_clear:
++#endif
++
+ /* Test - DRAM initial time */
+     ldr   r0, =0x1e78203c
+     ldr   r1, =0x0000F000
+@@ -2335,6 +2360,13 @@ spi_checksum_wait_0:
+     ldr   r1, [r0]
+     tst   r1, r2
+     beq   spi_checksum_wait_0
++
++/* Debug - UART console message */
++    ldr   r0, =0x1e784000
++    mov   r1, #0x31                              @ '1'
++    str   r1, [r0]
++/* Debug - UART console message */
++
+     ldr   r0, =0x1e620090
+     ldr   r5, [r0]                               @ record golden checksum
+     ldr   r0, =0x1e620080
+@@ -2363,6 +2395,13 @@ spi_checksum_wait_1:
+     ldr   r1, [r0]
+     tst   r1, r2
+     beq   spi_checksum_wait_1
++
++/* Debug - UART console message */
++    ldr   r0, =0x1e784000
++    mov   r1, #0x2E                              @ '.'
++    str   r1, [r0]
++/* Debug - UART console message */
++
+     ldr   r0, =0x1e620090
+     ldr   r2, [r0]                               @ read checksum
+     ldr   r0, =0x1e620080
+@@ -2377,6 +2416,13 @@ spi_checksum_wait_2:
+     ldr   r1, [r0]
+     tst   r1, r2
+     beq   spi_checksum_wait_2
++
++/* Debug - UART console message */
++    ldr   r0, =0x1e784000
++    mov   r1, #0x2E                              @ '.'
++    str   r1, [r0]
++/* Debug - UART console message */
++
+     ldr   r0, =0x1e620090
+     ldr   r2, [r0]                               @ read checksum
+     ldr   r0, =0x1e620080
+@@ -2394,6 +2440,12 @@ spi_cbr_next_delay_e:
+     blt   spi_cbr_next_delay_s
+     b     spi_cbr_next_clkrate
+ 
++/* Debug - UART console message */
++    ldr   r0, =0x1e784000
++    mov   r1, #0x2E                              @ '.'
++    str   r1, [r0]
++/* Debug - UART console message */
++
+ spi_cbr_end:
+     ldr   r0, =0x1e620094
+     str   r8, [r0]
+@@ -2401,6 +2453,16 @@ spi_cbr_end:
+     mov   r1, #0x0
+     str   r1, [r0]
+ 
++/* Debug - UART console message */
++    ldr   r0, =0x1e784000
++    mov   r1, #0x32                              @ '2'
++    str   r1, [r0]
++    mov   r1, #0x2E                              @ '.'
++    str   r1, [r0]
++    mov   r1, #0x2E                              @ '.'
++    str   r1, [r0]
++/* Debug - UART console message */
++
+ /******************************************************************************
+  Miscellaneous Setting
+  ******************************************************************************/
+@@ -2447,6 +2509,16 @@ spi_cbr_end:
+     mov   r1, #0
+     str   r1, [r0]
+ 
++/* Debug - UART console message */
++    ldr   r0, =0x1e784000
++    mov   r1, #0x33                              @ '3'
++    str   r1, [r0]
++    mov   r1, #0x2E                              @ '.'
++    str   r1, [r0]
++    mov   r1, #0x2E                              @ '.'
++    str   r1, [r0]
++/* Debug - UART console message */
++
+ /******************************************************************************
+  Configure MAC timing
+  ******************************************************************************/
+@@ -2535,6 +2607,12 @@ set_D2PLL:
+     ldr   r1, =0xEA
+     str   r1, [r0]
+ 
++/* Debug - UART console message */
++    ldr   r0, =0x1e784000
++    mov   r1, #0x34                              @ '4'
++    str   r1, [r0]
++/* Debug - UART console message */
++
+     /* restore lr */
+     mov   lr, r4
+ 
+diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c
+index c46bd70b71b2..92518a66fa67 100644
+--- a/board/aspeed/ast-g5/ast-g5-intel.c
++++ b/board/aspeed/ast-g5/ast-g5-intel.c
+@@ -701,6 +701,9 @@ void ast_g5_intel(void)
+ 	timer8_init();
+ 	enable_onboard_tpm();
+ 	if (intel_force_firmware_jumper_enabled()) {
++#ifdef CONFIG_HW_WATCHDOG
++		hw_watchdog_disable();
++#endif
+ 		/* FFUJ mode:- ChassisID: Solid Blue, StatusLED: Solid Amber */
+ 		id_led_control(GPIO_ID_LED, EIDLED_On);
+ 		id_led_control(GPIO_GREEN_LED, EIDLED_Off);
+diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
+index 00bd92ae5f94..3f27503bce62 100644
+--- a/board/aspeed/ast-g5/ast-g5.c
++++ b/board/aspeed/ast-g5/ast-g5.c
+@@ -125,9 +125,35 @@ int board_eth_init(bd_t *bd)
+ 
+ /* Called by macro WATCHDOG_RESET */
+ #if defined(CONFIG_HW_WATCHDOG)
++#define AST_WDT_COUNTER_STATUS		0x00
++#define AST_WDT_COUNTER_RELOAD_VALUE	0x04
++#define AST_WDT_COUNTER_RESTART_CTRL	0x08
++#define  AST_WDT_RESTART_VALUE		0x4755
++#define AST_WDT_CTRL			0x0c
++#define  AST_WDT_EN_1MHZ_CLK		BIT(4)
++#define  AST_WDT_SYS_RESET		BIT(1)
++#define  AST_WDT_ENABLE			BIT(0)
++#define AST_WDT_TIMEOUT_DEFAULT		0x6000000 /* ~100 seconds */
+ void hw_watchdog_reset(void)
+ {
+-	/* Restart WD2 timer */
+-	writel(0x4755, AST_WDT2_BASE + 0x08);
++	/* Restart WDT1 */
++	writel(AST_WDT_RESTART_VALUE,
++	       AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL);
++}
++
++void hw_watchdog_init(void)
++{
++	writel(0, AST_WDT1_BASE + AST_WDT_CTRL);
++	writel(AST_WDT_TIMEOUT_DEFAULT,
++	       AST_WDT1_BASE + AST_WDT_COUNTER_RELOAD_VALUE);
++	writel(AST_WDT_RESTART_VALUE,
++	       AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL);
++	writel(AST_WDT_EN_1MHZ_CLK | AST_WDT_SYS_RESET | AST_WDT_ENABLE,
++	       AST_WDT1_BASE + AST_WDT_CTRL);
++}
++
++void hw_watchdog_disable(void)
++{
++	writel(0, AST_WDT1_BASE + AST_WDT_CTRL);
+ }
+ #endif /* CONFIG_WATCHDOG */
+diff --git a/common/bootm_os.c b/common/bootm_os.c
+index b56eb39780e8..ec0e12ac84b9 100644
+--- a/common/bootm_os.c
++++ b/common/bootm_os.c
+@@ -473,11 +473,16 @@ __weak void arch_preboot_os(void)
+ 	/* please define platform specific arch_preboot_os() */
+ }
+ 
++extern void hw_watchdog_init(void);
++
+ int boot_selected_os(int argc, char * const argv[], int state,
+ 		     bootm_headers_t *images, boot_os_fn *boot_fn)
+ {
+ 	disable_interrupts();
+ 	arch_preboot_os();
++#ifdef CONFIG_HW_WATCHDOG
++	hw_watchdog_init(); /* Re-init WDT with 100 seconds timeout */
++#endif
+ 	boot_fn(state, argc, argv, images);
+ 
+ 	/* Stand-alone may return when 'autostart' is 'no' */
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch
new file mode 100644
index 000000000..3c1705c05
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch
@@ -0,0 +1,124 @@
+From b6f1f040f515a43d1903f4c4020032dfe436670d Mon Sep 17 00:00:00 2001
+From: Kuiying Wang <kuiying.wang@intel.com>
+Date: Sun, 27 Sep 2020 17:45:56 +0800
+Subject: [PATCH] Fix issue on host console is broken due to BMC reset by
+ watchdog.
+
+obmc-console service changed uart routing to support SOL.
+UART routing must be changed to normal, when BMC reset happens,
+as BMC reset must be treated as SOL connection closure.
+User needs to establish a new SOL connection after BMC reset,
+and routing will be initialized for SOL at that time.
+Which need several seconds (depends on BMC cycle time),
+or even never been recoverred if stopped at u-boot shell.
+
+error situaton as below:
+root@intel-obmc:~# devmem 0x1e78909c
+0x03450003
+root@intel-obmc:~# /sbin/watchdog -T 0 -F /dev/watchdog1
+
+U-Boot 2016.07 (Aug 25 2020 - 05:24:44 +0000)
+
+SOC : AST2500-A2
+RST : 0x08 (WDT2)
+PLL :     24 MHz
+CPU :    792 MHz
+MEM :    792 MHz, EEC: Disable, Cache: Disable
+VGA :    16 MiB
+DRAM :   init by SOC
+       Watchdog enabled
+DRAM:  496 MiB
+Flash: 64 MiB
+In:    serial
+Out:   serial
+Err:   serial
+Un-Protected 1 sectors
+Un-Protected 1 sectors
+Erasing Flash...
+. done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+Protected 1 sectors
+Net:   MAC0 : RMII/NCSI
+MAC1 : RGMII
+FTGMAC100#0, FTGMAC100#1
+ast#
+ast#
+ast# md 0x1e78909c
+1e78909c: 03450003 ffceff00 19000000 00000000
+
+Tested:
+u-boot could reset HICRA 0x1e78909c
+
+correct situation as below:
+root@intel-obmc:~# devmem 0x1e78909c
+0x03450003
+root@intel-obmc:~# /sbin/watchdog -T 0 -F /dev/watchdog1
+
+U-Boot 2016.07 (Sep 27 2020 - 09:34:20 +0000)
+
+SOC : AST2500-A2
+RST : 0x08 (WDT2)
+PLL :     24 MHz
+CPU :    792 MHz
+MEM :    792 MHz, EEC: Disable, Cache: Disable
+VGA :    16 MiB
+DRAM :   init by SOC
+       Watchdog enabled
+DRAM:  496 MiB
+Flash: 64 MiB
+In:    serial
+Out:   serial
+Err:   serial
+Un-Protected 1 sectors
+Un-Protected 1 sectors
+Erasing Flash...
+. done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+Protected 1 sectors
+Net:   MAC0 : RMII/NCSI
+MAC1 : RGMII
+FTGMAC100#0, FTGMAC100#1
+ast#
+ast#
+ast# md 0x1e78909c
+1e78909c: 00000000 ffceff00 19000000 00000000
+
+Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
+---
+ arch/arm/include/asm/arch-aspeed/regs-lpc.h | 1 +
+ board/aspeed/ast-g5/ast-g5.c                | 3 +++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-aspeed/regs-lpc.h b/arch/arm/include/asm/arch-aspeed/regs-lpc.h
+index b0162ae4f3..b4d3da2906 100644
+--- a/arch/arm/include/asm/arch-aspeed/regs-lpc.h
++++ b/arch/arm/include/asm/arch-aspeed/regs-lpc.h
+@@ -18,6 +18,7 @@
+  */
+ 
+ #define AST_LPC_HICR5		0x80
++#define AST_LPC_HICRA   	0x9C
+ #define AST_LPC_HICRB		0x100
+ 
+ /*	AST_LPC_HICR5 : 0x80	Host Interface Control Register 5 */
+diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
+index 00bd92ae5f..4c5997ab8a 100644
+--- a/board/aspeed/ast-g5/ast-g5.c
++++ b/board/aspeed/ast-g5/ast-g5.c
+@@ -45,6 +45,9 @@ int board_init(void)
+ 	val |= LPC_HICRB_ILPC2AHB;
+ 	writel(val, AST_LPC_BASE + AST_LPC_HICRB);
+ 
++	/* Reset UART routing */
++	writel(0x0, AST_LPC_BASE + AST_LPC_HICRA);
++
+ 	/* P2A, PCIe BMC */
+ 	val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
+ 	val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
index f5b54893f..a3bce3262 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
+++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
@@ -46,6 +46,8 @@ SRC_URI_append_intel-ast2500 = " \
     file://0045-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch \
     file://0046-Enable-FMC-DMA-for-memmove.patch \
     file://0047-ast2500-parse-reset-reason.patch \
+    file://0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch \
+    file://0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch \
     "
 # CVE-2020-10648 vulnerability fix
 SRC_URI_append_intel-ast2500 = " \
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json
index 94e7e7daa..0346c3f90 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CPC-Baseboard.json
@@ -1914,6 +1914,12 @@
             "Bus": 4,
             "Name": "PFR",
             "Type": "PFR"
+        },
+        {
+            "Name": "PCH SMBUS Slave",
+            "PchSmbusSlaveI2cBus": 3,
+            "PchSmbusSlaveI2cAddress": "0x44",
+            "Type": "PchSmbusSlave"
         }
     ],
     "Name": "CPC Baseboard",
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json
index 83e6deabe..909c47621 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json
@@ -499,96 +499,112 @@
         {
             "BindConnector": "System Fan connector 1",
             "Index": 0,
+            "MaxReading": 8000,
             "Name": "Fan 1a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 1",
             "Index": 1,
+            "MaxReading": 8000,
             "Name": "Fan 1b",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 2",
             "Index": 2,
+            "MaxReading": 8000,
             "Name": "Fan 2a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 2",
             "Index": 3,
+            "MaxReading": 8000,
             "Name": "Fan 2b",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 3",
             "Index": 4,
+            "MaxReading": 8000,
             "Name": "Fan 3a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 3",
             "Index": 5,
+            "MaxReading": 8000,
             "Name": "Fan 3b",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 4",
             "Index": 6,
+            "MaxReading": 8000,
             "Name": "Fan 4a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 4",
             "Index": 7,
+            "MaxReading": 8000,
             "Name": "Fan 4b",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 5",
             "Index": 8,
+            "MaxReading": 8000,
             "Name": "Fan 5a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 5",
             "Index": 9,
+            "MaxReading": 8000,
             "Name": "Fan 5b",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 6",
             "Index": 10,
+            "MaxReading": 8000,
             "Name": "Fan 6a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 6",
             "Index": 11,
+            "MaxReading": 8000,
             "Name": "Fan 6b",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 7",
             "Index": 12,
+            "MaxReading": 8000,
             "Name": "Fan 7a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 7",
             "Index": 13,
+            "MaxReading": 8000,
             "Name": "Fan 7b",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 8",
             "Index": 14,
+            "MaxReading": 8000,
             "Name": "Fan 8a",
             "Type": "AspeedFan"
         },
         {
             "BindConnector": "System Fan connector 8",
             "Index": 15,
+            "MaxReading": 8000,
             "Name": "Fan 8b",
             "Type": "AspeedFan"
         },
@@ -620,6 +636,7 @@
             "Type": "CFMSensor"
         },
         {
+            "LED": "fan1_fault",
             "Name": "System Fan connector 1",
             "Pwm": 0,
             "Tachs": [
@@ -629,6 +646,7 @@
             "Type": "IntelFanConnector"
         },
         {
+            "LED": "fan2_fault",
             "Name": "System Fan connector 2",
             "Pwm": 1,
             "Tachs": [
@@ -638,6 +656,7 @@
             "Type": "IntelFanConnector"
         },
         {
+            "LED": "fan3_fault",
             "Name": "System Fan connector 3",
             "Pwm": 2,
             "Tachs": [
@@ -647,6 +666,7 @@
             "Type": "IntelFanConnector"
         },
         {
+            "LED": "fan4_fault",
             "Name": "System Fan connector 4",
             "Pwm": 3,
             "Tachs": [
@@ -656,6 +676,7 @@
             "Type": "IntelFanConnector"
         },
         {
+            "LED": "fan5_fault",
             "Name": "System Fan connector 5",
             "Pwm": 4,
             "Tachs": [
@@ -665,6 +686,7 @@
             "Type": "IntelFanConnector"
         },
         {
+            "LED": "fan6_fault",
             "Name": "System Fan connector 6",
             "Pwm": 5,
             "Tachs": [
@@ -674,6 +696,7 @@
             "Type": "IntelFanConnector"
         },
         {
+            "LED": "fan7_fault",
             "Name": "System Fan connector 7",
             "Pwm": 6,
             "Tachs": [
@@ -683,6 +706,7 @@
             "Type": "IntelFanConnector"
         },
         {
+            "LED": "fan8_fault",
             "Name": "System Fan connector 8",
             "Pwm": 7,
             "Tachs": [
@@ -1048,27 +1072,61 @@
             "Address": 190,
             "Class": "MESensor",
             "Name": "Host Cpu Utilization",
-            "SensorType": "utilization",
             "ScaleValue": 0.392,
+            "SensorType": "utilization",
             "Type": "IpmbSensor"
         },
         {
             "Address": 191,
             "Class": "MESensor",
             "Name": "Host Pci Bandwidth Utilization",
-            "SensorType": "utilization",
             "ScaleValue": 0.392,
+            "SensorType": "utilization",
             "Type": "IpmbSensor"
         },
         {
             "Address": 192,
             "Class": "MESensor",
             "Name": "Host Memory Bandwidth Utilization",
-            "SensorType": "utilization",
             "ScaleValue": 0.392,
+            "SensorType": "utilization",
             "Type": "IpmbSensor"
         },
         {
+            "Name": "Node Manager Sensor",
+            "Type": "NMSensor"
+        },
+        {
+            "ARPOwnerSupport": false,
+            "BMCReceiverAddress": 18,
+            "BindingType": "MctpSMBus",
+            "Bus": "/dev/i2c-2",
+            "DefaultEID": 8,
+            "EIDPool": [
+                9,
+                10,
+                11,
+                12,
+                13,
+                14,
+                15,
+                16,
+                17,
+                18,
+                19,
+                20
+            ],
+            "Index": 0,
+            "Name": "MCTP SMBus PCIe slot",
+            "PhysicalMediumID": "Smbus3OrI2c400khzCompatible",
+            "ReqRetryCount": 2,
+            "ReqToRespTimeMs": 100,
+            "Role": "BusOwner",
+	    "TopMostBusOwner":false,
+	    "OwnEidPool":true,
+            "Type": "MctpConfiguration"
+        },
+        {
             "EthIndex": 0,
             "Name": "Dedicated Management NIC",
             "Type": "NIC"
@@ -1137,6 +1195,12 @@
             "Type": "PCA9546Mux"
         },
         {
+            "Address": "0x38",
+            "Bus": 4,
+            "Name": "PFR",
+            "Type": "PFR"
+        },
+        {
             "Interface": [
                 "i2c",
                 "peci"
@@ -1668,6 +1732,11 @@
             "Type": "PSUPresence"
         },
         {
+            "Name": "Power Unit Redundancy",
+            "RedundantCount": 1,
+            "Type": "PURedundancy"
+        },
+        {
             "Class": "temp",
             "FFGainCoefficient": 0.0,
             "FFOffCoefficient": 0.0,
@@ -1951,7 +2020,7 @@
             "Outputs": [],
             "PCoefficient": -0.15,
             "PositiveHysteresis": 0.0,
-            "SetPoint": 80.0,
+            "SetPoint": 60.0,
             "SlewNeg": -1,
             "SlewPos": 0.0,
             "Type": "Pid",
@@ -1977,7 +2046,7 @@
             "Outputs": [],
             "PCoefficient": -0.15,
             "PositiveHysteresis": 0.0,
-            "SetPoint": 80.0,
+            "SetPoint": 60.0,
             "SlewNeg": -1,
             "SlewPos": 0.0,
             "Type": "Pid",
@@ -2002,7 +2071,7 @@
             "Outputs": [],
             "PCoefficient": -0.15,
             "PositiveHysteresis": 0.0,
-            "SetPoint": 80.0,
+            "SetPoint": 60.0,
             "SlewNeg": -1,
             "SlewPos": 0.0,
             "Type": "Pid",
@@ -2028,7 +2097,7 @@
             "Outputs": [],
             "PCoefficient": -0.15,
             "PositiveHysteresis": 0.0,
-            "SetPoint": 80.0,
+            "SetPoint": 60.0,
             "SlewNeg": -1,
             "SlewPos": 0.0,
             "Type": "Pid",
@@ -2335,7 +2404,7 @@
             "Type": "TMP75"
         },
         {
-            "Address": "0x48",
+            "Address": "0x4C",
             "Bus": 6,
             "Name": "PCH M.2 Temp",
             "Thresholds": [
@@ -2409,6 +2478,8 @@
                     "Polarity": "Low"
                 }
             ],
+            "PiromI2cBus": 13,
+            "PiromI2cAddress": "0x50",
             "Type": "XeonCPU"
         },
         {
@@ -2422,13 +2493,15 @@
                     "Polarity": "Low"
                 }
             ],
+            "PiromI2cBus": 13,
+            "PiromI2cAddress": "0x51",
             "Type": "XeonCPU"
         },
         {
-            "Address": "0x38",
-            "Bus": 4,
-            "Name": "PFR",
-            "Type": "PFR"
+            "Name": "PCH SMBUS Slave",
+            "PchSmbusSlaveI2cBus": 3,
+            "PchSmbusSlaveI2cAddress": "0x44",
+            "Type": "PchSmbusSlave"
         }
     ],
     "Name": "WC Baseboard",
@@ -2451,4 +2524,4 @@
         "ProductId": 145
     },
     "xyz.openbmc_project.Inventory.Item.System": {}
-}
\ No newline at end of file
+}
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Chassis.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Chassis.json
index 12c2e6084..ad10d87a4 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Chassis.json
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Chassis.json
@@ -3,6 +3,7 @@
         {
             "BindConnector": "System Fan connector 1",
             "Index": 0,
+            "MaxReading": 21000,
             "Name": "Fan 1",
             "Thresholds": [
                 {
@@ -23,6 +24,7 @@
         {
             "BindConnector": "System Fan connector 2",
             "Index": 2,
+            "MaxReading": 21000,
             "Name": "Fan 2",
             "Thresholds": [
                 {
@@ -43,6 +45,7 @@
         {
             "BindConnector": "System Fan connector 3",
             "Index": 4,
+            "MaxReading": 21000,
             "Name": "Fan 3",
             "Thresholds": [
                 {
@@ -63,6 +66,7 @@
         {
             "BindConnector": "System Fan connector 6",
             "Index": 10,
+            "MaxReading": 21000,
             "Name": "Fan 4",
             "Thresholds": [
                 {
@@ -83,6 +87,7 @@
         {
             "BindConnector": "System Fan connector 7",
             "Index": 12,
+            "MaxReading": 21000,
             "Name": "Fan 5",
             "Thresholds": [
                 {
@@ -103,6 +108,7 @@
         {
             "BindConnector": "System Fan connector 8",
             "Index": 14,
+            "MaxReading": 21000,
             "Name": "Fan 6",
             "Thresholds": [
                 {
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json
index 573f1aec6..23869e812 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json
@@ -2414,6 +2414,12 @@
                 }
             ],
             "Type": "XeonCPU"
+        },
+        {
+            "Name": "PCH SMBUS Slave",
+            "PchSmbusSlaveI2cBus": 3,
+            "PchSmbusSlaveI2cAddress": "0x44",
+            "Type": "PchSmbusSlave"
         }
     ],
     "Name": "WP Baseboard",
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/blocklist.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/blocklist.json
new file mode 100644
index 000000000..477c87062
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/blocklist.json
@@ -0,0 +1,3 @@
+{
+    "buses": [9]
+}
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager_%.bbappend
index 6528bd513..80aba4906 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager_%.bbappend
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager_%.bbappend
@@ -9,11 +9,13 @@ SRC_URI_append = " file://0001-Blacklist-DIMM-Bus.patch \
                    file://J85894-HSBP.json \
                    file://CPC-Baseboard.json \
                    file://MIDPLANE-2U2X12SWITCH.json \
-                   file://WC-Chassis.json"
+                   file://WC-Chassis.json \
+                   file://blocklist.json"
 
 RDEPENDS_${PN} += " default-fru"
 
 do_install_append() {
      install -d ${D}/usr/share/entity-manager/configurations
      install -m 0444 ${WORKDIR}/*.json ${D}/usr/share/entity-manager/configurations
+     rm  ${D}/usr/share/entity-manager/configurations/blocklist.json
 }