diff options
| author | jmbills <jason.m.bills@intel.com> | 2021-08-03 01:45:08 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-03 01:45:08 +0300 |
| commit | 10ad77d5bc86709d8ff7f95e7040e39f1c153903 (patch) | |
| tree | 307cedb87f4c0a329740c55ac364ed489d1d8fc2 /meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch | |
| parent | c6b1c6ba7a01b7987d65d61c262c44c320193108 (diff) | |
| parent | 67327ddc580cb9a85219a534844832a1682780d4 (diff) | |
| download | openbmc-10ad77d5bc86709d8ff7f95e7040e39f1c153903.tar.xz | |
Update
Diffstat (limited to 'meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch index b01b96e16..ee1a8f7a4 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch @@ -1,4 +1,4 @@ -From 8534fb50dfe7c4e1c042843ded54c4ed23ee7bc2 Mon Sep 17 00:00:00 2001 +From cd13ae4e64d57af84dc98ff6c8d5b31661bc450d Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Tue, 8 Jan 2019 13:33:15 -0800 Subject: [PATCH] Enable PCIe L1 support @@ -11,12 +11,12 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index d7115c96f117..803ff94c4fc0 100644 +index 3db7d993d3ca..e2fcb732b6a6 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S -@@ -329,6 +329,20 @@ wait_lock: - bic r1, r2 - str r1, [r0] +@@ -349,6 +349,20 @@ wait_lock: + movt r1, #0x0000 + str r1, [r0] + /* enable PCIe L1 support */ + ldr r0, =0x1e6ed07c |