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| author | jmbills <jason.m.bills@intel.com> | 2021-06-25 18:34:41 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-25 18:34:41 +0300 |
| commit | c6b1c6ba7a01b7987d65d61c262c44c320193108 (patch) | |
| tree | c31fba338a65c86741b16e061d66e0e060e3b768 /meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch | |
| parent | e7436234669703196c5ed56f33050d2dc19127cd (diff) | |
| parent | defdca82c107f46e980c84bffb1b2c1263522fa0 (diff) | |
| download | openbmc-c6b1c6ba7a01b7987d65d61c262c44c320193108.tar.xz | |
Update
Diffstat (limited to 'meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch new file mode 100644 index 000000000..b01b96e16 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch @@ -0,0 +1,40 @@ +From 8534fb50dfe7c4e1c042843ded54c4ed23ee7bc2 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Tue, 8 Jan 2019 13:33:15 -0800 +Subject: [PATCH] Enable PCIe L1 support + +This commit enables PCIe L1 support using magic registers. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/mach-aspeed/ast2600/platform.S | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S +index d7115c96f117..803ff94c4fc0 100644 +--- a/arch/arm/mach-aspeed/ast2600/platform.S ++++ b/arch/arm/mach-aspeed/ast2600/platform.S +@@ -329,6 +329,20 @@ wait_lock: + bic r1, r2 + str r1, [r0] + ++ /* enable PCIe L1 support */ ++ ldr r0, =0x1e6ed07c ++ ldr r1, =0xa8 ++ str r1, [r0] ++ ldr r0, =0x1e6ed010 ++ ldr r1, =0x27040fe1 ++ str r1, [r0] ++ ldr r0, =0x1e6ed068 ++ ldr r1, =0xc81f0a ++ str r1, [r0] ++ ldr r0, =0x1e6ed07c ++ mov r1, #0 ++ str r1, [r0] ++ + /* MMIO decode setting */ + ldr r0, =AST_SCU_MMIO_DEC_SET + mov r1, #0x2000 +-- +2.17.1 + |