diff options
author | Jason M. Bills <jason.m.bills@linux.intel.com> | 2019-10-28 20:43:30 +0300 |
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committer | Jason M. Bills <jason.m.bills@linux.intel.com> | 2019-10-29 18:58:16 +0300 |
commit | 6f65bb40d3e8b7fe978698488c2ea93f077bfcd6 (patch) | |
tree | 41861c8b837d122abac15f18dbdf99cbd4835507 /meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files | |
parent | da710c8bb0dea17982efc20ab4ee226a86992e6f (diff) | |
download | openbmc-6f65bb40d3e8b7fe978698488c2ea93f077bfcd6.tar.xz |
Update to internal 10-28-19
Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files')
3 files changed, 175 insertions, 33 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch index 10a45fa23..4714dd6cc 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch @@ -1,19 +1,19 @@ -From 34ccbd14d8f5caa66523a762e2030b6f105206cb Mon Sep 17 00:00:00 2001 +From 039b9a278a4d075e455a38ec93171dc812aec8b2 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Fri, 16 Nov 2018 15:57:57 -0800 -Subject: [PATCH] aspeed: add Pwm Driver +Subject: [PATCH 1/1] aspeed: add Pwm Driver Change-Id: Ia8b80212f7c70aafcc6a71782936ec95cf9b7f38 - +Signed-off-by: James Feist <james.feist@linux.intel.com> --- - board/aspeed/ast-g5/ast-g5-intel.c | 105 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 105 insertions(+) + board/aspeed/ast-g5/ast-g5-intel.c | 113 +++++++++++++++++++++++++++++ + 1 file changed, 113 insertions(+) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e53f5eb..c7ae566 100644 +index e74999223b..74e218dfd0 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -255,9 +255,114 @@ int intel_force_firmware_jumper_enabled(void) +@@ -257,9 +257,122 @@ int intel_force_firmware_jumper_enabled(void) return gpio_get_value(GPIO_FF_UPD_JUMPER); } @@ -35,7 +35,7 @@ index e53f5eb..c7ae566 100644 + +#define PWM_CLK_ENABLE BIT(0) +#define PWM_DUTY(PCT) (((PCT) * 128) / 100) -+#define PWM_DUTY_VALUE PWM_DUTY(57) ++#define DEFAULT_PWM_DUTY_VALUE PWM_DUTY(57) + + +static inline uint32_t ast_scu_read(uint32_t reg) @@ -57,10 +57,34 @@ index e53f5eb..c7ae566 100644 +#endif +} + ++static void set_pwm_duty_cycle(int duty) ++{ ++ uint32_t chan; ++ uint32_t val; ++ ++ /* enable pwm channels */ ++ for (chan = 0; chan < PWM_CHANNEL_COUNT; chan++) { ++ uint32_t base = chan < 4 ? PWM_BASE_ADDR : PWM_BASE_ADDR + 0x40; ++ uint8_t ch_duty_shift = 16 * (chan & 0x1); ++ uint8_t ch_pair = (chan & 0x3) / 2; ++ ++ /* enable pwm for the channel */ ++ val = readl(base); ++ val |= ((1 << (chan & 0x3)) << 8); ++ writel(val, base); ++ ++ /* set duty cycle */ ++ val = readl(base + PWM_DUTY_CYCLE + ch_pair * 4); ++ val &= ~(0xffff << ch_duty_shift); ++ val |= (((uint32_t)duty) << 8) << ch_duty_shift; ++ writel(val, base + PWM_DUTY_CYCLE + ch_pair * 4); ++ } ++ ++} ++ +static void pwm_init(void) +{ + uint32_t val; -+ uint32_t chan; + + /* select pwm 0-7 */ + val = ast_scu_read(AST_SCU_FUN_PIN_CTRL3); @@ -93,23 +117,7 @@ index e53f5eb..c7ae566 100644 + writel(0x1, PWM_BASE_ADDR + PWM_CONTROL); + writel(0x1, PWM_BASE_ADDR + PWM_CONTROL_EXT); + -+ /* enable pwm channels */ -+ for (chan = 0; chan < PWM_CHANNEL_COUNT; chan++) { -+ uint32_t base = chan < 4 ? PWM_BASE_ADDR : PWM_BASE_ADDR + 0x40; -+ uint8_t ch_duty_shift = 16 * (chan & 0x1); -+ uint8_t ch_pair = (chan & 0x3) / 2; -+ -+ /* enable pwm for the channel */ -+ val = readl(base); -+ val |= ((1 << (chan & 0x3)) << 8); -+ writel(val, base); -+ -+ /* set duty cycle */ -+ val = readl(base + PWM_DUTY_CYCLE + ch_pair * 4); -+ val &= ~(0xffff << ch_duty_shift); -+ val |= (((uint32_t)PWM_DUTY_VALUE) << 8) << ch_duty_shift; -+ writel(val, base + PWM_DUTY_CYCLE + ch_pair * 4); -+ } ++ set_pwm_duty_cycle(DEFAULT_PWM_DUTY_VALUE); + + /* set up clock type M: period = 127 units at 24MHz/8 (resulting ~23kHz period) */ + writel(0x7f30, PWM_BASE_ADDR + PWM_CLOCK_SELECTION); @@ -128,3 +136,6 @@ index e53f5eb..c7ae566 100644 gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); espi_init(); sgpio_init(); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch index b41403fe3..575d0ceae 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch @@ -1,7 +1,7 @@ -From 2c5ae4ff71edda4d2d9cc0d289f61635409c3be4 Mon Sep 17 00:00:00 2001 +From fa89d568a5ad08fdf936a4ac0b2445ba4df5e948 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Wed, 24 Jul 2019 20:11:30 +0530 -Subject: [PATCH 2/2] PFR FW update and checkpoint support in u-boot +Subject: [PATCH 1/1] PFR FW update and checkpoint support in u-boot 1) Added firmware update ipmi commands support for PFR images. This enables PFR based firmware @@ -45,7 +45,7 @@ index 0b2d936c23..9021d7fc08 100644 obj-y += fw-update.o +obj-y += pfr-mgr.o diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index c58fd3591b..13889594bf 100644 +index 5f1bc625ff..8c3c9948a7 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -16,6 +16,7 @@ @@ -56,7 +56,7 @@ index c58fd3591b..13889594bf 100644 /* Names to match the GPIOs */ enum gpio_names { -@@ -582,6 +583,10 @@ void ast_g5_intel(void) +@@ -634,6 +635,10 @@ void ast_g5_intel(void) ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); @@ -67,10 +67,10 @@ index c58fd3591b..13889594bf 100644 uart_init(); pwm_init(); gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); -@@ -595,6 +600,11 @@ void ast_g5_intel(void) - id_led_control(GPIO_GREEN_LED, EIDLED_Off); - id_led_control(GPIO_AMBER_LED, EIDLED_On); +@@ -649,6 +654,11 @@ void ast_g5_intel(void) kcs_init(); + if (intel_get_platform_id() == COOPER_CITY_BOARD_ID) + set_pwm_duty_cycle(ELEVATED_PWM_DUTY_VALUE); + /* Notify CPLD about FFUJ jumper set and pause + * of booting for indefinitely time. It will be + * resumed once reset is done. */ diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0038-Increase-default-fan-speed-for-cooper-city.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0038-Increase-default-fan-speed-for-cooper-city.patch new file mode 100644 index 000000000..53cdd763e --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0038-Increase-default-fan-speed-for-cooper-city.patch @@ -0,0 +1,131 @@ +From e465945672408b632d5e3c2cf7f08ade1268419e Mon Sep 17 00:00:00 2001 +From: James Feist <james.feist@linux.intel.com> +Date: Thu, 24 Oct 2019 14:39:22 -0700 +Subject: [PATCH 1/1] Increase default fan speed for cooper city + +This increases the uboot fan speed for cooper city +as it has high core count CPUS. + +Tested: In uboot fans appeared to run faster + +Signed-off-by: James Feist <james.feist@linux.intel.com> +--- + board/aspeed/ast-g5/ast-g5-gpio.h | 6 ++++ + board/aspeed/ast-g5/ast-g5-intel.c | 46 ++++++++++++++++++++++++++++++ + 2 files changed, 52 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h +index ed2499f5cc..9088cdd3e3 100644 +--- a/board/aspeed/ast-g5/ast-g5-gpio.h ++++ b/board/aspeed/ast-g5/ast-g5-gpio.h +@@ -70,9 +70,15 @@ + #define ID_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_6) + #define GRN_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_4) + #define AMB_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_5) ++#define PLATFORM_ID0_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_0) ++#define PLATFORM_ID1_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_1) ++#define PLATFORM_ID2_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_2) ++#define PLATFORM_ID3_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_3) ++#define PLATFORM_ID4_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_4) + #define FORCE_BMC_UPDATE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_0) + #define TPM_EN_PULSE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_6) + #define FP_PWR_BTN_PORT_PIN PORT_PIN(GPIO_PORT_E, GPIO_PIN_2) ++#define PLATFORM_ID5_PORT_PIN PORT_PIN(GPIO_PORT_G, GPIO_PIN_5) + + // GPIO Configuration Register bits + #define GPCFG_EVENT_TO_SMI (1 << 7) // 1 == enabled +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index c58fd3591b..9d5db68b7e 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -25,6 +25,12 @@ enum gpio_names { + GPIO_FF_UPD_JUMPER, + GPIO_ENABLE_TPM_PULSE, + GPIO_FP_PWR_BTN, ++ GPIO_PLATFORM_ID_0, ++ GPIO_PLATFORM_ID_1, ++ GPIO_PLATFORM_ID_2, ++ GPIO_PLATFORM_ID_3, ++ GPIO_PLATFORM_ID_4, ++ GPIO_PLATFORM_ID_5, + }; + + #define GPIO_CFG_DEFAULT (GPCFG_ACTIVE_HIGH | GPCFG_LEVEL_TRIG) +@@ -60,6 +66,21 @@ static const GPIOValue gpio_table[] = { + [GPIO_FP_PWR_BTN] = {FP_PWR_BTN_PORT_PIN, GPIO_CFG_DEFAULT, 0, + GPIO_DEBOUNCE_8MS}, + ++ /* Platform ID Pins */ ++ [GPIO_PLATFORM_ID_0] = {PLATFORM_ID0_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ GPIO_DEBOUNCE_8MS}, ++ [GPIO_PLATFORM_ID_1] = {PLATFORM_ID1_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ GPIO_DEBOUNCE_8MS}, ++ [GPIO_PLATFORM_ID_2] = {PLATFORM_ID2_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ GPIO_DEBOUNCE_8MS}, ++ [GPIO_PLATFORM_ID_3] = {PLATFORM_ID3_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ GPIO_DEBOUNCE_8MS}, ++ [GPIO_PLATFORM_ID_4] = {PLATFORM_ID4_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ GPIO_DEBOUNCE_8MS}, ++ [GPIO_PLATFORM_ID_5] = {PLATFORM_ID5_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ GPIO_DEBOUNCE_8MS}, ++ ++ + }; + + #define LPC_SNOOP_ADDR 0x80 +@@ -114,6 +135,8 @@ static const GPIOValue gpio_table[] = { + #define WATCHDOG_RESET_BIT 0x8 + #define BOOT_FAILURE_LIMIT 0x3 + ++#define COOPER_CITY_BOARD_ID 40 ++ + static int get_boot_failures(void) + { + return getenv_ulong("bootfailures", 10, 0); +@@ -295,6 +318,26 @@ int intel_failed_boot(void) + return get_boot_failures() >= BOOT_FAILURE_LIMIT; + } + ++int intel_get_platform_id(void) ++{ ++ int id = 0; ++ int temp = 0; ++ int gpios[] = {GPIO_PLATFORM_ID_0, ++ GPIO_PLATFORM_ID_1, ++ GPIO_PLATFORM_ID_2, ++ GPIO_PLATFORM_ID_3, ++ GPIO_PLATFORM_ID_4, ++ GPIO_PLATFORM_ID_5}; ++ int ii; ++ for (ii = 0; ii < ARRAY_SIZE(gpios); ii++){ ++ temp = gpio_get_value(gpios[ii]); ++ if(temp < 0) ++ return temp; ++ id |= temp << ii; ++ } ++ return id; ++} ++ + void arch_preboot_os(void) + { + // last second before booting... set the LEDs +@@ -322,6 +365,7 @@ void arch_preboot_os(void) + #define PWM_CLK_ENABLE BIT(0) + #define PWM_DUTY(PCT) (((PCT) * 128) / 100) + #define DEFAULT_PWM_DUTY_VALUE PWM_DUTY(57) ++#define ELEVATED_PWM_DUTY_VALUE PWM_DUTY(80) + + + static inline uint32_t ast_scu_read(uint32_t reg) +@@ -595,6 +639,8 @@ void ast_g5_intel(void) + id_led_control(GPIO_GREEN_LED, EIDLED_Off); + id_led_control(GPIO_AMBER_LED, EIDLED_On); + kcs_init(); ++ if (intel_get_platform_id() == COOPER_CITY_BOARD_ID) ++ set_pwm_duty_cycle(ELEVATED_PWM_DUTY_VALUE); + /* TODO: need to stop the booting here. */ + } + } +-- +2.17.1 + |