diff options
| author | Ed Tanous <ed.tanous@intel.com> | 2019-07-31 20:43:37 +0300 |
|---|---|---|
| committer | Ed Tanous <ed.tanous@intel.com> | 2019-08-01 18:19:38 +0300 |
| commit | d0f63ef62c76c932a2003eaa42c0b250065ae06f (patch) | |
| tree | 4c0e3cb32dc80f80460bdbf82ff6d401d4ff194f /meta-openbmc-mods/meta-common/recipes-bsp/u-boot | |
| parent | b4f66bacb1b8e661d794fa7a189e2f66f5092e2e (diff) | |
| download | openbmc-d0f63ef62c76c932a2003eaa42c0b250065ae06f.tar.xz | |
Update to internal 7-31-19
Signed-off-by: Ed Tanous <ed.tanous@intel.com>
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot')
32 files changed, 1196 insertions, 439 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch index 86fa5b7d5..8937047c5 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch @@ -1,28 +1,16 @@ -Index: u-boot/include/configs/ast-common.h -=================================================================== ---- u-boot.orig/include/configs/ast-common.h -+++ u-boot/include/configs/ast-common.h -@@ -103,10 +103,13 @@ - #define CONFIG_SYS_MAX_FLASH_BANKS (CONFIG_FMC_CS) - #define CONFIG_SYS_MAX_FLASH_SECT (8192) /* max number of sectors on one chip */ - #define CONFIG_ENV_IS_IN_FLASH 1 --#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + 0x60000) -+#define CONFIG_ENV_OFFSET 0x2400000 /* environment starts here */ -+#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) -+#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - --#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */ --#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -+#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET_REDUND) -+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - - #define CONFIG_BOOTCOMMAND "bootm 20080000" - #define CONFIG_ENV_OVERWRITE -Index: u-boot/common/board_r.c -=================================================================== ---- u-boot.orig/common/board_r.c -+++ u-boot/common/board_r.c +From 7979a73fba832747ed3c037c0b47c9e67dcf283e Mon Sep 17 00:00:00 2001 +From: Vernon Mauery <vernon.mauery@intel.com> +Date: Mon, 30 Apr 2018 10:52:37 -0700 + +--- + common/board_r.c | 8 ++++++-- + include/configs/ast-common.h | 9 ++++++--- + 2 files changed, 12 insertions(+), 5 deletions(-) + +diff --git a/common/board_r.c b/common/board_r.c +index d959ad3..74797ed 100644 +--- a/common/board_r.c ++++ b/common/board_r.c @@ -494,10 +494,14 @@ static int should_load_env(void) static int initr_env(void) { @@ -40,3 +28,24 @@ Index: u-boot/common/board_r.c #ifdef CONFIG_OF_CONTROL setenv_addr("fdtcontroladdr", gd->fdt_blob); #endif +diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h +index eff6d2b..b7d7192 100644 +--- a/include/configs/ast-common.h ++++ b/include/configs/ast-common.h +@@ -103,10 +103,13 @@ + #define CONFIG_SYS_MAX_FLASH_BANKS (CONFIG_FMC_CS) + #define CONFIG_SYS_MAX_FLASH_SECT (8192) /* max number of sectors on one chip */ + #define CONFIG_ENV_IS_IN_FLASH 1 +-#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + 0x60000) ++#define CONFIG_ENV_OFFSET 0x2400000 /* environment starts here */ ++#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) ++#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +-#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */ +-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ ++#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) ++#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET_REDUND) ++#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + + #define CONFIG_BOOTCOMMAND "bootm 20080000" + #define CONFIG_ENV_OVERWRITE diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch index 8bc0a3ed3..e7e6c56d7 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch @@ -1,4 +1,4 @@ -From 2f0e14630abec2c9679d21901072648c7802f2c4 Mon Sep 17 00:00:00 2001 +From 954e7dd9ff9c5d1159f0896afa34c673061b82ea Mon Sep 17 00:00:00 2001 From: Yong Li <yong.b.li@linux.intel.com> Date: Tue, 11 Sep 2018 16:24:06 +0800 Subject: [PATCH] Make sure debug uart is using 24MHz clock source @@ -7,6 +7,7 @@ u-boot defines the uart5(debug console) as 24MHz, set the SCU14[28] to 0, to make sure the clock source is 24M Signed-off-by: Yong Li <yong.b.li@linux.intel.com> + --- arch/arm/include/asm/arch-aspeed/ast_scu.h | 2 ++ arch/arm/include/asm/arch-aspeed/platform.h | 1 + @@ -15,10 +16,10 @@ Signed-off-by: Yong Li <yong.b.li@linux.intel.com> 4 files changed, 17 insertions(+) diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h -index d248416..98e6335 100644 +index dcbc673..06825ce 100644 --- a/arch/arm/include/asm/arch-aspeed/ast_scu.h +++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h -@@ -45,4 +45,6 @@ extern void ast_scu_init_eth(u8 num); +@@ -46,4 +46,6 @@ extern void ast_scu_init_eth(u8 num); extern void ast_scu_multi_func_eth(u8 num); extern void ast_scu_multi_func_romcs(u8 num); @@ -26,7 +27,7 @@ index d248416..98e6335 100644 + #endif diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h -index c9c7a81..a423052 100644 +index 1c02914..92ea33b 100644 --- a/arch/arm/include/asm/arch-aspeed/platform.h +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -27,6 +27,7 @@ @@ -38,10 +39,10 @@ index c9c7a81..a423052 100644 #err "No define for platform.h" #endif diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index 0cc0d67..902263b 100644 +index 12de9b8..fff02dc 100644 --- a/arch/arm/mach-aspeed/ast-scu.c +++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -496,3 +496,9 @@ void ast_scu_get_who_init_dram(void) +@@ -538,3 +538,9 @@ void ast_scu_get_who_init_dram(void) break; } } @@ -70,6 +71,3 @@ index e67a4bf..5a1fade 100644 int board_init(void) { gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch index 0385a5e31..6bd063e39 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch @@ -1,7 +1,7 @@ -From b344cf4462acb1f043ed903ccee713e24ce7226d Mon Sep 17 00:00:00 2001 +From 7e11461d6b65969005605f13677269eb91d39643 Mon Sep 17 00:00:00 2001 From: Kuiying Wang <kuiying.wang@intel.com> Date: Wed, 7 Nov 2018 13:57:57 +0800 -Subject: [PATCH 1/1] enable passthrough in uboot +Subject: [PATCH] enable passthrough in uboot --- arch/arm/mach-aspeed/ast-scu.c | 22 ++++++++++++++++++++++ @@ -9,10 +9,10 @@ Subject: [PATCH 1/1] enable passthrough in uboot 2 files changed, 24 insertions(+) diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index 902263b28b..c83931ed54 100644 +index fff02dc..d27f3d3 100644 --- a/arch/arm/mach-aspeed/ast-scu.c +++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -502,3 +502,25 @@ void ast_config_uart5_clk(void) +@@ -544,3 +544,25 @@ void ast_config_uart5_clk(void) ast_scu_write(ast_scu_read(AST_SCU_MISC2_CTRL) & ~(1 << 28), AST_SCU_MISC2_CTRL); } @@ -39,7 +39,7 @@ index 902263b28b..c83931ed54 100644 + } +} diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index 5a1fadeedd..b492003f51 100644 +index 5a1fade..b492003 100644 --- a/board/aspeed/ast-g5/ast-g5.c +++ b/board/aspeed/ast-g5/ast-g5.c @@ -20,6 +20,8 @@ int board_early_init_f(void) @@ -51,6 +51,3 @@ index 5a1fadeedd..b492003f51 100644 return 0; } --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch index dbaf7b362..4f90d6dfe 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch @@ -1,7 +1,7 @@ -From f33755167ddcdebbf56bc875e4091990273c6997 Mon Sep 17 00:00:00 2001 +From e782f6a90468fee35877b78e248a17f39f67c94c Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 10:21:40 -0800 -Subject: [PATCH 1/7] Add Aspeed g5 interrupt support +Subject: [PATCH] Add Aspeed g5 interrupt support This adds a few new files to the board g5 directory. Several Intel features require interrupts running in U-Boot, so this adds basic @@ -9,25 +9,26 @@ interrupt registration and handling support. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> Change-Id: Id7072f1408dcf364968b1b74f2192e50a22a82f0 + --- - Kconfig | 13 ++ - arch/arm/lib/interrupts.c | 11 ++ - board/aspeed/ast-g5/Makefile | 4 +- - board/aspeed/ast-g5/ast-g5-irq.c | 176 ++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-irq.h | 39 ++++++ + Kconfig | 13 +++ + arch/arm/lib/interrupts.c | 11 +++ + board/aspeed/ast-g5/Makefile | 3 +- + board/aspeed/ast-g5/ast-g5-irq.c | 176 ++++++++++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-irq.h | 39 ++++++++ board/aspeed/ast-g5/ast-g5.c | 3 + board/aspeed/ast-g5/ast-g5.h | 7 ++ cmd/Kconfig | 5 + configs/ast_g5_ncsi_2boot_defconfig | 1 + configs/ast_g5_ncsi_defconfig | 1 + configs/ast_g5_phy_defconfig | 1 + - 11 files changed, 260 insertions(+), 1 deletion(-) + 11 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 board/aspeed/ast-g5/ast-g5-irq.c create mode 100644 board/aspeed/ast-g5/ast-g5-irq.h create mode 100644 board/aspeed/ast-g5/ast-g5.h diff --git a/Kconfig b/Kconfig -index 3ceff25032..d6439d01ca 100644 +index 3ceff25..d6439d0 100644 --- a/Kconfig +++ b/Kconfig @@ -115,6 +115,19 @@ if EXPERT @@ -51,7 +52,7 @@ index 3ceff25032..d6439d01ca 100644 menu "Boot images" diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c -index ed83043abb..a96b3aa070 100644 +index ed83043..a96b3aa 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -94,6 +94,17 @@ int disable_interrupts (void) @@ -73,7 +74,7 @@ index ed83043abb..a96b3aa070 100644 int interrupt_init (void) { diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index d1d7f8525e..d41b11589f 100644 +index d1d7f85..df4e639 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -1 +1,2 @@ @@ -82,7 +83,7 @@ index d1d7f8525e..d41b11589f 100644 +obj-y += ast-g5-irq.o diff --git a/board/aspeed/ast-g5/ast-g5-irq.c b/board/aspeed/ast-g5/ast-g5-irq.c new file mode 100644 -index 0000000000..860f16cf05 +index 0000000..860f16c --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-irq.c @@ -0,0 +1,176 @@ @@ -264,7 +265,7 @@ index 0000000000..860f16cf05 +#endif diff --git a/board/aspeed/ast-g5/ast-g5-irq.h b/board/aspeed/ast-g5/ast-g5-irq.h new file mode 100644 -index 0000000000..703eeabf13 +index 0000000..703eeab --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-irq.h @@ -0,0 +1,39 @@ @@ -308,7 +309,7 @@ index 0000000000..703eeabf13 + +#endif /* __AST_G5_IRQ_H__ */ diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index b492003f51..2472aa3603 100644 +index b492003..2472aa3 100644 --- a/board/aspeed/ast-g5/ast-g5.c +++ b/board/aspeed/ast-g5/ast-g5.c @@ -14,6 +14,8 @@ @@ -330,7 +331,7 @@ index b492003f51..2472aa3603 100644 } diff --git a/board/aspeed/ast-g5/ast-g5.h b/board/aspeed/ast-g5/ast-g5.h new file mode 100644 -index 0000000000..9fd10eccb3 +index 0000000..9fd10ec --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5.h @@ -0,0 +1,7 @@ @@ -342,7 +343,7 @@ index 0000000000..9fd10eccb3 + +#endif /* _AST_G5_H_ */ diff --git a/cmd/Kconfig b/cmd/Kconfig -index d69b817c82..33be2407d2 100644 +index d69b817..33be240 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -313,6 +313,11 @@ endmenu @@ -358,7 +359,7 @@ index d69b817c82..33be2407d2 100644 bool "dm - Access to driver model information" depends on DM diff --git a/configs/ast_g5_ncsi_2boot_defconfig b/configs/ast_g5_ncsi_2boot_defconfig -index 2d28c86966..d5b7894a9e 100644 +index 2d28c86..d5b7894 100644 --- a/configs/ast_g5_ncsi_2boot_defconfig +++ b/configs/ast_g5_ncsi_2boot_defconfig @@ -33,3 +33,4 @@ CONFIG_CMD_CRC32=y @@ -367,7 +368,7 @@ index 2d28c86966..d5b7894a9e 100644 CONFIG_CMD_MX_CYCLIC=y +CONFIG_USE_IRQ=y diff --git a/configs/ast_g5_ncsi_defconfig b/configs/ast_g5_ncsi_defconfig -index 74029ed514..9481e5fb6e 100644 +index 74029ed..9481e5f 100644 --- a/configs/ast_g5_ncsi_defconfig +++ b/configs/ast_g5_ncsi_defconfig @@ -11,3 +11,4 @@ CONFIG_HUSH_PARSER=y @@ -376,7 +377,7 @@ index 74029ed514..9481e5fb6e 100644 CONFIG_SYS_NS16550=y +CONFIG_USE_IRQ=y diff --git a/configs/ast_g5_phy_defconfig b/configs/ast_g5_phy_defconfig -index 767f3af605..4aefcf49e8 100644 +index 767f3af..4aefcf4 100644 --- a/configs/ast_g5_phy_defconfig +++ b/configs/ast_g5_phy_defconfig @@ -12,3 +12,4 @@ CONFIG_HUSH_PARSER=y @@ -384,6 +385,3 @@ index 767f3af605..4aefcf49e8 100644 CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_USE_IRQ=y --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch index 18cc2f9c8..b37aee7e6 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch @@ -1,7 +1,7 @@ -From 7ad0ea13337550f35c1e726f21d4751bf74078d6 Mon Sep 17 00:00:00 2001 +From c46cb2dd703f55ca63ed9c5cf2a97868a7e6c209 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 10:21:40 -0800 -Subject: [PATCH 2/7] Add espi support +Subject: [PATCH] Add espi support This adds basic eSPI support for U-Boot. The eSPI driver works best with interrupts because the timing of the initialization with the PCH is not @@ -13,18 +13,19 @@ functions. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> Change-Id: Id7072f1408dcf364968b1b74f2192e50a22a82f0 + --- arch/arm/include/asm/arch-aspeed/regs-scu.h | 2 + - board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-espi.c | 231 ++++++++++++++++++++ + board/aspeed/ast-g5/Makefile | 2 + + board/aspeed/ast-g5/ast-g5-espi.c | 231 ++++++++++++++++++++++++++++ board/aspeed/ast-g5/ast-g5-intel.c | 16 ++ board/aspeed/ast-g5/ast-g5.c | 3 + - 5 files changed, 253 insertions(+) + 5 files changed, 254 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-espi.c create mode 100644 board/aspeed/ast-g5/ast-g5-intel.c diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h -index b714fa9234..10b983a966 100644 +index b714fa9..10b983a 100644 --- a/arch/arm/include/asm/arch-aspeed/regs-scu.h +++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h @@ -552,6 +552,8 @@ @@ -37,7 +38,7 @@ index b714fa9234..10b983a966 100644 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index d41b11589f..58e0c648f4 100644 +index df4e639..58e0c64 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -1,2 +1,4 @@ @@ -47,7 +48,7 @@ index d41b11589f..58e0c648f4 100644 obj-y += ast-g5-irq.o diff --git a/board/aspeed/ast-g5/ast-g5-espi.c b/board/aspeed/ast-g5/ast-g5-espi.c new file mode 100644 -index 0000000000..79ef253b86 +index 0000000..79ef253 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-espi.c @@ -0,0 +1,231 @@ @@ -284,7 +285,7 @@ index 0000000000..79ef253b86 +} diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c new file mode 100644 -index 0000000000..e79235c8d0 +index 0000000..e79235c --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -0,0 +1,16 @@ @@ -305,7 +306,7 @@ index 0000000000..e79235c8d0 + espi_init(); +} diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index 2472aa3603..d41ef9cbd3 100644 +index 2472aa3..d41ef9c 100644 --- a/board/aspeed/ast-g5/ast-g5.c +++ b/board/aspeed/ast-g5/ast-g5.c @@ -18,6 +18,8 @@ @@ -325,6 +326,3 @@ index 2472aa3603..d41ef9cbd3 100644 return 0; } --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch index e16b0f158..5fa4bffa1 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch @@ -1,4 +1,4 @@ -From c3b44c02392d33cfec85056fd323d93fdc6e523f Mon Sep 17 00:00:00 2001 +From 40e02e4ffa13c0128db555a3a3982a7cdc0ebf60 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 12:09:52 -0800 Subject: [PATCH] add sgio support for port80 snoop post LEDs @@ -8,6 +8,7 @@ ultimately drives the POST code LEDs. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> Change-Id: Iaa1b91cd40f4b6323dba0598da373cb631459e66 + --- arch/arm/include/asm/arch-aspeed/ast_scu.h | 1 + arch/arm/mach-aspeed/ast-scu.c | 8 +++ @@ -155,6 +156,3 @@ index e79235c..c2a8b33 100644 espi_init(); + sgpio_init(); } --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch index a49f196ac..f7dd80504 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch @@ -1,7 +1,7 @@ -From 89728d8c255204c8d9ec46a1dc0d412b04708f22 Mon Sep 17 00:00:00 2001 +From 0fbd5fe6fa08f709b64bdbad6440ea77b422fc4b Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Fri, 16 Nov 2018 09:58:01 -0800 -Subject: [PATCH 4/7] Add basic GPIO support +Subject: [PATCH] Add basic GPIO support Add a table of well-known gpios (such as FP LEDs and FF UPD jumper) and initialize them at boot. @@ -10,18 +10,19 @@ Add a mechanism to get/set well known gpios from command line. Change-Id: I4136a5ccb048b3604f13b17ea0c18a4bc596c249 Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> + --- board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-gpio.c | 195 +++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-gpio.h | 102 +++++++++++++++ - board/aspeed/ast-g5/ast-g5-intel.c | 42 +++++++ + board/aspeed/ast-g5/ast-g5-gpio.c | 195 +++++++++++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-gpio.h | 102 +++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 42 ++++++++ board/aspeed/ast-g5/ast-g5.h | 1 + 5 files changed, 341 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-gpio.c create mode 100644 board/aspeed/ast-g5/ast-g5-gpio.h diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 58e0c648f4..2970ae5741 100644 +index 58e0c64..2970ae5 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -2,3 +2,4 @@ obj-y += ast-g5.o @@ -31,7 +32,7 @@ index 58e0c648f4..2970ae5741 100644 +obj-y += ast-g5-gpio.o diff --git a/board/aspeed/ast-g5/ast-g5-gpio.c b/board/aspeed/ast-g5/ast-g5-gpio.c new file mode 100644 -index 0000000000..d596c15914 +index 0000000..d596c15 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-gpio.c @@ -0,0 +1,195 @@ @@ -232,7 +233,7 @@ index 0000000000..d596c15914 + ""); diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h new file mode 100644 -index 0000000000..a820c0fcad +index 0000000..a820c0f --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-gpio.h @@ -0,0 +1,102 @@ @@ -339,7 +340,7 @@ index 0000000000..a820c0fcad + +#endif /* __HW_GPIO_H__ */ diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index fca4d91115..252a05dd73 100644 +index c2a8b33..069e7a3 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -14,6 +14,47 @@ @@ -399,7 +400,7 @@ index fca4d91115..252a05dd73 100644 sgpio_init(); } diff --git a/board/aspeed/ast-g5/ast-g5.h b/board/aspeed/ast-g5/ast-g5.h -index 9fd10eccb3..908db1477b 100644 +index 9fd10ec..908db14 100644 --- a/board/aspeed/ast-g5/ast-g5.h +++ b/board/aspeed/ast-g5/ast-g5.h @@ -3,5 +3,6 @@ @@ -409,6 +410,3 @@ index 9fd10eccb3..908db1477b 100644 +#include "ast-g5-gpio.h" #endif /* _AST_G5_H_ */ --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch index c97e6d74f..c6ee49f57 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch @@ -1,4 +1,4 @@ -From 1f710737f2fe8dea4bc5ebef1e6011de294764b4 Mon Sep 17 00:00:00 2001 +From d08d22af794eed7b928ab96030a103cfb7bf6ce1 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Fri, 16 Nov 2018 14:59:04 -0800 Subject: [PATCH] Update Force Firmware Update Jumper to use new gpio API @@ -8,17 +8,18 @@ functions, such as autoboot. Change-Id: I8ead931e9dd828522095a0ef386875be652ec885 Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> + --- - .../include/asm/arch-aspeed/ast-g5-intel.h | 19 +++++++++++++++++++ - arch/arm/include/asm/arch-aspeed/platform.h | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 5 +++++ - common/autoboot.c | 6 ++++++ + arch/arm/include/asm/arch-aspeed/ast-g5-intel.h | 19 +++++++++++++++++++ + arch/arm/include/asm/arch-aspeed/platform.h | 1 + + board/aspeed/ast-g5/ast-g5-intel.c | 5 +++++ + common/autoboot.c | 6 ++++++ 4 files changed, 31 insertions(+) create mode 100644 arch/arm/include/asm/arch-aspeed/ast-g5-intel.h diff --git a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h new file mode 100644 -index 0000000000..cd9a0994fa +index 0000000..cd9a099 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h @@ -0,0 +1,19 @@ @@ -42,7 +43,7 @@ index 0000000000..cd9a0994fa + +#endif /* __AST_INTEL_G5_H__ */ diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h -index 9f339e913a..3ea1c99089 100644 +index 92ea33b..3b06e52 100644 --- a/arch/arm/include/asm/arch-aspeed/platform.h +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -27,6 +27,7 @@ @@ -54,7 +55,7 @@ index 9f339e913a..3ea1c99089 100644 #else #err "No define for platform.h" diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 252a05dd73..58ad6a55b8 100644 +index 069e7a3..144765a 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -145,6 +145,11 @@ static void sgpio_init(void) @@ -70,7 +71,7 @@ index 252a05dd73..58ad6a55b8 100644 void ast_g5_intel(void) { diff --git a/common/autoboot.c b/common/autoboot.c -index c52bad84a4..d66c0fa63a 100644 +index c52bad8..d66c0fa 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -14,6 +14,7 @@ @@ -93,6 +94,3 @@ index c52bad84a4..d66c0fa63a 100644 if (bootdelay >= 0) abort = __abortboot(bootdelay); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch index 11a474b96..26b4c4fc9 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch @@ -1,25 +1,26 @@ -From 83d67b5b3cbffcefda5efdc0060b9e30f44c9aca Mon Sep 17 00:00:00 2001 +From 320cf189fd017e3578b6949ff640213d7bddb20c Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Fri, 16 Nov 2018 14:44:49 -0800 -Subject: [PATCH 6/7] Add basic timer support for Aspeed g5 in U-Boot +Subject: [PATCH] Add basic timer support for Aspeed g5 in U-Boot Timers will be used for timing events and making blinky LEDs. This just adds the API and infrastructure. Change-Id: I8ff03b26070b43a47fb970ddf6124d6c3f29b058 Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> + --- board/aspeed/ast-g5/Makefile | 1 + board/aspeed/ast-g5/ast-g5-intel.c | 1 + - board/aspeed/ast-g5/ast-g5-timer.c | 66 ++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-timer.h | 27 ++++++++++++ + board/aspeed/ast-g5/ast-g5-timer.c | 66 ++++++++++++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-timer.h | 27 ++++++++++++++++ board/aspeed/ast-g5/ast-g5.h | 1 + 5 files changed, 96 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-timer.c create mode 100644 board/aspeed/ast-g5/ast-g5-timer.h diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 2970ae5741..90224333c4 100644 +index 2970ae5..9022433 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -3,3 +3,4 @@ obj-y += ast-g5-intel.o @@ -28,7 +29,7 @@ index 2970ae5741..90224333c4 100644 obj-y += ast-g5-gpio.o +obj-y += ast-g5-timer.o diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 58ad6a55b8..23bf4e4352 100644 +index 144765a..6e45cb4 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -15,6 +15,7 @@ @@ -41,7 +42,7 @@ index 58ad6a55b8..23bf4e4352 100644 enum gpio_names { diff --git a/board/aspeed/ast-g5/ast-g5-timer.c b/board/aspeed/ast-g5/ast-g5-timer.c new file mode 100644 -index 0000000000..56157222d9 +index 0000000..5615722 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-timer.c @@ -0,0 +1,66 @@ @@ -113,7 +114,7 @@ index 0000000000..56157222d9 +} diff --git a/board/aspeed/ast-g5/ast-g5-timer.h b/board/aspeed/ast-g5/ast-g5-timer.h new file mode 100644 -index 0000000000..4b1ac28a9f +index 0000000..4b1ac28 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-timer.h @@ -0,0 +1,27 @@ @@ -145,7 +146,7 @@ index 0000000000..4b1ac28a9f + +#endif /* __AST_G5_TIMER_H__ */ diff --git a/board/aspeed/ast-g5/ast-g5.h b/board/aspeed/ast-g5/ast-g5.h -index 908db1477b..28fe5eafcb 100644 +index 908db14..28fe5ea 100644 --- a/board/aspeed/ast-g5/ast-g5.h +++ b/board/aspeed/ast-g5/ast-g5.h @@ -4,5 +4,6 @@ @@ -155,6 +156,3 @@ index 908db1477b..28fe5eafcb 100644 +#include "ast-g5-timer.h" #endif /* _AST_G5_H_ */ --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch index 5a2c2206f..16eb31250 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch @@ -1,7 +1,7 @@ -From f0e3631ea3005640f988727f051106d83b5dfdaf Mon Sep 17 00:00:00 2001 +From bc6ea87d8213ecdc5ab7cced8b2fc4284fdef019 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 12:16:53 -0800 -Subject: [PATCH 7/7] Add status and ID LED support +Subject: [PATCH] Add status and ID LED support Add status (amber and green) and ID (blue) LED support. In the bootloader phase, the LEDs should be blinking. When booting linux, they @@ -9,12 +9,13 @@ should turn to a fixed state. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> Change-Id: Ic9595621b21000ef465ff57ed2047855296e2714 + --- - board/aspeed/ast-g5/ast-g5-intel.c | 118 +++++++++++++++++++++++++++++ - 1 file changed, 118 insertions(+) + board/aspeed/ast-g5/ast-g5-intel.c | 110 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 110 insertions(+) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 23bf4e4352..5ff2cbd0e2 100644 +index 6e45cb4..e53f5eb 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -146,6 +146,110 @@ static void sgpio_init(void) @@ -128,7 +129,7 @@ index 23bf4e4352..5ff2cbd0e2 100644 int intel_force_firmware_jumper_enabled(void) { return gpio_get_value(GPIO_FF_UPD_JUMPER); -@@ -157,4 +269,10 @@ void ast_g5_intel(void) +@@ -157,4 +261,10 @@ void ast_g5_intel(void) gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); espi_init(); sgpio_init(); @@ -139,6 +140,3 @@ index 23bf4e4352..5ff2cbd0e2 100644 + id_led_control(GPIO_GREEN_LED, EIDLED_On); + } } --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch index d235aea62..10a45fa23 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch @@ -1,18 +1,19 @@ -From 3134584998f624bb6c4ee11102b0bd9b7bb1cbba Mon Sep 17 00:00:00 2001 +From 34ccbd14d8f5caa66523a762e2030b6f105206cb Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Fri, 16 Nov 2018 15:57:57 -0800 -Subject: [PATCH 1/1] aspeed: add Pwm Driver +Subject: [PATCH] aspeed: add Pwm Driver Change-Id: Ia8b80212f7c70aafcc6a71782936ec95cf9b7f38 + --- - board/aspeed/ast-g5/ast-g5-intel.c | 105 +++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 105 +++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 5ff2cbd0e2..f810ded4e7 100644 +index e53f5eb..c7ae566 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -263,9 +263,114 @@ int intel_force_firmware_jumper_enabled(void) +@@ -255,9 +255,114 @@ int intel_force_firmware_jumper_enabled(void) return gpio_get_value(GPIO_FF_UPD_JUMPER); } @@ -127,6 +128,3 @@ index 5ff2cbd0e2..f810ded4e7 100644 gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); espi_init(); sgpio_init(); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch index 91665e064..22191f07a 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch @@ -1,7 +1,7 @@ -From 2078771e0ff84be710250b2e9b2e887f7238f9cc Mon Sep 17 00:00:00 2001 +From 040c9c13778076403198ce93f43c4aa3a1ed3907 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Sat, 17 Nov 2018 14:17:27 -0800 -Subject: [PATCH 2/3] Keep interrupts enabled until last second +Subject: [PATCH] Keep interrupts enabled until last second The U-Boot bootm command disabled interrupts almost first thing. This would prevent a person hitting the power button on the host immediatly @@ -10,6 +10,7 @@ and the host would power off. Change-Id: I6c0fb5cca1be6c326da4c9a3d3dfbab89dac9928 Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> + --- board/aspeed/ast-g5/ast-g5-intel.c | 8 ++++++++ common/bootm.c | 7 ------- @@ -17,10 +18,10 @@ Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index f810ded4e7..4d399be392 100644 +index c7ae566..01f8a13 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -263,6 +263,14 @@ int intel_force_firmware_jumper_enabled(void) +@@ -255,6 +255,14 @@ int intel_force_firmware_jumper_enabled(void) return gpio_get_value(GPIO_FF_UPD_JUMPER); } @@ -36,7 +37,7 @@ index f810ded4e7..4d399be392 100644 #define PWM_BASE_ADDR 0x1E786000 diff --git a/common/bootm.c b/common/bootm.c -index 2431019b3f..46909ecdbb 100644 +index 2431019..46909ec 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -602,7 +602,6 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], @@ -75,7 +76,7 @@ index 2431019b3f..46909ecdbb 100644 bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL); else if (ret == BOOTM_ERR_RESET) diff --git a/common/bootm_os.c b/common/bootm_os.c -index 9ec84bd0db..b56eb39780 100644 +index 9ec84bd..b56eb39 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -476,6 +476,7 @@ __weak void arch_preboot_os(void) @@ -86,6 +87,3 @@ index 9ec84bd0db..b56eb39780 100644 arch_preboot_os(); boot_fn(state, argc, argv, images); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch index 475b8c3ff..d93d9c4a1 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch @@ -1,4 +1,4 @@ -From a71794fc928429e199c5ea48181e5edfbb0c4f39 Mon Sep 17 00:00:00 2001 +From 711c7bc5a07b62e8369bc76a9db265c960bacef8 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Mon, 19 Nov 2018 11:04:02 -0800 Subject: [PATCH] Rewrite memmove to optimize on word transfers @@ -10,12 +10,13 @@ trailer, where the body is all done with word-sized transfers. Change-Id: Ie0a1f3261e507fb34a908571883d9bf04a1059ee Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> + --- - lib/string.c | 77 +++++++++++++++++++++++++++++++++++++++++++--------- + lib/string.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 64 insertions(+), 13 deletions(-) diff --git a/lib/string.c b/lib/string.c -index 67d5f6a421..0bf472f1f6 100644 +index 67d5f6a..0bf472f 100644 --- a/lib/string.c +++ b/lib/string.c @@ -505,26 +505,77 @@ void * memcpy(void *dest, const void *src, size_t count) @@ -109,6 +110,3 @@ index 67d5f6a421..0bf472f1f6 100644 return dest; } #endif --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch index 1d2b02954..8a63edbb7 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch @@ -1,4 +1,4 @@ -From bb490aa226dcf261d3d6865be37130765ecbe9f4 Mon Sep 17 00:00:00 2001 +From 9b05a276af65dd436f30b1b2680a09821c5a81aa Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@intel.com> Date: Mon, 17 Dec 2018 20:37:23 -0800 Subject: [PATCH] u-boot: full platform reset + espi oob-ready @@ -8,12 +8,13 @@ reset and then immediately set oob-ready so the espi master controller can initiate communication. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> + --- arch/arm/mach-aspeed/platform_g5.S | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S -index 2ac1ca4721..66427b6f33 100644 +index 2ac1ca4..66427b6 100644 --- a/arch/arm/mach-aspeed/platform_g5.S +++ b/arch/arm/mach-aspeed/platform_g5.S @@ -139,7 +139,7 @@ @@ -43,6 +44,3 @@ index 2ac1ca4721..66427b6f33 100644 /* Enable Timer separate clear mode */ ldr r0, =0x1e782038 mov r1, #0xAE --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch index 2e541561a..afdd610b3 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch @@ -1,4 +1,4 @@ -From 06445210bfda7f9bbbb36133e6818575bd6a0cc1 Mon Sep 17 00:00:00 2001 +From 54616ade08517374200a332e50f68ee9d0fbf5c5 Mon Sep 17 00:00:00 2001 From: Yong Li <yong.b.li@linux.intel.com> Date: Tue, 9 Apr 2019 14:42:05 +0800 Subject: [PATCH] Add system reset status support @@ -7,13 +7,16 @@ Will display the reset reasons and other CPU information in u-boot, and save the reset reasons into kernel command line, for applications to query. +Change-Id: I87ada3ecf14368519e4d09035bb1e09fdc05469b Signed-off-by: Yong Li <yong.b.li@linux.intel.com> +Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- - arch/arm/include/asm/arch-aspeed/platform.h | 2 ++ - arch/arm/mach-aspeed/ast-scu.c | 4 ++++ - board/aspeed/ast-g5/ast-g5-intel.c | 30 +++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5.c | 7 +++++++ - 4 files changed, 43 insertions(+) + arch/arm/include/asm/arch-aspeed/platform.h | 2 + + arch/arm/mach-aspeed/ast-scu.c | 4 ++ + board/aspeed/ast-g5/ast-g5-intel.c | 73 +++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5.c | 7 +++ + 4 files changed, 86 insertions(+) diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h index 3b06e52..4e4140d 100644 @@ -51,41 +54,84 @@ index 3a9ba05..976c59b 100644 u32 ast_scu_get_vga_memsize(void) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index bcaf81e..1e8708a 100644 +index 01f8a13..e0bf9ee 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -303,6 +303,36 @@ static inline void ast_scu_write(uint32_t val, uint32_t reg) +@@ -303,6 +303,79 @@ static inline void ast_scu_write(uint32_t val, uint32_t reg) #endif } -+void ast_g5_intel_late_init(void) ++ ++static void update_bootargs_cmd(const char *key, const char *value) +{ -+ char *cmdline = NULL; -+ char *cmdline_new = NULL; -+ char buf[32]; -+ u32 rest = 0; ++ int buf_len; ++ char *buf; ++ char *cmdline; ++ char comp_key[128]; + -+ /* save and clear reset status */ -+ rest = ast_scu_read(AST_SCU_SYS_CTRL); -+ snprintf(buf, sizeof(buf), " resetreason=0x%x", rest); -+ ast_scu_write(0, AST_SCU_SYS_CTRL); ++ if (!key || (key[0] == '\0')) { ++ printf("%s - Empty key not allowed\n", __func__); ++ return; ++ } + + cmdline = getenv("bootargs"); -+ if (!cmdline) { -+ printf("Get bootargs fail!\n"); ++ ++ /* Allocate space for maximum possible new command line */ ++ if (value) ++ buf_len = strlen(cmdline) + strlen(key) + 3 + strlen(value); ++ else ++ buf_len = strlen(cmdline) + strlen(key) + 3; ++ ++ buf = malloc(buf_len); ++ if (!buf) { ++ printf("%s: out of memory\n", __func__); + return; + } ++ memset(buf, 0, buf_len); + -+ cmdline_new = malloc(strlen(cmdline) + strlen(buf) + 1); -+ if (!cmdline_new) { -+ printf("Cannot malloc memory!\n"); ++ if (!cmdline) { ++ /* lets add key-value, though bootargs are empty */ ++ snprintf(buf, buf_len, "%s=%s", key, (value ? value : "")); ++ setenv("bootargs", buf); ++ free(buf); + return; + } + -+ /* append the reset status into kernel command line */ -+ snprintf(cmdline_new, strlen(cmdline) + strlen(buf) + 1, "%s%s", cmdline, buf); -+ setenv("bootargs", cmdline_new); -+ free(cmdline_new); ++ snprintf(comp_key, sizeof(comp_key), "%s=", key); ++ char *start = strstr(cmdline, comp_key); ++ ++ /* Check for full word match. Match should be start of cmdline ++ * or there should be space before match */ ++ if (start && ((start == cmdline) || (*(start-1) == ' '))) { ++ char *end = strchr(start, ' '); ++ strncpy(buf, cmdline, (start - cmdline)); ++ ++ if (end) ++ snprintf(buf, buf_len, "%s%s=%s %s", buf, key, ++ (value ? value : ""), end+1); ++ else ++ snprintf(buf, buf_len, "%s%s=%s", buf, key, ++ (value ? value : "")); ++ } else { ++ snprintf(buf, buf_len, "%s %s=%s", cmdline, key, ++ (value ? value : "")); ++ } ++ ++ setenv("bootargs", buf); ++ free(buf); ++} ++ ++void ast_g5_intel_late_init(void) ++{ ++ char value[32]; ++ u32 reset_reason = 0; ++ ++ /* save and clear reset status */ ++ reset_reason = ast_scu_read(AST_SCU_SYS_CTRL); ++ snprintf(value, sizeof(value), "0x%x", reset_reason); ++ ast_scu_write(0, AST_SCU_SYS_CTRL); ++ ++ update_bootargs_cmd("resetreason", value); +} + static void pwm_init(void) @@ -116,6 +162,3 @@ index d41ef9c..0953677 100644 int dram_init(void) { u32 vga = ast_scu_get_vga_memsize(); --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch index bdf3d2ddd..6949856db 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch @@ -1,4 +1,4 @@ -From 22c61ba094d8ebdbdcb44f848eef1f5d87a4be87 Mon Sep 17 00:00:00 2001 +From 647cc2538ed6b64054c742b4668386fda9394221 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Tue, 8 Jan 2019 13:33:15 -0800 Subject: [PATCH] Enable PCIe L1 support @@ -6,12 +6,13 @@ Subject: [PATCH] Enable PCIe L1 support This commit enables PCIe L1 support using magic registers. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> + --- arch/arm/mach-aspeed/platform_g5.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S -index 66427b6f33e7..b4043534b083 100644 +index 66427b6..b404353 100644 --- a/arch/arm/mach-aspeed/platform_g5.S +++ b/arch/arm/mach-aspeed/platform_g5.S @@ -2432,6 +2432,18 @@ spi_cbr_end: @@ -33,6 +34,3 @@ index 66427b6f33e7..b4043534b083 100644 /****************************************************************************** Configure MAC timing ******************************************************************************/ --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch index 310d9359b..32a40261f 100755 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch @@ -1,4 +1,4 @@ -From c82ba33ea40e0007945cbc93da58f296fdeedeaf Mon Sep 17 00:00:00 2001 +From 30c634b4969b8a3cd3afc079d60d23d2cb9f5f5c Mon Sep 17 00:00:00 2001 From: Yong Li <yong.b.li@linux.intel.com> Date: Mon, 11 Feb 2019 15:19:56 +0800 Subject: [PATCH] Config host uart clock source using environment variable @@ -25,6 +25,7 @@ ipmitool raw 0x32 0x90 1 3; reboot cat /sys/class/tty/ttyS*/uartclk, ttyS0/12/3 should be 192MHz Signed-off-by: Yong Li <yong.b.li@linux.intel.com> + --- arch/arm/include/asm/arch-aspeed/regs-scu.h | 5 ++++ board/aspeed/ast-g5/ast-g5-intel.c | 39 +++++++++++++++++++++++++++++ @@ -47,7 +48,7 @@ index 10b983a..8a596ce 100644 #define SCU_PCIE_MAPPING_HIGH (1 << 15) #define SCU_MALI_DTY_MODE (1 << 8) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 1e8708a..f810a40 100644 +index e0bf9ee..e19df03 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -103,6 +103,9 @@ static const GPIOValue gpio_table[] = { @@ -60,9 +61,9 @@ index 1e8708a..f810a40 100644 static void sgpio_init(void) { uint32_t value; -@@ -310,6 +313,42 @@ void ast_g5_intel_late_init(void) - char buf[32]; - u32 rest = 0; +@@ -368,6 +371,42 @@ void ast_g5_intel_late_init(void) + char value[32]; + u32 reset_reason = 0; + /* By default host serail A and B use normal speed */ + uint32_t host_serial_cfg = 0; @@ -101,8 +102,5 @@ index 1e8708a..f810a40 100644 + } + /* save and clear reset status */ - rest = ast_scu_read(AST_SCU_SYS_CTRL); - snprintf(buf, sizeof(buf), " resetreason=0x%x", rest); --- -2.7.4 - + reset_reason = ast_scu_read(AST_SCU_SYS_CTRL); + snprintf(value, sizeof(value), "0x%x", reset_reason); diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch index c79b2f2dc..63eebe56b 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch @@ -1,4 +1,4 @@ -From b11377c73c85bdee1975402084c3760b70cc99c4 Mon Sep 17 00:00:00 2001 +From 1264c57a485a238b715c489b7ca14982af396442 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Wed, 13 Mar 2019 14:28:05 +0530 Subject: [PATCH] KCS driver support in uBoot @@ -25,6 +25,7 @@ via KCS interfaces using cmdtool.efi. Res: C1 (Invalid). Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- board/aspeed/ast-g5/Makefile | 1 + board/aspeed/ast-g5/ast-g5-intel.c | 3 + @@ -44,10 +45,10 @@ index 9022433..05972b9 100644 obj-y += ast-g5-timer.o +obj-y += ast-g5-kcs.o diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 409b1a7..41d41ea 100644 +index e19df03..adc6d10 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -437,6 +437,7 @@ static void pwm_init(void) +@@ -480,6 +480,7 @@ static void pwm_init(void) } extern void espi_init(void); @@ -55,7 +56,7 @@ index 409b1a7..41d41ea 100644 void ast_g5_intel(void) { pwm_init(); -@@ -446,6 +447,8 @@ void ast_g5_intel(void) +@@ -489,6 +490,8 @@ void ast_g5_intel(void) timer8_init(); if (intel_force_firmware_jumper_enabled()) { id_led_control(GPIO_AMBER_LED, EIDLED_On); @@ -608,6 +609,3 @@ index 0000000..bb697c4 + u16 data_out_idx; + u8 data_out[MAX_KCS_PKT_SIZE]; +}; --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch index 746063a56..afba07abf 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch @@ -1,18 +1,20 @@ -From 6651a2663ee3e9f02c6ed8377097456528a2ee1a Mon Sep 17 00:00:00 2001 +From 4cbfb21b7792e6dae74e2db6e2e2d6803bf6cc1d Mon Sep 17 00:00:00 2001 From: Vikram Bodireddy <vikram.bodireddy@intel.com> Date: Tue, 26 Mar 2019 20:34:51 +0530 Subject: [PATCH] u-boot env change for PFR image +Tested: verified BMC booting from 0x20b00000 + Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> --- include/configs/ast-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h -index b7d7192..dd89d91 100644 +index 0bc7f2d..821ea8f 100644 --- a/include/configs/ast-common.h +++ b/include/configs/ast-common.h -@@ -103,7 +103,7 @@ +@@ -108,7 +108,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS (CONFIG_FMC_CS) #define CONFIG_SYS_MAX_FLASH_SECT (8192) /* max number of sectors on one chip */ #define CONFIG_ENV_IS_IN_FLASH 1 @@ -21,12 +23,12 @@ index b7d7192..dd89d91 100644 #define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -@@ -111,7 +111,7 @@ +@@ -116,7 +116,7 @@ #define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET_REDUND) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_BOOTCOMMAND "bootm 20080000" -+#define CONFIG_BOOTCOMMAND "bootm 21100000" ++#define CONFIG_BOOTCOMMAND "bootm 20b00000" #define CONFIG_ENV_OVERWRITE #define ASPEED_ENV_SETTINGS \ diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch index 5e8cd103d..f3fc0738b 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch @@ -1,4 +1,4 @@ -From f762526077a7af02fc93bacc74fb9d49481d664f Mon Sep 17 00:00:00 2001 +From 6b0f858e2dda7afce82797835f950e3501b3046d Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Fri, 29 Mar 2019 12:30:20 -0700 Subject: [PATCH] Add TPM enable pulse triggering @@ -6,12 +6,13 @@ Subject: [PATCH] Add TPM enable pulse triggering This commit adds onboard TPM enable pulse triggering. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> + --- board/aspeed/ast-g5/ast-g5-intel.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index f9955c70d2f2..d9ba4a47a413 100644 +index adc6d10..55afa09 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -53,8 +53,8 @@ static const GPIOValue gpio_table[] = { @@ -39,7 +40,7 @@ index f9955c70d2f2..d9ba4a47a413 100644 static void timer8_irq_handler(void *regs) { int i; -@@ -445,6 +452,7 @@ void ast_g5_intel(void) +@@ -488,6 +495,7 @@ void ast_g5_intel(void) espi_init(); sgpio_init(); timer8_init(); @@ -47,6 +48,3 @@ index f9955c70d2f2..d9ba4a47a413 100644 if (intel_force_firmware_jumper_enabled()) { id_led_control(GPIO_AMBER_LED, EIDLED_On); kcs_init(); --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch index 9096b09b2..252a9ea1b 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch @@ -1,4 +1,4 @@ -From 50d3a7264fc0ecdd61ae1686839b19091b124e8d Mon Sep 17 00:00:00 2001 +From 2314db61ea792a98c35fcc75b0ac09cbc0db005d Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Tue, 21 May 2019 00:19:16 +0530 Subject: [PATCH] IPMI command handler implementation in uboot @@ -20,6 +20,7 @@ and got proper response. Change-Id: I18b205bc45c34f7c4ef16adc29fa5bd494624ceb Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- board/aspeed/ast-g5/Makefile | 1 + board/aspeed/ast-g5/ast-g5-kcs.c | 77 +++++++++++++----------- @@ -327,6 +328,3 @@ index 0000000..9d46d9b +}; + +void ipmi_cmd_handler(struct ipmi_cmd_data *ipmi_data); --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch index f6f402bc9..7e75acb02 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch @@ -1,6 +1,6 @@ -From 6b4e1b3672433c0d7d392404e19d114ae25e0eb2 Mon Sep 17 00:00:00 2001 -From: Richard Marian Thomaiyar <richard.marian.thomaiyar@linux.intel.com> -Date: Wed, 24 Apr 2019 22:35:43 +0530 +From 0e83d58efe5bd34430c953713285293cd0756b69 Mon Sep 17 00:00:00 2001 +From: AppaRao Puli <apparao.puli@linux.intel.com> +Date: Thu, 20 Jun 2019 18:11:43 +0530 Subject: [PATCH] Manufacturing mode physical presence detection Support for physical presence of manufacturing mode added. @@ -15,10 +15,12 @@ special=mfg string Change-Id: Id7e7c7e7860c7ef3ae8e3a7a7cfda7ff506c0f2b Signed-off-by: Richard Marian Thomaiyar <richard.marian.thomaiyar@linux.intel.com> +Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- board/aspeed/ast-g5/ast-g5-gpio.h | 2 +- - board/aspeed/ast-g5/ast-g5-intel.c | 39 ++++++++++++++++++++++++++++++++++++-- - 2 files changed, 38 insertions(+), 3 deletions(-) + board/aspeed/ast-g5/ast-g5-intel.c | 31 +++++++++++++++++++++++++++++++ + 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h index a820c0f..ed2499f 100644 @@ -34,7 +36,7 @@ index a820c0f..ed2499f 100644 // GPIO Configuration Register bits #define GPCFG_EVENT_TO_SMI (1 << 7) // 1 == enabled diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 881ab89..86b422f 100644 +index 55afa09..812e3ef 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -24,6 +24,7 @@ enum gpio_names { @@ -56,8 +58,8 @@ index 881ab89..86b422f 100644 }; #define LPC_SNOOP_ADDR 0x80 -@@ -313,12 +318,35 @@ static inline void ast_scu_write(uint32_t val, uint32_t reg) - #endif +@@ -373,6 +378,26 @@ static void update_bootargs_cmd(const char *key, const char *value) + free(buf); } +static bool is_mfg_mode_phy_req(void) @@ -82,40 +84,17 @@ index 881ab89..86b422f 100644 + void ast_g5_intel_late_init(void) { - char *cmdline = NULL; - char *cmdline_new = NULL; - char buf[32]; - u32 rest = 0; -+ const char *special_mfg_str = " special=mfg"; -+ const u32 special_str_size = strlen(special_mfg_str); -+ u32 buf_count = 0; - - /* By default host serail A and B use normal speed */ - uint32_t host_serial_cfg = 0; -@@ -367,14 +395,21 @@ void ast_g5_intel_late_init(void) - return; - } - -- cmdline_new = malloc(strlen(cmdline) + strlen(buf) + 1); -+ cmdline_new = malloc(strlen(cmdline) + strlen(buf) + -+ special_str_size + 1); - if (!cmdline_new) { - printf("Cannot malloc memory!\n"); - return; - } + char value[32]; +@@ -420,6 +445,12 @@ void ast_g5_intel_late_init(void) + ast_scu_write(0, AST_SCU_SYS_CTRL); - /* append the reset status into kernel command line */ -- snprintf(cmdline_new, strlen(cmdline) + strlen(buf) + 1, "%s%s", cmdline, buf); -+ buf_count = snprintf(cmdline_new, strlen(cmdline) + strlen(buf) + 1, -+ "%s%s", cmdline, buf); + update_bootargs_cmd("resetreason", value); + ++ /* Update the special mode in bootargs */ + if (is_mfg_mode_phy_req()) -+ snprintf(cmdline_new + buf_count - 1, special_str_size + 1, -+ "%s", special_mfg_str); -+ - setenv("bootargs", cmdline_new); - free(cmdline_new); ++ update_bootargs_cmd("special", "mfg"); ++ else ++ update_bootargs_cmd("special", NULL); } --- -2.7.4 - + + static void pwm_init(void) diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch index 950763d8e..be2c4018d 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch @@ -1,4 +1,4 @@ -From a1626519109c9bda02119114224f3759add21f00 Mon Sep 17 00:00:00 2001 +From ea4f14a24b67d5085149d48c7fb38d00f3a7444a Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Mon, 6 May 2019 03:01:55 +0530 Subject: [PATCH] Aspeed I2C support in U-Boot @@ -14,6 +14,7 @@ i2c functionalities like probe, read and write. Change-Id: Iad9af4a57a58bc8dc5c470bfadad9dac1371c238 Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- arch/arm/include/asm/arch-aspeed/ast_g5_platform.h | 14 + arch/arm/include/asm/arch-aspeed/ast_scu.h | 5 + @@ -23,10 +24,10 @@ Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> configs/ast_g5_phy_defconfig | 2 + drivers/i2c/Kconfig | 5 + drivers/i2c/Makefile | 1 + - drivers/i2c/ast_i2c.c | 849 +++++++++++++++++++++ + drivers/i2c/ast_i2c.c | 852 +++++++++++++++++++++ drivers/i2c/ast_i2c.h | 131 ++++ include/configs/ast-common.h | 5 + - 11 files changed, 1346 insertions(+) + 11 files changed, 1349 insertions(+) create mode 100644 arch/arm/include/asm/arch-aspeed/regs-iic.h create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h @@ -88,7 +89,7 @@ index 369c4e3..b94d13e 100644 diff --git a/arch/arm/include/asm/arch-aspeed/regs-iic.h b/arch/arm/include/asm/arch-aspeed/regs-iic.h new file mode 100644 -index 0000000..2847430 +index 0000000..5eb3f0a --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/regs-iic.h @@ -0,0 +1,204 @@ @@ -129,175 +130,175 @@ index 0000000..2847430 +#endif + +/* I2C Register */ -+#define I2C_FUN_CTRL_REG 0x00 -+#define I2C_AC_TIMING_REG1 0x04 -+#define I2C_AC_TIMING_REG2 0x08 -+#define I2C_INTR_CTRL_REG 0x0c -+#define I2C_INTR_STS_REG 0x10 -+#define I2C_CMD_REG 0x14 -+#define I2C_DEV_ADDR_REG 0x18 -+#define I2C_BUF_CTRL_REG 0x1c -+#define I2C_BYTE_BUF_REG 0x20 -+#define I2C_DMA_BASE_REG 0x24 -+#define I2C_DMA_LEN_REG 0x28 ++#define I2C_FUN_CTRL_REG 0x00 ++#define I2C_AC_TIMING_REG1 0x04 ++#define I2C_AC_TIMING_REG2 0x08 ++#define I2C_INTR_CTRL_REG 0x0c ++#define I2C_INTR_STS_REG 0x10 ++#define I2C_CMD_REG 0x14 ++#define I2C_DEV_ADDR_REG 0x18 ++#define I2C_BUF_CTRL_REG 0x1c ++#define I2C_BYTE_BUF_REG 0x20 ++#define I2C_DMA_BASE_REG 0x24 ++#define I2C_DMA_LEN_REG 0x28 + + +/* Gloable Register Definition */ +/* 0x00 : I2C Interrupt Status Register */ +/* 0x08 : I2C Interrupt Target Assignment */ +#if defined(CONFIG_ARCH_AST2400) -+#define AST_I2CG_INTR14 (0x1 << 13) -+#define AST_I2CG_INTR13 (0x1 << 12) -+#define AST_I2CG_INTR12 (0x1 << 11) -+#define AST_I2CG_INTR11 (0x1 << 10) -+#define AST_I2CG_INTR10 (0x1 << 9) ++#define AST_I2CG_INTR14 (0x1 << 13) ++#define AST_I2CG_INTR13 (0x1 << 12) ++#define AST_I2CG_INTR12 (0x1 << 11) ++#define AST_I2CG_INTR11 (0x1 << 10) ++#define AST_I2CG_INTR10 (0x1 << 9) +#elif defined(CONFIG_ARCH_AST1010) -+#define AST_I2CG_INTR14 (0x1 << 13) -+#define AST_I2CG_INTR13 (0x1 << 12) -+#define AST_I2CG_INTR12 (0x1 << 11) -+#define AST_I2CG_INTR11 (0x1 << 10) -+#define AST_I2CG_INTR10 (0x1 << 9) ++#define AST_I2CG_INTR14 (0x1 << 13) ++#define AST_I2CG_INTR13 (0x1 << 12) ++#define AST_I2CG_INTR12 (0x1 << 11) ++#define AST_I2CG_INTR11 (0x1 << 10) ++#define AST_I2CG_INTR10 (0x1 << 9) +#endif -+#define AST_I2CG_INTR09 (0x1 << 8) -+#define AST_I2CG_INTR08 (0x1 << 7) -+#define AST_I2CG_INTR07 (0x1 << 6) -+#define AST_I2CG_INTR06 (0x1 << 5) -+#define AST_I2CG_INTR05 (0x1 << 4) -+#define AST_I2CG_INTR04 (0x1 << 3) -+#define AST_I2CG_INTR03 (0x1 << 2) -+#define AST_I2CG_INTR02 (0x1 << 1) -+#define AST_I2CG_INTR01 (0x1 ) ++#define AST_I2CG_INTR09 (0x1 << 8) ++#define AST_I2CG_INTR08 (0x1 << 7) ++#define AST_I2CG_INTR07 (0x1 << 6) ++#define AST_I2CG_INTR06 (0x1 << 5) ++#define AST_I2CG_INTR05 (0x1 << 4) ++#define AST_I2CG_INTR04 (0x1 << 3) ++#define AST_I2CG_INTR03 (0x1 << 2) ++#define AST_I2CG_INTR02 (0x1 << 1) ++#define AST_I2CG_INTR01 (0x1) + +/* Device Register Definition */ +/* 0x00 : I2CD Function Control Register */ -+#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) -+#define AST_I2CD_BUFF_SEL(x) (x << 20) // page 0 ~ 7 -+#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) -+#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) -+#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) -+#define AST_I2CD_MSB_STS (0x1 << 9) -+#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) -+#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) -+#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) -+#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) -+#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) -+#define AST_I2CD_DEF_ARP_EN (0x1 << 3) -+#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) -+#define AST_I2CD_SLAVE_EN (0x1 << 1) -+#define AST_I2CD_MASTER_EN (0x1 ) ++#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) ++#define AST_I2CD_BUFF_SEL(x) (x << 20) // page 0 ~ 7 ++#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) ++#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) ++#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) ++#define AST_I2CD_MSB_STS (0x1 << 9) ++#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) ++#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) ++#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) ++#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) ++#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) ++#define AST_I2CD_DEF_ARP_EN (0x1 << 3) ++#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) ++#define AST_I2CD_SLAVE_EN (0x1 << 1) ++#define AST_I2CD_MASTER_EN (0x1) + +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ -+#define AST_I2CD_tBUF (0x1 << 28) // 0~7 -+#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7 -+#define AST_I2CD_tACST (0x1 << 20) // 0~7 -+#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7 -+#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7 -+#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7 -+#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3 -+#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf ++#define AST_I2CD_tBUF (0x1 << 28) // 0~7 ++#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7 ++#define AST_I2CD_tACST (0x1 << 20) // 0~7 ++#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7 ++#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7 ++#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7 ++#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3 ++#define AST_I2CD_CLK_BASE_DIV (0x1) // 0~0xf + +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ -+#define AST_I2CD_tTIMEOUT (0x1 ) // 0~7 -+#define AST_NO_TIMEOUT_CTRL 0x0 ++#define AST_I2CD_tTIMEOUT (0x1) // 0~7 ++#define AST_NO_TIMEOUT_CTRL 0x0 + + +/* 0x0c : I2CD Interrupt Control Register */ -+#define AST_I2CD_SDA_DL_TO_INTR_EN (0x1 << 14) -+#define AST_I2CD_BUS_RECOVER_INTR_EN (0x1 << 13) -+#define AST_I2CD_SMBUS_ALT_INTR_EN (0x1 << 12) -+#define AST_I2CD_SLAVE_MATCH_INTR_EN (0x1 << 7) -+#define AST_I2CD_SCL_TO_INTR_EN (0x1 << 6) -+#define AST_I2CD_ABNORMAL_INTR_EN (0x1 << 5) -+#define AST_I2CD_NORMAL_STOP_INTR_EN (0x1 << 4) -+#define AST_I2CD_ARBIT_LOSS_INTR_EN (0x1 << 3) -+#define AST_I2CD_RX_DOWN_INTR_EN (0x1 << 2) -+#define AST_I2CD_TX_NAK_INTR_EN (0x1 << 1) -+#define AST_I2CD_TX_ACK_INTR_EN (0x1 ) ++#define AST_I2CD_SDA_DL_TO_INTR_EN (0x1 << 14) ++#define AST_I2CD_BUS_RECOVER_INTR_EN (0x1 << 13) ++#define AST_I2CD_SMBUS_ALT_INTR_EN (0x1 << 12) ++#define AST_I2CD_SLAVE_MATCH_INTR_EN (0x1 << 7) ++#define AST_I2CD_SCL_TO_INTR_EN (0x1 << 6) ++#define AST_I2CD_ABNORMAL_INTR_EN (0x1 << 5) ++#define AST_I2CD_NORMAL_STOP_INTR_EN (0x1 << 4) ++#define AST_I2CD_ARBIT_LOSS_INTR_EN (0x1 << 3) ++#define AST_I2CD_RX_DOWN_INTR_EN (0x1 << 2) ++#define AST_I2CD_TX_NAK_INTR_EN (0x1 << 1) ++#define AST_I2CD_TX_ACK_INTR_EN (0x1) + +/* 0x10 : I2CD Interrupt Status Register : WC */ -+#define AST_I2CD_INTR_STS_SDA_DL_TO (0x1 << 14) -+#define AST_I2CD_INTR_STS_BUS_RECOVER (0x1 << 13) -+#define AST_I2CD_INTR_STS_SMBUS_ALT (0x1 << 12) -+#define AST_I2CD_INTR_STS_SMBUS_ARP_ADDR (0x1 << 11) -+#define AST_I2CD_INTR_STS_SMBUS_DEV_ALT (0x1 << 10) -+#define AST_I2CD_INTR_STS_SMBUS_DEF_ADDR (0x1 << 9) -+#define AST_I2CD_INTR_STS_GCALL_ADDR (0x1 << 8) -+#define AST_I2CD_INTR_STS_SLAVE_MATCH (0x1 << 7) -+#define AST_I2CD_INTR_STS_SCL_TO (0x1 << 6) -+#define AST_I2CD_INTR_STS_ABNORMAL (0x1 << 5) -+#define AST_I2CD_INTR_STS_NORMAL_STOP (0x1 << 4) -+#define AST_I2CD_INTR_STS_ARBIT_LOSS (0x1 << 3) -+#define AST_I2CD_INTR_STS_RX_DOWN (0x1 << 2) -+#define AST_I2CD_INTR_STS_TX_NAK (0x1 << 1) -+#define AST_I2CD_INTR_STS_TX_ACK (0x1 ) ++#define AST_I2CD_INTR_STS_SDA_DL_TO (0x1 << 14) ++#define AST_I2CD_INTR_STS_BUS_RECOVER (0x1 << 13) ++#define AST_I2CD_INTR_STS_SMBUS_ALT (0x1 << 12) ++#define AST_I2CD_INTR_STS_SMBUS_ARP_ADDR (0x1 << 11) ++#define AST_I2CD_INTR_STS_SMBUS_DEV_ALT (0x1 << 10) ++#define AST_I2CD_INTR_STS_SMBUS_DEF_ADDR (0x1 << 9) ++#define AST_I2CD_INTR_STS_GCALL_ADDR (0x1 << 8) ++#define AST_I2CD_INTR_STS_SLAVE_MATCH (0x1 << 7) ++#define AST_I2CD_INTR_STS_SCL_TO (0x1 << 6) ++#define AST_I2CD_INTR_STS_ABNORMAL (0x1 << 5) ++#define AST_I2CD_INTR_STS_NORMAL_STOP (0x1 << 4) ++#define AST_I2CD_INTR_STS_ARBIT_LOSS (0x1 << 3) ++#define AST_I2CD_INTR_STS_RX_DOWN (0x1 << 2) ++#define AST_I2CD_INTR_STS_TX_NAK (0x1 << 1) ++#define AST_I2CD_INTR_STS_TX_ACK (0x1) + +/* 0x14 : I2CD Command/Status Register */ -+#define AST_I2CD_SDA_OE (0x1 << 28) -+#define AST_I2CD_SDA_O (0x1 << 27) -+#define AST_I2CD_SCL_OE (0x1 << 26) -+#define AST_I2CD_SCL_O (0x1 << 25) -+#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3 -+#define AST_I2CD_TX_STATUS (0x1 << 23) -+// Tx State Machine -+#define AST_I2CD_IDLE 0x0 ++#define AST_I2CD_SDA_OE (0x1 << 28) ++#define AST_I2CD_SDA_O (0x1 << 27) ++#define AST_I2CD_SCL_OE (0x1 << 26) ++#define AST_I2CD_SCL_O (0x1 << 25) ++#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3 ++#define AST_I2CD_TX_STATUS (0x1 << 23) ++// Tx State Machine ++#define AST_I2CD_IDLE 0x0 +#define AST_I2CD_MACTIVE 0x8 +#define AST_I2CD_MSTART 0x9 +#define AST_I2CD_MSTARTR 0xa +#define AST_I2CD_MSTOP 0xb +#define AST_I2CD_MTXD 0xc +#define AST_I2CD_MRXACK 0xd -+#define AST_I2CD_MRXD 0xe -+#define AST_I2CD_MTXACK 0xf ++#define AST_I2CD_MRXD 0xe ++#define AST_I2CD_MTXACK 0xf +#define AST_I2CD_SWAIT 0x1 -+#define AST_I2CD_SRXD 0x4 -+#define AST_I2CD_STXACK 0x5 ++#define AST_I2CD_SRXD 0x4 ++#define AST_I2CD_STXACK 0x5 +#define AST_I2CD_STXD 0x6 -+#define AST_I2CD_SRXACK 0x7 -+#define AST_I2CD_RECOVER 0x3 -+ -+#define AST_I2CD_SCL_LINE_STS (0x1 << 18) -+#define AST_I2CD_SDA_LINE_STS (0x1 << 17) -+#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) -+#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) -+#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) -+#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) -+#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) -+#define AST_I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) -+#define AST_I2CD_S_ALT_EN (0x1 << 10) ++#define AST_I2CD_SRXACK 0x7 ++#define AST_I2CD_RECOVER 0x3 ++ ++#define AST_I2CD_SCL_LINE_STS (0x1 << 18) ++#define AST_I2CD_SDA_LINE_STS (0x1 << 17) ++#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) ++#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) ++#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) ++#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) ++#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) ++#define AST_I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) ++#define AST_I2CD_S_ALT_EN (0x1 << 10) +// 0 : DMA Buffer, 1: Pool Buffer -+//AST1070 DMA register -+#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) -+#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) ++//AST1070 DMA register ++#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) ++#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) + +/* Command Bit */ -+#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) -+#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) -+#define AST_I2CD_M_STOP_CMD (0x1 << 5) -+#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) -+#define AST_I2CD_M_RX_CMD (0x1 << 3) -+#define AST_I2CD_S_TX_CMD (0x1 << 2) -+#define AST_I2CD_M_TX_CMD (0x1 << 1) -+#define AST_I2CD_M_START_CMD (0x1 ) ++#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) ++#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) ++#define AST_I2CD_M_STOP_CMD (0x1 << 5) ++#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) ++#define AST_I2CD_M_RX_CMD (0x1 << 3) ++#define AST_I2CD_S_TX_CMD (0x1 << 2) ++#define AST_I2CD_M_TX_CMD (0x1 << 1) ++#define AST_I2CD_M_START_CMD (0x1) + +/* 0x18 : I2CD Slave Device Address Register */ + +/* 0x1C : I2CD Pool Buffer Control Register */ -+#define AST_I2CD_RX_BUF_ADDR_GET(x) ((x>> 24)& 0xff) -+#define AST_I2CD_RX_BUF_END_ADDR_SET(x) (x << 16) -+#define AST_I2CD_TX_DATA_BUF_END_SET(x) ((x&0xff) << 8) -+#define AST_I2CD_TX_DATA_BUF_GET(x) ((x >>8) & 0xff) -+#define AST_I2CD_BUF_BASE_ADDR_SET(x) (x & 0x3f) ++#define AST_I2CD_RX_BUF_ADDR_GET(x) ((x >> 24) & 0xff) ++#define AST_I2CD_RX_BUF_END_ADDR_SET(x) (x << 16) ++#define AST_I2CD_TX_DATA_BUF_END_SET(x) ((x & 0xff) << 8) ++#define AST_I2CD_TX_DATA_BUF_GET(x) ((x >> 8) & 0xff) ++#define AST_I2CD_BUF_BASE_ADDR_SET(x) (x & 0x3f) + +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ -+#define AST_I2CD_GET_MODE(x) ((x >> 8) & 0x1) ++#define AST_I2CD_GET_MODE(x) ((x >> 8) & 0x1) + -+#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8) -+#define AST_I2CD_TX_BYTE_BUFFER (0xff ) ++#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8) ++#define AST_I2CD_TX_BYTE_BUFFER (0xff) + + +#endif /* __ASM_ARCH_REGS_IIC_H */ diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index 976c59b..7e8d4c8 100644 +index 976c59b..537cd4b 100644 --- a/arch/arm/mach-aspeed/ast-scu.c +++ b/arch/arm/mach-aspeed/ast-scu.c @@ -112,6 +112,12 @@ static struct soc_id soc_map_table[] = { @@ -319,18 +320,18 @@ index 976c59b..7e8d4c8 100644 +u32 ast_get_pclk(void) +{ -+ unsigned int div, hpll; ++ unsigned int div, hpll; + -+ hpll = ast_get_h_pll_clk(); -+ div = SCU_GET_PCLK_DIV(ast_scu_read(AST_SCU_CLK_SEL)); ++ hpll = ast_get_h_pll_clk(); ++ div = SCU_GET_PCLK_DIV(ast_scu_read(AST_SCU_CLK_SEL)); +#ifdef AST_SOC_G5 -+ div = (div+1) << 2; ++ div = (div+1) << 2; +#else -+ div = (div+1) << 1; ++ div = (div+1) << 1; +#endif + -+ debug("HPLL=%d, Div=%d, PCLK=%d\n", hpll, div, hpll/div); -+ return (hpll/div); ++ debug("HPLL=%d, Div=%d, PCLK=%d\n", hpll, div, hpll/div); ++ return (hpll/div); +} + + @@ -444,7 +445,7 @@ index 976c59b..7e8d4c8 100644 { int i; diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index 0953677..7309589 100644 +index 0953677..3c33546 100644 --- a/board/aspeed/ast-g5/ast-g5.c +++ b/board/aspeed/ast-g5/ast-g5.c @@ -13,6 +13,7 @@ @@ -461,20 +462,20 @@ index 0953677..7309589 100644 + /* Initialize I2C */ +#if defined(CONFIG_SYS_I2C) -+ i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr); ++ i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr); +#else -+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + ast_g5_intel(); return 0; } diff --git a/configs/ast_g5_phy_defconfig b/configs/ast_g5_phy_defconfig -index 8f09190..47d9563 100644 +index 4aefcf4..1b96ab7 100644 --- a/configs/ast_g5_phy_defconfig +++ b/configs/ast_g5_phy_defconfig -@@ -15,3 +15,5 @@ CONFIG_SPI_FLASH_MACRONIX=y - CONFIG_SPI_FLASH_STMICRO=y +@@ -13,3 +13,5 @@ CONFIG_OF_LIBFDT=y + CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USE_IRQ=y +CONFIG_CMD_I2C=y @@ -509,10 +510,10 @@ index 167424d..b2a69ea 100644 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c new file mode 100644 -index 0000000..0b12fc2 +index 0000000..533419f --- /dev/null +++ b/drivers/i2c/ast_i2c.c -@@ -0,0 +1,849 @@ +@@ -0,0 +1,852 @@ +/* + * i2c_adap_ast.c + * @@ -868,7 +869,7 @@ index 0000000..0b12fc2 +static inline void ast_i2c_write(struct ast_i2c_bus *i2c_bus, u32 val, u32 reg) +{ +#if 0 -+ printf("%x: W : reg %x , val: %x \n",i2c_bus->reg_base, reg, val); ++ printf("%x: W : reg %x , val: %x\n", i2c_bus->reg_base, reg, val); +#endif + __raw_writel(val, i2c_bus->reg_base + reg); +} @@ -877,7 +878,7 @@ index 0000000..0b12fc2 +{ +#if 0 + u32 val = __raw_readl(i2c_bus->reg_base + reg); -+ printf("%x: R : reg %x , val: %x \n",i2c_bus->reg_base, reg, val); ++ printf("%x: R : reg %x , val: %x\n", i2c_bus->reg_base, reg, val); + return val; +#else + return __raw_readl(i2c_bus->reg_base + reg); @@ -891,7 +892,7 @@ index 0000000..0b12fc2 + u32 SCL_Low, SCL_High, data; + + clk = ast_get_pclk(); -+// debug("pclk = %d \n",clk); ++// debug("pclk = %d\n", clk); + divider_ratio = clk / bus_clk; + for (div = 0; divider_ratio >= 16; div++) + { @@ -910,7 +911,7 @@ index 0000000..0b12fc2 + u32 data; + + clk = ast_get_pclk(); -+ // debug("pclk = %d \n",clk); ++ // debug("pclk = %d\n", clk); + + for (i = 0; + i < sizeof(i2c_timing_table) / sizeof(struct ast_i2c_timing_table); @@ -920,7 +921,7 @@ index 0000000..0b12fc2 + } + } + data = i2c_timing_table[i].timing; -+ // printk("divisor [%d], timing [%x] \n", i2c_timing_table[i].divisor, ++ // printk("divisor [%d], timing [%x]\n", i2c_timing_table[i].divisor, + // i2c_timing_table[i].timing); + return data; +#endif @@ -1059,7 +1060,7 @@ index 0000000..0b12fc2 + + /* Send Offset */ + for (i = 0; i < i2c_bus->a_len; i++) { -+ debug("offset [%x] \n", i2c_bus->a_buf[i]); ++ debug("offset [%x]\n", i2c_bus->a_buf[i]); + ast_i2c_write(i2c_bus, i2c_bus->a_buf[i], + I2C_BYTE_BUF_REG); + ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD, @@ -1119,7 +1120,7 @@ index 0000000..0b12fc2 + + /* Send Offset */ + for (i = 0; i < i2c_bus->a_len; i++) { -+ debug("offset [%x] \n", i2c_bus->a_buf[i]); ++ debug("offset [%x]\n", i2c_bus->a_buf[i]); + ast_i2c_write(i2c_bus, i2c_bus->a_buf[i], + I2C_BYTE_BUF_REG); + ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD, I2C_CMD_REG); @@ -1130,7 +1131,7 @@ index 0000000..0b12fc2 + + /* Tx data */ + for (i = 0; i < i2c_bus->d_len; i++) { -+ debug("Tx data [%x] \n", i2c_bus->d_buf[i]); ++ debug("Tx data [%x]\n", i2c_bus->d_buf[i]); + ast_i2c_write(i2c_bus, i2c_bus->d_buf[i], + I2C_BYTE_BUF_REG); + ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD, I2C_CMD_REG); @@ -1213,7 +1214,7 @@ index 0000000..0b12fc2 + return AST_I2C_DEV13_BASE; + break; + default: -+ printf("i2c base error \n"); ++ printf("i2c base error\n"); + break; + }; + return 0; @@ -1247,10 +1248,13 @@ index 0000000..0b12fc2 + ast_i2c_write(i2c_bus, AST_I2CD_MASTER_EN, I2C_FUN_CTRL_REG); + + // SLAVE mode enable -+#if 0 -+ if(slaveaddr) { -+ ast_i2c_write(i2c_bus, slaveaddr, I2C_DEV_ADDR_REG); -+ ast_i2c_write(i2c_bus, ast_i2c_read(i2c_bus,I2C_FUN_CTRL_REG) | AST_I2CD_SLAVE_EN, I2C_FUN_CTRL_REG); ++#if 0 ++ if (slaveaddr) { ++ ast_i2c_write(i2c_bus, slaveaddr, I2C_DEV_ADDR_REG); ++ ast_i2c_write(i2c_bus, ++ ast_i2c_read(i2c_bus, I2C_FUN_CTRL_REG) | ++ AST_I2CD_SLAVE_EN, ++ I2C_FUN_CTRL_REG); + } +#endif + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch index d8e7c4645..b5f7ccf07 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch @@ -1,4 +1,4 @@ -From 35a50c959b290ba8a6f0e70a42ae952b65df8a9d Mon Sep 17 00:00:00 2001 +From cdb62eb60de0b99276ff755b896fc51c8ed2606d Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Tue, 7 May 2019 11:26:35 +0530 Subject: [PATCH] CPLD u-boot commands support for PFR @@ -27,6 +27,7 @@ CPLD read successful. Reg:0x00 Val:0x04 ast# Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- cmd/Makefile | 1 + cmd/cpld.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ @@ -47,7 +48,7 @@ index a1731be..c8ac0af 100644 obj-$(CONFIG_CMD_IDE) += ide.o diff --git a/cmd/cpld.c b/cmd/cpld.c new file mode 100644 -index 0000000..63220cb +index 0000000..06b2e98 --- /dev/null +++ b/cmd/cpld.c @@ -0,0 +1,244 @@ @@ -65,8 +66,8 @@ index 0000000..63220cb +#include <errno.h> +#include <linux/compiler.h> + -+#define PFR_CPLD_I2C_BUSNO 5 -+#define PFR_CPLD_SLAVE_ADDR 0x0E ++#define PFR_CPLD_I2C_BUSNO 4 ++#define PFR_CPLD_SLAVE_ADDR 0xE0 + +#define CPLD_READ_TIMEOUT_ATTEMPTS 5 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch index 7601f6dea..0113fc3fe 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch @@ -1,4 +1,4 @@ -From 56d13790a713659e34eca884ce36dca76b3bdf3d Mon Sep 17 00:00:00 2001 +From 41c08f1fcb5fa0b07ea541fc3d8bc322ddf8701d Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Mon, 13 May 2019 23:49:02 +0530 Subject: [PATCH] Enabling uart1&uart2 in u-boot for BIOS messages @@ -13,16 +13,17 @@ to uefi, checked bios serial logs working fine and accessed keyboard in uefi without any issues. Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- board/aspeed/ast-g5/ast-g5-intel.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 86b422f..fe5128f 100644 +index 812e3ef..e68ab85 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -414,6 +414,26 @@ void ast_g5_intel_late_init(void) - free(cmdline_new); +@@ -453,6 +453,26 @@ void ast_g5_intel_late_init(void) + update_bootargs_cmd("special", NULL); } +static void uart_init(void) @@ -48,7 +49,7 @@ index 86b422f..fe5128f 100644 static void pwm_init(void) { uint32_t val; -@@ -482,6 +502,7 @@ extern void espi_init(void); +@@ -521,6 +541,7 @@ extern void espi_init(void); extern void kcs_init(void); void ast_g5_intel(void) { @@ -56,6 +57,3 @@ index 86b422f..fe5128f 100644 pwm_init(); gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); espi_init(); --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch index 00dbd68da..f91ab8fea 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch @@ -1,4 +1,4 @@ -From bd4a64d7ea394d0b418d491699853112229f098e Mon Sep 17 00:00:00 2001 +From 513ff559cd6fedd29412fb59b6f436f617620511 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Tue, 21 May 2019 00:53:04 +0530 Subject: [PATCH] FFUJ: FW IPMI commands and flash support in u-boot @@ -28,6 +28,7 @@ Tested: image transfer via KCS and flashing. Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> + --- arch/arm/include/asm/arch-aspeed/ast-g5-intel.h | 1 + board/aspeed/ast-g5/Makefile | 2 + @@ -1258,14 +1259,11 @@ index d66c0fa..45a600e 100644 #if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) int prev = disable_ctrlc(1); /* disable Control C checking */ diff --git a/configs/ast_g5_phy_defconfig b/configs/ast_g5_phy_defconfig -index 47d9563..f070494 100644 +index 1b96ab7..5965a9b 100644 --- a/configs/ast_g5_phy_defconfig +++ b/configs/ast_g5_phy_defconfig -@@ -17,3 +17,4 @@ CONFIG_SYS_NS16550=y +@@ -15,3 +15,4 @@ CONFIG_SYS_NS16550=y CONFIG_USE_IRQ=y CONFIG_CMD_I2C=y CONFIG_SYS_I2C_AST=y +CONFIG_LIB_RAND=y --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0030-Support-Get-Set-Security-mode-command.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0030-Support-Get-Set-Security-mode-command.patch new file mode 100644 index 000000000..519977e19 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0030-Support-Get-Set-Security-mode-command.patch @@ -0,0 +1,124 @@ +From 294a5971c94099277ee5b5589c060896cf22c495 Mon Sep 17 00:00:00 2001 +From: Richard Marian Thomaiyar <richard.marian.thomaiyar@linux.intel.com> +Date: Thu, 20 Jun 2019 15:26:50 +0530 +Subject: [PATCH] Support Get/Set Security mode command + +Support added for get/set security mode oem command. This +command is used to read / write the RestrictionMode property +which is saved in U-Boot environment variable. U-Boot +command provides a way to downgrade RestrictionMode property +value, which is not allowed in normal mode from Host interface + +Tested: +1. Verified get security mode returns proper value read from +U-Boot environment variable. cmdtool.efi 20 C0 B3 +2. Verified set security mode updates U-Boot environment variable +and it is reflected in linux too cmdtool.efi 20 C0 B4 4 +3. Verified negative test cases with improper values and it +throws correct errors + +Signed-off-by: Richard Marian Thomaiyar <richard.marian.thomaiyar@linux.intel.com> + +--- + board/aspeed/ast-g5/ipmi-handler.c | 63 +++++++++++++++++++++++++++++++++++++- + 1 file changed, 62 insertions(+), 1 deletion(-) + +diff --git a/board/aspeed/ast-g5/ipmi-handler.c b/board/aspeed/ast-g5/ipmi-handler.c +index 5e78546..4e921bd 100644 +--- a/board/aspeed/ast-g5/ipmi-handler.c ++++ b/board/aspeed/ast-g5/ipmi-handler.c +@@ -20,10 +20,19 @@ + #define CMD_FWUPD_SET_OPTIONS 0x2B + #define CMD_FWUPD_IMAGE_WRITE 0x2C + #define CMD_INTL_OEM_GET_BUFFER_SIZE 0x66 ++#define CMD_INTL_OEM_GET_SEC_MODE 0xB3 ++#define CMD_INTL_OEM_SET_SEC_MODE 0xB4 + + #define MAX_KCS_BUF_SIZE 1020 /* (0xFF * 4) */ + #define MAX_IPMB_BUF_SIZE 1020 /* (0xFF * 4) */ + ++/* Restriction mode values */ ++#define RESTRICTION_MODE_MIN_VALUE 3 /*Provisioning*/ ++#define RESTRICION_MODE_MAX_VALUE 5 /*Provisioned host disabled */ ++ ++#define STR_ENV_PROVISION "provision" ++ ++ + typedef u16 (*fun_handler)(u8 *req, u16 req_len, u8 *res); + + struct ipmi_cmd_table { +@@ -53,6 +62,11 @@ struct intc_get_buf_size_res { + u8 kcs_size; + u8 ipmb_size; + }; ++struct intc_get_secuirty_mode_res { ++ u8 completion_code; ++ u8 restriction_mode; ++ u8 special_mode; ++}; + + static u16 get_device_id(u8 *req, u16 req_len, u8 *res) + { +@@ -120,6 +134,51 @@ static u16 intel_get_buffer_size(u8 *req, u16 req_len, u8 *res) + return sizeof(struct intc_get_buf_size_res); + } + ++static u16 intel_get_security_mode(u8 *req, u16 req_len, u8 *res) ++{ ++ char *cmdline = NULL; ++ struct intc_get_secuirty_mode_res *result = ++ (struct intc_get_secuirty_mode_res *)res; ++ ++ if (req_len != 0) { ++ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; ++ return sizeof(result->completion_code); ++ } ++ ++ cmdline = getenv(STR_ENV_PROVISION); ++ if (!cmdline) { ++ /* Default provision must be set only by linux */ ++ result->completion_code = IPMI_CC_UNSPECIFIED; ++ return sizeof(result->completion_code); ++ } ++ result->restriction_mode = simple_strtol(cmdline, NULL, 10); ++ /* special mode is non-volatile and not applicable in U-Boot */ ++ result->special_mode = 0; ++ result->completion_code = IPMI_CC_OK; ++ ++ return sizeof(*result); ++} ++ ++static u16 intel_set_security_mode(u8 *req, u16 req_len, u8 *res) ++{ ++ if (req_len != sizeof(*req)) { ++ *res = IPMI_CC_INVALID_DATA_LENGTH; ++ return sizeof(*res); ++ } ++ ++ if (*req > RESTRICION_MODE_MAX_VALUE || ++ *req < RESTRICTION_MODE_MIN_VALUE) { ++ *res = IPMI_CC_INVALID_DATA_FIELD; ++ return sizeof(*res); ++ } ++ ++ setenv_ulong(STR_ENV_PROVISION, *req); ++ saveenv(); ++ *res = IPMI_CC_OK; ++ ++ return sizeof(*res); ++} ++ + const struct ipmi_cmd_table cmd_info[] = { + { NETFN_APP, CMD_APP_GET_DEV_ID, get_device_id }, + { NETFN_APP, CMD_APP_GET_SELF_TEST_RESULTS, get_self_test_result }, +@@ -131,7 +190,9 @@ const struct ipmi_cmd_table cmd_info[] = { + { NETFN_FIRMWARE, CMD_FWUPD_GET_UPDATE_STATUS, fwupd_get_update_status }, + { NETFN_FIRMWARE, CMD_FWUPD_SET_OPTIONS, fwupd_set_options }, + { NETFN_FIRMWARE, CMD_FWUPD_IMAGE_WRITE, fwupd_image_write }, +- { NETFN_INTEL_OEM, CMD_INTL_OEM_GET_BUFFER_SIZE, intel_get_buffer_size } ++ { NETFN_INTEL_OEM, CMD_INTL_OEM_GET_BUFFER_SIZE, intel_get_buffer_size }, ++ { NETFN_INTEL_OEM, CMD_INTL_OEM_GET_SEC_MODE, intel_get_security_mode }, ++ { NETFN_INTEL_OEM, CMD_INTL_OEM_SET_SEC_MODE, intel_set_security_mode }, + }; + + #define CMD_TABLE_SIZE ARRAY_SIZE(cmd_info) diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0031-Make-it-so-TFTP-port-can-be-modified.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0031-Make-it-so-TFTP-port-can-be-modified.patch new file mode 100644 index 000000000..b70427fe0 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0031-Make-it-so-TFTP-port-can-be-modified.patch @@ -0,0 +1,40 @@ +From 1d680678abb76bdea7cf2128b7ce6db4a5652151 Mon Sep 17 00:00:00 2001 +From: James Feist <james.feist@linux.intel.com> +Date: Tue, 16 Jul 2019 16:30:02 -0700 +Subject: [PATCH 1/1] Make it so TFTP port can be modified + +This makes it so we can use non-privileged tftp ports. + +Tested: Can load fw from non-privileged port. + +Signed-off-by: James Feist <james.feist@linux.intel.com> +--- + include/configs/ast-g5-ncsi.h | 2 ++ + include/configs/ast-g5-phy.h | 2 ++ + 2 files changed, 4 insertions(+) + +diff --git a/include/configs/ast-g5-ncsi.h b/include/configs/ast-g5-ncsi.h +index 12d6684551..20864b2798 100644 +--- a/include/configs/ast-g5-ncsi.h ++++ b/include/configs/ast-g5-ncsi.h +@@ -28,4 +28,6 @@ + + #define CONFIG_HW_WATCHDOG + ++#define CONFIG_TFTP_PORT ++ + #endif /* __AST_G5_NCSI_CONFIG_H */ +diff --git a/include/configs/ast-g5-phy.h b/include/configs/ast-g5-phy.h +index 62ddb841e5..371f50a1db 100644 +--- a/include/configs/ast-g5-phy.h ++++ b/include/configs/ast-g5-phy.h +@@ -30,4 +30,6 @@ + /* platform.S */ + #define CONFIG_DRAM_ECC_SIZE 0x10000000 + ++#define CONFIG_TFTP_PORT ++ + #endif /* __AST_G5_PHY_CONFIG_H */ +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch new file mode 100644 index 000000000..b76a3dba0 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch @@ -0,0 +1,102 @@ +From dda24946edd0a4ec54e3ecaa8bd493cce9bdfa15 Mon Sep 17 00:00:00 2001 +From: AppaRao Puli <apparao.puli@linux.intel.com> +Date: Mon, 22 Jul 2019 08:26:15 +0530 +Subject: [PATCH] Adding PFR boot flow checkpoint in u-boot + +Added two PFR boot flow check points in u-boot +1) Set the booting starts checkpoint(0x01) +2) Set FFUJ checkpoint(0x07) when jumper on. + +Tested: +Loaded the image, dumped all cpld registers and +cross verified the check-points properly set or not. + +Change-Id: I3c725b0e15c1fea5bdb7b085826bdabad19bda80 +Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> +--- + board/aspeed/ast-g5/ast-g5-intel.c | 46 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index e68ab85..9f0a64d 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -12,11 +12,21 @@ + #include <asm/arch/regs-scu.h> + #include <asm/arch/ast_scu.h> + #include <asm/arch/aspeed.h> ++#include <i2c.h> + + #include "ast-g5.h" + #include "ast-g5-gpio.h" + #include "ast-g5-timer.h" + ++/* PFR Specific defines */ ++#define PFR_CPLD_I2C_BUSNO 4 ++#define PFR_CPLD_SLAVE_ADDR 0xE0 ++#define PFR_CPLD_BOOT_CHECKPOINT_REG 0x13 ++ ++#define PFR_CPLD_CHKPOINT_START 0x01 ++#define PFR_CPLD_CHKPOINT_FFUJ 0x07 ++#define PFR_CPLD_CHKPOINT_FINISHED 0x09 ++ + /* Names to match the GPIOs */ + enum gpio_names { + GPIO_ID_LED = 0, +@@ -537,10 +547,42 @@ static void pwm_init(void) + writel(val, PWM_BASE_ADDR + PWM_CONTROL); + } + ++static void set_boot_checkpoint(u8 chk_point) ++{ ++ int ret = 0; ++ int chip = (PFR_CPLD_SLAVE_ADDR >> 1); ++ u32 reg_addr = PFR_CPLD_BOOT_CHECKPOINT_REG; ++ ++ /* Get current I2C bus number to restore later. */ ++ int current_bus_no = i2c_get_bus_num(); ++ ++ /* Set I2C bus number to PFR CPLD I2C bus. */ ++ ret = i2c_set_bus_num(PFR_CPLD_I2C_BUSNO); ++ if (ret) { ++ printf("Failed to change I2C bus number (%d)\n", ret); ++ goto done; ++ } ++ ++ ret = i2c_write(chip, reg_addr, 1, &chk_point, 1); ++ if (ret) { ++ printf("Error writing the chip: %d\n", ret); ++ goto done; ++ } ++ ++done: ++ /* Restore I2C bus number */ ++ if (i2c_set_bus_num(current_bus_no)) ++ printf("Failed to restore I2C bus number.\n"); ++} ++ + extern void espi_init(void); + extern void kcs_init(void); + void ast_g5_intel(void) + { ++ /* To notify the CPLD about the start of bootloader ++ * and hardware initialization */ ++ set_boot_checkpoint(PFR_CPLD_CHKPOINT_START); ++ + uart_init(); + pwm_init(); + gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); +@@ -551,6 +593,10 @@ void ast_g5_intel(void) + if (intel_force_firmware_jumper_enabled()) { + id_led_control(GPIO_AMBER_LED, EIDLED_On); + kcs_init(); ++ /* Notify CPLD about FFUJ jumper set and pause ++ * of booting for indefinitely time. It will be ++ * resumed once reset is done. */ ++ set_boot_checkpoint(PFR_CPLD_CHKPOINT_FFUJ); + /* TODO: need to stop the booting here. */ + } else { + id_led_control(GPIO_GREEN_LED, EIDLED_On); +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0033-PFR-firmware-update-support-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0033-PFR-firmware-update-support-in-u-boot.patch new file mode 100644 index 000000000..80a949a87 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0033-PFR-firmware-update-support-in-u-boot.patch @@ -0,0 +1,480 @@ +From d9287ee5f3b797fd492ec78617c174ad20e85bc4 Mon Sep 17 00:00:00 2001 +From: AppaRao Puli <apparao.puli@linux.intel.com> +Date: Wed, 24 Jul 2019 20:11:30 +0530 +Subject: [PATCH] PFR firmware update support in u-boot + +Added firmware update ipmi commands support +for PFR images. This enables PFR based firmware +updates for components BMC, BIOS and CPLD during +FFUJ mode. + +Tested: +Using debug fwpiaupd.efi utility, validated the PFR +BMC image update. + +Change-Id: Ic2b550c42208f52ec865da463e6518bf8c503c15 +Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> +--- + board/aspeed/ast-g5/Makefile | 1 + + board/aspeed/ast-g5/fw-update.c | 112 ++++++++++++++++++++------------------- + board/aspeed/ast-g5/fw-update.h | 7 +++ + board/aspeed/ast-g5/ipmi-fwupd.c | 37 +++++++++++++ + board/aspeed/ast-g5/ipmi-fwupd.h | 6 --- + board/aspeed/ast-g5/pfr-mgr.c | 73 +++++++++++++++++++++++++ + board/aspeed/ast-g5/pfr-mgr.h | 67 +++++++++++++++++++++++ + 7 files changed, 242 insertions(+), 61 deletions(-) + create mode 100644 board/aspeed/ast-g5/pfr-mgr.c + create mode 100644 board/aspeed/ast-g5/pfr-mgr.h + +diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile +index 0b2d936..9021d7f 100644 +--- a/board/aspeed/ast-g5/Makefile ++++ b/board/aspeed/ast-g5/Makefile +@@ -8,3 +8,4 @@ obj-y += ast-g5-kcs.o + obj-y += ipmi-handler.o + obj-y += ipmi-fwupd.o + obj-y += fw-update.o ++obj-y += pfr-mgr.o +diff --git a/board/aspeed/ast-g5/fw-update.c b/board/aspeed/ast-g5/fw-update.c +index 9923993..89fe5fd 100644 +--- a/board/aspeed/ast-g5/fw-update.c ++++ b/board/aspeed/ast-g5/fw-update.c +@@ -6,6 +6,7 @@ + #include <flash.h> + + #include "fw-update.h" ++#include "pfr-mgr.h" + + #define BOOTCMD_BOOTM_STR "bootm " + #define RANDOM_NUM_TIMEOUT 30 /* in seconds */ +@@ -15,7 +16,7 @@ + #define PROTECT_ON 1 + + extern struct fwupd_global_setting g_fwupd_settings; +-extern u32 g_write_addr; ++extern struct fwupd_image_info g_img_info; + + bool g_fwupd_settings_lock = false; + unsigned long long etime; +@@ -36,16 +37,8 @@ void fwupd_settings_unlock(void) + + u8 get_active_boot_image(void) + { +- char *bootcmd = getenv("bootcmd"); +- char *start = strstr(bootcmd, BOOTCMD_BOOTM_STR); ++ /* For PFR, its always active region */ + u8 boot_image = PRIMARY_IMAGE; +- +- if (start) { +- ulong boot_addr = simple_strtoul( +- (start + strlen(BOOTCMD_BOOTM_STR)), NULL, 16); +- if (boot_addr == SECONDARY_FITIMAGE_START_ADDR) +- return SECONDARY_IMAGE; +- } + return boot_image; + } + +@@ -318,45 +311,22 @@ static int erase_flash_sector(ulong addr_first, ulong addr_last) + return rcode; + } + +-static int verify_image(void) ++static int verify_image(ulong src_addr, ulong img_length) + { +- ulong src_addr = IMAGE_LOAD_RAM_ADDR; +- void *hdr = (void *)src_addr; +- +- printf("\n## Checking Image at 0x%08lx ...\n", src_addr); +- /* AT the moment, we only support FIT image flash */ +- switch (genimg_get_format(hdr)) { +- case IMAGE_FORMAT_FIT: +- printf(" FIT image found\n"); +- if (!fit_check_format(hdr)) { +- printf("Bad FIT image format!\n"); +- return -1; +- } +- +- if (!fit_all_image_verify(hdr)) { +- printf("Bad hash in FIT image!\n"); +- return -1; +- } +- break; +- default: +- printf("Unknown image format!\n"); +- return -1; +- } +- ++ /* TODO: Verify the hash alone here.*/ ++ /* Full image verification is done in CPLD. */ + return 0; + } + +-static int flash_image(void) ++static int flash_image(ulong src_addr, ulong addr_first, ulong max_size, ++ ulong img_length) + { + int rcode; +- ulong max_size = MAX_FITIMAGE_SIZE; +- ulong src_addr = IMAGE_LOAD_RAM_ADDR; +- ulong addr_first = get_flash_image_address(); + ulong addr_last = addr_first + max_size - 1; + +- if ((g_write_addr > max_size) || (g_write_addr == 0)) { ++ if ((img_length > max_size) || (img_length == 0)) { + printf("ERROR: %s(): Invalid file uploaded. filesize(0x%08x)\n", +- __func__, g_write_addr); ++ __func__, img_length); + return -1; + } + +@@ -398,7 +368,7 @@ static int flash_image(void) + + /* write to flash area */ + printf("Copy to Flash... "); +- rcode = flash_write((char *)src_addr, addr_first, g_write_addr * 1); ++ rcode = flash_write((char *)src_addr, addr_first, img_length); + if (rcode != 0) { + printf("%s(): Flash copy failed(%d).\n", __func__, rcode); + flash_perror(rcode); +@@ -430,10 +400,27 @@ void start_fw_update_loop(void) + } + + if (g_fwupd_settings.start_update) { ++ printf("Starting image copy to staging area.....\n"); + update_processing_status(IMG_VALIDATING, 0); +- +- rc = verify_image(); ++ u8 update_intent = 0x00; ++ if ((g_fwupd_settings.options_mask & ++ g_fwupd_settings.options_value) & DEFER_BMC_RESET) ++ update_intent |= DEFER_UPDATES_TO_RESET; ++ ++ ulong offset = ++ get_flash_region_offset(g_img_info.img_type); ++ ulong max_size = ++ get_image_max_size(g_img_info.img_type); ++ ulong src_addr = IMAGE_LOAD_RAM_ADDR; ++ ulong flash_addr = PFR_IMAGE_STAGING_BASE_ADDR + offset; ++ ++ debug("FWUPD: offset:0x%08lx, max_size:0x%08lx, " ++ "src_addr:0x%08lx, flash_addr:0x%08lx\n", ++ offset, max_size, src_addr, flash_addr); ++ ++ rc = verify_image(src_addr, g_img_info.img_length); + if (rc != 0) { ++ printf("Image verification failed.\n"); + update_processing_status(UPDATE_ERROR, 100); + /* Adding delay to make consumer gets status */ + mdelay(WAIT_STATE_TIMEOUT); +@@ -441,31 +428,46 @@ void start_fw_update_loop(void) + reset_all_settings(); + continue; + } ++ printf("Image verification success.\n"); + + update_processing_status(IMG_PROGRAMMING, 10); + +- rc = flash_image(); ++ rc = flash_image(src_addr, flash_addr, max_size, ++ g_img_info.img_length); + if (rc == 0) { +- /* Update successful, change the boot command */ +- boot_addr = get_flash_image_address(); +- snprintf(boot_cmd, sizeof(boot_cmd), +- "bootm %08x", boot_addr); +- setenv("bootcmd", boot_cmd); +- saveenv(); ++ update_processing_status(IMG_PROGRAMMING, 90); ++ } else { ++ update_processing_status(UPDATE_ERROR, 100); ++ } + ++ printf("Image copy to staging area %s.\n", ++ ((rc == 0) ? "successful" : "failed")); ++ ++ /* Set the BMC update intent BIT to CPLD register */ ++ update_intent != get_update_intent(g_img_info.img_type); ++ ++ /* TODO: We ned a way to protect the staging area from ++ * next write data. After setting cpld intent bit, CPLD ++ * read the stagging region for associated image types ++ * and update active/recovery area. During this stage, ++ * staging area should be protected from next write. ++ * Working with CPLD team for identifying this state. */ ++ if (0 != set_cpld_reg(PFR_CPLD_BMC_UPDATE_INTENT_REG, ++ update_intent)) { ++ update_processing_status(UPDATE_ERROR, 100); ++ } else { ++ printf("CPLD: Update intent set successfully.\n"); + update_processing_status(UPDATE_SUCCESSFUL, + 100); +- } else { +- update_processing_status(UPDATE_ERROR, 100); ++ ++ if (update_intent & DEFER_UPDATES_TO_RESET) ++ printf("CPLD: Update defered to next reset.\n"); + } + + /* Adding delay to make sure consumer gets status */ + mdelay(WAIT_STATE_TIMEOUT); +- + reset_all_settings(); + +- /* Reset BMC */ +- do_reset(NULL, 0, 0, NULL); + } + mdelay(WAIT_STATE_TIMEOUT); + } +diff --git a/board/aspeed/ast-g5/fw-update.h b/board/aspeed/ast-g5/fw-update.h +index ed033ad..45e46ba 100644 +--- a/board/aspeed/ast-g5/fw-update.h ++++ b/board/aspeed/ast-g5/fw-update.h +@@ -28,6 +28,12 @@ enum update_status { + UPDATE_FORBIDDEN = 0x80, + AC_CYCLE_REQUIRED = 0x83 + }; ++enum update_options { ++ NO_DOWN_REVISION = BIT(0), ++ DEFER_BMC_RESET = BIT(1), ++ SHA32_INTEGRITY_CHECK = BIT(2), ++ CRC32_INTEGRITY_CHECK = BIT(3) ++}; + + struct fwupd_global_setting { + bool fwupd_mode_active; +@@ -48,3 +54,4 @@ bool fwupd_settings_trylock(void); + void fwupd_settings_unlock(void); + u8 get_active_boot_image(void); + int generate_random_number(void); ++ +diff --git a/board/aspeed/ast-g5/ipmi-fwupd.c b/board/aspeed/ast-g5/ipmi-fwupd.c +index 3eba056..6afc8d6 100644 +--- a/board/aspeed/ast-g5/ipmi-fwupd.c ++++ b/board/aspeed/ast-g5/ipmi-fwupd.c +@@ -2,10 +2,14 @@ + // Copyright (c) 2018-2019 Intel Corporation + + #include "ipmi-fwupd.h" ++#include "pfr-mgr.h" + + struct fwupd_global_setting g_fwupd_settings; + u32 g_write_addr = 0; + ++struct fwupd_image_info g_img_info; ++static bool block0_mapped = false; ++ + u16 fwupd_get_execution_ctx(u8 *req, u16 req_len, u8 *res) + { + int booting_image = 0x01; +@@ -395,6 +399,39 @@ u16 fwupd_image_write(u8 *req, u16 req_len, u8 *res) + memcpy(mem_addr, req, req_len); + g_write_addr += req_len; + ++ /* Get the PFR block 0 data and read the uploaded image ++ * information( Image type, length, hash etc) */ ++ if ((g_write_addr >= sizeof(struct pfr_image_block0)) && ++ (!block0_mapped)) { ++ struct pfr_image_block0 *block0_data = ++ (struct pfr_image_block0 *)IMAGE_LOAD_RAM_ADDR; ++ u32 magic_num = (u32)((*block0_data->tag) | ++ LSH(*(block0_data->tag + 1), 8) | ++ LSH(*(block0_data->tag + 2), 16) | ++ LSH(*(block0_data->tag + 3), 24)); ++ /* Validate the magic number */ ++ if (magic_num != PFR_BLOCK0_MAGIC_NUM) { ++ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; ++ return sizeof(result->completion_code); ++ } ++ ++ /* Fill the image info structure for later use */ ++ g_img_info.magic_num = magic_num; ++ g_img_info.img_length = ++ (u32)((*block0_data->pc_length) | ++ LSH(*(block0_data->pc_length + 1), 8) | ++ LSH(*(block0_data->pc_length + 2), 16) | ++ LSH(*(block0_data->pc_length + 3), 24)); ++ g_img_info.img_type = ++ (u32)((*block0_data->pc_type) | ++ LSH(*(block0_data->pc_type + 1), 8) | ++ LSH(*(block0_data->pc_type + 2), 16) | ++ LSH(*(block0_data->pc_type + 3), 24)); ++ /* Add Authentication data struct length for full image */ ++ g_img_info.img_length += PFR_AUTH_DATA_STRUCT_LEN; ++ block0_mapped = true; ++ } ++ + result->completion_code = IPMI_CC_OK; + result->no_of_bytes_written = (u8)req_len; + +diff --git a/board/aspeed/ast-g5/ipmi-fwupd.h b/board/aspeed/ast-g5/ipmi-fwupd.h +index e490f6b..7409d2e 100644 +--- a/board/aspeed/ast-g5/ipmi-fwupd.h ++++ b/board/aspeed/ast-g5/ipmi-fwupd.h +@@ -19,12 +19,6 @@ enum control_state_bit { + IMG_TRANSFER_CTRL_BIT_ABORT = (0x01 << 2), + USB_CTRL_BIT_ATTACH = (0x01 << 3) + }; +-enum update_options_bit { +- NO_DOWN_REVISION = 0, +- DEFER_BMC_RESET = 1, +- SHA32_INTEGRITY_CHECK = 2, +- CRC32_INTEGRITY_CHECK = 3 +-}; + + struct fwupd_get_exe_ctx_res { + u8 completion_code; +diff --git a/board/aspeed/ast-g5/pfr-mgr.c b/board/aspeed/ast-g5/pfr-mgr.c +new file mode 100644 +index 0000000..7713168 +--- /dev/null ++++ b/board/aspeed/ast-g5/pfr-mgr.c +@@ -0,0 +1,73 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++// Copyright (c) 2018-2019 Intel Corporation ++ ++#include "pfr-mgr.h" ++ ++int set_cpld_reg(u8 reg_addr, u8 value) ++{ ++ int ret = 0; ++ int chip = (PFR_CPLD_SLAVE_ADDR >> 1); ++ ++ /* Get current I2C bus number to restore later. */ ++ int current_bus_no = i2c_get_bus_num(); ++ ++ /* Set I2C bus number to PFR CPLD I2C bus. */ ++ ret = i2c_set_bus_num(PFR_CPLD_I2C_BUSNO); ++ if (ret) { ++ printf("Failed to change I2C bus number (%d)\n", ret); ++ goto done; ++ } ++ ++ ret = i2c_write(chip, reg_addr, 1, &value, 1); ++ if (ret) { ++ printf("Error writing the chip: %d\n", ret); ++ goto done; ++ } ++ ++done: ++ /* Restore I2C bus number */ ++ if (i2c_set_bus_num(current_bus_no)) ++ printf("Failed to restore I2C bus number.\n"); ++ ++ return ret; ++} ++ ++ulong get_update_intent(u32 type) ++{ ++ ulong intent = 0; ++ if (type == PFR_CPLD_UPDATE_CAPSULE) ++ intent = CPLD_IMAGE_UPDATE; ++ else if (type == PFR_PCH_UPDATE_CAPSULE) ++ intent = PCH_SPI_FLASH_ACTIVE; ++ else if (type == PFR_BMC_UPDATE_CAPSULE) ++ intent = BMC_SPI_FLASH_ACTIVE; ++ ++ return intent; ++} ++ ++ulong get_image_max_size(u32 type) ++{ ++ ulong max_size = MAX_BMC_IMAGE_SIZE; ++ if (type == PFR_CPLD_UPDATE_CAPSULE) ++ max_size = MAX_CPLD_IMAGE_SIZE; ++ else if (type == PFR_PCH_UPDATE_CAPSULE) ++ max_size = MAX_BIOS_IMAGE_SIZE; ++ else if (type == PFR_BMC_UPDATE_CAPSULE) ++ max_size = MAX_BMC_IMAGE_SIZE; ++ ++ return max_size; ++} ++ ++ulong get_flash_region_offset(u32 type) ++{ ++ ulong offset = 0; ++ if (type == PFR_CPLD_UPDATE_CAPSULE) ++ offset = PFR_CPLD_IMAGE_REGION_OFFSET; ++ else if (type == PFR_PCH_UPDATE_CAPSULE) ++ offset = PFR_BIOS_IMAGE_REGION_OFFSET; ++ else if (type == PFR_BMC_UPDATE_CAPSULE) ++ offset = PFR_BMC_IMAGE_REGION_OFFSET; ++ ++ return offset; ++} ++ +diff --git a/board/aspeed/ast-g5/pfr-mgr.h b/board/aspeed/ast-g5/pfr-mgr.h +new file mode 100644 +index 0000000..b2368e1 +--- /dev/null ++++ b/board/aspeed/ast-g5/pfr-mgr.h +@@ -0,0 +1,67 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++// Copyright (c) 2018-2019 Intel Corporation ++ ++#include <common.h> ++ ++/* CPLD I2C device defines */ ++#define PFR_CPLD_I2C_BUSNO 4 ++#define PFR_CPLD_SLAVE_ADDR 0xE0 ++ ++/* CPLD registers */ ++#define PFR_CPLD_BMC_UPDATE_INTENT_REG 0x13 ++ ++#define PFR_BLOCK0_MAGIC_NUM 0xB6EAFD19 ++#define PFR_AUTH_DATA_STRUCT_LEN 1024 /* Block0 & Block1 */ ++ ++/* SPI Flash MAP */ ++#define PFR_IMAGE_STAGING_BASE_ADDR 0x24A00000 /* 54MB */ ++#define MAX_BMC_IMAGE_SIZE 0x2000000 /* 32MB */ ++#define MAX_BIOS_IMAGE_SIZE 0x1000000 /* 16MB */ ++#define MAX_CPLD_IMAGE_SIZE 0x400000 /* 4MB */ ++#define PFR_BMC_IMAGE_REGION_OFFSET 0 ++#define PFR_BIOS_IMAGE_REGION_OFFSET \ ++ (PFR_BMC_IMAGE_REGION_OFFSET + MAX_BMC_IMAGE_SIZE) ++#define PFR_CPLD_IMAGE_REGION_OFFSET \ ++ (PFR_BIOS_IMAGE_REGION_OFFSET + MAX_BIOS_IMAGE_SIZE) ++ ++#define LSH(data, num) ((data) << (num)) ++ ++/* Bit mapping for CPLD 'BMC update intent' */ ++enum cpld_update_intent { ++ PCH_SPI_FLASH_ACTIVE = BIT(0), ++ PCH_SPI_FLASH_RECOVERY = BIT(1), ++ CPLD_IMAGE_UPDATE = BIT(2), ++ BMC_SPI_FLASH_ACTIVE = BIT(3), ++ BMC_SPI_FLASH_RECOVERY = BIT(4), ++ DEFER_UPDATES_TO_RESET = BIT(7) ++}; ++ ++enum pfr_block0_pc_type { ++ PFR_CPLD_UPDATE_CAPSULE = 0x00, ++ PFR_PCH_PFM = 0x01, ++ PFR_PCH_UPDATE_CAPSULE = 0x02, ++ PFR_BMC_PFM = 0x03, ++ PFR_BMC_UPDATE_CAPSULE = 0x04 ++}; ++ ++/* PFR image block 0 - As defined in HAS */ ++struct pfr_image_block0 { ++ u8 tag[4]; ++ u8 pc_length[4]; ++ u8 pc_type[4]; ++ u8 reserved_1[4]; ++ u8 hash_256[32]; ++ u8 hash_384[48]; ++ u8 reserved_2[32]; ++}; ++ ++struct fwupd_image_info { ++ u32 magic_num; ++ u32 img_length; ++ u32 img_type; ++}; ++ ++int set_cpld_reg(u8 reg_addr, u8 value); ++ulong get_update_intent(u32 type); ++ulong get_flash_region_offset(u32 type); ++ulong get_image_max_size(u32 type); +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend index acac46d70..5d8c10a76 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend @@ -31,8 +31,15 @@ SRC_URI_append_intel-ast2500 = " \ file://0027-CPLD-u-boot-commands-support-for-PFR.patch \ file://0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch \ file://0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch \ + file://0030-Support-Get-Set-Security-mode-command.patch \ + file://0031-Make-it-so-TFTP-port-can-be-modified.patch \ " -SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('IMAGE_TYPE', 'pfr', 'file://0022-u-boot-env-change-for-PFR-image.patch', '', d)}" +PFR_SRC_URI = " \ + file://0022-u-boot-env-change-for-PFR-image.patch \ + file://0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch \ + file://0033-PFR-firmware-update-support-in-u-boot.patch \ + " +SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" require recipes-core/os-release/version-vars.inc diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend index acac46d70..5d8c10a76 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend @@ -31,8 +31,15 @@ SRC_URI_append_intel-ast2500 = " \ file://0027-CPLD-u-boot-commands-support-for-PFR.patch \ file://0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch \ file://0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch \ + file://0030-Support-Get-Set-Security-mode-command.patch \ + file://0031-Make-it-so-TFTP-port-can-be-modified.patch \ " -SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('IMAGE_TYPE', 'pfr', 'file://0022-u-boot-env-change-for-PFR-image.patch', '', d)}" +PFR_SRC_URI = " \ + file://0022-u-boot-env-change-for-PFR-image.patch \ + file://0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch \ + file://0033-PFR-firmware-update-support-in-u-boot.patch \ + " +SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" require recipes-core/os-release/version-vars.inc |