Update to internal 0.44

Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

4 files changed, 328 insertions, 51 deletions

diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch
new file mode 100644
index 000000000..2ec774144
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch
@@ -0,0 +1,265 @@
+From 8c9e2fffa9ea72ddc8734ee74b30cc62ba06fd3a Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Mon, 2 Mar 2020 13:54:50 -0800
+Subject: [PATCH] AST2600: Add the latest chip initialization code
+
+This commit cherry picked the latest chip initialization code from
+Aspped SDK v00.05.05 to support AST2600 A1 revision.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ arch/arm/mach-aspeed/ast2600/Makefile   |   2 +-
+ arch/arm/mach-aspeed/ast2600/cache.c    |  26 +++++++
+ arch/arm/mach-aspeed/ast2600/platform.S | 132 +++++++++++++++++++++++++-------
+ 3 files changed, 130 insertions(+), 30 deletions(-)
+ create mode 100644 arch/arm/mach-aspeed/ast2600/cache.c
+
+diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile
+index b074d4b70a14..2889388fab75 100644
+--- a/arch/arm/mach-aspeed/ast2600/Makefile
++++ b/arch/arm/mach-aspeed/ast2600/Makefile
+@@ -1,2 +1,2 @@
+-obj-y   += platform.o aspeed_scu_info.o
++obj-y   += platform.o aspeed_scu_info.o cache.o
+ obj-$(CONFIG_SPL_BUILD) += spl.o
+diff --git a/arch/arm/mach-aspeed/ast2600/cache.c b/arch/arm/mach-aspeed/ast2600/cache.c
+new file mode 100644
+index 000000000000..82de0b0fda8a
+--- /dev/null
++++ b/arch/arm/mach-aspeed/ast2600/cache.c
+@@ -0,0 +1,26 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) ASPEED Technology Inc.
++ * Chia-Wei Wang <chiawei_wang@aspeedtech.com>
++ */
++
++#include <common.h>
++#include <asm/system.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++void enable_caches(void)
++{
++#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
++	enum dcache_option opt = DCACHE_WRITETHROUGH;
++#else
++	enum dcache_option opt = DCACHE_WRITEBACK;
++#endif
++	/* enable D-cache as well as MMU */
++	dcache_enable();
++
++	/* setup cache attribute for DRAM region */
++	mmu_set_region_dcache_behaviour(ASPEED_DRAM_BASE,
++				       gd->ram_size,
++				       opt);
++}
+diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
+index de97cccc78b7..f1a1f057c09b 100644
+--- a/arch/arm/mach-aspeed/ast2600/platform.S
++++ b/arch/arm/mach-aspeed/ast2600/platform.S
+@@ -26,39 +26,45 @@
+  * +----------------------+ AST_SMP_MAILBOX_BASE
+  */
+ 
+-#define AST_SMP_MAILBOX_BASE		0x1E6E2180
++#define AST_SMP_MAILBOX_BASE		(0x1E6E2180)
+ #define AST_SMP_MBOX_FIELD_ENTRY	(AST_SMP_MAILBOX_BASE + 0x0)
+ #define AST_SMP_MBOX_FIELD_GOSIGN	(AST_SMP_MAILBOX_BASE + 0x4)
+ #define AST_SMP_MBOX_FIELD_READY	(AST_SMP_MAILBOX_BASE + 0x8)
+ #define AST_SMP_MBOX_FIELD_POLLINSN	(AST_SMP_MAILBOX_BASE + 0xc)
+ 
+ /* AST2600 HW registers */
+-#define AST_SCU_BASE		0x1E6E2000
+-#define AST_SCU_PROT_KEY1	(AST_SCU_BASE)
+-#define AST_SCU_PROT_KEY2	(AST_SCU_BASE + 0x010)
+-#define AST_SCU_REV_ID		(AST_SCU_BASE + 0x014)
+-#define AST_SCU_HPLL_PARAM	(AST_SCU_BASE + 0x200)
+-#define AST_SCU_HPLL_PARAM_EXT	(AST_SCU_BASE + 0x204)
+-#define AST_SCU_HW_STRAP1	(AST_SCU_BASE + 0x500)
+-#define AST_SCU_CA7_PARITY_CHK	(AST_SCU_BASE + 0x820)
+-#define AST_SCU_CA7_PARITY_CLR	(AST_SCU_BASE + 0x824)
+-
+-#define AST_FMC_BASE		0x1E620000
++#define AST_SCU_BASE			(0x1E6E2000)
++#define AST_SCU_PROT_KEY1		(AST_SCU_BASE)
++#define AST_SCU_PROT_KEY2		(AST_SCU_BASE + 0x010)
++#define AST_SCU_REV_ID			(AST_SCU_BASE + 0x014)
++#define AST_SCU_SYSRST_CTRL		(AST_SCU_BASE + 0x040)
++#define AST_SCU_SYSRST_CTRL_CLR		(AST_SCU_BASE + 0x044)
++#define AST_SCU_DEBUG_CTRL              (AST_SCU_BASE + 0x0C8)
++#define AST_SCU_DEBUG_CTRL2             (AST_SCU_BASE + 0x0D8)
++#define AST_SCU_HPLL_PARAM		(AST_SCU_BASE + 0x200)
++#define AST_SCU_HPLL_PARAM_EXT		(AST_SCU_BASE + 0x204)
++#define AST_SCU_HW_STRAP1		(AST_SCU_BASE + 0x500)
++#define AST_SCU_HW_STRAP1_CLR		(AST_SCU_BASE + 0x504)
++#define AST_SCU_HW_STRAP2		(AST_SCU_BASE + 0x510)
++#define AST_SCU_HW_STRAP2_CLR		(AST_SCU_BASE + 0x514)
++#define AST_SCU_CA7_CTRL		(AST_SCU_BASE + 0x800)
++#define AST_SCU_CA7_AXI_PREFETCH_START	(AST_SCU_BASE + 0x808)
++#define AST_SCU_CA7_AXI_PREFETCH_END	(AST_SCU_BASE + 0x80C)
++#define AST_SCU_CA7_PARITY_CHK		(AST_SCU_BASE + 0x820)
++#define AST_SCU_CA7_PARITY_CLR		(AST_SCU_BASE + 0x824)
++#define AST_SCU_MMIO_DEC_SET		(AST_SCU_BASE + 0xC24)
++
++#define AST_FMC_BASE		(0x1E620000)
++#define AST_FMC_CE0_CTRL	(AST_FMC_BASE + 0x010)
+ #define AST_FMC_WDT1_CTRL_MODE	(AST_FMC_BASE + 0x060)
+ #define AST_FMC_WDT2_CTRL_MODE	(AST_FMC_BASE + 0x064)
+ 
++#define AST_GPIO_BASE		(0x1E780000)
++#define AST_GPIOYZ_DATA_VALUE	(AST_GPIO_BASE + 0x1E0)
++
+ /* Revision ID */
+ #define REV_ID_AST2600A0	0x05000303
+ 
+-ENTRY(ast_bootmode)
+-	ldr	r1, =AST_SCU_HW_STRAP1
+-	ldr	r0, [r1]
+-	tst	r0, #0x4
+-	moveq	r0, #0x0	@; AST_BOOTMODE_SPI
+-	movne	r0, #0x1	@; AST_BOOTMODE_EMMC
+-	mov	pc, lr
+-ENDPROC(ast_bootmode)
+-
+ .macro scu_unlock
+ 	movw	r0, #0xA8A8
+ 	movt	r0, #0x1688	@; magic key to unlock SCU
+@@ -71,11 +77,19 @@ ENDPROC(ast_bootmode)
+ 
+ .macro timer_init
+ #ifdef CONFIG_FPGA_ASPEED
+-	movw	r0, #0x7840
+-	movt	r0, #0x17D
++	movw	r0, #0xF080
++	movt	r0, #0x2FA
+ #else
+-	movw 	r0, #0x2340
+-	movt	r0, #0x430E
++	ldr	r0, =AST_SCU_REV_ID
++	ldr	r0, [r0]
++
++	ldr	r1, =REV_ID_AST2600A0
++	cmp	r0, r1
++
++	movweq 	r0, #0x32C0
++	movteq	r0, #0x4013
++	movwne	r0, #0x8C00
++	movtne	r0, #0x4786
+ #endif
+ 	mcr	p15, 0, r0, c14, c0, 0	@; update CNTFRQ
+ .endm
+@@ -133,7 +147,7 @@ do_primary_core_setup:
+ 	/* unlock system control unit */
+ 	scu_unlock
+ 
+-	/* tune-up CPU clock for AST2600 A0 */
++	/* identify AST2600 A0/A1 */
+ 	ldr	r0, =AST_SCU_REV_ID
+ 	ldr	r0, [r0]
+ 
+@@ -142,7 +156,7 @@ do_primary_core_setup:
+ 
+ 	bne	0f
+ 
+-	/* setup CPU clocks */
++	/* tune up CPU clocks (A0 only) */
+ 	ldr	r0, =AST_SCU_HW_STRAP1
+ 	ldr	r1, [r0]
+ 	bic	r1, #0x1800
+@@ -150,7 +164,7 @@ do_primary_core_setup:
+ 	str	r1, [r0]
+ 
+ 	ldr	r0, =AST_SCU_HPLL_PARAM
+-	movw	r1, #0x4087
++	movw	r1, #0x4080
+ 	movt	r1, #0x1000
+ 	str	r1, [r0]
+ 
+@@ -163,13 +177,54 @@ wait_lock:
+ 	tst	r1, #0x80000000
+ 	beq	wait_lock
+ 
++	/* skip A1 only area */
++	b 1f
++
+ 0:
++	/* enable AXI prefetch (A1 only) */
++	ldr	r0, =AST_SCU_CA7_AXI_PREFETCH_START
++	ldr r1, =ASPEED_DRAM_BASE
++	str r1, [r0]
++
++	ldr	r0, =AST_SCU_CA7_AXI_PREFETCH_END
++	ldr	r1, =0xFFFFFFFF
++	str r1, [r0]
++
++	ldr	r0, =AST_SCU_CA7_CTRL
++	ldr	r1, [r0]
++	orr	r1, #0x8000
++	str	r1, [r0]
++
++	/* LPC/eSPI mode selection (A1 only) */
++	ldr	r0, =AST_GPIOYZ_DATA_VALUE
++	ldr	r0, [r0]
++	tst	r0, #0x1000
++	beq	1f
++
++	/* switch to LPC mode if GPIOZ[4]=1 */
++	ldr	r0, =AST_SCU_HW_STRAP2
++	ldr	r1, [r0]
++	orr	r1, #0x40
++	str	r1, [r0]
++
++1:
++	/* release display port reset */
++	ldr	r0, =AST_SCU_SYSRST_CTRL_CLR
++	movw	r1, #0x0000
++	movt	r1, #0x3000
++	str	r1, [r0]
++
++	/* MMIO decode setting */
++	ldr	r0, =AST_SCU_MMIO_DEC_SET
++	mov	r1, #0x2000
++	str	r1, [r0]
++
+ 	/* enable cache & SRAM parity check */
+ 	mov	r0, #0
+ 	ldr	r1, =AST_SCU_CA7_PARITY_CLR
+ 	str	r0, [r1]
+ 
+-	mov	r0, #0x11
++	mov	r0, #0x1
+ 	ldr	r1, =AST_SCU_CA7_PARITY_CHK
+ 	str	r0, [r1]
+ 
+@@ -177,8 +232,27 @@ wait_lock:
+ 	mov	r0, #0
+ 	ldr	r1, =AST_FMC_WDT1_CTRL_MODE
+ 	str	r0, [r1]
++#if 0
+ 	ldr	r1, =AST_FMC_WDT2_CTRL_MODE
+ 	str	r0, [r1]
++#endif
++	/* tune up SPI clock */
++	movw	r0, #0x0641
++	movt	r0, #0x203B
++	ldr	r1, =AST_FMC_CE0_CTRL
++	str	r0, [r1]
++
++	/* disable UART-based SoC Debug Interface UART5 and P2A bridge*/
++	ldr     r0, =AST_SCU_DEBUG_CTRL
++	ldr     r1, [r0]
++	orr     r1, #0x03
++	str     r1, [r0]
++
++	/* disable UART-based SoC Debug Interface UART1 and LPC2AHB bridge */
++	ldr     r0, =AST_SCU_DEBUG_CTRL2
++	ldr     r1, [r0]
++	orr     r1, #0x0A
++	str     r1, [r0]
+ 
+ 	/* relocate mailbox insn. for cpuN polling SMP go signal */
+ 	adrl	r0, mailbox_insn
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch
index fac5a64ef..40336d3dd 100644
--- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch
@@ -1,4 +1,4 @@
-From 74a1399befdb0f7604d116ac8578e7e4004728d8 Mon Sep 17 00:00:00 2001
+From dff3a123b0318f83ecd753eea8945ebdc15fd2f9 Mon Sep 17 00:00:00 2001
 From: Vernon Mauery <vernon.mauery@linux.intel.com>
 Date: Wed, 14 Nov 2018 10:21:40 -0800
 Subject: [PATCH 1/1] Add espi support
@@ -16,10 +16,10 @@ Signed-off-by: James Feist <james.feist@linux.intel.com>
 ---
  arch/arm/include/asm/arch-aspeed/regs-scu.h |   2 +
  board/aspeed/ast-g5/Makefile                |   2 +
- board/aspeed/ast-g5/ast-g5-espi.c           | 242 ++++++++++++++++++++
+ board/aspeed/ast-g5/ast-g5-espi.c           | 248 ++++++++++++++++++++
  board/aspeed/ast-g5/ast-g5-intel.c          |  16 ++
  board/aspeed/ast-g5/ast-g5.c                |   3 +
- 5 files changed, 265 insertions(+)
+ 5 files changed, 271 insertions(+)
  create mode 100644 board/aspeed/ast-g5/ast-g5-espi.c
  create mode 100644 board/aspeed/ast-g5/ast-g5-intel.c
 
@@ -47,10 +47,10 @@ index df4e63966e..58e0c648f4 100644
  obj-y += ast-g5-irq.o
 diff --git a/board/aspeed/ast-g5/ast-g5-espi.c b/board/aspeed/ast-g5/ast-g5-espi.c
 new file mode 100644
-index 0000000000..dda7ac7cd5
+index 0000000000..5a3ffe7bef
 --- /dev/null
 +++ b/board/aspeed/ast-g5/ast-g5-espi.c
-@@ -0,0 +1,242 @@
+@@ -0,0 +1,248 @@
 +/*
 + * Copyright 2018 Intel Corporation
 + *
@@ -191,55 +191,60 @@ index 0000000000..dda7ac7cd5
 +static int espi_irq_handler(struct pt_regs *regs)
 +{
 +	uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008);
-+
 +	DBG_ESPI("ISR irq_status : 0x%08X\n", irq_status);
 +
++	if (irq_status & AST_ESPI_VW_SYS_EV1) {
++		uint32_t sys1_status = readl(AST_ESPI_BASE + ESPI12C);
++		uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104);
 +
-+	if (irq_status & AST_ESPI_IEN_HW_RST) {
-+	    uint32_t v = readl(AST_ESPI_BASE + ESPI000);
-+	    writel(v & ~ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
-+	    writel(v | ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
-+	    espi_handshake_ack();
++		DBG_ESPI("sys1_status : 0x%08X\n", sys1_status);
++		if (sys1_status & AST_ESPI_SUS_WARN) {
++			DBG_ESPI("SUS WARN ev: %08X\n", sys1_event);
++			if (sys1_event & AST_ESPI_SUS_WARN) {
++				uint32_t v = readl(AST_ESPI_BASE + ESPI104)
++						 | AST_ESPI_SUS_ACK;
++				writel(v, AST_ESPI_BASE + ESPI104);
++			}
++		}
++		writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status
 +	}
 +
 +	if (irq_status & AST_ESPI_VW_SYS_EVT) {
 +		uint32_t sys_status = readl(AST_ESPI_BASE + ESPI11C);
 +		uint32_t sys_event = readl(AST_ESPI_BASE + ESPI098);
 +
++		if (!(sys_event & AST_ESPI_SL_BT_STATUS)) {
++			DBG_ESPI("Setting espi slave boot done\n");
++			uint32_t v = readl(AST_ESPI_BASE + ESPI098)
++					| AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE;
++			writel(v, AST_ESPI_BASE + ESPI098);
++		 }
++
 +		DBG_ESPI("sys_status : 0x%08X\n", sys_status);
 +		if (sys_status & AST_ESPI_HOST_RST_WARN) {
-+			DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event);
-+			if (sys_event & AST_ESPI_HOST_RST_WARN) {
-+				uint32_t v = readl(AST_ESPI_BASE + ESPI098)
-+					     | AST_ESPI_HOST_RST_ACK;
-+				writel(v, AST_ESPI_BASE + ESPI098);
-+			}
++				DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event);
++				if (sys_event & AST_ESPI_HOST_RST_WARN) {
++						uint32_t v = readl(AST_ESPI_BASE + ESPI098)
++										| AST_ESPI_HOST_RST_ACK;
++						writel(v, AST_ESPI_BASE + ESPI098);
++				}
 +		}
 +		if (sys_status & AST_ESPI_OOB_RST_WARN) {
 +			DBG_ESPI("OOB_RST_WARN ev: %08X\n", sys_event);
 +			if (sys_event & AST_ESPI_OOB_RST_WARN) {
 +				uint32_t v = readl(AST_ESPI_BASE + ESPI098)
-+					     | AST_ESPI_OOB_RST_ACK;
++							| AST_ESPI_OOB_RST_ACK;
 +				writel(v, AST_ESPI_BASE + ESPI098);
 +			}
 +		}
 +		writel(sys_status, AST_ESPI_BASE + ESPI11C); // clear status
 +	}
 +
-+	if (irq_status & AST_ESPI_VW_SYS_EV1) {
-+		uint32_t sys1_status = readl(AST_ESPI_BASE + ESPI12C);
-+		uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104);
-+
-+		DBG_ESPI("sys1_status : 0x%08X\n", sys1_status);
-+		if (sys1_status & AST_ESPI_SUS_WARN) {
-+			DBG_ESPI("SUS WARN ev: %08X\n", sys1_event);
-+			if (sys1_event & AST_ESPI_SUS_WARN) {
-+				uint32_t v = readl(AST_ESPI_BASE + ESPI104)
-+					     | AST_ESPI_SUS_ACK;
-+				writel(v, AST_ESPI_BASE + ESPI104);
-+			}
-+		}
-+		writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status
++	if (irq_status & AST_ESPI_IEN_HW_RST) {
++		uint32_t v = readl(AST_ESPI_BASE + ESPI000);
++		writel(v & ~ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
++		writel(v | ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000);
++		espi_handshake_ack();
 +	}
 +
 +	writel(irq_status, AST_ESPI_BASE + ESPI008); // clear irq_status
@@ -255,7 +260,7 @@ index 0000000000..dda7ac7cd5
 +
 +		/* Block flash access from Host */
 +		v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_FLASH_SW_CHRDY;
-+		v |= AST_ESPI_FLASH_SW_READ | AST_ESPI_OOB_CHRDY;
++		v |= AST_ESPI_FLASH_SW_READ;
 +		writel(v, AST_ESPI_BASE + ESPI000);
 +
 +		/* Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for
@@ -283,8 +288,9 @@ index 0000000000..dda7ac7cd5
 +		       AST_ESPI_BASE
 +			       + ESPI100); // Enable sysev1 ints for susp warn
 +
-+		writel(AST_ESPI_IEN_SYS_EV | AST_ESPI_IEN_HW_RST,
-+		       AST_ESPI_BASE + ESPI00C); // Enable events
++		writel(AST_ESPI_IEN_SYS_EV | AST_ESPI_IEN_HW_RST
++			   | AST_ESPI_VW_SYS_EV1,
++			   AST_ESPI_BASE + ESPI00C); // Enable events
 +
 +		espi_handshake_ack();
 +
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
index e309f6a98..94a658610 100644
--- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch
@@ -1,4 +1,4 @@
-From 899934a036171eb9174e800ba6367b8b8a3e70c4 Mon Sep 17 00:00:00 2001
+From 3f53513c2b16ce2f9a24975cb23b2b58e70ba0f2 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 29 Jan 2020 14:55:44 -0800
 Subject: [PATCH] Override OTP strap settings
@@ -7,33 +7,38 @@ This commit adds settings to override OTP strap.
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- arch/arm/mach-aspeed/ast2600/platform.S | 8 ++++++++
- 1 file changed, 8 insertions(+)
+ arch/arm/mach-aspeed/ast2600/platform.S | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
 
 diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
-index de97cccc78b7..ab8d10b70b9a 100644
+index 80ba06802acd..e7ae9041093c 100644
 --- a/arch/arm/mach-aspeed/ast2600/platform.S
 +++ b/arch/arm/mach-aspeed/ast2600/platform.S
-@@ -40,6 +40,7 @@
- #define AST_SCU_HPLL_PARAM	(AST_SCU_BASE + 0x200)
- #define AST_SCU_HPLL_PARAM_EXT	(AST_SCU_BASE + 0x204)
- #define AST_SCU_HW_STRAP1	(AST_SCU_BASE + 0x500)
-+#define AST_SCU_HW_STRAP2	(AST_SCU_BASE + 0x510)
- #define AST_SCU_CA7_PARITY_CHK	(AST_SCU_BASE + 0x820)
- #define AST_SCU_CA7_PARITY_CLR	(AST_SCU_BASE + 0x824)
- 
-@@ -133,6 +134,13 @@ do_primary_core_setup:
+@@ -147,6 +147,26 @@ do_primary_core_setup:
  	/* unlock system control unit */
  	scu_unlock
  
-+	/* enable eSPI and ACPI */
++	/* disable CA7 CPU boot */
++	ldr	r0, =AST_SCU_HW_STRAP1_CLR
++	movw	r1, #0x0001		@; Disable ARM CA7 CPU boot
++	movt	r1, #0x0000
++	str	r1, [r0]
++
++	/* enable eSPI, debug interface and disable UART5 boot*/
++	ldr	r0, =AST_SCU_HW_STRAP2_CLR
++	movw	r1, #0x0040		@; Select eSPI
++	movt	r1, #0x0000
++	orr	r1, #0x0010		@; Enable debug interface
++	orr	r1, #0x0100		@; Disable UART5 boot
++	str	r1, [r0]
++
++	/* enable ACPI */
 +	ldr	r0, =AST_SCU_HW_STRAP2
 +	ldr	r1, [r0]
-+	bic	r1, #0x40		@; Select eSPI
 +	orr	r1, #0x20		@; Enable ACPI
 +	str	r1, [r0]
 +
- 	/* tune-up CPU clock for AST2600 A0 */
+ 	/* identify AST2600 A0/A1 */
  	ldr	r0, =AST_SCU_REV_ID
  	ldr	r0, [r0]
 -- 
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
index bc5d2f415..04496acf7 100644
--- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
@@ -6,6 +6,7 @@ FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:"
 SRC_URI_append_intel-ast2600 = " \
     file://fw_env.config \
     file://intel.cfg \
+    file://0000-AST2600-Add-the-latest-chip-initialization-code.patch \
     file://0001-Add-ast2600-intel-as-a-new-board.patch \
     file://0021-AST2600-Enable-host-searial-port-clock-configuration.patch \
     file://0003-ast2600-intel-layout-environment-addr.patch \