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author | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-12-08 00:45:20 +0300 |
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committer | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-12-10 01:15:05 +0300 |
commit | 82dbc15a05125a812c140a3c8cff81c366482229 (patch) | |
tree | 9c8f1ad262a2e281f20340cf8646aca6f8596044 /meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-base-aspeed-g6-dtsi-fixups.patch | |
parent | 8d6ae7f2a817751fad151168fa10ce28ee0869d8 (diff) | |
download | openbmc-82dbc15a05125a812c140a3c8cff81c366482229.tar.xz |
Update to internal 0.26
Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-base-aspeed-g6-dtsi-fixups.patch')
-rw-r--r-- | meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-base-aspeed-g6-dtsi-fixups.patch | 212 |
1 files changed, 0 insertions, 212 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-base-aspeed-g6-dtsi-fixups.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-base-aspeed-g6-dtsi-fixups.patch deleted file mode 100644 index d75229a15..000000000 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-base-aspeed-g6-dtsi-fixups.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 5e5758fe5929766a9b4677b86f9343a777526fe8 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery <vernon.mauery@linux.intel.com> -Date: Thu, 12 Sep 2019 15:55:39 +0800 -Subject: [PATCH] arm: dts: base aspeed g6 dtsi fixups - -Additions to the base g6 dtsi file for Aspeed ast2600 systems. -This mostly includes entries for the drivers that are not upstream. - -Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> ---- - arch/arm/boot/dts/aspeed-g6.dtsi | 129 +++++++++++++++++++++++++++++- - include/dt-bindings/clock/ast2600-clock.h | 8 ++ - 2 files changed, 135 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi -index 2af9efa1faa1..54add29d8217 100644 ---- a/arch/arm/boot/dts/aspeed-g6.dtsi -+++ b/arch/arm/boot/dts/aspeed-g6.dtsi -@@ -28,6 +28,12 @@ - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; -+ i3c0 = &i3c0; -+ i3c1 = &i3c1; -+ i3c2 = &i3c2; -+ i3c3 = &i3c3; -+ i3c4 = &i3c4; -+ i3c5 = &i3c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; -@@ -297,11 +303,21 @@ - quality = <100>; - }; - -+ adc: adc@1e6e9000 { -+ compatible = "aspeed,ast2500-adc"; -+ reg = <0x1e6e9000 0x100>; -+ clocks = <&syscon ASPEED_CLK_APB2>; -+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; -+ resets = <&syscon ASPEED_RESET_ADC>; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ - gpio0: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-gpio"; -- reg = <0x1e780000 0x800>; -+ reg = <0x1e780000 0x200>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - gpio-ranges = <&pinctrl 0 0 208>; - ngpios = <208>; -@@ -314,7 +330,7 @@ - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-gpio"; -- reg = <0x1e780800 0x800>; -+ reg = <0x1e780800 0x200>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - gpio-ranges = <&pinctrl 0 208 36>; - ngpios = <36>; -@@ -398,6 +414,13 @@ - ranges = <0x0 0x1e78b000 0x100>; - }; - -+ i3c: bus@1e7a0000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x1e7a0000 0x8000>; -+ }; -+ - lpc: lpc@1e789000 { - compatible = "aspeed,ast2600-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; -@@ -486,6 +509,20 @@ - sio_regs: regs { - compatible = "aspeed,bmc-misc"; - }; -+ -+ lpc_sio: lpc-sio@100 { -+ compatible = "aspeed,ast2500-lpc-sio"; -+ reg = <0x100 0x20>; -+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>; -+ status = "disabled"; -+ }; -+ -+ mbox: mbox@180 { -+ compatible = "aspeed,ast2600-mbox"; -+ reg = <0x180 0x5c>; -+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; -+ #mbox-cells = <1>; -+ }; - }; - }; - -@@ -871,3 +908,91 @@ - status = "disabled"; - }; - }; -+ -+&i3c { -+ i3c0: i3c0@2000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #interrupt-cells = <1>; -+ reg = <0x2000 0x1000>; -+ compatible = "snps,dw-i3c-master-1.00a"; -+ clocks = <&syscon ASPEED_CLK_APB2>; -+ resets = <&syscon ASPEED_RESET_I3C0>; -+ bus-frequency = <100000>; -+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ i3c1: i3c1@3000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #interrupt-cells = <1>; -+ reg = <0x3000 0x1000>; -+ compatible = "snps,dw-i3c-master-1.00a"; -+ clocks = <&syscon ASPEED_CLK_APB2>; -+ resets = <&syscon ASPEED_RESET_I3C1>; -+ bus-frequency = <100000>; -+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ i3c2: i3c2@4000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #interrupt-cells = <1>; -+ reg = <0x4000 0x1000>; -+ compatible = "snps,dw-i3c-master-1.00a"; -+ clocks = <&syscon ASPEED_CLK_APB2>; -+ resets = <&syscon ASPEED_RESET_I3C2>; -+ bus-frequency = <100000>; -+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i3c3_default>; -+ status = "disabled"; -+ }; -+ -+ i3c3: i3c3@5000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #interrupt-cells = <1>; -+ reg = <0x5000 0x1000>; -+ compatible = "snps,dw-i3c-master-1.00a"; -+ clocks = <&syscon ASPEED_CLK_APB2>; -+ resets = <&syscon ASPEED_RESET_I3C3>; -+ bus-frequency = <100000>; -+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i3c4_default>; -+ status = "disabled"; -+ }; -+ -+ i3c4: i3c4@6000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #interrupt-cells = <1>; -+ reg = <0x6000 0x1000>; -+ compatible = "snps,dw-i3c-master-1.00a"; -+ clocks = <&syscon ASPEED_CLK_APB2>; -+ resets = <&syscon ASPEED_RESET_I3C4>; -+ bus-frequency = <100000>; -+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i3c5_default>; -+ status = "disabled"; -+ }; -+ -+ i3c5: i3c5@7000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #interrupt-cells = <1>; -+ reg = <0x7000 0x1000>; -+ compatible = "snps,dw-i3c-master-1.00a"; -+ clocks = <&syscon ASPEED_CLK_APB2>; -+ resets = <&syscon ASPEED_RESET_I3C5>; -+ bus-frequency = <100000>; -+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i3c6_default>; -+ status = "disabled"; -+ }; -+}; -diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h -index 62b9520a00fd..3d90582a813f 100644 ---- a/include/dt-bindings/clock/ast2600-clock.h -+++ b/include/dt-bindings/clock/ast2600-clock.h -@@ -91,6 +91,14 @@ - /* Only list resets here that are not part of a gate */ - #define ASPEED_RESET_ADC 55 - #define ASPEED_RESET_JTAG_MASTER2 54 -+#define ASPEED_RESET_I3C7 47 -+#define ASPEED_RESET_I3C6 46 -+#define ASPEED_RESET_I3C5 45 -+#define ASPEED_RESET_I3C4 44 -+#define ASPEED_RESET_I3C3 43 -+#define ASPEED_RESET_I3C2 42 -+#define ASPEED_RESET_I3C1 41 -+#define ASPEED_RESET_I3C0 40 - #define ASPEED_RESET_I3C_DMA 39 - #define ASPEED_RESET_PWM 37 - #define ASPEED_RESET_PECI 36 --- -2.7.4 - |