Update to internal 0.53

Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

10 files changed, 805 insertions, 76 deletions

diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch
index 31061624c..5a01aaeed 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch
@@ -1,4 +1,4 @@
-From da2fecd5d5b3f69bcc4d07fd1265415bd350e5a6 Mon Sep 17 00:00:00 2001
+From c2019bbf210e0e750478a3e6c0c9bfa557c5bc0f Mon Sep 17 00:00:00 2001
 From: Yuan Li <yuan.li@linux.intel.com>
 Date: Tue, 19 Sep 2017 15:55:39 +0800
 Subject: [PATCH] arm: dts: add DTS for Intel ast2500 platforms
@@ -17,16 +17,16 @@ Signed-off-by: Zhikui Ren <zhikui.ren@intel.com>
 Signed-off-by: jayaprakash Mutyala <mutyalax.jayaprakash@intel.com>
 Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com>
 ---
- arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts | 460 +++++++++++++++++++++++++
- 1 file changed, 460 insertions(+)
+ arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts | 474 +++++++++++++++++++++++++
+ 1 file changed, 474 insertions(+)
  create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
 
 diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
 new file mode 100644
-index 0000000..1fe6240
+index 000000000000..18fa1f804874
 --- /dev/null
 +++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
-@@ -0,0 +1,460 @@
+@@ -0,0 +1,468 @@
 +/dts-v1/;
 +
 +#include "aspeed-g5.dtsi"
@@ -166,6 +166,14 @@ index 0000000..1fe6240
 +			bit-shift = <17>;
 +			read-only;
 +		};
++		chip_id {
++			offset = <0x150>;
++			bit-mask = <0x0fffffff 0xffffffff>;
++			bit-shift = <0>;
++			read-only;
++			reg-width = <64>;
++			hash-data = "d44f9b804976fa23c2e25d62f16154d26520a7e24c5555095fd1b55c027804f1570dcd16189739c640cd7d9a6ce14944a2c4eaf1dc429eed6940e8a83498a474";
++		};
 +	};
 +};
 +
@@ -487,6 +495,6 @@ index 0000000..1fe6240
 +&vhub {
 +	status = "okay";
 +};
---
+-- 
 2.7.4
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
index 885e15e4c..b3e7342c5 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
@@ -1,4 +1,4 @@
-From c8c8503401e8593860b4b78340a50d55a1a780b3 Mon Sep 17 00:00:00 2001
+From 0fca4f924e45f1968f610ad8903f18d638188784 Mon Sep 17 00:00:00 2001
 From: Vernon Mauery <vernon.mauery@linux.intel.com>
 Date: Tue, 19 Sep 2017 15:55:39 +0800
 Subject: [PATCH] arm: dts: add DTS for Intel ast2600 platforms
@@ -12,16 +12,16 @@ Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 Signed-off-by: arun-pm <arun.p.m@linux.intel.com>
 Signed-off-by: Ayushi Smriti <smriti.ayushi@intel.com>
 ---
- arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 498 +++++++++++++++++++++++++
- 1 file changed, 498 insertions(+)
+ arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 516 +++++++++++++++++++++++++
+ 1 file changed, 516 insertions(+)
  create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
 
 diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
 new file mode 100644
-index 000000000000..c51ed3c57f3e
+index 000000000000..6d626338232e
 --- /dev/null
 +++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
-@@ -0,0 +1,498 @@
+@@ -0,0 +1,510 @@
 +// SPDX-License-Identifier: GPL-2.0+
 +/dts-v1/;
 +
@@ -134,6 +134,18 @@ index 000000000000..c51ed3c57f3e
 +&syscon {
 +	uart-clock-high-speed;
 +	status = "okay";
++
++	misc_control {
++		compatible = "aspeed,bmc-misc";
++		chip_id {
++			offset = <0x5b0>;
++			bit-mask = <0xffffffff 0xffffffff>;
++			bit-shift = <0>;
++			read-only;
++			reg-width = <64>;
++			hash-data = "d44f9b804976fa23c2e25d62f16154d26520a7e24c5555095fd1b55c027804f1570dcd16189739c640cd7d9a6ce14944a2c4eaf1dc429eed6940e8a83498a474";
++		};
++	};
 +};
 +
 +#if 0
@@ -186,7 +198,7 @@ index 000000000000..c51ed3c57f3e
 +	/*I0-I7*/	"JTAG_ASD_NTRST_R_N","JTAG_ASD_TDI_R","JTAG_ASD_TCK_R","JTAG_ASD_TMS_R","JTAG_ASD_TDO","FM_BMC_PWRBTN_OUT_R_N","FM_BMC_PWR_BTN_N","",
 +	/*J0-J7*/	"SMB_CHASSENSOR_STBY_LVC3_SCL","SMB_CHASSENSOR_STBY_LVC3_SDA","FM_NODE_ID0","FM_NODE_ID1","","","","",
 +	/*K0-K7*/	"SMB_HSBP_STBY_LVC3_R_SCL","SMB_HSBP_STBY_LVC3_R_SDA","SMB_SMLINK0_STBY_LVC3_R2_SCL","SMB_SMLINK0_STBY_LVC3_R2_SDA","SMB_TEMPSENSOR_STBY_LVC3_R_SCL","SMB_TEMPSENSOR_STBY_LVC3_R_SDA","SMB_PMBUS_SML1_STBY_LVC3_R_SCL","SMB_PMBUS_SML1_STBY_LVC3_R_SDA",
-+	/*L0-L7*/	"SMB_PCIE_STBY_LVC3_R_SCL","SMB_PCIE_STBY_LVC3_R_SDA","SMB_HOST_STBY_BMC_LVC3_R_SCL","SMB_HOST_STBY_BMC_LVC3_R_SDA","PREQ_N","DEBUG_EN_N","V_BMC_GFX_HSYNC_R","V_BMC_GFX_VSYNC_R",
++	/*L0-L7*/	"SMB_PCIE_STBY_LVC3_R_SCL","SMB_PCIE_STBY_LVC3_R_SDA","SMB_HOST_STBY_BMC_LVC3_R_SCL","SMB_HOST_STBY_BMC_LVC3_R_SDA","PREQ_N","TCK_MUX_SEL","V_BMC_GFX_HSYNC_R","V_BMC_GFX_VSYNC_R",
 +	/*M0-M7*/	"SPA_CTS_N","SPA_DCD_N","SPA_DSR_N","PU_SPA_RI_N","SPA_DTR_N","SPA_RTS_N","SPA_SOUT","SPA_SIN",
 +	/*N0-N7*/	"SPB_CTS_N","SPB_DCD_N","SPB_DSR_N","PU_SPB_RI_N","SPB_DTR_N","SPB_RTS_N","SPB_SOUT","SPB_SIN",
 +	/*O0-O7*/	"FAN_BMC_PWM0","FAN_BMC_PWM1","FAN_BMC_PWM2","FAN_BMC_PWM3","FAN_BMC_PWM4","FAN_BMC_PWM5","NMI_BUTTON","SPEAKER_BMC_R",
@@ -517,7 +529,7 @@ index 000000000000..c51ed3c57f3e
 +	status = "okay";
 +};
 +
-+&jtag {
++&jtag1 {
 +	status = "okay";
 +};
 -- 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0020-misc-aspeed-add-lpc-mbox-driver.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0020-misc-aspeed-add-lpc-mbox-driver.patch
index bd468e29d..c5add2dd5 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0020-misc-aspeed-add-lpc-mbox-driver.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0020-misc-aspeed-add-lpc-mbox-driver.patch
@@ -1,4 +1,4 @@
-From 5d411ed0d66d3d00232519ed7d4ab6fac45e7c6e Mon Sep 17 00:00:00 2001
+From 42326dfecd45c52918272cf6b65e6eb5b8499c46 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 10 Jul 2019 16:19:33 -0700
 Subject: [PATCH] misc: aspeed: add lpc mbox driver
@@ -10,13 +10,15 @@ This driver should be rewritten later.
 
 Signed-off-by: Cyril Bur <cyrilbur@gmail.com>"
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
 ---
  arch/arm/boot/dts/aspeed-g4.dtsi     |   9 +
  arch/arm/boot/dts/aspeed-g5.dtsi     |   9 +
+ arch/arm/boot/dts/aspeed-g6.dtsi     |   1 +
  drivers/soc/aspeed/Kconfig           |   7 +
  drivers/soc/aspeed/Makefile          |   1 +
- drivers/soc/aspeed/aspeed-lpc-mbox.c | 376 +++++++++++++++++++++++++++++++++++
- 5 files changed, 402 insertions(+)
+ drivers/soc/aspeed/aspeed-lpc-mbox.c | 377 +++++++++++++++++++++++++++
+ 6 files changed, 404 insertions(+)
  create mode 100644 drivers/soc/aspeed/aspeed-lpc-mbox.c
 
 diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -40,10 +42,10 @@ index e9fd66ab3099..f3edda4ae477 100644
  			};
  
 diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
-index 20b2eb8052b7..bd6d1461e4bd 100644
+index b4ae3827ed1d..b69110b9eab9 100644
 --- a/arch/arm/boot/dts/aspeed-g5.dtsi
 +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
-@@ -502,6 +502,15 @@
+@@ -522,6 +522,15 @@
  					sio_regs: regs {
  						compatible = "aspeed,bmc-misc";
  					};
@@ -59,8 +61,20 @@ index 20b2eb8052b7..bd6d1461e4bd 100644
  				};
  			};
  
+diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
+index 825e64ce317a..183869eaf79a 100644
+--- a/arch/arm/boot/dts/aspeed-g6.dtsi
++++ b/arch/arm/boot/dts/aspeed-g6.dtsi
+@@ -594,6 +594,7 @@
+ 						reg = <0x180 0x5c>;
+ 						interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ 						#mbox-cells = <1>;
++						clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ 					};
+ 				};
+ 			};
 diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
-index 78dd74c49ddb..a4be8e566bc7 100644
+index a4b3cac87ce2..464a55c7eb39 100644
 --- a/drivers/soc/aspeed/Kconfig
 +++ b/drivers/soc/aspeed/Kconfig
 @@ -21,6 +21,13 @@ config ASPEED_LPC_CTRL
@@ -78,22 +92,23 @@ index 78dd74c49ddb..a4be8e566bc7 100644
  	tristate "Aspeed ast2500 HOST LPC snoop support"
  	depends on SOC_ASPEED && REGMAP && MFD_SYSCON
 diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
-index e631b23d519b..f3ff29b874ed 100644
+index 217d876fec25..26924c111af3 100644
 --- a/drivers/soc/aspeed/Makefile
 +++ b/drivers/soc/aspeed/Makefile
-@@ -1,5 +1,6 @@
+@@ -1,6 +1,7 @@
  # SPDX-License-Identifier: GPL-2.0-only
  obj-$(CONFIG_ASPEED_BMC_MISC)	+= aspeed-bmc-misc.o
  obj-$(CONFIG_ASPEED_LPC_CTRL)	+= aspeed-lpc-ctrl.o
 +obj-$(CONFIG_ASPEED_LPC_MBOX)	+= aspeed-lpc-mbox.o
  obj-$(CONFIG_ASPEED_LPC_SNOOP)	+= aspeed-lpc-snoop.o
  obj-$(CONFIG_ASPEED_P2A_CTRL)	+= aspeed-p2a-ctrl.o
+ obj-$(CONFIG_ASPEED_XDMA)	+= aspeed-xdma.o
 diff --git a/drivers/soc/aspeed/aspeed-lpc-mbox.c b/drivers/soc/aspeed/aspeed-lpc-mbox.c
 new file mode 100644
-index 000000000000..795107206022
+index 000000000000..583feecc4f18
 --- /dev/null
 +++ b/drivers/soc/aspeed/aspeed-lpc-mbox.c
-@@ -0,0 +1,376 @@
+@@ -0,0 +1,377 @@
 +// SPDX-License-Identifier: GPL-2.0-or-later
 +// Copyright 2017 IBM Corporation
 +// TODO: Rewrite this driver
@@ -452,6 +467,7 @@ index 000000000000..795107206022
 +static const struct of_device_id aspeed_mbox_match[] = {
 +	{ .compatible = "aspeed,ast2400-mbox" },
 +	{ .compatible = "aspeed,ast2500-mbox" },
++	{ .compatible = "aspeed,ast2600-mbox" },
 +	{ },
 +};
 +MODULE_DEVICE_TABLE(of, aspeed_mbox_match);
@@ -471,5 +487,5 @@ index 000000000000..795107206022
 +MODULE_AUTHOR("Cyril Bur <cyrilbur@gmail.com>");
 +MODULE_DESCRIPTION("Aspeed mailbox device driver");
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0051-Add-AST2500-JTAG-device.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0051-Add-AST2500-JTAG-device.patch
index 4230c077b..db94b13fd 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0051-Add-AST2500-JTAG-device.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0051-Add-AST2500-JTAG-device.patch
@@ -1,4 +1,4 @@
-From 1bf4e5a8cd7ca069092bfe7ac3fd3d1879b7a87d Mon Sep 17 00:00:00 2001
+From 79d407327558f27a7df9d04b1d66cbe63129b622 Mon Sep 17 00:00:00 2001
 From: "Hunt, Bryan" <bryan.hunt@intel.com>
 Date: Mon, 6 May 2019 10:02:14 -0700
 Subject: [PATCH] Add AST2500 JTAG device
@@ -7,15 +7,15 @@ Adding aspeed jtag device
 
 Signed-off-by: Hunt, Bryan <bryan.hunt@intel.com>
 ---
- arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++++++++
- arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++++++++
- 2 files changed, 18 insertions(+)
+ arch/arm/boot/dts/aspeed-g5.dtsi |  9 +++++++++
+ arch/arm/boot/dts/aspeed-g6.dtsi | 20 ++++++++++++++++++++
+ 2 files changed, 29 insertions(+)
 
 diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
-index 751a8f0316d6..eb1f9c9d9cca 100644
+index f5c25dab5337..5999cd5e0f2e 100644
 --- a/arch/arm/boot/dts/aspeed-g5.dtsi
 +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
-@@ -418,6 +418,15 @@
+@@ -438,6 +438,15 @@
  				pinctrl-0 = <&pinctrl_espi_default>;
  			};
  
@@ -32,14 +32,14 @@ index 751a8f0316d6..eb1f9c9d9cca 100644
  				compatible = "aspeed,ast2500-lpc", "simple-mfd";
  				reg = <0x1e789000 0x1000>;
 diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
-index bc2ce43827fc..31903b08e731 100644
+index 09f50afea11b..4d8b561fe582 100644
 --- a/arch/arm/boot/dts/aspeed-g6.dtsi
 +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
-@@ -333,6 +333,15 @@
- 				quality = <100>;
+@@ -367,6 +367,26 @@
+ 				status = "disabled";
  			};
  
-+			jtag: jtag@1e6e4000 {
++			jtag0: jtag@1e6e4000 {
 +				compatible = "aspeed,ast2600-jtag";
 +				reg = <0x1e6e4000 0x40>;
 +				clocks = <&syscon ASPEED_CLK_APB1>;
@@ -48,6 +48,17 @@ index bc2ce43827fc..31903b08e731 100644
 +				status = "disabled";
 +			};
 +
++			jtag1: jtag@1e6e4100 {
++				compatible = "aspeed,ast2600-jtag";
++				reg = <0x1e6e4100 0x40>;
++				clocks = <&syscon ASPEED_CLK_APB1>;
++				resets = <&syscon ASPEED_RESET_JTAG_MASTER2>;
++				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
++				pinctrl-names = "default";
++				pinctrl-0 = <&pinctrl_jtagm_default>;
++				status = "disabled";
++			};
++
  			adc: adc@1e6e9000 {
  				compatible = "aspeed,ast2500-adc";
  				reg = <0x1e6e9000 0x100>;
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0053-Add-Aspeed-SoC-24xx-and-25xx-families-JTAG.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0053-Add-Aspeed-SoC-24xx-and-25xx-families-JTAG.patch
index 69c993d86..b70629f18 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0053-Add-Aspeed-SoC-24xx-and-25xx-families-JTAG.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0053-Add-Aspeed-SoC-24xx-and-25xx-families-JTAG.patch
@@ -1,9 +1,9 @@
-From 3b7175753cafcee67cfc13eefc30438a518ad348 Mon Sep 17 00:00:00 2001
+From e01c562db28797e3b6be9030f1f52507115c6765 Mon Sep 17 00:00:00 2001
 From: "Corona, Ernesto" <ernesto.corona@intel.com>
-Date: Mon, 3 Jun 2019 08:22:09 -0800
+Date: Mon, 6 Apr 2020 09:48:32 -0700
 Subject: [PATCH] Add Aspeed SoC 24xx and 25xx families JTAG
 
-Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.
+Driver adds support of Aspeed 2400-2600 series SOC JTAG master controller.
 
 Driver implements the following jtag ops:
 - freq_get;
@@ -22,6 +22,8 @@ Aspeed 2520 SoC for programming CPLD devices.
 It has also been tested on Intel system using Aspeed 25xx SoC
 for JTAG communication.
 
+Tested on Intel system using Aspeed 26xx SoC for JTAG communication.
+
 Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
 Signed-off-by: Jiri Pirko <jiri@mellanox.com>
 Signed-off-by: Corona, Ernesto <ernesto.corona@intel.com>
@@ -33,6 +35,10 @@ Cc: Andrew Jeffery <andrew@aj.id.au>
 Cc: Steven A Filary <steven.a.filary@intel.com>
 Cc: Bryan Hunt <bryan.hunt@intel.com>
 ---
+v29->v30
+Comments pointed by Steven Filary <steven.a.filary@intel.com>
+- Add Suport for 26xx series
+
 v28->v29
 Comments pointed by Steven Filary <steven.a.filary@intel.com>
 - Expand bitbang function to accept multiples bitbang operations within a
@@ -199,12 +205,12 @@ Comments pointed by kbuild test robot <lkp@intel.com>
 ---
  drivers/jtag/Kconfig       |   14 +
  drivers/jtag/Makefile      |    1 +
- drivers/jtag/jtag-aspeed.c | 1051 ++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 1066 insertions(+)
+ drivers/jtag/jtag-aspeed.c | 1217 ++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 1232 insertions(+)
  create mode 100644 drivers/jtag/jtag-aspeed.c
 
 diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
-index 47771fcd3c5b..0cc163f9ad44 100644
+index 47771fc..0cc163f 100644
 --- a/drivers/jtag/Kconfig
 +++ b/drivers/jtag/Kconfig
 @@ -15,3 +15,17 @@ menuconfig JTAG
@@ -226,7 +232,7 @@ index 47771fcd3c5b..0cc163f9ad44 100644
 +	  To compile this driver as a module, choose M here: the module will
 +	  be called jtag-aspeed.
 diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
-index af374939a9e6..04a855e2df28 100644
+index af37493..04a855e 100644
 --- a/drivers/jtag/Makefile
 +++ b/drivers/jtag/Makefile
 @@ -1 +1,2 @@
@@ -234,10 +240,10 @@ index af374939a9e6..04a855e2df28 100644
 +obj-$(CONFIG_JTAG_ASPEED)	+= jtag-aspeed.o
 diff --git a/drivers/jtag/jtag-aspeed.c b/drivers/jtag/jtag-aspeed.c
 new file mode 100644
-index 000000000000..0c9da1b8986c
+index 0000000..1e6ace6
 --- /dev/null
 +++ b/drivers/jtag/jtag-aspeed.c
-@@ -0,0 +1,1051 @@
+@@ -0,0 +1,1217 @@
 +// SPDX-License-Identifier: GPL-2.0
 +// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
 +// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
@@ -270,7 +276,7 @@ index 000000000000..0c9da1b8986c
 +#define ASPEED_JTAG_DATA_MSB		0x01
 +#define ASPEED_JTAG_DATA_CHUNK_SIZE	0x20
 +
-+/* ASPEED_JTAG_CTRL: Engine Control */
++/* ASPEED_JTAG_CTRL: Engine Control 24xx and 25xx series*/
 +#define ASPEED_JTAG_CTL_ENG_EN		BIT(31)
 +#define ASPEED_JTAG_CTL_ENG_OUT_EN	BIT(30)
 +#define ASPEED_JTAG_CTL_FORCE_TMS	BIT(29)
@@ -283,6 +289,15 @@ index 000000000000..0c9da1b8986c
 +#define ASPEED_JTAG_CTL_LASPEED_DATA	BIT(1)
 +#define ASPEED_JTAG_CTL_DATA_EN		BIT(0)
 +
++/* ASPEED_JTAG_CTRL: Engine Control 26xx series*/
++#define ASPEED_JTAG_CTL_26XX_RESET_FIFO	BIT(21)
++#define ASPEED_JTAG_CTL_26XX_FIFO_MODE_CTRL BIT(20)
++#define ASPEED_JTAG_CTL_26XX_TRANS_LEN(x) ((x) << 8)
++#define ASPEED_JTAG_CTL_26XX_MSB_FIRST	BIT(6)
++#define ASPEED_JTAG_CTL_26XX_TERM_TRANS	BIT(5)
++#define ASPEED_JTAG_CTL_26XX_LASPEED_TRANS BIT(4)
++#define ASPEED_JTAG_CTL_26XX_INST_EN	BIT(1)
++
 +/* ASPEED_JTAG_ISR : Interrupt status and enable */
 +#define ASPEED_JTAG_ISR_INST_PAUSE	BIT(19)
 +#define ASPEED_JTAG_ISR_INST_COMPLETE	BIT(18)
@@ -318,6 +333,11 @@ index 000000000000..0c9da1b8986c
 +	 ASPEED_JTAG_CTL_ENG_OUT_EN | \
 +	 ASPEED_JTAG_CTL_DATA_LEN(len))
 +
++#define ASPEED_JTAG_TRANS_LEN(len) \
++	(ASPEED_JTAG_CTL_ENG_EN | \
++	 ASPEED_JTAG_CTL_ENG_OUT_EN | \
++	 ASPEED_JTAG_CTL_26XX_TRANS_LEN(len))
++
 +#define ASPEED_JTAG_SW_TDIO (ASPEED_JTAG_SW_MODE_EN | ASPEED_JTAG_SW_MODE_TDIO)
 +
 +#define ASPEED_JTAG_GET_TDI(direction, byte) \
@@ -327,8 +347,55 @@ index 000000000000..0c9da1b8986c
 +#define ASPEED_JTAG_RESET_CNTR		10
 +#define WAIT_ITERATIONS		75
 +
++/* ASPEED JTAG HW MODE 2 (Only supported in AST26xx series) */
++#define ASPEED_JTAG_SHDATA0		0x20
++#define ASPEED_JTAG_SHDATA1		0x24
++#define ASPEED_JTAG_PADCTRL0		0x28
++#define ASPEED_JTAG_PADCTRL1		0x2C
++#define ASPEED_JTAG_SHCTRL		0x30
++#define ASPEED_JTAG_GBLCTRL		0x34
++#define ASPEED_JTAG_INTCTRL		0x38
++#define ASPEED_JTAG_STAT		0x3C
++
++/* ASPEED_JTAG_PADCTRLx : Padding control 0 and 1 */
++#define ASPEED_JTAG_PADCTRL_PAD_DATA	BIT(24)
++#define ASPEED_JTAG_PADCTRL_POSTPAD(x)	(((x) & GENMASK(8, 0)) << 12)
++#define ASPEED_JTAG_PADCTRL_PREPAD(x)	(((x) & GENMASK(8, 0)) << 0)
++
++/* ASPEED_JTAG_SHCTRL: Shift Control */
++#define ASPEED_JTAG_SHCTRL_FRUN_TCK_EN	BIT(31)
++#define ASPEED_JTAG_SHCTRL_STSHIFT_EN	BIT(30)
++#define ASPEED_JTAG_SHCTRL_TMS(x)	(((x) & GENMASK(13, 0)) << 16)
++#define ASPEED_JTAG_SHCTRL_POST_TMS(x)	(((x) & GENMASK(3, 0)) << 13)
++#define ASPEED_JTAG_SHCTRL_PRE_TMS(x)	(((x) & GENMASK(3, 0)) << 10)
++#define ASPEED_JTAG_SHCTRL_PAD_SEL0	(0)
++#define ASPEED_JTAG_SHCTRL_PAD_SEL1	BIT(9)
++#define ASPEED_JTAG_SHCTRL_END_SHIFT	BIT(8)
++#define ASPEED_JTAG_SHCTRL_START_SHIFT	BIT(7)
++#define ASPEED_JTAG_SHCTRL_LWRDT_SHIFT(x) ((x) & GENMASK(6, 0))
++
++/* ASPEED_JTAG_GBLCTRL : Global Control */
++#define ASPEED_JTAG_GBLCTRL_ENG_MODE_EN	BIT(31)
++#define ASPEED_JTAG_GBLCTRL_ENG_OUT_EN	BIT(30)
++#define ASPEED_JTAG_GBLCTRL_FORCE_TMS	BIT(29)
++#define ASPEED_JTAG_GBLCTRL_SHIFT_COMPLETE  BIT(28)
++#define ASPEED_JTAG_GBLCTRL_RESET_FIFO	BIT(25)
++#define ASPEED_JTAG_GBLCTRL_FIFO_MODE	BIT(24)
++#define ASPEED_JTAG_GBLCTRL_UPDT_SHIFT(x)	(((x) & GENMASK(3, 0)) << 20)
++#define ASPEED_JTAG_GBLCTRL_STSHIFT(x)	(((x) & GENMASK(0, 0)) << 16)
++#define ASPEED_JTAG_GBLCTRL_TRST	BIT(15)
++#define ASPEED_JTAG_CLK_DIVISOR_MASK	GENMASK(11, 0)
++#define ASPEED_JTAG_CLK_GET_DIV(x)	((x) & ASPEED_JTAG_CLK_DIVISOR_MASK)
++
++/* ASPEED_JTAG_INTCTRL: Interrupt Control */
++#define ASPEED_JTAG_INTCTRL_SHCPL_IRQ_EN BIT(16)
++#define ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT BIT(0)
++
++/* ASPEED_JTAG_STAT: JTAG HW mode 2 status */
++#define ASPEED_JTAG_STAT_ENG_IDLE	BIT(0)
++
 +/*#define USE_INTERRUPTS*/
-+/*#define DEBUG_JTAG*/
++#define DEBUG_JTAG
 +
 +static const char * const regnames[] = {
 +	[ASPEED_JTAG_DATA] = "ASPEED_JTAG_DATA",
@@ -338,6 +405,14 @@ index 000000000000..0c9da1b8986c
 +	[ASPEED_JTAG_SW]   = "ASPEED_JTAG_SW",
 +	[ASPEED_JTAG_TCK]  = "ASPEED_JTAG_TCK",
 +	[ASPEED_JTAG_EC]   = "ASPEED_JTAG_EC",
++	[ASPEED_JTAG_SHDATA0]  = "ASPEED_JTAG_SHDATA0",
++	[ASPEED_JTAG_SHDATA1]  = "ASPEED_JTAG_SHDATA1",
++	[ASPEED_JTAG_PADCTRL0] = "ASPEED_JTAG_PADCTRL0",
++	[ASPEED_JTAG_PADCTRL1] = "ASPEED_JTAG_PADCTRL1",
++	[ASPEED_JTAG_SHCTRL]   = "ASPEED_JTAG_SHCTRL",
++	[ASPEED_JTAG_GBLCTRL]  = "ASPEED_JTAG_GBLCTRL",
++	[ASPEED_JTAG_INTCTRL]  = "ASPEED_JTAG_INTCTRL",
++	[ASPEED_JTAG_STAT]     = "ASPEED_JTAG_STAT",
 +};
 +
 +#define ASPEED_JTAG_NAME		"jtag-aspeed"
@@ -352,6 +427,24 @@ index 000000000000..0c9da1b8986c
 +	u32				flag;
 +	wait_queue_head_t		jtag_wq;
 +	u32				mode;
++	struct jtag_low_level_functions *llops;
++};
++
++/* Multi generation support is enabled by fops and low level assped function
++ * mapping using asped_jtag_functions struct as config mechanism.
++ */
++
++struct jtag_low_level_functions {
++	void (*output_disable)(struct aspeed_jtag *aspeed_jtag);
++	int (*xfer_push_data)(struct aspeed_jtag *aspeed_jtag,
++			      enum jtag_xfer_type type, u32 bits_len);
++	int (*xfer_push_data_last)(struct aspeed_jtag *aspeed_jtag,
++				   enum jtag_xfer_type type, u32 bits_len);
++};
++
++struct aspeed_jtag_functions {
++	struct jtag_ops *aspeed_jtag_ops;
++	struct jtag_low_level_functions *aspeed_jtag_llops;
 +};
 +
 +/*
@@ -906,6 +999,26 @@ index 000000000000..0c9da1b8986c
 +	}
 +}
 +
++static int aspeed_jtag_xfer_push_data_26xx(struct aspeed_jtag *aspeed_jtag,
++				      enum jtag_xfer_type type, u32 bits_len)
++{
++	int res = 0;
++
++	aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_TRANS_LEN(bits_len),
++			  ASPEED_JTAG_CTRL);
++	if (type == JTAG_SIR_XFER) {
++		aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_TRANS_LEN(bits_len) |
++				  ASPEED_JTAG_CTL_26XX_INST_EN,
++				  ASPEED_JTAG_CTRL);
++		res = aspeed_jtag_wait_instruction_pause(aspeed_jtag);
++	} else {
++		aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_TRANS_LEN(bits_len) |
++				  ASPEED_JTAG_CTL_DATA_EN, ASPEED_JTAG_CTRL);
++		res = aspeed_jtag_wait_data_pause_complete(aspeed_jtag);
++	}
++	return res;
++}
++
 +static int aspeed_jtag_xfer_push_data(struct aspeed_jtag *aspeed_jtag,
 +				      enum jtag_xfer_type type, u32 bits_len)
 +{
@@ -927,6 +1040,32 @@ index 000000000000..0c9da1b8986c
 +	return res;
 +}
 +
++static int aspeed_jtag_xfer_push_data_last_26xx(struct aspeed_jtag *aspeed_jtag,
++					   enum jtag_xfer_type type,
++					   u32 shift_bits)
++{
++	int res = 0;
++
++	aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_TRANS_LEN(shift_bits) |
++			  ASPEED_JTAG_CTL_26XX_LASPEED_TRANS, ASPEED_JTAG_CTRL);
++	if (type == JTAG_SIR_XFER) {
++		aspeed_jtag_write(aspeed_jtag,
++				  ASPEED_JTAG_TRANS_LEN(shift_bits) |
++				  ASPEED_JTAG_CTL_26XX_LASPEED_TRANS |
++				  ASPEED_JTAG_CTL_26XX_INST_EN,
++				  ASPEED_JTAG_CTRL);
++		res = aspeed_jtag_wait_instruction_complete(aspeed_jtag);
++	} else {
++		aspeed_jtag_write(aspeed_jtag,
++				  ASPEED_JTAG_TRANS_LEN(shift_bits) |
++				  ASPEED_JTAG_CTL_26XX_LASPEED_TRANS |
++				  ASPEED_JTAG_CTL_DATA_EN,
++				  ASPEED_JTAG_CTRL);
++		res = aspeed_jtag_wait_data_complete(aspeed_jtag);
++	}
++	return res;
++}
++
 +static int aspeed_jtag_xfer_push_data_last(struct aspeed_jtag *aspeed_jtag,
 +					   enum jtag_xfer_type type,
 +					   u32 shift_bits)
@@ -1002,8 +1141,8 @@ index 000000000000..0c9da1b8986c
 +			 * Transmit bytes that were not equals to column length
 +			 * and after the transfer go to Pause IR/DR.
 +			 */
-+			if (aspeed_jtag_xfer_push_data(aspeed_jtag, xfer->type,
-+						       shift_bits) != 0) {
++			if (aspeed_jtag->llops->xfer_push_data(aspeed_jtag,
++						xfer->type, shift_bits) != 0) {
 +				return -EFAULT;
 +			}
 +		} else {
@@ -1023,7 +1162,7 @@ index 000000000000..0c9da1b8986c
 +					ASPEED_JTAG_DATA_CHUNK_SIZE,
 +					remain_xfer);
 +#endif
-+				if (aspeed_jtag_xfer_push_data_last(
++				if (aspeed_jtag->llops->xfer_push_data_last(
 +							aspeed_jtag,
 +							xfer->type,
 +							shift_bits) != 0) {
@@ -1042,7 +1181,8 @@ index 000000000000..0c9da1b8986c
 +					ASPEED_JTAG_DATA_CHUNK_SIZE,
 +					remain_xfer);
 +#endif
-+				if (aspeed_jtag_xfer_push_data(aspeed_jtag,
++				if (aspeed_jtag->llops->xfer_push_data(
++							       aspeed_jtag,
 +							       xfer->type,
 +							       shift_bits)
 +							       != 0) {
@@ -1228,13 +1368,50 @@ index 000000000000..0c9da1b8986c
 +	.disable = aspeed_jtag_disable
 +};
 +
++static const struct jtag_low_level_functions ast25xx_llops = {
++	.output_disable = aspeed_jtag_output_disable,
++	.xfer_push_data = aspeed_jtag_xfer_push_data,
++	.xfer_push_data_last = aspeed_jtag_xfer_push_data_last
++};
++
++static struct aspeed_jtag_functions ast25xx_functions = {
++	.aspeed_jtag_ops = &aspeed_jtag_ops,
++	.aspeed_jtag_llops = &ast25xx_llops
++};
++
++static const struct jtag_low_level_functions ast26xx_llops = {
++	.output_disable = aspeed_jtag_output_disable,
++	.xfer_push_data = aspeed_jtag_xfer_push_data_26xx,
++	.xfer_push_data_last = aspeed_jtag_xfer_push_data_last_26xx
++};
++
++static struct aspeed_jtag_functions ast26xx_functions = {
++	.aspeed_jtag_ops = &aspeed_jtag_ops,
++	.aspeed_jtag_llops = &ast26xx_llops
++};
++
++static const struct of_device_id aspeed_jtag_of_match[] = {
++	{ .compatible = "aspeed,ast2400-jtag", .data = &ast25xx_functions },
++	{ .compatible = "aspeed,ast2500-jtag", .data = &ast25xx_functions },
++	{ .compatible = "aspeed,ast2600-jtag", .data = &ast26xx_functions },
++	{}
++};
++
 +static int aspeed_jtag_probe(struct platform_device *pdev)
 +{
 +	struct aspeed_jtag *aspeed_jtag;
 +	struct jtag *jtag;
++	const struct of_device_id *match;
++	struct aspeed_jtag_functions *jtag_functions;
 +	int err;
 +
-+	jtag = jtag_alloc(&pdev->dev, sizeof(*aspeed_jtag), &aspeed_jtag_ops);
++	match = of_match_node(aspeed_jtag_of_match, pdev->dev.of_node);
++	if (!match)
++		return -ENODEV;
++	jtag_functions = match->data;
++
++	jtag = jtag_alloc(&pdev->dev, sizeof(*aspeed_jtag),
++			  jtag_functions->aspeed_jtag_ops);
 +	if (!jtag)
 +		return -ENOMEM;
 +
@@ -1242,6 +1419,8 @@ index 000000000000..0c9da1b8986c
 +	aspeed_jtag = jtag_priv(jtag);
 +	aspeed_jtag->dev = &pdev->dev;
 +
++	aspeed_jtag->llops = jtag_functions->aspeed_jtag_llops;
++
 +	/* Initialize device*/
 +	err = aspeed_jtag_init(pdev, aspeed_jtag);
 +	if (err)
@@ -1269,13 +1448,6 @@ index 000000000000..0c9da1b8986c
 +	return 0;
 +}
 +
-+static const struct of_device_id aspeed_jtag_of_match[] = {
-+	{ .compatible = "aspeed,ast2400-jtag", },
-+	{ .compatible = "aspeed,ast2500-jtag", },
-+	{ .compatible = "aspeed,ast2600-jtag", },
-+	{}
-+};
-+
 +static struct platform_driver aspeed_jtag_driver = {
 +	.probe = aspeed_jtag_probe,
 +	.remove = aspeed_jtag_remove,
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0100-Mailbox-Enabling-interrupt-based-mailbox.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0100-Mailbox-Enabling-interrupt-based-mailbox.patch
index e67adb729..cb06f9def 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0100-Mailbox-Enabling-interrupt-based-mailbox.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0100-Mailbox-Enabling-interrupt-based-mailbox.patch
@@ -1,4 +1,4 @@
-From 7094f4d8efea8e059c965ba70c73d5226af392cb Mon Sep 17 00:00:00 2001
+From d5bc758cee51d92c48f2835ca2b4ebb146f0f0b4 Mon Sep 17 00:00:00 2001
 From: "Arun P. Mohanan" <arun.p.m@linux.intel.com>
 Date: Wed, 11 Mar 2020 17:23:49 +0530
 Subject: [PATCH] [Mailbox] Enabling interrupt based mailbox
@@ -7,11 +7,11 @@ Modifying the mailbox driver to use FIFO queue while using interrupt.
 
 Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
 ---
- drivers/soc/aspeed/aspeed-lpc-mbox.c | 101 ++++++++++++++++++---------
- 1 file changed, 68 insertions(+), 33 deletions(-)
+ drivers/soc/aspeed/aspeed-lpc-mbox.c | 102 ++++++++++++++++++---------
+ 1 file changed, 69 insertions(+), 33 deletions(-)
 
 diff --git a/drivers/soc/aspeed/aspeed-lpc-mbox.c b/drivers/soc/aspeed/aspeed-lpc-mbox.c
-index 795107206022..99f38a4e4550 100644
+index 795107206022..1ca68bb3534c 100644
 --- a/drivers/soc/aspeed/aspeed-lpc-mbox.c
 +++ b/drivers/soc/aspeed/aspeed-lpc-mbox.c
 @@ -12,10 +12,11 @@
@@ -95,7 +95,7 @@ index 795107206022..99f38a4e4550 100644
  	int i;
  
  	if (!access_ok(buf, count))
-@@ -111,15 +134,29 @@ static ssize_t aspeed_mbox_read(struct file *file, char __user *buf,
+@@ -111,17 +134,32 @@ static ssize_t aspeed_mbox_read(struct file *file, char __user *buf,
  		return -EINVAL;
  
  #if MBX_USE_INTERRUPT
@@ -104,10 +104,10 @@ index 795107206022..99f38a4e4550 100644
 -				ASPEED_MBOX_CTRL_RECV))
 +	/*
 +	 * Restrict count as per the number of mailbox registers
-+	 * if interrupt is enabled.
++	 * to use kfifo.
 +	 */
 +	if (count != ASPEED_MBOX_NUM_REGS)
-+		return -EINVAL;
++		goto reg_read;
 +
 +	if (kfifo_is_empty(&mbox->fifo)) {
 +		if (file->f_flags & O_NONBLOCK){
@@ -131,8 +131,11 @@ index 795107206022..99f38a4e4550 100644
 +
  #endif
  
++reg_read:
  	mutex_lock(&mbox->mutex);
-@@ -134,11 +171,6 @@ static ssize_t aspeed_mbox_read(struct file *file, char __user *buf,
+ 
+ 	for (i = *ppos; count > 0 && i < ASPEED_MBOX_NUM_REGS; i++) {
+@@ -134,11 +172,6 @@ static ssize_t aspeed_mbox_read(struct file *file, char __user *buf,
  		p++;
  		count--;
  	}
@@ -144,7 +147,7 @@ index 795107206022..99f38a4e4550 100644
  	ret = p - buf;
  
  out_unlock:
-@@ -186,16 +218,9 @@ static ssize_t aspeed_mbox_write(struct file *file, const char __user *buf,
+@@ -186,16 +219,9 @@ static ssize_t aspeed_mbox_write(struct file *file, const char __user *buf,
  static unsigned int aspeed_mbox_poll(struct file *file, poll_table *wait)
  {
  	struct aspeed_mbox *mbox = file_mbox(file);
@@ -162,7 +165,7 @@ index 795107206022..99f38a4e4550 100644
  }
  
  static int aspeed_mbox_release(struct inode *inode, struct file *file)
-@@ -220,19 +245,23 @@ static irqreturn_t aspeed_mbox_irq(int irq, void *arg)
+@@ -220,19 +246,23 @@ static irqreturn_t aspeed_mbox_irq(int irq, void *arg)
  #if MBX_USE_INTERRUPT
  	int i;
  
@@ -193,7 +196,7 @@ index 795107206022..99f38a4e4550 100644
  #endif
  
  	/* Clear interrupt status */
-@@ -249,7 +278,6 @@ static int aspeed_mbox_config_irq(struct aspeed_mbox *mbox,
+@@ -249,7 +279,6 @@ static int aspeed_mbox_config_irq(struct aspeed_mbox *mbox,
  {
  	struct device *dev = &pdev->dev;
  	int rc;
@@ -201,7 +204,7 @@ index 795107206022..99f38a4e4550 100644
  	mbox->irq = platform_get_irq(pdev, 0);
  	if (!mbox->irq)
  		return -ENODEV;
-@@ -300,6 +328,7 @@ static int aspeed_mbox_probe(struct platform_device *pdev)
+@@ -300,6 +329,7 @@ static int aspeed_mbox_probe(struct platform_device *pdev)
  		return -ENODEV;
  	}
  
@@ -209,7 +212,7 @@ index 795107206022..99f38a4e4550 100644
  	mutex_init(&mbox->mutex);
  	init_waitqueue_head(&mbox->queue);
  
-@@ -316,6 +345,11 @@ static int aspeed_mbox_probe(struct platform_device *pdev)
+@@ -316,6 +346,11 @@ static int aspeed_mbox_probe(struct platform_device *pdev)
  		return rc;
  	}
  
@@ -221,7 +224,7 @@ index 795107206022..99f38a4e4550 100644
  	mbox->miscdev.minor = MISC_DYNAMIC_MINOR;
  	mbox->miscdev.name = DEVICE_NAME;
  	mbox->miscdev.fops = &aspeed_mbox_fops;
-@@ -349,6 +383,7 @@ static int aspeed_mbox_remove(struct platform_device *pdev)
+@@ -349,6 +384,7 @@ static int aspeed_mbox_remove(struct platform_device *pdev)
  
  	misc_deregister(&mbox->miscdev);
  	clk_disable_unprepare(mbox->clk);
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0101-Add-poll-fops-in-eSPI-driver.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0101-Add-poll-fops-in-eSPI-driver.patch
index 9c9704eff..b4118e169 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0101-Add-poll-fops-in-eSPI-driver.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0101-Add-poll-fops-in-eSPI-driver.patch
@@ -1,4 +1,4 @@
-From 56ea1fc793c97232c12ddc3b4936081fe14c962f Mon Sep 17 00:00:00 2001
+From 9479d8f12efc845faca4bb1aef9b6e63799a7e5c Mon Sep 17 00:00:00 2001
 From: "Arun P. Mohanan" <arun.p.m@linux.intel.com>
 Date: Wed, 18 Mar 2020 08:34:43 +0530
 Subject: [PATCH] Add poll fops in eSPI driver
@@ -7,11 +7,11 @@ Modify eSPI driver to support poll fops.
 
 Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
 ---
- drivers/misc/aspeed-espi-slave.c | 83 +++++++++++++++++++++++---------
- 1 file changed, 59 insertions(+), 24 deletions(-)
+ drivers/misc/aspeed-espi-slave.c | 85 +++++++++++++++++++++++---------
+ 1 file changed, 61 insertions(+), 24 deletions(-)
 
 diff --git a/drivers/misc/aspeed-espi-slave.c b/drivers/misc/aspeed-espi-slave.c
-index 87bc81948694..f4a0d7528414 100644
+index 87bc81948694..cb8ed585c69f 100644
 --- a/drivers/misc/aspeed-espi-slave.c
 +++ b/drivers/misc/aspeed-espi-slave.c
 @@ -9,6 +9,7 @@
@@ -41,7 +41,16 @@ index 87bc81948694..f4a0d7528414 100644
  		wake_up_interruptible(&priv->pltrstn_waitq);
  		dev_dbg(priv->dev, "SYSEVT_PLTRSTN: %c\n", priv->pltrstn);
  	}
-@@ -284,41 +289,71 @@ static ssize_t aspeed_espi_pltrstn_read(struct file *filp, char __user *buf,
+@@ -269,6 +274,8 @@ static int aspeed_espi_pltrstn_open(struct inode *inode, struct file *filp)
+ {
+ 	if ((filp->f_flags & O_ACCMODE) != O_RDONLY)
+ 		return -EACCES;
++	struct aspeed_espi *priv = to_aspeed_espi(filp);
++	priv->pltrstn_in_avail = true ; /*Setting true returns first data after file open*/
+ 
+ 	return 0;
+ }
+@@ -284,41 +291,71 @@ static ssize_t aspeed_espi_pltrstn_read(struct file *filp, char __user *buf,
  
  	spin_lock_irqsave(&priv->pltrstn_lock, flags);
  
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0102-Fix-for-dirty-node-in-jffs2-summary-entry.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0102-Fix-for-dirty-node-in-jffs2-summary-entry.patch
new file mode 100644
index 000000000..f3bb26a8a
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0102-Fix-for-dirty-node-in-jffs2-summary-entry.patch
@@ -0,0 +1,94 @@
+From 9d4191d2702ad5a368ca79eb253de26ce94b91c7 Mon Sep 17 00:00:00 2001
+From: AppaRao Puli <apparao.puli@linux.intel.com>
+Date: Mon, 30 Mar 2020 11:00:16 +0530
+Subject: [PATCH] From: Thomas Betker <thomas.betker@rohde-schwarz.com>
+
+jffs2_flash_direct_writev() always invokes jffs2_sum_add_kvec(), even
+if mtd_writev() fails. Usually, this results in an extra summary entry
+pointing to dirty node space, which should be ignored -- it is a bit of
+a waste, but harmless.
+
+When mtd_writev() returns *retlen == 0, though, the node space is not
+reserved as dirty, but re-used; the extra summary entry then points
+into the space of the next node. After the erase block has been closed,
+we get the following messages on remount:
+
+    jffs2: error: (79) jffs2_link_node_ref:
+        Adding new ref c3048d18 at (0x00ec5b88-0x00ec6bcc)
+        not immediately after previous (0x00ec5b88-0x00ec5b88)
+    ...
+    jffs2: Checked all inodes but still 0x2088 bytes of unchecked space?
+    jffs2: No space for garbage collection. Aborting GC thread
+
+The extra summary entries amount to "unchecked space", so that
+jffs2_garbage_collect_pass() returns -ENOSPC. And without garbage
+collection, the filesystem becomes unuseable over time as the erase
+blocks fill up.
+
+Fix this by skipping jffs2_sum_add_kvec() when the MTD write fails. We
+don't need the summary entry anyway, and the behaviour matches that of
+jffs2_flash_writev() in wbuf.c (with write buffering enabled).
+
+Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
+---
+ fs/jffs2/writev.c | 16 +++++++++++++++-
+ 1 file changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/fs/jffs2/writev.c b/fs/jffs2/writev.c
+index a1bda9d..eec4197 100644
+--- a/fs/jffs2/writev.c
++++ b/fs/jffs2/writev.c
+@@ -16,9 +16,18 @@
+ int jffs2_flash_direct_writev(struct jffs2_sb_info *c, const struct kvec *vecs,
+ 			      unsigned long count, loff_t to, size_t *retlen)
+ {
++	int ret;
++
++	ret = mtd_writev(c->mtd, vecs, count, to, retlen);
++
+ 	if (!jffs2_is_writebuffered(c)) {
+ 		if (jffs2_sum_active()) {
+ 			int res;
++
++			if (ret ||
++			    *retlen != iov_length((struct iovec *) vecs, count))
++				return ret;
++
+ 			res = jffs2_sum_add_kvec(c, vecs, count, (uint32_t) to);
+ 			if (res) {
+ 				return res;
+@@ -26,19 +35,23 @@ int jffs2_flash_direct_writev(struct jffs2_sb_info *c, const struct kvec *vecs,
+ 		}
+ 	}
+ 
+-	return mtd_writev(c->mtd, vecs, count, to, retlen);
++	return ret;
+ }
+ 
+ int jffs2_flash_direct_write(struct jffs2_sb_info *c, loff_t ofs, size_t len,
+ 			size_t *retlen, const u_char *buf)
+ {
+ 	int ret;
++
+ 	ret = mtd_write(c->mtd, ofs, len, retlen, buf);
+ 
+ 	if (jffs2_sum_active()) {
+ 		struct kvec vecs[1];
+ 		int res;
+ 
++		if (ret || *retlen != len)
++			return ret;
++
+ 		vecs[0].iov_base = (unsigned char *) buf;
+ 		vecs[0].iov_len = len;
+ 
+@@ -47,5 +60,6 @@ int jffs2_flash_direct_write(struct jffs2_sb_info *c, loff_t ofs, size_t len,
+ 			return res;
+ 		}
+ 	}
++
+ 	return ret;
+ }
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch
new file mode 100644
index 000000000..4d7440185
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch
@@ -0,0 +1,191 @@
+From dd7498a847b3e908dabaed2e9a27b43a26d0dba0 Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Thu, 26 Mar 2020 14:20:19 -0700
+Subject: [PATCH] Refine clock settings
+
+This commit refines clock settings with cherry picking the latest
+code from Aspeed SDK v00.05.05
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ drivers/clk/clk-ast2600.c | 104 +++++++++++++++++++++++++++++++++++++---------
+ 1 file changed, 85 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
+index af908b2dbeb6..e5079c5f4fcf 100644
+--- a/drivers/clk/clk-ast2600.c
++++ b/drivers/clk/clk-ast2600.c
+@@ -31,6 +31,24 @@
+ #define ASPEED_G6_CLK_SELECTION1	0x300
+ #define ASPEED_G6_CLK_SELECTION2	0x304
+ #define ASPEED_G6_CLK_SELECTION4	0x310
++#define ASPEED_G6_CLK_SELECTION5	0x314
++
++#define ASPEED_G6_MAC12_CLK_CTRL0	0x340
++#define ASPEED_G6_MAC12_CLK_CTRL1	0x348
++#define ASPEED_G6_MAC12_CLK_CTRL2	0x34C
++
++#define ASPEED_G6_MAC34_CLK_CTRL0	0x350
++#define ASPEED_G6_MAC34_CLK_CTRL1	0x358
++#define ASPEED_G6_MAC34_CLK_CTRL2	0x35C
++
++#define ASPEED_G6_MAC34_DRIVING_CTRL	0x458
++
++#define ASPEED_G6_DEF_MAC12_DELAY_1G	0x0041b410
++#define ASPEED_G6_DEF_MAC12_DELAY_100M	0x00417410
++#define ASPEED_G6_DEF_MAC12_DELAY_10M	0x00417410
++#define ASPEED_G6_DEF_MAC34_DELAY_1G	0x00104208
++#define ASPEED_G6_DEF_MAC34_DELAY_100M	0x00104208
++#define ASPEED_G6_DEF_MAC34_DELAY_10M	0x00104208
+ 
+ #define ASPEED_HPLL_PARAM		0x200
+ #define ASPEED_APLL_PARAM		0x210
+@@ -40,9 +58,6 @@
+ 
+ #define ASPEED_G6_STRAP1		0x500
+ 
+-#define ASPEED_MAC12_CLK_DLY		0x340
+-#define ASPEED_MAC34_CLK_DLY		0x350
+-
+ #define ASPEED_G6_GEN_UART_REF		0x338
+ #define UART_192MHZ_R_N_VALUE		0x3c38e
+ 
+@@ -515,7 +530,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
+ 
+ 	/* RMII1 50MHz (RCLK) output enable */
+ 	hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
+-			scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
++			scu_g6_base + ASPEED_G6_MAC12_CLK_CTRL0, 29, 0,
+ 			&aspeed_g6_clk_lock);
+ 	if (IS_ERR(hw))
+ 		return PTR_ERR(hw);
+@@ -523,7 +538,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
+ 
+ 	/* RMII2 50MHz (RCLK) output enable */
+ 	hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
+-			scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
++			scu_g6_base + ASPEED_G6_MAC12_CLK_CTRL0, 30, 0,
+ 			&aspeed_g6_clk_lock);
+ 	if (IS_ERR(hw))
+ 		return PTR_ERR(hw);
+@@ -545,7 +560,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
+ 
+ 	/* RMII3 50MHz (RCLK) output enable */
+ 	hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
+-			scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
++			scu_g6_base + ASPEED_G6_MAC34_CLK_CTRL0, 29, 0,
+ 			&aspeed_g6_clk_lock);
+ 	if (IS_ERR(hw))
+ 		return PTR_ERR(hw);
+@@ -553,7 +568,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
+ 
+ 	/* RMII4 50MHz (RCLK) output enable */
+ 	hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
+-			scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
++			scu_g6_base + ASPEED_G6_MAC34_CLK_CTRL0, 30, 0,
+ 			&aspeed_g6_clk_lock);
+ 	if (IS_ERR(hw))
+ 		return PTR_ERR(hw);
+@@ -650,12 +665,20 @@ static struct platform_driver aspeed_g6_clk_driver = {
+ };
+ builtin_platform_driver(aspeed_g6_clk_driver);
+ 
+-static const u32 ast2600_a0_axi_ahb_div_table[] = {
+-	2, 2, 3, 5,
++static u32 ast2600_a0_axi_ahb_div_table[] = {
++	2, 2, 3, 4,
+ };
+ 
+-static const u32 ast2600_a1_axi_ahb_div_table[] = {
+-	4, 6, 2, 4,
++static u32 ast2600_a1_axi_ahb_div0_table[] = {
++	3, 2, 3, 4,
++};
++
++static u32 ast2600_a1_axi_ahb_div1_table[] = {
++	3, 4, 6, 8,
++};
++
++static const u32 ast2600_a1_axi_ahb_default_table[] = {
++	3, 4, 3, 4, 2, 2, 2, 2,
+ };
+ 
+ static void __init aspeed_g6_cc(struct regmap *map)
+@@ -686,16 +709,28 @@ static void __init aspeed_g6_cc(struct regmap *map)
+ 
+ 	/* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
+ 	regmap_read(map, ASPEED_G6_STRAP1, &val);
+-	if (val & BIT(16))
+-		axi_div = 1;
+-	else
+-		axi_div = 2;
+-
+ 	regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
+-	if (chip_id & BIT(16))
+-		ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
+-	else
++	if (chip_id & BIT(16)) {
++		if (val & BIT(16)) {
++			axi_div = 1;
++			ast2600_a1_axi_ahb_div1_table[0] =
++				ast2600_a1_axi_ahb_default_table[(val >> 8) &
++								 0x3];
++			ahb_div = ast2600_a1_axi_ahb_div1_table[(val >> 11) &
++								0x3];
++		} else {
++			axi_div = 2;
++			ast2600_a1_axi_ahb_div0_table[0] =
++				ast2600_a1_axi_ahb_default_table[(val >> 8) &
++								 0x3];
++			ahb_div = ast2600_a1_axi_ahb_div0_table[(val >> 11) &
++								0x3];
++		}
++	} else {
++		/* a0 : fix axi = hpll/2 */
++		axi_div = 2;
+ 		ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
++	}
+ 
+ 	hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
+ 	aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
+@@ -751,6 +786,37 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
+ 		return;
+ 	}
+ 
++	/* fixed settings for RGMII/RMII clock generator */
++	/* MAC1/2 RGMII 125MHz = EPLL / 8 */
++	regmap_update_bits(map, ASPEED_G6_CLK_SELECTION2, GENMASK(23, 20),
++			   (0x7 << 20));
++
++	/* MAC3/4 RMII 50MHz = HCLK / 4 */
++	regmap_update_bits(map, ASPEED_G6_CLK_SELECTION4, GENMASK(18, 16),
++			   (0x3 << 16));
++
++	/*
++	 * BIT[31]: MAC1/2 RGMII 125M source = internal PLL
++	 * BIT[28]: RGMIICK pad direction = output
++	 */
++	regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL0,
++		     BIT(31) | BIT(28) | ASPEED_G6_DEF_MAC12_DELAY_1G);
++	regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL1,
++		     ASPEED_G6_DEF_MAC12_DELAY_100M);
++	regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL2,
++		     ASPEED_G6_DEF_MAC12_DELAY_10M);
++
++	/* MAC3/4 RGMII 125M source = RGMIICK pad */
++	regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL0,
++		     ASPEED_G6_DEF_MAC34_DELAY_1G);
++	regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL1,
++		     ASPEED_G6_DEF_MAC34_DELAY_100M);
++	regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL2,
++		     ASPEED_G6_DEF_MAC34_DELAY_10M);
++
++	/* MAC3/4 default pad driving strength */
++	regmap_write(map, ASPEED_G6_MAC34_DRIVING_CTRL, 0x0000000a);
++
+ 	aspeed_g6_cc(map);
+ 	aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
+ 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0104-Add-chip-unique-id-reading-interface.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0104-Add-chip-unique-id-reading-interface.patch
new file mode 100644
index 000000000..f366287f1
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0104-Add-chip-unique-id-reading-interface.patch
@@ -0,0 +1,213 @@
+From 61fd1c976a0867deec8607183849969e2d96aef7 Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Fri, 27 Mar 2020 14:42:05 -0700
+Subject: [PATCH] Add chip unique id reading interface
+
+This commit adds an interface for reading chip unique id value.
+Optionally, the id can be encrypted using a dts-supplied hash data.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
+---
+ drivers/soc/aspeed/aspeed-bmc-misc.c | 118 ++++++++++++++++++++++++---
+ 1 file changed, 105 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/soc/aspeed/aspeed-bmc-misc.c b/drivers/soc/aspeed/aspeed-bmc-misc.c
+index 04d97ab17274..c80b2e71f254 100644
+--- a/drivers/soc/aspeed/aspeed-bmc-misc.c
++++ b/drivers/soc/aspeed/aspeed-bmc-misc.c
+@@ -7,15 +7,18 @@
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/mfd/syscon.h>
++#include <crypto/hash.h>
+ 
+ #define DEVICE_NAME "aspeed-bmc-misc"
+ 
+ struct aspeed_bmc_ctrl {
+ 	const char *name;
+ 	u32 offset;
+-	u32 mask;
++	u64 mask;
+ 	u32 shift;
+ 	bool read_only;
++	u32 reg_width;
++	const char *hash_data;
+ 	struct regmap *map;
+ 	struct kobj_attribute attr;
+ };
+@@ -31,6 +34,7 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
+ 					  struct aspeed_bmc_ctrl *ctrl)
+ {
+ 	int rc;
++	u32 mask;
+ 
+ 	/* Example child:
+ 	 *
+@@ -38,6 +42,7 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
+ 	 *     offset = <0x80>;
+ 	 *     bit-mask = <0x1>;
+ 	 *     bit-shift = <6>;
++	 *     reg-width = <64>;
+ 	 *     label = "foo";
+ 	 * }
+ 	 */
+@@ -48,9 +53,22 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
+ 	if (rc < 0)
+ 		return rc;
+ 
+-	rc = of_property_read_u32(child, "bit-mask", &ctrl->mask);
+-	if (rc < 0)
+-		return rc;
++	/* optional reg-width, default to 32 */
++	rc = of_property_read_u32(child, "reg-width", &ctrl->reg_width);
++	if (rc < 0 || ctrl->reg_width != 64)
++		ctrl->reg_width = 32;
++
++	if (ctrl->reg_width == 32) {
++		rc = of_property_read_u32(child, "bit-mask", &mask);
++		if (rc < 0)
++			return rc;
++		ctrl->mask = mask;
++	} else {
++		rc = of_property_read_u64(child, "bit-mask", &ctrl->mask);
++		if (rc < 0)
++			return rc;
++	}
++	ctrl->mask <<= ctrl->shift;
+ 
+ 	rc = of_property_read_u32(child, "bit-shift", &ctrl->shift);
+ 	if (rc < 0)
+@@ -58,7 +76,9 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
+ 
+ 	ctrl->read_only = of_property_read_bool(child, "read-only");
+ 
+-	ctrl->mask <<= ctrl->shift;
++	/* optional hash_data for obfuscating reads */
++	if (of_property_read_string(child, "hash-data", &ctrl->hash_data))
++		ctrl->hash_data = NULL;
+ 
+ 	return 0;
+ }
+@@ -88,22 +108,94 @@ static int aspeed_bmc_misc_parse_dt(struct aspeed_bmc_misc *bmc,
+ 	return 0;
+ }
+ 
++#define SHA256_DIGEST_LEN 32
++static int hmac_sha256(u8 *key, u8 ksize, const char *plaintext, u8 psize,
++		u8 *output)
++{
++	struct crypto_shash *tfm;
++	struct shash_desc *shash;
++	int ret;
++
++	if (!ksize)
++		return -EINVAL;
++
++	tfm = crypto_alloc_shash("hmac(sha256)", 0, 0);
++	if (IS_ERR(tfm)) {
++		return -ENOMEM;
++	}
++
++	ret = crypto_shash_setkey(tfm, key, ksize);
++	if (ret)
++		goto failed;
++
++	shash = kzalloc(sizeof(*shash) + crypto_shash_descsize(tfm), GFP_KERNEL);
++	if (!shash) {
++		ret = -ENOMEM;
++		goto failed;
++	}
++
++	shash->tfm = tfm;
++	ret = crypto_shash_digest(shash, plaintext, psize, output);
++
++	kfree(shash);
++
++failed:
++	crypto_free_shash(tfm);
++	return ret;
++}
++
+ static ssize_t aspeed_bmc_misc_show(struct kobject *kobj,
+ 				    struct kobj_attribute *attr, char *buf)
+ {
+ 	struct aspeed_bmc_ctrl *ctrl;
+-	unsigned int val;
++	u32 val;
++	u64 val64;
+ 	int rc;
++	u8 *binbuf;
++	size_t buf_len;
++	u8 hashbuf[SHA256_DIGEST_LEN];
+ 
+ 	ctrl = container_of(attr, struct aspeed_bmc_ctrl, attr);
++
++	if (ctrl->reg_width == 32) {
++		rc = regmap_read(ctrl->map, ctrl->offset, &val);
++		if (rc)
++			return rc;
++		val &= (u32)ctrl->mask;
++		val >>= ctrl->shift;
++
++		return sprintf(buf, "%u\n", val);
++	}
+ 	rc = regmap_read(ctrl->map, ctrl->offset, &val);
+ 	if (rc)
+ 		return rc;
++	val64 = val;
++	rc = regmap_read(ctrl->map, ctrl->offset + sizeof(u32), &val);
++	if (rc)
++		return rc;
++	/* aspeed puts 64-bit regs as L, H in address space */
++	val64 |= (u64)val << 32;
++	val64 &= ctrl->mask;
++	val64 >>= ctrl->shift;
++	buf_len = sizeof(val64);
++
++	if (ctrl->hash_data) {
++		rc = hmac_sha256((u8*)&val64, buf_len, ctrl->hash_data,
++				strlen(ctrl->hash_data), hashbuf);
++		if (rc)
++			return rc;
++		buf_len = SHA256_DIGEST_LEN;
++		binbuf = hashbuf;
++	} else {
++		binbuf = (u8*)&val64;
++		buf_len = sizeof(val64);
++	}
++	bin2hex(buf, binbuf, buf_len);
++	buf[buf_len * 2] = '\n';
++	rc = buf_len * 2 + 1;
+ 
+-	val &= ctrl->mask;
+-	val >>= ctrl->shift;
++	return rc;
+ 
+-	return sprintf(buf, "%u\n", val);
+ }
+ 
+ static ssize_t aspeed_bmc_misc_store(struct kobject *kobj,
+@@ -114,15 +206,15 @@ static ssize_t aspeed_bmc_misc_store(struct kobject *kobj,
+ 	long val;
+ 	int rc;
+ 
+-	rc = kstrtol(buf, 0, &val);
+-	if (rc)
+-		return rc;
+-
+ 	ctrl = container_of(attr, struct aspeed_bmc_ctrl, attr);
+ 
+ 	if (ctrl->read_only)
+ 		return -EROFS;
+ 
++	rc = kstrtol(buf, 0, &val);
++	if (rc)
++		return rc;
++
+ 	val <<= ctrl->shift;
+ 	rc = regmap_update_bits(ctrl->map, ctrl->offset, ctrl->mask, val);
+ 
+-- 
+2.17.1
+