diff options
author | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-07-10 01:11:22 +0300 |
---|---|---|
committer | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-07-10 20:11:31 +0300 |
commit | d071adf43ac87f21dde2f84287120960c723962c (patch) | |
tree | 05a1d365e0faa6ce8570b2d0c2d0f100dc8df1d4 /meta-openbmc-mods/meta-common/recipes-kernel | |
parent | f24c1e9afc47a421831278b57377951e71494d92 (diff) | |
download | openbmc-d071adf43ac87f21dde2f84287120960c723962c.tar.xz |
Update to internal 0.66
Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-kernel')
8 files changed, 206 insertions, 185 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch index 8ad7b3c0a..a077e7cdb 100644 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch @@ -1,4 +1,4 @@ -From 498b7829800ec27c7787b3ae77ee59e7b10ec40e Mon Sep 17 00:00:00 2001 +From 20c08d8ba976f43ebb98fbbe8f27dff352d41c40 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Tue, 19 Sep 2017 15:55:39 +0800 Subject: [PATCH] arm: dts: add DTS for Intel ast2600 platforms @@ -14,16 +14,16 @@ Signed-off-by: Ayushi Smriti <smriti.ayushi@intel.com> Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com> Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com> --- - arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 528 +++++++++++++++++++++++++ - 1 file changed, 528 insertions(+) + arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 530 +++++++++++++++++++++++++ + 1 file changed, 530 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts new file mode 100644 -index 000000000000..c68314d3901b +index 000000000000..b7f47623c021 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts -@@ -0,0 +1,528 @@ +@@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + @@ -246,23 +246,25 @@ index 000000000000..c68314d3901b + /*DUMMY*/ "","","","","","","","", + + /* SGPIO input lines */ -+ /* Some lines have been renamed from the net names: -+ CPU1_PRESENCE -> FM_CPU0_SKTOCC_LVT3_N -+ CPU1_THERMTRIP -> H_CPU0_THERMTRIP_LVC1_N -+ CPU1_VRHOT -> IRQ_CPU0_VRHOT_N -+ CPU1_FIVR_FAULT -> H_CPU0_MON_FAIL_PLD_LVC1_N -+ CPU1_MEM_ABCD_VRHOT -> ?? -+ CPU1_MEM_EFGH_VRHOT -> ?? -+ CPU2_PRESENCE -> FM_CPU1_SKTOCC_LVT3_N -+ CPU2_THERMTRIP -> H_CPU1_THERMTRIP_LVC1_N -+ CPU2_VRHOT -> IRQ_CPU1_VRHOT_N -+ CPU2_FIVR_FAULT -> H_CPU1_MON_FAIL_PLD_LVC1_N -+ CPU2_MEM_ABCD_VRHOT -> ?? -+ CPU2_MEM_EFGH_VRHOT -> ?? -+ -+ /*IA0-IA7*/ "CPU1_PRESENCE","CPU1_THERMTRIP","CPU1_VRHOT","CPU1_FIVR_FAULT","IRQ_CPU0_MEM_VRHOT_N","H_CPU0_MEMHOT_OUT_LVC1_N","FM_CPU0_PROC_ID0","FM_CPU0_PROC_ID1", -+ /*IB0-IB7*/ "WCPU_MISMATCH","IRQ_PSYS_CRIT_N","CPU2_PRESENCE","CPU2_THERMTRIP","CPU2_VRHOT","CPU2_FIVR_FAULT","IRQ_CPU1_MEM_VRHOT_N","H_CPU1_MEMHOT_OUT_LVC1_N", -+ /*IC0-IC7*/ "FM_CPU1_PROC_ID0","FM_CPU1_PROC_ID1","","","","","","", ++/* SGPIO Alias: (runtime alias -> net name) ++ CPU1_PRESENCE -> FM_CPU0_SKTOCC_LVT3_N ++ CPU1_THERMTRIP -> H_CPU0_THERMTRIP_LVC1_N ++ CPU1_VRHOT -> IRQ_CPU0_VRHOT_N ++ CPU1_FIVR_FAULT -> EV_MON_FAIL_CPU0_N ++ CPU1_MEM_VRHOT -> IRQ_CPU0_MEM_VRHOT_N ++ CPU1_MEM_THERM_EVENT -> H_CPU0_MEMHOT_OUT_LVC1_N ++ CPU1_MISMATCH -> FM_CPU0_MISMATCH ++ CPU2_PRESENCE -> FM_CPU1_SKTOCC_LVT3_N ++ CPU2_THERMTRIP -> H_CPU1_THERMTRIP_LVC1_N ++ CPU2_VRHOT -> IRQ_CPU1_VRHOT_N ++ CPU2_FIVR_FAULT -> EV_MON_FAIL_CPU1_N ++ CPU2_MEM_VRHOT -> IRQ_CPU1_MEM_VRHOT_N ++ CPU2_MEM_THERM_EVENT -> H_CPU1_MEMHOT_OUT_LVC1_N ++ CPU2_MISMATCH -> FM_CPU1_MISMATCH ++*/ ++ /*IA0-IA7*/ "CPU1_PRESENCE","CPU1_THERMTRIP","CPU1_VRHOT","CPU1_FIVR_FAULT","CPU1_MEM_VRHOT","CPU1_MEM_THERM_EVENT","FM_CPU0_PROC_ID0","FM_CPU0_PROC_ID1", ++ /*IB0-IB7*/ "CPU1_MISMATCH","IRQ_PSYS_CRIT_N","CPU2_PRESENCE","CPU2_THERMTRIP","CPU2_VRHOT","CPU2_FIVR_FAULT","CPU1_MEM_VRHOT","CPU2_MEM_THERM_EVENT", ++ /*IC0-IC7*/ "FM_CPU1_PROC_ID0","FM_CPU1_PROC_ID1","CPU2_MISMATCH","","","","","", + /*ID0-ID7*/ "","","","","","","","", + /*IE0-IE7*/ "","","","","","","","", + /*IF0-IF7*/ "FPGA_REV_TEST_0","FPGA_REV_TEST_1","FPGA_REV_TEST_2","FPGA_REV_TEST_3","FPGA_REV_TEST_4","FPGA_REV_TEST_5","FPGA_REV_TEST_6","FPGA_REV_TEST_7", @@ -485,7 +487,7 @@ index 000000000000..c68314d3901b +}; + +&pwm_tacho { -+ status = "disabled"; ++ status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default + &pinctrl_pwm1_default &pinctrl_tach1_default @@ -504,7 +506,7 @@ index 000000000000..c68314d3901b + }; + fan@1 { + reg = <0x01>; -+ aspeed,fan-tach-ch = /bits/ 8 <0x01>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + fan@2 { + reg = <0x02>; @@ -523,19 +525,19 @@ index 000000000000..c68314d3901b + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + fan@6 { -+ reg = <0x06>; ++ reg = <0x0c>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + fan@7 { -+ reg = <0x07>; ++ reg = <0x0d>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + fan@8 { -+ reg = <0x08>; ++ reg = <0x0e>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + fan@9 { -+ reg = <0x09>; ++ reg = <0x0f>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; +}; diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0080-i2c-aspeed-filter-garbage-interrupts-out.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0080-i2c-aspeed-filter-garbage-interrupts-out.patch index 89e7b894f..d8e911a54 100644 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0080-i2c-aspeed-filter-garbage-interrupts-out.patch +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0080-i2c-aspeed-filter-garbage-interrupts-out.patch @@ -1,4 +1,4 @@ -From a90b8f7dfcfcab2d40d1a575e3948ef3a34f643f Mon Sep 17 00:00:00 2001 +From 063957ca24903e7cbebcaa11bde4cc1cc3cbb6a1 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Fri, 8 Nov 2019 15:57:27 -0800 Subject: [PATCH] i2c: aspeed: filter garbage interrupts out @@ -12,7 +12,7 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 1 file changed, 14 insertions(+) diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c -index 62b803e15ce2..c24cecdcfe89 100644 +index 24850fb78ee1..d5a8da4a9009 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -87,7 +87,11 @@ @@ -39,10 +39,10 @@ index 62b803e15ce2..c24cecdcfe89 100644 /* 0x14 : I2CD Command/Status Register */ #define ASPEED_I2CD_SCL_LINE_STS BIT(18) -@@ -1021,6 +1030,11 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) - /* Ack all interrupts except for Rx done */ +@@ -1065,6 +1074,11 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE, bus->base + ASPEED_I2C_INTR_STS_REG); + readl(bus->base + ASPEED_I2C_INTR_STS_REG); + /* + * AST2600 makes a garbage interrupt which is decribed as 'reserved' + * in datasheet so filter them out. diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0095-pwm-and-tach-driver-changes-for-ast2600.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0095-pwm-and-tach-driver-changes-for-ast2600.patch index 377ec2b36..2d624d10f 100644 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0095-pwm-and-tach-driver-changes-for-ast2600.patch +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0095-pwm-and-tach-driver-changes-for-ast2600.patch @@ -1,4 +1,4 @@ -From 0301f9b2bc948069aaad2899e15e6c94a07ca818 Mon Sep 17 00:00:00 2001 +From ffa6dd9617c65d6387bea50827a2843925aedde9 Mon Sep 17 00:00:00 2001 From: Ayushi Smriti <smriti.ayushi@intel.com> Date: Mon, 2 Mar 2020 22:51:46 +0530 Subject: [PATCH] pwm and tach driver changes for ast2600 @@ -9,23 +9,24 @@ ast2600 Signed-off-by: Ayushi Smriti <smriti.ayushi@intel.com> --- - drivers/hwmon/aspeed-g6-pwm-tacho.c | 328 +++++++++++++++------------- + drivers/hwmon/aspeed-g6-pwm-tacho.c | 328 +++++++++++++++++++----------------- 1 file changed, 171 insertions(+), 157 deletions(-) diff --git a/drivers/hwmon/aspeed-g6-pwm-tacho.c b/drivers/hwmon/aspeed-g6-pwm-tacho.c -index 1894f6ad5edb..1ff788bf1133 100644 +index 1894f6ad5edb..9551a17e7f55 100644 --- a/drivers/hwmon/aspeed-g6-pwm-tacho.c +++ b/drivers/hwmon/aspeed-g6-pwm-tacho.c -@@ -64,6 +64,8 @@ +@@ -64,6 +64,9 @@ #define PWM_RISING_FALLING_BIT (8) //pwm falling point bit [7:0] #define PWM_RISING_RISING_BIT (0) //pwm rising point bit [7:0] -+#define DEF_PWM_PERIOD 0xff ++#define PWM_PERIOD_MAX 255 ++#define PWM_FALLING_DEFAULT 150 /* 58% */ + #define ASPEED_TACHO_CTRL 0x08 //TACH0 General Register #define ASPEED_TACHO_CTRL_CH(x) ((x * 0x10) + 0x08) #define TACHO_IER BIT(31) //enable tacho interrupt -@@ -72,8 +74,7 @@ +@@ -72,8 +75,7 @@ #define TACHO_ENABLE BIT(28) //{enable tacho} #define TACHO_DEBOUNCE_BIT (26) //{tacho de-bounce} #define TACHO_DEBOUNCE_MASK (0x3 << 26) //{tacho de-bounce} @@ -35,15 +36,13 @@ index 1894f6ad5edb..1ff788bf1133 100644 #define TACHO_CLK_DIV_T_MASK (0xf << 20) #define TACHO_CLK_DIV_BIT (20) #define TACHO_THRESHOLD_MASK (0xfffff) //tacho threshold bit -@@ -102,211 +103,183 @@ +@@ -102,211 +104,181 @@ #define MAX_CDEV_NAME_LEN 16 +#define DEFAULT_TARGET_PWM_FREQ 25000 +#define DEFAULT_MIN_RPM 2900 + -+#define PWM_FALLING_VALUE 0xff -+ struct aspeed_pwm_channel_params { + int target_freq; + int pwm_freq; @@ -72,7 +71,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [1] = { + .target_freq = 25000, @@ -86,7 +85,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [2] = { + .target_freq = 25000, @@ -100,7 +99,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [3] = { + .target_freq = 25000, @@ -114,7 +113,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [4] = { + .target_freq = 25000, @@ -128,7 +127,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [5] = { + .target_freq = 25000, @@ -142,7 +141,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [6] = { + .target_freq = 25000, @@ -156,7 +155,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [7] = { + .target_freq = 25000, @@ -170,7 +169,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [8] = { + .target_freq = 25000, @@ -184,7 +183,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [9] = { + .target_freq = 25000, @@ -198,7 +197,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [10] = { + .target_freq = 25000, @@ -212,7 +211,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [11] = { + .target_freq = 25000, @@ -226,7 +225,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [12] = { + .target_freq = 25000, @@ -240,7 +239,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [13] = { + .target_freq = 25000, @@ -254,7 +253,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [14] = { + .target_freq = 25000, @@ -268,7 +267,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, [15] = { + .target_freq = 25000, @@ -282,11 +281,11 @@ index 1894f6ad5edb..1ff788bf1133 100644 - .period = 0x13, //5% ~~ .rising = 0x00, - .falling = 0x0a, -+ .falling = PWM_FALLING_VALUE, ++ .falling = PWM_FALLING_DEFAULT, }, }; -@@ -318,125 +291,146 @@ static struct aspeed_pwm_channel_params default_pwm_params[] = { +@@ -318,125 +290,146 @@ static struct aspeed_pwm_channel_params default_pwm_params[] = { * 11: reserved. */ @@ -450,7 +449,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 .tacho_debounce = 0, .divide = 8, }, -@@ -501,29 +495,28 @@ static void aspeed_set_pwm_channel_enable(struct regmap *regmap, u8 pwm_channel, +@@ -501,29 +494,29 @@ static void aspeed_set_pwm_channel_enable(struct regmap *regmap, u8 pwm_channel, static void aspeed_set_fan_tach_ch_enable(struct aspeed_pwm_tachometer_data *priv, u8 fan_tach_ch, bool enable) { @@ -473,6 +472,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 + break; + } + } else { ++ i = 0; divide_val = 1; - for (j = 1; j <= i; j++) - divide_val *= 4; @@ -505,7 +505,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 } else { - duty_value = (priv->pwm_channel[index].period << PWM_PERIOD_BIT) | - (0 << PWM_RISING_RISING_BIT) | (fan_ctrl << PWM_RISING_FALLING_BIT); -+ cal_freq = priv->clk_freq / (DEF_PWM_PERIOD + 1); ++ cal_freq = priv->clk_freq / (PWM_PERIOD_MAX + 1); + /*calculate for target frequence*/ + for (div_l = 0; div_l < 0x100; div_l++) { + for (div_h = 0; div_h < 0x10; div_h++) { @@ -515,13 +515,13 @@ index 1894f6ad5edb..1ff788bf1133 100644 + if ((cal_freq / (BIT(div_h) * (div_l + 1))) < priv->pwm_channel[index].target_freq) + break; + } -+ -+ priv->pwm_channel[index].pwm_freq = cal_freq / (BIT(div_h) * (div_l + 1)); - ctrl_value = (priv->pwm_channel[index].divide_h << 8) | priv->pwm_channel[index].divide_l; ++ priv->pwm_channel[index].pwm_freq = cal_freq / (BIT(div_h) * (div_l + 1)); ++ + ctrl_value = (div_h << 8) | div_l; + -+ duty_value = (DEF_PWM_PERIOD << PWM_PERIOD_BIT) | ++ duty_value = (PWM_PERIOD_MAX << PWM_PERIOD_BIT) | + (0 << PWM_RISING_RISING_BIT) | (fan_ctrl << PWM_RISING_FALLING_BIT); if (priv->pwm_channel[index].load_wdt_enable) { @@ -578,7 +578,7 @@ index 1894f6ad5edb..1ff788bf1133 100644 return ret; - if (fan_ctrl < 0 || fan_ctrl > priv->pwm_channel[index].period) -+ if (fan_ctrl < 0 || fan_ctrl > DEF_PWM_PERIOD) ++ if (fan_ctrl < 0 || fan_ctrl > PWM_PERIOD_MAX) return -EINVAL; if (priv->pwm_channel[index].falling == fan_ctrl) @@ -779,5 +779,5 @@ index 1894f6ad5edb..1ff788bf1133 100644 } -- -2.17.1 +2.7.4 diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0106-enable-AST2600-I3C.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0106-enable-AST2600-I3C.patch index 7eac39e5b..4cc88cbeb 100644 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0106-enable-AST2600-I3C.patch +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0106-enable-AST2600-I3C.patch @@ -1,4 +1,4 @@ -From ec463c332c3b954a5a0ef4ceb253701b8190bbb9 Mon Sep 17 00:00:00 2001 +From c3be31a18ef1755c86c169b9d0e54bdbbea99d8a Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Wed, 6 May 2020 18:11:29 -0700 Subject: [PATCH] enable AST2600 I3C @@ -20,10 +20,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> drivers/i3c/master.c | 39 ++- drivers/i3c/master/Kconfig | 5 + drivers/i3c/master/Makefile | 1 + - drivers/i3c/master/aspeed-i3c-global.c | 89 +++++++ + drivers/i3c/master/aspeed-i3c-global.c | 77 ++++++ include/dt-bindings/clock/ast2600-clock.h | 3 +- include/uapi/linux/i3c/i3cdev.h | 38 +++ - 12 files changed, 646 insertions(+), 24 deletions(-) + 12 files changed, 634 insertions(+), 24 deletions(-) create mode 100644 drivers/i3c/i3cdev.c create mode 100644 drivers/i3c/master/aspeed-i3c-global.c create mode 100644 include/uapi/linux/i3c/i3cdev.h @@ -756,31 +756,23 @@ index 4e80a1fcbf91..693f9aba2b17 100644 + depends on I3C + depends on MACH_ASPEED_G6 diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile -index 7eea9e086144..09057d1432cc 100644 +index 7eea9e086144..b5ec8e8dd622 100644 --- a/drivers/i3c/master/Makefile +++ b/drivers/i3c/master/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_ASPEED_I3C_GLOBAL) += aspeed-i3c-global.o obj-$(CONFIG_CDNS_I3C_MASTER) += i3c-master-cdns.o obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o -+obj-$(CONFIG_ASPEED_I3C_GLOBAL) += aspeed-i3c-global.o diff --git a/drivers/i3c/master/aspeed-i3c-global.c b/drivers/i3c/master/aspeed-i3c-global.c new file mode 100644 -index 000000000000..9c3e58794a3e +index 000000000000..8db6c1397a6c --- /dev/null +++ b/drivers/i3c/master/aspeed-i3c-global.c -@@ -0,0 +1,89 @@ -+/* -+ * Aspeed I2C Interrupt Controller. -+ * -+ * Copyright (C) 2012-2017 ASPEED Technology Inc. -+ * Copyright 2017 IBM Corporation -+ * Copyright 2017 Google, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// Copyright (C) 2019 ASPEED Technology Inc. ++ +#include <linux/clk.h> +#include <linux/irq.h> +#include <linux/irqchip.h> @@ -803,11 +795,6 @@ index 000000000000..9c3e58794a3e + struct reset_control *rst; +}; + -+static const struct of_device_id aspeed_i3c_of_match[] = { -+ { .compatible = "aspeed,ast2600-i3c-global", }, -+ {}, -+}; -+ +static int aspeed_i3c_global_probe(struct platform_device *pdev) +{ + struct aspeed_i3c_global *i3c_global; @@ -826,8 +813,8 @@ index 000000000000..9c3e58794a3e + i3c_global->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + + if (IS_ERR(i3c_global->rst)) { -+ dev_err(&pdev->dev, -+ "missing or invalid reset controller device tree entry"); ++ if (PTR_ERR(i3c_global->rst) != -EPROBE_DEFER) ++ dev_err(&pdev->dev, "missing or invalid reset controller device tree entry\n"); + return PTR_ERR(i3c_global->rst); + } + @@ -842,6 +829,12 @@ index 000000000000..9c3e58794a3e + return 0; +} + ++static const struct of_device_id aspeed_i3c_of_match[] = { ++ { .compatible = "aspeed,ast2600-i3c-global", }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, aspeed_i3c_of_match); ++ +static struct platform_driver aspeed_i3c_driver = { + .probe = aspeed_i3c_global_probe, + .driver = { @@ -849,12 +842,7 @@ index 000000000000..9c3e58794a3e + .of_match_table = aspeed_i3c_of_match, + }, +}; -+ -+static int __init aspeed_i3c_global_init(void) -+{ -+ return platform_driver_register(&aspeed_i3c_driver); -+} -+postcore_initcall(aspeed_i3c_global_init); ++module_platform_driver(aspeed_i3c_driver); + +MODULE_AUTHOR("Ryan Chen"); +MODULE_DESCRIPTION("ASPEED I3C Global Driver"); diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0109-signal-Extend-exec_id-to-64bits.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0109-signal-Extend-exec_id-to-64bits.patch deleted file mode 100644 index 7d879ab82..000000000 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0109-signal-Extend-exec_id-to-64bits.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 5f2d04139aa5ed04eab54b84e8a25bab87a2449c Mon Sep 17 00:00:00 2001 -From: "Eric W. Biederman" <ebiederm@xmission.com> -Date: Mon, 30 Mar 2020 19:01:04 -0500 -Subject: [PATCH] signal: Extend exec_id to 64bits - -commit d1e7fd6462ca9fc76650fbe6ca800e35b24267da upstream. - -Replace the 32bit exec_id with a 64bit exec_id to make it impossible -to wrap the exec_id counter. With care an attacker can cause exec_id -wrap and send arbitrary signals to a newly exec'd parent. This -bypasses the signal sending checks if the parent changes their -credentials during exec. - -The severity of this problem can been seen that in my limited testing -of a 32bit exec_id it can take as little as 19s to exec 65536 times. -Which means that it can take as little as 14 days to wrap a 32bit -exec_id. Adam Zabrocki has succeeded wrapping the self_exe_id in 7 -days. Even my slower timing is in the uptime of a typical server. -Which means self_exec_id is simply a speed bump today, and if exec -gets noticably faster self_exec_id won't even be a speed bump. - -Extending self_exec_id to 64bits introduces a problem on 32bit -architectures where reading self_exec_id is no longer atomic and can -take two read instructions. Which means that is is possible to hit -a window where the read value of exec_id does not match the written -value. So with very lucky timing after this change this still -remains expoiltable. - -I have updated the update of exec_id on exec to use WRITE_ONCE -and the read of exec_id in do_notify_parent to use READ_ONCE -to make it clear that there is no locking between these two -locations. - -Link: https://lore.kernel.org/kernel-hardening/20200324215049.GA3710@pi3.com.pl -Fixes: 2.3.23pre2 -Cc: stable@vger.kernel.org -Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> ---- - fs/exec.c | 2 +- - include/linux/sched.h | 4 ++-- - kernel/signal.c | 2 +- - 3 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/fs/exec.c b/fs/exec.c -index c27231234764..fc2870f2aca9 100644 ---- a/fs/exec.c -+++ b/fs/exec.c -@@ -1383,7 +1383,7 @@ void setup_new_exec(struct linux_binprm * bprm) - - /* An exec changes our domain. We are no longer part of the thread - group */ -- current->self_exec_id++; -+ WRITE_ONCE(current->self_exec_id, current->self_exec_id + 1); - flush_signal_handlers(current, 0); - } - EXPORT_SYMBOL(setup_new_exec); -diff --git a/include/linux/sched.h b/include/linux/sched.h -index b968d736833b..5710b80f8050 100644 ---- a/include/linux/sched.h -+++ b/include/linux/sched.h -@@ -934,8 +934,8 @@ struct task_struct { - struct seccomp seccomp; - - /* Thread group tracking: */ -- u32 parent_exec_id; -- u32 self_exec_id; -+ u64 parent_exec_id; -+ u64 self_exec_id; - - /* Protection against (de-)allocation: mm, files, fs, tty, keyrings, mems_allowed, mempolicy: */ - spinlock_t alloc_lock; -diff --git a/kernel/signal.c b/kernel/signal.c -index eea748174ade..7d3d35eb7a0b 100644 ---- a/kernel/signal.c -+++ b/kernel/signal.c -@@ -1931,7 +1931,7 @@ bool do_notify_parent(struct task_struct *tsk, int sig) - * This is only possible if parent == real_parent. - * Check if it has changed security domain. - */ -- if (tsk->parent_exec_id != tsk->parent->self_exec_id) -+ if (tsk->parent_exec_id != READ_ONCE(tsk->parent->self_exec_id)) - sig = SIGCHLD; - } - --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0111-Unconditionally-calculate-the-PECI-AW-FCS.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0111-Unconditionally-calculate-the-PECI-AW-FCS.patch new file mode 100644 index 000000000..9b68f8036 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0111-Unconditionally-calculate-the-PECI-AW-FCS.patch @@ -0,0 +1,73 @@ +From e985c1cbb4cf6971c82afacb16737749a2d25452 Mon Sep 17 00:00:00 2001 +From: Johnathan Mantey <johnathanx.mantey@intel.com> +Date: Tue, 19 May 2020 11:39:00 -0700 +Subject: [PATCH] Unconditionally calculate the PECI AW FCS + +The PECI write commands that include the AW FCS byte were failing due +to the way AW FCS bytes were being managed. The current paradigm +permitted in the Redfish interface was to allow the AW FCS byte to be +omitted. The peci-core logic attempted to create the AW FCS byte. The +algorithm being used left the possibility of a bad FCS byte being +appended to the PECI command. + +This change manages the issue by always overwriting the AW FCS byte +with a value freshly calculated from the write payload. The user +supplying the AW FCS byte no longer matters. + +Tested: +Submitted this PECI sequence: +48 10 1 165 0 26 0 0 223 134 21 0 + +The sequence was sent from Redfish, and a return code of 0x40 +resulted. +Prior to this the sequence would report 0x90. + +Supplied the same sequence to "peci_cmds raw" in the console. +It failed because the number of bytes did not include the AW FCS +byte. Adding any additional byte allows the command to succeed. + +Change-Id: I217a8f136b48282634a7c8fdde7b440720c010c6 +Signed-off-by: Johnathan Mantey <johnathanx.mantey@intel.com> +--- + drivers/peci/peci-core.c | 21 ++++++--------------- + 1 file changed, 6 insertions(+), 15 deletions(-) + +diff --git a/drivers/peci/peci-core.c b/drivers/peci/peci-core.c +index efb73b09a9c0..426ee2be3271 100644 +--- a/drivers/peci/peci-core.c ++++ b/drivers/peci/peci-core.c +@@ -397,25 +397,16 @@ static int peci_cmd_xfer(struct peci_adapter *adapter, void *vmsg) + case PECI_WRPCICFG_CMD: + case PECI_WRPCICFGLOCAL_CMD: + case PECI_WRENDPTCFG_CMD: +- /* Check if the AW FCS byte is already provided */ ++ /* ++ * The sender may not have supplied the AW FCS byte. ++ * Unconditionally add an Assured Write Frame Check ++ * Sequence byte ++ */ + ret = peci_aw_fcs(msg, 2 + msg->tx_len, &aw_fcs); + if (ret) + break; + +- if (msg->tx_buf[msg->tx_len - 1] != (0x80 ^ aw_fcs)) { +- /* +- * Add an Assured Write Frame Check Sequence +- * byte and increment the tx_len to include +- * the new byte. +- */ +- msg->tx_len++; +- ret = peci_aw_fcs(msg, 2 + msg->tx_len, +- &aw_fcs); +- if (ret) +- break; +- +- msg->tx_buf[msg->tx_len - 1] = 0x80 ^ aw_fcs; +- } ++ msg->tx_buf[msg->tx_len - 1] = 0x80 ^ aw_fcs; + + ret = peci_xfer_with_retries(adapter, msg, true); + break; +-- +2.26.2 + diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0112-AST2600-enable-UART-routing.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0112-AST2600-enable-UART-routing.patch new file mode 100644 index 000000000..7d14f9e91 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0112-AST2600-enable-UART-routing.patch @@ -0,0 +1,45 @@ +From 47bb1475893aab85067b286fee7f6b126ea2b633 Mon Sep 17 00:00:00 2001 +From: Kuiying Wang <kuiying.wang@intel.com> +Date: Wed, 10 Jun 2020 13:07:59 +0800 +Subject: [PATCH] AST2600: enable UART routing. + +Enable UART routing. + +Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> +--- + arch/arm/boot/dts/aspeed-g6.dtsi | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi +index 90a060db20c7..0361a7ee6e14 100644 +--- a/arch/arm/boot/dts/aspeed-g6.dtsi ++++ b/arch/arm/boot/dts/aspeed-g6.dtsi +@@ -331,12 +331,6 @@ + compatible = "aspeed,ast2600-pinctrl"; + }; + +- uart_routing: uart_routing@9c { +- compatible = "aspeed,ast2500-uart-routing"; +- reg = <0x9c 0x4>; +- status = "disabled"; +- }; +- + smp-memram@180 { + compatible = "aspeed,ast2600-smpmem"; + reg = <0x180 0x40>; +@@ -688,6 +682,12 @@ + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + }; + }; ++ ++ uart_routing: uart_routing@9c { ++ compatible = "aspeed,ast2500-uart-routing"; ++ reg = <0x9c 0x4>; ++ status = "disabled"; ++ }; + }; + + sdc: sdc@1e740000 { +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend index f1d781f6f..1c6a307ff 100644 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend @@ -79,8 +79,9 @@ SRC_URI += " \ file://0106-enable-AST2600-I3C.patch \ file://0107-arm-dts-aspeed-g6-Add-ast2600-mctp-node.patch \ file://0108-soc-aspeed-mctp-Add-initial-driver-for-ast2600-mctp.patch \ - file://0109-signal-Extend-exec_id-to-64bits.patch \ file://0110-USB-gadget-fix-illegal-array-access-in-binding-with-.patch \ + file://0111-Unconditionally-calculate-the-PECI-AW-FCS.patch \ + file://0112-AST2600-enable-UART-routing.patch \ " SRC_URI += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', 'file://0005-128MB-flashmap-for-PFR.patch', '', d)}" |