diff options
author | Ed Tanous <ed.tanous@intel.com> | 2019-05-29 20:29:58 +0300 |
---|---|---|
committer | Ed Tanous <ed.tanous@intel.com> | 2019-06-06 04:30:22 +0300 |
commit | 87a65e63bac789bca0607e0b4ab09d62517b95e7 (patch) | |
tree | 3254b912d6468012543e127a19ba2f1cd13b108f /meta-openbmc-mods/meta-wolfpass/recipes-kernel | |
parent | 5364646cb66fa75cdcbf148e039e0383cda94f2a (diff) | |
download | openbmc-87a65e63bac789bca0607e0b4ab09d62517b95e7.tar.xz |
Update to internal
Signed-off-by: Ed Tanous <ed.tanous@intel.com>
Diffstat (limited to 'meta-openbmc-mods/meta-wolfpass/recipes-kernel')
-rw-r--r-- | meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-platforms.patch (renamed from meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-Create-intel-purley-dts.patch) | 116 | ||||
-rw-r--r-- | meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Define-the-gpio-line-names-property-for-purley-platform.patch | 63 | ||||
-rw-r--r-- | meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch | 121 | ||||
-rw-r--r-- | meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch | 70 | ||||
-rw-r--r-- | meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Leave-GPIOE-in-passthrough-after-boot.patch | 46 | ||||
-rw-r--r-- | meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed_%.bbappend | 6 |
6 files changed, 258 insertions, 164 deletions
diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-Create-intel-purley-dts.patch b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-platforms.patch index 2a3f547d5..5f8e0fd5c 100644 --- a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-Create-intel-purley-dts.patch +++ b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-platforms.patch @@ -1,44 +1,26 @@ -From 7bee096fd87485d1095c6b6940b62681ff873045 Mon Sep 17 00:00:00 2001 +From 429f3710a88d81d6875aec7a848dde96074ee8df Mon Sep 17 00:00:00 2001 From: Yuan Li <yuan.li@linux.intel.com> Date: Tue, 19 Sep 2017 15:55:39 +0800 -Subject: [PATCH] ARM: dts: purley: Merge all dts node in the unified patch. +Subject: [PATCH] arm: dts: add DTS for Intel platforms -The below changes to the dts file are merged together: -* 0006: the original one for purley -* 0008: sgpio -* 0009: peci -* 0015: leds_gpio -* 0018: kcs3 & kcs4 -* i2c4 for HSBP access -* i2c3 for PCH access -* LPC SIO device -* i2c0 for IPMB -* 12c5 bus-freq -* vuart -* uart1/serial0 -* uart2/serial1 -* uart3/serial2 -* uart4/serail3 -* enable high speed uart clock -* timer pwm -* cpu0/1fault LEDs -* i2c9 for SPD on WP / Disable beeper and timer-pwm +Add the DTS file for Intel systems. Signed-off-by: Yuan Li <yuan.li@linux.intel.com> Signed-off-by: Yong Li <yong.b.li@linux.intel.com> Signed-off-by: James Feist <james.feist@linux.intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com> --- - arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 358 ++++++++++++++++++++++++++ - 1 file changed, 358 insertions(+) + arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 388 ++++++++++++++++++++++++++ + 1 file changed, 388 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-purley.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts new file mode 100644 -index 000000000000..432f10186547 +index 0000000..20067f5 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts -@@ -0,0 +1,358 @@ +@@ -0,0 +1,388 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" @@ -80,7 +62,7 @@ index 000000000000..432f10186547 + }; + + video_engine_memory: jpegbuffer { -+ size = <0x02000000>; /* 32MM */ ++ size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; @@ -117,20 +99,12 @@ index 000000000000..432f10186547 + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; + }; -+ -+ cpu0fault { -+ gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>; -+ }; -+ -+ cpu1fault { -+ gpios = <&gpio ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>; -+ }; + }; + -+ //beeper { -+ // compatible = "pwm-beeper"; -+ // pwms = <&timer 5 1000000 0>; -+ //}; ++ beeper { ++ compatible = "pwm-beeper"; ++ pwms = <&timer 5 1000000 0>; ++ }; +}; + +&fmc { @@ -165,6 +139,36 @@ index 000000000000..432f10186547 + +&gpio { + status = "okay"; ++ gpio-line-names = ++ /*A0-A7*/ "","","","","","","","", ++ /*B0-B7*/ "","","","","","","","", ++ /*C0-C7*/ "","","","","","","","", ++ /*D0-D7*/ "","","","","","","","", ++ /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", ++ /*F0-F7*/ "","","","","","","","", ++ /*G0-G7*/ "","","","","","","","", ++ /*H0-H7*/ "","","","","","","","", ++ /*I0-I7*/ "","","","","","","","", ++ /*J0-J7*/ "","","","","","","","", ++ /*K0-K7*/ "","","","","","","","", ++ /*L0-L7*/ "","","","","","","","", ++ /*M0-M7*/ "","","","","","","","", ++ /*N0-N7*/ "","","","","","","","", ++ /*O0-O7*/ "","","","","","","","", ++ /*P0-P7*/ "","","","","","","","", ++ /*Q0-Q7*/ "","","","","","","","", ++ /*R0-R7*/ "","","","","","","","", ++ /*S0-S7*/ "","","","","","","ID_BUTTON","", ++ /*T0-T7*/ "","","","","","","","", ++ /*U0-U7*/ "","","","","","","","", ++ /*V0-V7*/ "","","","","","","","", ++ /*W0-W7*/ "","","","","","","","", ++ /*X0-X7*/ "","","","","","","","", ++ /*Y0-Y7*/ "","","","","","","","", ++ /*Z0-Z7*/ "","","","","","","","", ++ /*AA0-AA7*/ "","","","","","","","POST_COMPLETE", ++ /*AB0-AB7*/ "","","","PGOOD","","","","", ++ /*AC0-AC7*/ "","","","","","","",""; +}; + +&kcs3 { @@ -240,6 +244,8 @@ index 000000000000..432f10186547 + +&uart4 { + status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <>; +}; + +&uart5 { @@ -263,6 +269,7 @@ index 000000000000..432f10186547 + +&i2c0 { + multi-master; ++ general-call; + status = "okay"; + + ipmb0@10 { @@ -323,6 +330,11 @@ index 000000000000..432f10186547 + status = "okay"; +}; + ++&i2c13 { ++ multi-master; ++ status = "okay"; ++}; ++ +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; @@ -375,19 +387,19 @@ index 000000000000..432f10186547 + +}; + -+//&timer { -+///* -+// * Available settings: -+// * fttmr010,pwm-outputs = <5>, <6>, <7>, <8>; -+// * pinctrl-0 = <&pinctrl_timer5_default &pinctrl_timer6_default -+// * &pinctrl_timer7_default &pinctrl_timer8_default>; -+// */ -+// fttmr010,pwm-outputs = <5>; -+// pinctrl-names = "default"; -+// pinctrl-0 = <&pinctrl_timer5_default>; -+// #pwm-cells = <3>; -+// status = "okay"; -+//}; ++&timer { ++/* ++ * Available settings: ++ * fttmr010,pwm-outputs = <5>, <6>, <7>, <8>; ++ * pinctrl-0 = <&pinctrl_timer5_default &pinctrl_timer6_default ++ * &pinctrl_timer7_default &pinctrl_timer8_default>; ++ */ ++ fttmr010,pwm-outputs = <5>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_timer5_default>; ++ #pwm-cells = <3>; ++ status = "okay"; ++}; + +&video { + status = "okay"; diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Define-the-gpio-line-names-property-for-purley-platform.patch b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Define-the-gpio-line-names-property-for-purley-platform.patch deleted file mode 100644 index 7055ee575..000000000 --- a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Define-the-gpio-line-names-property-for-purley-platform.patch +++ /dev/null @@ -1,63 +0,0 @@ -From d36b385e17eb21c305200048007d3cc6ad38f072 Mon Sep 17 00:00:00 2001 -From: Kuiying Wang <kuiying.wang@intel.com> -Date: Wed, 19 Sep 2018 17:51:06 +0800 -Subject: [PATCH] Define the gpio-line-names property for purley platform - -Based on aspeed AST-2500 Datasheet and Intel Purley platform spec, -defined following gpios. - -"name": "PGOOD", "pin": "AB3"; -"name": "POWER_BUTTON", "pin": "E2"; -"name": "POWER_UP_PIN", "pin": "E3"; -"name": "RESET_BUTTON", "pin": "E0"; -"name": "RESET_OUT", "pin": "E1"; -"name": "ID_BUTTON", "pin": "S6"; - -Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> ---- - arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 29 +++++++++++++++++++++++++++ - 1 file changed, 29 insertions(+) - -diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts -index 144d59642a71..8aba46cdce46 100644 ---- a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts -+++ b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts -@@ -117,6 +117,35 @@ - - &gpio { - status = "okay"; -+ gpio-line-names = "A0","A1","A2","A3","A4","A5","A6","A7", -+ "B0","B1","B2","B3","B4","B5","B6","B7", -+ "C0","C1","C2","C3","C4","C5","C6","C7", -+ "D0","D1","D2","D3","D4","D5","D6","D7", -+ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_UP_PIN","E4","E5","E6","E7", -+ "F0","F1","F2","F3","F4","F5","F6","F7", -+ "G0","G1","G2","G3","G4","G5","G6","G7", -+ "H0","H1","H2","H3","H4","H5","H6","H7", -+ "I0","I1","I2","I3","I4","I5","I6","I7", -+ "J0","J1","J2","J3","J4","J5","J6","J7", -+ "K0","E1","E2","E3","E4","E5","E6","E7", -+ "L0","L1","L2","L3","L4","L5","L6","L7", -+ "M0","M1","M2","M3","M4","M5","M6","M7", -+ "N0","N1","N2","N3","N4","N5","N6","N7", -+ "O0","O1","O2","O3","O4","O5","O6","O7", -+ "P0","P1","P2","P3","P4","P5","P6","P7", -+ "Q0","Q1","Q2","Q3","Q4","Q5","Q6","Q7", -+ "R0","R1","R2","R3","R4","R5","R6","R7", -+ "S0","S1","S2","S3","S4","S5","ID_BUTTON","S7", -+ "T0","T1","T2","T3","T4","T5","T6","T7", -+ "U0","U1","U2","U3","U4","U5","U6","U7", -+ "V0","V1","V2","V3","V4","V5","V6","V7", -+ "W0","W1","W2","W3","W4","W5","W6","W7", -+ "X0","X1","X2","X3","X4","X5","X6","X7", -+ "Y0","Y1","Y2","Y3","Y4","Y5","Y6","Y7", -+ "Z0","Z1","Z2","Z3","Z4","Z5","Z6","Z7", -+ "AA0","AA1","AA2","AA3","AA4","AA5","AA6","AA7", -+ "AB0","AB1","AB2","PGOOD","AB4","AB5","AB6","AB7", -+ "AC0","AC1","AC2","AC3","AC4","AC5","AC6","AC7"; - }; - - &kcs3 { --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch new file mode 100644 index 000000000..b05ad2502 --- /dev/null +++ b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch @@ -0,0 +1,121 @@ +From 9537923d6e6a793cb2bf3c1daacd12562263bc0a Mon Sep 17 00:00:00 2001 +From: "Jason M. Bills" <jason.m.bills@linux.intel.com> +Date: Fri, 3 May 2019 16:12:39 -0700 +Subject: [PATCH] Enable pass-through on GPIOE1 and GPIOE3 free + +This change adds a gpio_disable_free() implementation that checks +if the GPIO being freed is GPIOE1 (33) or GPIOE3 (35) and will +re-enable the pass-through mux. + +Tested: +Requested GPIOs 33 and 35 and used devmem to check that pass-through +was disabled. Then freed them and checked that pass-through was +enabled again. + +Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com> +--- + drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1 + + drivers/pinctrl/aspeed/pinctrl-aspeed.c | 60 ++++++++++++++++++++++++++++++ + drivers/pinctrl/aspeed/pinctrl-aspeed.h | 3 ++ + 3 files changed, 64 insertions(+) + +diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +index 187abd7..beb0729 100644 +--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c ++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +@@ -2498,6 +2498,7 @@ static const struct pinmux_ops aspeed_g5_pinmux_ops = { + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, ++ .gpio_disable_free = aspeed_gpio_disable_free, + .strict = true, + }; + +diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c +index eb87ab7..f06d752 100644 +--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c ++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c +@@ -538,6 +538,66 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, + return aspeed_sig_expr_enable(expr, pdata->maps); + } + ++void aspeed_gpio_disable_free(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int offset) ++{ ++ const struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); ++ const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data; ++ const struct aspeed_sig_expr ***prios, **funcs, *expr; ++ int ret; ++ ++ /* ++ * If we're freeing GPIOE1 (33) or GPIOE3 (35) then re-enable the ++ * pass-through mux setting; otherwise, do nothing. ++ */ ++ if (offset != 33 && offset != 35) ++ return; ++ ++ dev_dbg(pctldev->dev, ++ "Freeing pass-through pin %s (%d). Re-enabling pass-through.\n", ++ pdesc->name, offset); ++ ++ if (!pdesc) ++ return; ++ ++ prios = pdesc->prios; ++ ++ if (!prios) ++ return; ++ ++ /* Disable any functions of higher priority than GPIO just in case */ ++ while (funcs = *prios) { ++ if (aspeed_gpio_in_exprs(funcs)) ++ break; ++ ++ ret = aspeed_disable_sig(funcs, pdata->maps); ++ if (ret) ++ return; ++ ++ prios++; ++ } ++ ++ if (!funcs) { ++ char *signals = get_defined_signals(pdesc); ++ ++ pr_warn("No GPIO signal type found on pin %s (%d). Found: %s\n", ++ pdesc->name, offset, signals); ++ kfree(signals); ++ ++ return; ++ } ++ ++ /* ++ * Pass-through should be one priority higher than the GPIO function, ++ * so decrement our prios and enable that function ++ */ ++ prios--; ++ funcs = *prios; ++ expr = *funcs; ++ aspeed_sig_expr_enable(expr, pdata->maps); ++} ++ + int aspeed_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *pdesc, + struct aspeed_pinctrl_data *pdata) +diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h +index d4d7f03..0037b11 100644 +--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h ++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h +@@ -595,6 +595,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset); ++void aspeed_gpio_disable_free(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int offset); + int aspeed_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *pdesc, + struct aspeed_pinctrl_data *pdata); +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch new file mode 100644 index 000000000..1d26b9667 --- /dev/null +++ b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch @@ -0,0 +1,70 @@ +From d26dd7c4ef1a2cb88440420deccc54eb88129c60 Mon Sep 17 00:00:00 2001 +From: "Jason M. Bills" <jason.m.bills@linux.intel.com> +Date: Mon, 6 May 2019 14:18:27 -0700 +Subject: [PATCH] Enable GPIOE0 and GPIOE2 pass-through by default + +This change sets the gpio DT pinctrl default configuration to +enable GPIOE0 and GPIOE2 pass-through. Since this causes +pinctrl_get_select_default() to be called automatically for +the gpio driver to claim the GPIO pins in those groups, we +also need to call pinctrl_put() to release claim on the +pass-through GPIOs so they can be requested at runtime. + +Tested: +Disabled pass-through in uboot and confirmed that after booting +Linux, pass-through is enabled and 'cat /sys/kernel/debug/pinctrl/ +1e6e2000.syscon\:pinctrl-aspeed-g5-pinctrl/pinmux-pins' shows that +the pass-through GPIOs are UNCLAIMED. + +Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com> +--- + arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 4 ++++ + drivers/gpio/gpio-aspeed.c | 10 ++++++++++ + 2 files changed, 14 insertions(+) + +diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +index 45556ac..051e927 100644 +--- a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts ++++ b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +@@ -124,6 +124,10 @@ + + &gpio { + status = "okay"; ++ /* Enable GPIOE0 and GPIOE2 pass-through by default */ ++ pinctrl-names = "pass-through"; ++ pinctrl-0 = <&pinctrl_gpie0_default ++ &pinctrl_gpie2_default>; + gpio-line-names = + /*A0-A8*/ "","","","","","","","", + /*B0-B8*/ "","","","","","","","", +diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c +index 2175070..f47d139 100644 +--- a/drivers/gpio/gpio-aspeed.c ++++ b/drivers/gpio/gpio-aspeed.c +@@ -1157,6 +1157,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) + const struct of_device_id *gpio_id; + struct aspeed_gpio *gpio; + struct resource *res; ++ struct pinctrl *pinctrl; + int rc, i, banks; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); +@@ -1205,6 +1206,15 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) + return -ENOMEM; + + /* ++ * Select the pass-through pinctrl config to enable the pass-through ++ * mux for GPIOs E0 and E2. Then call pinctrl_put() to release claim ++ * of the GPIO pins, so they can be requested at runtime. ++ */ ++ pinctrl = pinctrl_get_select(&pdev->dev, "pass-through"); ++ if (pinctrl) ++ pinctrl_put(pinctrl); ++ ++ /* + * Populate it with initial values read from the HW and switch + * all command sources to the ARM by default + */ +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Leave-GPIOE-in-passthrough-after-boot.patch b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Leave-GPIOE-in-passthrough-after-boot.patch deleted file mode 100644 index 2593ee8f6..000000000 --- a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0003-Leave-GPIOE-in-passthrough-after-boot.patch +++ /dev/null @@ -1,46 +0,0 @@ -From c11a8ffcea24352579614d13d13ac4bda9a965cf Mon Sep 17 00:00:00 2001 -From: James Feist <james.feist@linux.intel.com> -Date: Mon, 5 Nov 2018 15:38:19 -0800 -Subject: [PATCH] Leave GPIOE in passthrough after boot - -This is a temporary patch that seems to leave exported -gpio in passthrough mode. It's hard to understand why this -works because all the macros are _very_ confusing, but -SIG_DESC_SET is equal to SIG_DESC_BIT(arg1, arg2, 1) so as -a test I used SIG_DESC_BIT set to 0 for SCU8C and I noticed -the correct result for exported gpios. As of today I'm unsure -why setting 0 results in the bit being 1 and vise versa, but -as this is only a short-term fix, I don't think we really care. -This is not a long term fix, but it was a quick and easy -change that can get us the correct result in the short term. - -Signed-off-by: James Feist <james.feist@linux.intel.com> ---- - drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c -index 187abd7693cf..4230e1038a88 100644 ---- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c -+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c -@@ -246,7 +246,7 @@ FUNC_GROUP_DECL(GPID6, G18, C21); - FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); - - #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) --#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) -+#define GPIE0_DESC SIG_DESC_BIT(SCU8C, 12, 0) - - #define B20 32 - SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); -@@ -266,7 +266,7 @@ FUNC_GROUP_DECL(NDCD3, C20); - - FUNC_GROUP_DECL(GPIE0, B20, C20); - --#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) -+#define GPIE2_DESC SIG_DESC_BIT(SCU8C, 13, 0) - - #define F18 34 - SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed_%.bbappend b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed_%.bbappend index 7a386c848..782fc6532 100644 --- a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed_%.bbappend @@ -1,8 +1,8 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/linux-aspeed:" SRC_URI += "file://wolfpass.cfg \ - file://0001-Create-intel-purley-dts.patch \ - file://0002-Define-the-gpio-line-names-property-for-purley-platform.patch \ - file://0003-Leave-GPIOE-in-passthrough-after-boot.patch \ + file://0001-arm-dts-add-DTS-for-Intel-platforms.patch \ + file://0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch \ + file://0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch \ file://0004-Test-code-for-LPC-MBOX.patch \ " SRC_URI += "${@bb.utils.contains('IMAGE_TYPE', 'pfr', 'file://0005-128MB-flashmap-for-PFR.patch', '', d)}" |