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| author | Jason M. Bills <jason.m.bills@linux.intel.com> | 2019-10-28 20:16:02 +0300 |
|---|---|---|
| committer | Jason M. Bills <jason.m.bills@linux.intel.com> | 2019-10-28 20:16:02 +0300 |
| commit | da710c8bb0dea17982efc20ab4ee226a86992e6f (patch) | |
| tree | 06c83c9e85c881f40532972aaa1453298236e029 /meta-openembedded/meta-oe/recipes-multimedia/jack/a2jmidid/riscv_ucontext.patch | |
| parent | 6656af78e6c7b48a1252459a61b3b72dce77ab44 (diff) | |
| parent | 2795589128d1f7509ac0ab9eba940d868413ac7d (diff) | |
| download | openbmc-da710c8bb0dea17982efc20ab4ee226a86992e6f.tar.xz | |
Merge branch 'master' of ssh://git-amr-1.devtools.intel.com:29418/openbmc-openbmc into update
Diffstat (limited to 'meta-openembedded/meta-oe/recipes-multimedia/jack/a2jmidid/riscv_ucontext.patch')
| -rw-r--r-- | meta-openembedded/meta-oe/recipes-multimedia/jack/a2jmidid/riscv_ucontext.patch | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/meta-openembedded/meta-oe/recipes-multimedia/jack/a2jmidid/riscv_ucontext.patch b/meta-openembedded/meta-oe/recipes-multimedia/jack/a2jmidid/riscv_ucontext.patch new file mode 100644 index 000000000..23618f18a --- /dev/null +++ b/meta-openembedded/meta-oe/recipes-multimedia/jack/a2jmidid/riscv_ucontext.patch @@ -0,0 +1,24 @@ +Add riscv specific checks to choose correct gregs and context structure definitions + +Upstream-Status: Pending +Signed-off-by: Khem Raj <raj.khem@gmail.com> +--- a/sigsegv.c ++++ b/sigsegv.c +@@ -91,7 +91,7 @@ static void signal_segv(int signum, sigi + a2j_error("info.si_errno = %d", info->si_errno); + a2j_error("info.si_code = %d (%s)", info->si_code, si_codes[info->si_code]); + a2j_error("info.si_addr = %p", info->si_addr); +-#if !defined(__alpha__) && !defined(__ia64__) && !defined(__FreeBSD_kernel__) && !defined(__arm__) && !defined(__hppa__) && !defined(__sh__) && !defined(__aarch64__) ++#if !defined(__alpha__) && !defined(__ia64__) && !defined(__FreeBSD_kernel__) && !defined(__arm__) && !defined(__hppa__) && !defined(__sh__) && !defined(__aarch64__) && !defined(__riscv) + for(i = 0; i < NGREG; i++) + a2j_error("reg[%02d] = 0x" REGFORMAT, i, + #if defined(__powerpc__) +@@ -102,7 +102,7 @@ static void signal_segv(int signum, sigi + ucontext->uc_mcontext.gregs[i] + #endif + ); +-#endif /* alpha, ia64, kFreeBSD, arm, hppa aarch64 */ ++#endif /* alpha, ia64, kFreeBSD, arm, hppa aarch64 riscv */ + + #if defined(SIGSEGV_STACK_X86) || defined(SIGSEGV_STACK_IA64) + # if defined(SIGSEGV_STACK_IA64) |