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author | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-12-08 00:38:17 +0300 |
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committer | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-12-08 00:38:17 +0300 |
commit | 8d6ae7f2a817751fad151168fa10ce28ee0869d8 (patch) | |
tree | 281032f7ec07c41589aa094bd165cc2a98f2d3a7 /meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch | |
parent | c16fb8893b19075db4bcf3b5bf33c1db8c3ca2bd (diff) | |
parent | 5da3c2284560a7e08ffafd03c5b5ba44a3242228 (diff) | |
download | openbmc-8d6ae7f2a817751fad151168fa10ce28ee0869d8.tar.xz |
Merge tag '0.26' of ssh://git-amr-1.devtools.intel.com:29418/openbmc-openbmc into update
Diffstat (limited to 'meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch')
-rw-r--r-- | meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch new file mode 100644 index 000000000..b9e39928d --- /dev/null +++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch @@ -0,0 +1,49 @@ +From 9da28a01ffb778fc5cb5df27332cef21f890a63f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 12 Jan 2017 16:52:56 +0530 +Subject: [PATCH 12/58] [Patch, microblaze]: Added ashrsi3_with_size_opt + +Added ashrsi3_with_size_opt pattern to optimize the sra instructions +when the -Os optimization is used. lshrsi3_with_size_opt is +being removed as it has conflicts with unsigned int variables + +Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> +--- + gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index eba2776ae56..187ad522dcc 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1508,6 +1508,27 @@ + (set_attr "length" "4,4")] + ) + ++(define_insn "*ashrsi3_with_size_opt" ++ [(set (match_operand:SI 0 "register_operand" "=&d") ++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "immediate_operand" "I")))] ++ "(INTVAL (operands[2]) > 5 && optimize_size)" ++ { ++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("ori\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addik\t%3,%3,-1", operands); ++ output_asm_insn ("bneid\t%3,.-4", operands); ++ return "sra\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "20")] ++) ++ + (define_insn "*ashrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +-- +2.17.1 + |