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author | Andrew Geissler <geissonator@yahoo.com> | 2020-12-12 01:25:29 +0300 |
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committer | Andrew Geissler <geissonator@yahoo.com> | 2020-12-12 01:25:34 +0300 |
commit | 10fa14942b9cb27780f9496382107516639208b4 (patch) | |
tree | f4b195505178e47c4b21ece7b3a898d9402b2daa /meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch | |
parent | 6d8913e6c02e578d4e41b7fe88113f4e4822992d (diff) | |
download | openbmc-10fa14942b9cb27780f9496382107516639208b4.tar.xz |
meta-xilinx: subtree update:569f52f275..b3e37df5d9
Mark Hatle (11):
meta-microblaze: Move gcc patch that was missed in the prior work
Uprev standalone toolchain bbappends
pmu-firmware: Latest toolchain always treats 'assert' as a macro
binutils: update to early gatesgarth version
gdb: update to early gatesgarth version
gcc: update to early gatesgarth version
newlib: update to early gatesgarth version
machine/aarch64-tc.conf: Fix incorrect ilp32 pkgarch
libgcc.bbappend: Clear empty lib directory
newlib: Upstream now disabled builtin symbols
gdb: Fix on-target GDB compilation
Sai Hari Chandana Kalluri (5):
linux-xlnx_2020.2: Fix previous git cherry-pick
xrt: Remove stale patch to fix endian issues with latest version of boost
opencl-clhpp, ocl-icd: Remove recipes from meta-xilinx
esw.bbclass: Remove trailing / after S
Remove recipe bbappends pointing to older versions
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: I18b028388a5b55a49ef135b98290228fa797e38d
Diffstat (limited to 'meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch')
-rw-r--r-- | meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch | 143 |
1 files changed, 0 insertions, 143 deletions
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch deleted file mode 100644 index dfdb479cd..000000000 --- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch +++ /dev/null @@ -1,143 +0,0 @@ -From 341bf8ad4e55693d00d4d8c916f4c347e7186dd4 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Wed, 18 Jan 2017 12:14:51 +0530 -Subject: [PATCH 29/58] [Patch, microblaze]: Add new bit-field instructions - -This patches adds new bsefi and bsifi instructions. -BSEFI- The instruction shall extract a bit field from a -register and place it right-adjusted in the destination register. -The other bits in the destination register shall be set to zero -BSIFI- The instruction shall insert a right-adjusted bit field -from a register at another position in the destination register. -The rest of the bits in the destination register shall be unchanged - -Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> - -ChangeLog: - 2016-02-03 Nagaraju Mekala <nmekala@xilix.com> - - *microblaze.md (Update): Added new patterns ---- - gcc/config/microblaze/microblaze.h | 2 + - gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++ - 2 files changed, 75 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 8b0db2c1718..b5b7b22cec9 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; - - extern int microblaze_no_unsafe_delay; - extern int microblaze_has_clz; -+extern int microblaze_has_bitfield; - extern enum pipeline_type microblaze_pipe; - - #define OBJECT_FORMAT_ELF -@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe; - - /* Do we have CLZ? */ - #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz) -+#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield) - - /* The default is to support PIC. */ - #define TARGET_SUPPORTS_PIC 1 -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index c407a81c51e..fa6aabdb9d4 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -982,6 +982,8 @@ - (set_attr "mode" "DI") - (set_attr "length" "20,20,20")]) - -+ -+ - ;;---------------------------------------------------------------- - ;; Data movement - ;;---------------------------------------------------------------- -@@ -1776,6 +1778,7 @@ - (set_attr "length" "28")] - ) - -+ - ;;---------------------------------------------------------------- - ;; Setting a register from an integer comparison. - ;;---------------------------------------------------------------- -@@ -2489,4 +2492,74 @@ - DONE; - }") - -+(define_expand "extvsi" -+ [(set (match_operand:SI 0 "register_operand" "r") -+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "I") -+ (match_operand:SI 3 "immediate_operand" "I")))] -+"TARGET_HAS_BITFIELD" -+" -+{ -+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); -+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); -+ -+ if ((len == 0) || (pos + len > 32) ) -+ FAIL; -+ -+ ;;if (!register_operand (operands[1], VOIDmode)) -+ ;; FAIL; -+ if (operands[0] == operands[1]) -+ FAIL; -+ if (GET_CODE (operands[1]) == ASHIFT) -+ FAIL; -+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); -+ emit_insn (gen_extv_32 (operands[0], operands[1], -+ operands[2], operands[3])); -+ DONE; -+}") -+ -+(define_insn "extv_32" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "I") -+ (match_operand:SI 3 "immediate_operand" "I")))] -+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0) -+ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" -+ "bsefi %0,%1,%2,%3" -+ [(set_attr "type" "bshift") -+ (set_attr "length" "4")]) -+ -+(define_expand "insvsi" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (match_operand:SI 1 "immediate_operand" "I") -+ (match_operand:SI 2 "immediate_operand" "I")) -+ (match_operand:SI 3 "register_operand" "r"))] -+ "TARGET_HAS_BITFIELD" -+ " -+{ -+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); -+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); -+ -+ if (len <= 0 || pos + len > 32) -+ FAIL; -+ -+ ;;if (!register_operand (operands[0], VOIDmode)) -+ ;; FAIL; -+ -+ emit_insn (gen_insv_32 (operands[0], operands[1], -+ operands[2], operands[3])); -+ DONE; -+}") -+ -+(define_insn "insv_32" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (match_operand:SI 1 "immediate_operand" "I") -+ (match_operand:SI 2 "immediate_operand" "I")) -+ (match_operand:SI 3 "register_operand" "r"))] -+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0 -+ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" -+ "bsifi %0, %3, %1, %2" -+ [(set_attr "type" "bshift") -+ (set_attr "length" "4")]) -+ - (include "sync.md") --- -2.17.1 - |