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author | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-12-08 00:38:17 +0300 |
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committer | Jason M. Bills <jason.m.bills@linux.intel.com> | 2020-12-08 00:38:17 +0300 |
commit | 8d6ae7f2a817751fad151168fa10ce28ee0869d8 (patch) | |
tree | 281032f7ec07c41589aa094bd165cc2a98f2d3a7 /meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch | |
parent | c16fb8893b19075db4bcf3b5bf33c1db8c3ca2bd (diff) | |
parent | 5da3c2284560a7e08ffafd03c5b5ba44a3242228 (diff) | |
download | openbmc-8d6ae7f2a817751fad151168fa10ce28ee0869d8.tar.xz |
Merge tag '0.26' of ssh://git-amr-1.devtools.intel.com:29418/openbmc-openbmc into update
Diffstat (limited to 'meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch')
-rw-r--r-- | meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch new file mode 100644 index 000000000..458af563b --- /dev/null +++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch @@ -0,0 +1,80 @@ +From 3e8779308d1901b273b2b360bea719aa72d24ab9 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 19 Feb 2018 18:06:16 +0530 +Subject: [PATCH 32/58] [Patch,Microblaze]: update in constraints for bitfield + insert and extract instructions. + +--- + gcc/config/microblaze/microblaze.md | 43 +++++------------------------ + 1 file changed, 7 insertions(+), 36 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 9de46d0ce24..fe94807182b 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2492,33 +2492,17 @@ + DONE; + }") + +-(define_expand "extvsi" ++(define_expand "extzvsi" + [(set (match_operand:SI 0 "register_operand" "r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") + (match_operand:SI 3 "immediate_operand" "I")))] + "TARGET_HAS_BITFIELD" +-" +-{ +- unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); +- unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); +- +- if ((len == 0) || (pos + len > 32) ) +- FAIL; +- +- ;;if (!register_operand (operands[1], VOIDmode)) +- ;; FAIL; +- if (operands[0] == operands[1]) +- FAIL; +- if (GET_CODE (operands[1]) == ASHIFT) +- FAIL; +-;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); +- emit_insn (gen_extv_32 (operands[0], operands[1], +- operands[2], operands[3])); +- DONE; +-}") ++"" ++) + +-(define_insn "extv_32" ++ ++(define_insn "extzv_32" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") +@@ -2535,21 +2519,8 @@ + (match_operand:SI 2 "immediate_operand" "I")) + (match_operand:SI 3 "register_operand" "r"))] + "TARGET_HAS_BITFIELD" +- " +-{ +- unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); +- unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); +- +- if (len <= 0 || pos + len > 32) +- FAIL; +- +- ;;if (!register_operand (operands[0], VOIDmode)) +- ;; FAIL; +- +- emit_insn (gen_insv_32 (operands[0], operands[1], +- operands[2], operands[3])); +- DONE; +-}") ++"" ++) + + (define_insn "insv_32" + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") +-- +2.17.1 + |