diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch | 30 |
1 files changed, 24 insertions, 6 deletions
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch index 40336d3dd..5e459b85d 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch @@ -1,7 +1,7 @@ -From dff3a123b0318f83ecd753eea8945ebdc15fd2f9 Mon Sep 17 00:00:00 2001 +From 1752e8b935996fe9359ba4990156d9b57d7a7b8e Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 10:21:40 -0800 -Subject: [PATCH 1/1] Add espi support +Subject: [PATCH] Add espi support This adds basic eSPI support for U-Boot. The eSPI driver works best with interrupts because the timing of the initialization with the PCH is not @@ -13,13 +13,15 @@ functions. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: James Feist <james.feist@linux.intel.com> +Signed-off-by: Saravanan Palanisamy <saravanan.palanisamy@intel.com> +Signed-off-by: Richard Marian Thomaiyar <richard.marian.thomaiyar@linux.intel.com> --- arch/arm/include/asm/arch-aspeed/regs-scu.h | 2 + board/aspeed/ast-g5/Makefile | 2 + - board/aspeed/ast-g5/ast-g5-espi.c | 248 ++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-espi.c | 264 ++++++++++++++++++++ board/aspeed/ast-g5/ast-g5-intel.c | 16 ++ board/aspeed/ast-g5/ast-g5.c | 3 + - 5 files changed, 271 insertions(+) + 5 files changed, 287 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-espi.c create mode 100644 board/aspeed/ast-g5/ast-g5-intel.c @@ -47,10 +49,10 @@ index df4e63966e..58e0c648f4 100644 obj-y += ast-g5-irq.o diff --git a/board/aspeed/ast-g5/ast-g5-espi.c b/board/aspeed/ast-g5/ast-g5-espi.c new file mode 100644 -index 0000000000..5a3ffe7bef +index 0000000000..3f169d4141 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-espi.c -@@ -0,0 +1,248 @@ +@@ -0,0 +1,264 @@ +/* + * Copyright 2018 Intel Corporation + * @@ -186,6 +188,22 @@ index 0000000000..5a3ffe7bef + uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; + writel(v, AST_ESPI_BASE + ESPI104); + } ++ ++ if (readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_HOST_RST_WARN) { ++ DBG_ESPI("Boot HOST_RST WARN set %08x\n", ++ readl(AST_ESPI_BASE + ESPI098)); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) ++ | AST_ESPI_HOST_RST_ACK; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ } ++ ++ if (readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_OOB_RST_WARN) { ++ DBG_ESPI("Boot OOB_RST WARN set %08x\n", ++ readl(AST_ESPI_BASE + ESPI098)); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) ++ | AST_ESPI_OOB_RST_ACK; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ } +} + +static int espi_irq_handler(struct pt_regs *regs) |