diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0042-Disable-PCIe-L1-settings-for-BrightonCity-BRC.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0042-Disable-PCIe-L1-settings-for-BrightonCity-BRC.patch | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0042-Disable-PCIe-L1-settings-for-BrightonCity-BRC.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0042-Disable-PCIe-L1-settings-for-BrightonCity-BRC.patch new file mode 100644 index 000000000..2b11ae8fe --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0042-Disable-PCIe-L1-settings-for-BrightonCity-BRC.patch @@ -0,0 +1,100 @@ +From 8d94d9f394b37ca4d40103f0f71c7f9a495303fb Mon Sep 17 00:00:00 2001 +From: Saravanan Palanisamy <saravanan.palanisamy@intel.com> +Date: Fri, 7 Feb 2020 15:16:16 +0000 +Subject: [PATCH] Disable PCIe L1 settings for BrightonCity (BRC). + +PCIe L1 settings are enabled very early during boot (platform_g5.S). +PCH used in BrightonCity can not support this power mode and +BRC's VGA functionality is not working, if enabled. +Disable PCIe L1 for BRC platform when platform id can be +computed after GPIOs initialization. + +Tested: +1.) Checked BrightonCity VGA works fine with PFR and non-PFR image. +2.) Checked WilsonCity VGA works fine with PFR and non-PFR image. + +Change-Id: I86ad134adc26334a0a168c1b7ab461859eb5af08 +Signed-off-by: Saravanan Palanisamy <saravanan.palanisamy@intel.com> +--- + board/aspeed/ast-g5/ast-g5-intel.c | 30 +++++++++++++++++++++++++++++- + 1 file changed, 29 insertions(+), 1 deletion(-) + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index 6c193d8afb..775c7947cd 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -127,6 +127,14 @@ static const GPIOValue gpio_table[] = { + /* HICRB Bits */ + #define HICRB_EN80HSGIO (1 << 13) /* Enable 80hSGIO */ + ++/* PCI Express Configuration Registers. */ ++#define PCI_CONFIG_LOCK_KEY 0x0 ++#define PCI_CONFIG_UNLOCK_KEY 0xa8 ++#define PCI_PWR_CTRL_REG_OFFSET 0x7c ++#define PCI_L1_CONFIG_REG_OFFSET 0x68 ++#define PCI_L1_ENABLE_VALUE 0xc81f0a ++#define PCI_L1_DISABLE_VALUE 0xc807fa ++ + #define SGPIO_CLK_DIV(N) ((N) << 16) + #define SGPIO_BYTES(N) ((N) << 6) + #define SGPIO_ENABLE 1 +@@ -138,6 +146,7 @@ static const GPIOValue gpio_table[] = { + #define WATCHDOG_RESET_BIT 0x8 + #define BOOT_FAILURE_LIMIT 0x3 + ++#define BRIGHTON_CITY_BOARD_ID 0 + #define COOPER_CITY_BOARD_ID 40 + + static int get_boot_failures(void) +@@ -154,6 +163,18 @@ static void set_boot_failures(u32 count) + saveenv(); + } + ++static inline void pcie_l1_disable() ++{ ++ /* Unlock Power Management registers. */ ++ writel(PCI_CONFIG_UNLOCK_KEY, ++ AST_PCIE_PLDA_BASE + PCI_PWR_CTRL_REG_OFFSET); ++ /* Disable PCIe L1. */ ++ writel(PCI_L1_DISABLE_VALUE, ++ AST_PCIE_PLDA_BASE + PCI_L1_CONFIG_REG_OFFSET); ++ /* Relock the registers. */ ++ writel(PCI_CONFIG_LOCK_KEY, ++ AST_PCIE_PLDA_BASE + PCI_PWR_CTRL_REG_OFFSET); ++} + + static void sgpio_init(void) + { +@@ -660,6 +681,8 @@ extern void espi_init(void); + extern void kcs_init(void); + void ast_g5_intel(void) + { ++ int platform_id; ++ + /* Disable uart port debug function */ + ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | + SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); +@@ -668,6 +691,11 @@ void ast_g5_intel(void) + mailbox_init(); + pwm_init(); + gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); ++ platform_id = intel_get_platform_id(); ++ /* PCH used in BrightonCity does not support PCIe L1. */ ++ if (platform_id == BRIGHTON_CITY_BOARD_ID) ++ pcie_l1_disable(); ++ + espi_init(); + sgpio_init(); + timer8_init(); +@@ -678,7 +706,7 @@ void ast_g5_intel(void) + id_led_control(GPIO_GREEN_LED, EIDLED_Off); + id_led_control(GPIO_AMBER_LED, EIDLED_On); + kcs_init(); +- if (intel_get_platform_id() == COOPER_CITY_BOARD_ID) ++ if (platform_id == COOPER_CITY_BOARD_ID) + set_pwm_duty_cycle(ELEVATED_PWM_DUTY_VALUE); + /* TODO: need to stop the booting here. */ + } +-- +2.17.1 + |