diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch')
-rw-r--r-- | meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch | 185 |
1 files changed, 52 insertions, 133 deletions
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch index d52b1184a..4de12fd82 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch @@ -1,4 +1,4 @@ -From cc144438f78be5de8e9a67fd8cc898123e32d266 Mon Sep 17 00:00:00 2001 +From bd79f95696957ee1e63e4506e7f4d0693b7d1c6a Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Mon, 14 Sep 2020 17:38:28 -0700 Subject: [PATCH] Add WDT to u-boot to cover booting failures @@ -13,150 +13,69 @@ timeout is 100 seconds. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - arch/arm/mach-aspeed/platform_g5.S | 78 ++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-intel.c | 3 ++ - board/aspeed/ast-g5/ast-g5.c | 30 +++++++++++- - common/bootm_os.c | 5 ++ - 4 files changed, 114 insertions(+), 2 deletions(-) + arch/arm/mach-aspeed/flash.c | 7 +++++++ + arch/arm/mach-aspeed/platform_g5.S | 13 +++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 3 +++ + board/aspeed/ast-g5/ast-g5.c | 30 ++++++++++++++++++++++++++++-- + common/bootm_os.c | 5 +++++ + 5 files changed, 56 insertions(+), 2 deletions(-) +diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c +index d33fb9e0fe78..31bbf77e9e67 100644 +--- a/arch/arm/mach-aspeed/flash.c ++++ b/arch/arm/mach-aspeed/flash.c +@@ -30,6 +30,7 @@ + #include <asm/byteorder.h> + #include <asm/io.h> + #include <environment.h> ++#include <watchdog.h> + + #include <asm/arch/ast_scu.h> + #include <asm/arch/aspeed.h> +@@ -610,6 +611,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) + } + + putc ('.'); ++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) ++ WATCHDOG_RESET(); ++#endif + } + } + puts (" done\n"); +@@ -679,6 +683,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) + src += count; + cnt -= count; + printf("%c\b", pat[(patcnt++) & 0x03]); ++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) ++ WATCHDOG_RESET(); ++#endif + } + + reset_flash(info); diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S -index f221c97b19dc..e468ed68d687 100644 +index f221c97b19dc..3a06557fa99d 100644 --- a/arch/arm/mach-aspeed/platform_g5.S +++ b/arch/arm/mach-aspeed/platform_g5.S -@@ -582,6 +582,31 @@ espi_early_init_done: +@@ -582,6 +582,19 @@ espi_early_init_done: mov r1, #0xAE str r1, [r0] +#ifdef CONFIG_HW_WATCHDOG -+ /* Enable WDT1 to recover u-boot hang */ -+ ldr r0, =0x1e785004 ++ /* Enable WDT2 to recover u-boot hang */ ++ ldr r0, =0x1e785024 + ldr r1, =0x00500000 @ ~5 seconds + str r1, [r0] -+ ldr r0, =0x1e785008 ++ ldr r0, =0x1e785028 + ldr r1, =0x00004755 + str r1, [r0] -+ ldr r0, =0x1e78500c ++ ldr r0, =0x1e78502c + ldr r1, =0x00000033 + str r1, [r0] -+ -+ /* Clear Scratch register Bit 6 to do DDR training again on WDT1 reset */ -+ ldr r0, =0x1e6e203c -+ ldr r1, [r0] -+ tst r1, #(1<<2) -+ beq bypass_scratch_reg_clear -+ ldr r0, =0x1e6e2040 -+ ldr r1, [r0] -+ and r1, r1, #0xFFFFFFBF -+ str r1, [r0] -+ -+bypass_scratch_reg_clear: +#endif + /* Test - DRAM initial time */ ldr r0, =0x1e78203c ldr r1, =0x0000F000 -@@ -2335,6 +2360,13 @@ spi_checksum_wait_0: - ldr r1, [r0] - tst r1, r2 - beq spi_checksum_wait_0 -+ -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x31 @ '1' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - ldr r0, =0x1e620090 - ldr r5, [r0] @ record golden checksum - ldr r0, =0x1e620080 -@@ -2363,6 +2395,13 @@ spi_checksum_wait_1: - ldr r1, [r0] - tst r1, r2 - beq spi_checksum_wait_1 -+ -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - ldr r0, =0x1e620090 - ldr r2, [r0] @ read checksum - ldr r0, =0x1e620080 -@@ -2377,6 +2416,13 @@ spi_checksum_wait_2: - ldr r1, [r0] - tst r1, r2 - beq spi_checksum_wait_2 -+ -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - ldr r0, =0x1e620090 - ldr r2, [r0] @ read checksum - ldr r0, =0x1e620080 -@@ -2394,6 +2440,12 @@ spi_cbr_next_delay_e: - blt spi_cbr_next_delay_s - b spi_cbr_next_clkrate - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - spi_cbr_end: - ldr r0, =0x1e620094 - str r8, [r0] -@@ -2401,6 +2453,16 @@ spi_cbr_end: - mov r1, #0x0 - str r1, [r0] - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x32 @ '2' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - /****************************************************************************** - Miscellaneous Setting - ******************************************************************************/ -@@ -2447,6 +2509,16 @@ spi_cbr_end: - mov r1, #0 - str r1, [r0] - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x33 @ '3' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - /****************************************************************************** - Configure MAC timing - ******************************************************************************/ -@@ -2535,6 +2607,12 @@ set_D2PLL: - ldr r1, =0xEA - str r1, [r0] - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x34 @ '4' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - /* restore lr */ - mov lr, r4 - diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c index c46bd70b71b2..92518a66fa67 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c @@ -192,25 +111,25 @@ index 00bd92ae5f94..3f27503bce62 100644 { - /* Restart WD2 timer */ - writel(0x4755, AST_WDT2_BASE + 0x08); -+ /* Restart WDT1 */ ++ /* Restart WDT2 */ + writel(AST_WDT_RESTART_VALUE, -+ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++ AST_WDT2_BASE + AST_WDT_COUNTER_RESTART_CTRL); +} + +void hw_watchdog_init(void) +{ -+ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); ++ writel(0, AST_WDT2_BASE + AST_WDT_CTRL); + writel(AST_WDT_TIMEOUT_DEFAULT, -+ AST_WDT1_BASE + AST_WDT_COUNTER_RELOAD_VALUE); ++ AST_WDT2_BASE + AST_WDT_COUNTER_RELOAD_VALUE); + writel(AST_WDT_RESTART_VALUE, -+ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++ AST_WDT2_BASE + AST_WDT_COUNTER_RESTART_CTRL); + writel(AST_WDT_EN_1MHZ_CLK | AST_WDT_SYS_RESET | AST_WDT_ENABLE, -+ AST_WDT1_BASE + AST_WDT_CTRL); ++ AST_WDT2_BASE + AST_WDT_CTRL); +} + +void hw_watchdog_disable(void) +{ -+ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); ++ writel(0, AST_WDT2_BASE + AST_WDT_CTRL); } #endif /* CONFIG_WATCHDOG */ diff --git a/common/bootm_os.c b/common/bootm_os.c |