diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2500')
36 files changed, 8646 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-ast2500/conf/layer.conf b/meta-openbmc-mods/meta-ast2500/conf/layer.conf new file mode 100644 index 000000000..99ca15d28 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/conf/layer.conf @@ -0,0 +1,21 @@ +LOCALCONF_VERSION = "3" +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "ast2500" +BBFILE_PATTERN_ast2500 = "" +BBFILE_PRIORITY_ast2500 = "6" +LAYERSERIES_COMPAT_ast2500 = "warrior" + +INHERIT += "extrausers" +#INHERIT += " cve-check" + +EXTRA_USERS_PARAMS_append_pn-intel-platforms = " \ + usermod -p '\$1\$UGMqyqdG\$FZiylVFmRRfl9Z0Ue8G7e/' root; \ + " + +hostname_pn-base-files = "intel-obmc" diff --git a/meta-openbmc-mods/meta-ast2500/conf/machine/include/intel-ast2500.inc b/meta-openbmc-mods/meta-ast2500/conf/machine/include/intel-ast2500.inc new file mode 100644 index 000000000..cc9e30495 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/conf/machine/include/intel-ast2500.inc @@ -0,0 +1,19 @@ +KMACHINE = "aspeed" +KERNEL_DEVICETREE = "${KMACHINE}-bmc-intel-purley.dtb" + +require conf/machine/include/ast2500.inc +require conf/machine/include/obmc-bsp-si-common.inc +require conf/machine/include/intel.inc +require conf/distro/include/phosphor-tiny.inc + +UBOOT_MACHINE = "ast_g5_phy_config" + +#Developer to specify the appropriate IMAGE_TYPE and FLASH_SIZE +#On Intel Whitley platforms PFR feature requires 128MB flash, default is 64MB +#IMAGE_TYPE = "default" or "pfr" or "non-pfr" +# "non-pfr" setting for future which is for BMC secure boot +#for PFR its 128MB in KBs - 128*1024=131072, for non-pfr its 64MB= 64*1024 = 65536 +#pfr IMAGE_TYPE enforces the image signature verification during the image update +IMAGE_TYPE = "default" + +VIRTUAL-RUNTIME_skeleton_workbook = "${MACHINE}-config" diff --git a/meta-openbmc-mods/meta-ast2500/conf/machine/include/obmc-bsp-si-common.inc b/meta-openbmc-mods/meta-ast2500/conf/machine/include/obmc-bsp-si-common.inc new file mode 100644 index 000000000..24ec3113b --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/conf/machine/include/obmc-bsp-si-common.inc @@ -0,0 +1,31 @@ +#@TYPE: Machine +#@NAME: OpenBMC +#@DESCRIPTION: Common machine configuration for OpenBMC chips + +MACHINE_EXTRA_RRECOMMENDS = " kernel-modules" +EXTRA_IMAGEDEPENDS += "u-boot" + +IMAGE_FSTYPES += "squashfs-xz" +IMAGE_FSTYPES += "mtd-auto" +INITRAMFS_FSTYPES = "squashfs-xz" +EXTRA_IMAGECMD_squashfs-xz_append = "-processors ${BB_NUMBER_THREADS} -b 262144 -Xdict-size 100% -Xbcj arm" + +KERNEL_CLASSES ?= "kernel-fitimage" +KERNEL_IMAGETYPES ?= "fitImage" +KERNEL_EXTRA_ARGS += "LOADADDR=${UBOOT_ENTRYPOINT}" + +UBOOT_SUFFIX ?= "bin" + +MACHINEOVERRIDES =. "openbmc:" + +OBMC_PHOSPHOR_IMAGE_OVERLAY= "1" +OBMC_IMAGE_EXTRA_INSTALL_append = " u-boot-fw-utils-aspeed" + +IMAGE_CLASSES += "image_types image_types_phosphor_auto" + +INITRAMFS_CTYPE ?= "lzma" +INITRAMFS_IMAGE = "obmc-phosphor-initramfs" + +MACHINE_FEATURES_BACKFILL_CONSIDERED = "qemu-usermode" + +KERNEL_IMAGETYPES += "zImage" diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-platforms.patch b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-platforms.patch new file mode 100644 index 000000000..978489110 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-platforms.patch @@ -0,0 +1,414 @@ +From fbbad6c3a18ec7f1e9d95c09e44e765de303329c Mon Sep 17 00:00:00 2001 +From: Yuan Li <yuan.li@linux.intel.com> +Date: Tue, 19 Sep 2017 15:55:39 +0800 +Subject: [PATCH] arm: dts: add DTS for Intel platforms + +Add the DTS file for Intel systems. + +Signed-off-by: Yuan Li <yuan.li@linux.intel.com> +Signed-off-by: Yong Li <yong.b.li@linux.intel.com> +Signed-off-by: James Feist <james.feist@linux.intel.com> +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com> +--- + arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 388 ++++++++++++++++++++++++++ + 1 file changed, 388 insertions(+) + create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-purley.dts + +diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +new file mode 100644 +index 0000000..421699c +--- /dev/null ++++ b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +@@ -0,0 +1,388 @@ ++/dts-v1/; ++ ++#include "aspeed-g5.dtsi" ++#include <dt-bindings/gpio/aspeed-gpio.h> ++#include <dt-bindings/i2c/i2c.h> ++ ++/ { ++ model = "Purley BMC"; ++ compatible = "intel,purley-bmc", "aspeed,ast2500"; ++ ++ aliases { ++ serial4 = &uart5; ++ }; ++ ++ chosen { ++ stdout-path = &uart5; ++ bootargs = "console=ttyS4,115200 earlyprintk"; ++ }; ++ ++ memory@80000000 { ++ reg = <0x80000000 0x20000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ vga_memory: framebuffer@7f000000 { ++ no-map; ++ reg = <0x7f000000 0x01000000>; ++ }; ++ ++ gfx_memory: framebuffer { ++ size = <0x01000000>; ++ alignment = <0x01000000>; ++ compatible = "shared-dma-pool"; ++ reusable; ++ }; ++ ++ video_engine_memory: jpegbuffer { ++ size = <0x02000000>; /* 32M */ ++ alignment = <0x01000000>; ++ compatible = "shared-dma-pool"; ++ reusable; ++ }; ++ }; ++ ++ vga-shared-memory { ++ compatible = "aspeed,ast2500-vga-sharedmem"; ++ reg = <0x9ff00000 0x100000>; ++ }; ++ ++ iio-hwmon { ++ compatible = "iio-hwmon"; ++ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, ++ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, ++ <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, ++ <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ identify { ++ default-state = "off"; ++ gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; ++ }; ++ ++ status_amber { ++ default-state = "off"; ++ gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; ++ }; ++ ++ status_green { ++ default-state = "keep"; ++ gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ beeper { ++ compatible = "pwm-beeper"; ++ pwms = <&timer 5 1000000 0>; ++ }; ++}; ++ ++&fmc { ++ status = "okay"; ++ flash@0 { ++ status = "okay"; ++ m25p,fast-read; ++#include "openbmc-flash-layout-intel-64MB.dtsi" ++ }; ++}; ++ ++&espi { ++ status = "okay"; ++}; ++ ++&jtag { ++ status = "okay"; ++}; ++ ++&peci0 { ++ status = "okay"; ++}; ++ ++&syscon { ++ uart-clock-high-speed; ++ status = "okay"; ++}; ++ ++&adc { ++ status = "okay"; ++}; ++ ++&gpio { ++ status = "okay"; ++ gpio-line-names = ++ /*A0-A7*/ "","","","","","","","", ++ /*B0-B7*/ "","","","","","","","", ++ /*C0-C7*/ "","","","","","","","", ++ /*D0-D7*/ "","","","","","","","", ++ /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", ++ /*F0-F7*/ "","","","","","","","", ++ /*G0-G7*/ "","","","","","","","", ++ /*H0-H7*/ "","","","","","","","", ++ /*I0-I7*/ "","","","","","","","", ++ /*J0-J7*/ "","","","","","","","", ++ /*K0-K7*/ "","","","","","","","", ++ /*L0-L7*/ "","","","","","","","", ++ /*M0-M7*/ "","","","","","","","", ++ /*N0-N7*/ "","","","","","","","", ++ /*O0-O7*/ "","","","","","","","", ++ /*P0-P7*/ "","","","","","","","", ++ /*Q0-Q7*/ "","","","","","","","", ++ /*R0-R7*/ "","","","","","","","", ++ /*S0-S7*/ "","","","","","","","", ++ /*T0-T7*/ "","","","","","","","", ++ /*U0-U7*/ "","","","","","","","", ++ /*V0-V7*/ "","","","","","","","", ++ /*W0-W7*/ "","","","","","","","", ++ /*X0-X7*/ "","","","","","","","", ++ /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", ++ /*Z0-Z7*/ "","SIO_POWER_GOOD","","","","","","", ++ /*AA0-AA7*/ "","","","","","","","POST_COMPLETE", ++ /*AB0-AB7*/ "","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", ++ /*AC0-AC7*/ "","","","","","","",""; ++}; ++ ++&kcs3 { ++ kcs_addr = <0xCA2>; ++ status = "okay"; ++}; ++ ++&kcs4 { ++ kcs_addr = <0xCA4>; ++ status = "okay"; ++}; ++ ++&lpc_sio { ++ status = "okay"; ++}; ++ ++&lpc_snoop { ++ snoop-ports = <0x80>; ++ status = "okay"; ++}; ++ ++&mbox { ++ status = "okay"; ++}; ++ ++/** ++ * SAFS through SPI1 is available only on Wilson Point. ++ * These pins are used as fan presence checking gpios in WFP ++ * so commenting it out for now. ++ * &spi1 { ++ * status = "okay"; ++ * ++ * flash@0 { ++ * m25p,fast-read; ++ * status = "okay"; ++ * }; ++ *}; ++ */ ++ ++&sgpio { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_txd1_default ++ &pinctrl_rxd1_default ++ &pinctrl_nrts1_default ++ &pinctrl_ndtr1_default ++ &pinctrl_ndsr1_default ++ &pinctrl_ncts1_default ++ &pinctrl_ndcd1_default ++ &pinctrl_nri1_default>; ++}; ++ ++&uart2 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_txd2_default ++ &pinctrl_rxd2_default ++ &pinctrl_nrts2_default ++ &pinctrl_ndtr2_default ++ &pinctrl_ndsr2_default ++ &pinctrl_ncts2_default ++ &pinctrl_ndcd2_default ++ &pinctrl_nri2_default>; ++}; ++ ++&uart3 { ++ status = "okay"; ++}; ++ ++&uart4 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <>; ++}; ++ ++&uart5 { ++ status = "okay"; ++}; ++ ++&mac1 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; ++}; ++ ++&mac0 { ++ status = "okay"; ++ use-ncsi; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_rmii1_default>; ++}; ++ ++&i2c0 { ++ multi-master; ++ general-call; ++ status = "okay"; ++ ++ ipmb0@10 { ++ compatible = "slave-mqueue"; ++ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; ++ }; ++}; ++ ++&i2c1 { ++ multi-master; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ multi-master; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ multi-master; ++ status = "okay"; ++}; ++ ++&i2c4 { ++ multi-master; ++ status = "okay"; ++ ++ hsbp0@10 { ++ compatible = "slave-mqueue"; ++ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; ++ }; ++}; ++ ++&i2c5 { ++ bus-frequency = <1000000>; ++ multi-master; ++ status = "okay"; ++ ++ smlink0@10 { ++ compatible = "slave-mqueue"; ++ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; ++ }; ++}; ++ ++&i2c6 { ++ multi-master; ++ status = "okay"; ++}; ++ ++&i2c7 { ++ multi-master; ++ #retries = <3>; ++ status = "okay"; ++}; ++ ++&i2c9 { ++ multi-master; ++ status = "okay"; ++}; ++ ++&i2c13 { ++ multi-master; ++ status = "okay"; ++}; ++ ++&gfx { ++ status = "okay"; ++ memory-region = <&gfx_memory>; ++}; ++ ++&vuart { ++ status = "okay"; ++}; ++ ++&pwm_tacho { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default ++ &pinctrl_pwm2_default &pinctrl_pwm3_default ++ &pinctrl_pwm4_default &pinctrl_pwm5_default ++ &pinctrl_pwm6_default &pinctrl_pwm7_default>; ++ ++ fan@0 { ++ reg = <0x00>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; ++ }; ++ fan@1 { ++ reg = <0x01>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; ++ }; ++ fan@2 { ++ reg = <0x02>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; ++ }; ++ fan@3 { ++ reg = <0x03>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; ++ }; ++ fan@4 { ++ reg = <0x04>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; ++ }; ++ fan@5 { ++ reg = <0x05>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x0A 0x0B>; ++ }; ++ fan@6 { ++ reg = <0x06>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x0C 0x0D>; ++ }; ++ fan@7 { ++ reg = <0x07>; ++ aspeed,fan-tach-ch = /bits/ 8 <0x0E 0x0F>; ++ }; ++ ++}; ++ ++&timer { ++/* ++ * Available settings: ++ * fttmr010,pwm-outputs = <5>, <6>, <7>, <8>; ++ * pinctrl-0 = <&pinctrl_timer5_default &pinctrl_timer6_default ++ * &pinctrl_timer7_default &pinctrl_timer8_default>; ++ */ ++ fttmr010,pwm-outputs = <5>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_timer5_default>; ++ #pwm-cells = <3>; ++ status = "okay"; ++}; ++ ++&video { ++ status = "okay"; ++ memory-region = <&video_engine_memory>; ++}; ++ ++&vhub { ++ status = "okay"; ++}; +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch new file mode 100644 index 000000000..b05ad2502 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch @@ -0,0 +1,121 @@ +From 9537923d6e6a793cb2bf3c1daacd12562263bc0a Mon Sep 17 00:00:00 2001 +From: "Jason M. Bills" <jason.m.bills@linux.intel.com> +Date: Fri, 3 May 2019 16:12:39 -0700 +Subject: [PATCH] Enable pass-through on GPIOE1 and GPIOE3 free + +This change adds a gpio_disable_free() implementation that checks +if the GPIO being freed is GPIOE1 (33) or GPIOE3 (35) and will +re-enable the pass-through mux. + +Tested: +Requested GPIOs 33 and 35 and used devmem to check that pass-through +was disabled. Then freed them and checked that pass-through was +enabled again. + +Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com> +--- + drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1 + + drivers/pinctrl/aspeed/pinctrl-aspeed.c | 60 ++++++++++++++++++++++++++++++ + drivers/pinctrl/aspeed/pinctrl-aspeed.h | 3 ++ + 3 files changed, 64 insertions(+) + +diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +index 187abd7..beb0729 100644 +--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c ++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +@@ -2498,6 +2498,7 @@ static const struct pinmux_ops aspeed_g5_pinmux_ops = { + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, ++ .gpio_disable_free = aspeed_gpio_disable_free, + .strict = true, + }; + +diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c +index eb87ab7..f06d752 100644 +--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c ++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c +@@ -538,6 +538,66 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, + return aspeed_sig_expr_enable(expr, pdata->maps); + } + ++void aspeed_gpio_disable_free(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int offset) ++{ ++ const struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); ++ const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data; ++ const struct aspeed_sig_expr ***prios, **funcs, *expr; ++ int ret; ++ ++ /* ++ * If we're freeing GPIOE1 (33) or GPIOE3 (35) then re-enable the ++ * pass-through mux setting; otherwise, do nothing. ++ */ ++ if (offset != 33 && offset != 35) ++ return; ++ ++ dev_dbg(pctldev->dev, ++ "Freeing pass-through pin %s (%d). Re-enabling pass-through.\n", ++ pdesc->name, offset); ++ ++ if (!pdesc) ++ return; ++ ++ prios = pdesc->prios; ++ ++ if (!prios) ++ return; ++ ++ /* Disable any functions of higher priority than GPIO just in case */ ++ while (funcs = *prios) { ++ if (aspeed_gpio_in_exprs(funcs)) ++ break; ++ ++ ret = aspeed_disable_sig(funcs, pdata->maps); ++ if (ret) ++ return; ++ ++ prios++; ++ } ++ ++ if (!funcs) { ++ char *signals = get_defined_signals(pdesc); ++ ++ pr_warn("No GPIO signal type found on pin %s (%d). Found: %s\n", ++ pdesc->name, offset, signals); ++ kfree(signals); ++ ++ return; ++ } ++ ++ /* ++ * Pass-through should be one priority higher than the GPIO function, ++ * so decrement our prios and enable that function ++ */ ++ prios--; ++ funcs = *prios; ++ expr = *funcs; ++ aspeed_sig_expr_enable(expr, pdata->maps); ++} ++ + int aspeed_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *pdesc, + struct aspeed_pinctrl_data *pdata) +diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h +index d4d7f03..0037b11 100644 +--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h ++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h +@@ -595,6 +595,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset); ++void aspeed_gpio_disable_free(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int offset); + int aspeed_pinctrl_probe(struct platform_device *pdev, + struct pinctrl_desc *pdesc, + struct aspeed_pinctrl_data *pdata); +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch new file mode 100644 index 000000000..1d26b9667 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch @@ -0,0 +1,70 @@ +From d26dd7c4ef1a2cb88440420deccc54eb88129c60 Mon Sep 17 00:00:00 2001 +From: "Jason M. Bills" <jason.m.bills@linux.intel.com> +Date: Mon, 6 May 2019 14:18:27 -0700 +Subject: [PATCH] Enable GPIOE0 and GPIOE2 pass-through by default + +This change sets the gpio DT pinctrl default configuration to +enable GPIOE0 and GPIOE2 pass-through. Since this causes +pinctrl_get_select_default() to be called automatically for +the gpio driver to claim the GPIO pins in those groups, we +also need to call pinctrl_put() to release claim on the +pass-through GPIOs so they can be requested at runtime. + +Tested: +Disabled pass-through in uboot and confirmed that after booting +Linux, pass-through is enabled and 'cat /sys/kernel/debug/pinctrl/ +1e6e2000.syscon\:pinctrl-aspeed-g5-pinctrl/pinmux-pins' shows that +the pass-through GPIOs are UNCLAIMED. + +Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com> +--- + arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 4 ++++ + drivers/gpio/gpio-aspeed.c | 10 ++++++++++ + 2 files changed, 14 insertions(+) + +diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +index 45556ac..051e927 100644 +--- a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts ++++ b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +@@ -124,6 +124,10 @@ + + &gpio { + status = "okay"; ++ /* Enable GPIOE0 and GPIOE2 pass-through by default */ ++ pinctrl-names = "pass-through"; ++ pinctrl-0 = <&pinctrl_gpie0_default ++ &pinctrl_gpie2_default>; + gpio-line-names = + /*A0-A8*/ "","","","","","","","", + /*B0-B8*/ "","","","","","","","", +diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c +index 2175070..f47d139 100644 +--- a/drivers/gpio/gpio-aspeed.c ++++ b/drivers/gpio/gpio-aspeed.c +@@ -1157,6 +1157,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) + const struct of_device_id *gpio_id; + struct aspeed_gpio *gpio; + struct resource *res; ++ struct pinctrl *pinctrl; + int rc, i, banks; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); +@@ -1205,6 +1206,15 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) + return -ENOMEM; + + /* ++ * Select the pass-through pinctrl config to enable the pass-through ++ * mux for GPIOs E0 and E2. Then call pinctrl_put() to release claim ++ * of the GPIO pins, so they can be requested at runtime. ++ */ ++ pinctrl = pinctrl_get_select(&pdev->dev, "pass-through"); ++ if (pinctrl) ++ pinctrl_put(pinctrl); ++ ++ /* + * Populate it with initial values read from the HW and switch + * all command sources to the ARM by default + */ +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0004-Test-code-for-LPC-MBOX.patch b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0004-Test-code-for-LPC-MBOX.patch new file mode 100644 index 000000000..dbb163d20 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0004-Test-code-for-LPC-MBOX.patch @@ -0,0 +1,112 @@ +From 2f3587cf9e44f261fe74413ef6a54467686c910b Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Tue, 20 Nov 2018 15:49:15 -0800 +Subject: [PATCH] Test code for LPC MBOX + +Blocked interrupt driven code for test. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + drivers/misc/aspeed-lpc-mbox.c | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/drivers/misc/aspeed-lpc-mbox.c b/drivers/misc/aspeed-lpc-mbox.c +index 0f0c711bafee..0933e0553953 100644 +--- a/drivers/misc/aspeed-lpc-mbox.c ++++ b/drivers/misc/aspeed-lpc-mbox.c +@@ -19,6 +19,8 @@ + + #define DEVICE_NAME "aspeed-mbox" + ++#define MBX_USE_INTERRUPT 0 ++ + #define ASPEED_MBOX_NUM_REGS 16 + + #define ASPEED_MBOX_DATA_0 0x00 +@@ -79,12 +81,14 @@ static int aspeed_mbox_open(struct inode *inode, struct file *file) + struct aspeed_mbox *mbox = file_mbox(file); + + if (atomic_inc_return(&aspeed_mbox_open_count) == 1) { ++#if MBX_USE_INTERRUPT + /* + * Clear the interrupt status bit if it was left on and unmask + * interrupts. + * ASPEED_MBOX_CTRL_RECV bit is W1C, this also unmasks in 1 step + */ + aspeed_mbox_outb(mbox, ASPEED_MBOX_CTRL_RECV, ASPEED_MBOX_BMC_CTRL); ++#endif + return 0; + } + +@@ -106,6 +110,7 @@ static ssize_t aspeed_mbox_read(struct file *file, char __user *buf, + if (count + *ppos > ASPEED_MBOX_NUM_REGS) + return -EINVAL; + ++#if MBX_USE_INTERRUPT + if (file->f_flags & O_NONBLOCK) { + if (!(aspeed_mbox_inb(mbox, ASPEED_MBOX_BMC_CTRL) & + ASPEED_MBOX_CTRL_RECV)) +@@ -115,6 +120,7 @@ static ssize_t aspeed_mbox_read(struct file *file, char __user *buf, + ASPEED_MBOX_CTRL_RECV)) { + return -ERESTARTSYS; + } ++#endif + + mutex_lock(&mbox->mutex); + +@@ -129,8 +135,10 @@ static ssize_t aspeed_mbox_read(struct file *file, char __user *buf, + count--; + } + ++#if MBX_USE_INTERRUPT + /* ASPEED_MBOX_CTRL_RECV bit is write to clear, this also unmasks in 1 step */ + aspeed_mbox_outb(mbox, ASPEED_MBOX_CTRL_RECV, ASPEED_MBOX_BMC_CTRL); ++#endif + ret = p - buf; + + out_unlock: +@@ -180,7 +188,9 @@ static unsigned int aspeed_mbox_poll(struct file *file, poll_table *wait) + + poll_wait(file, &mbox->queue, wait); + ++#if MBX_USE_INTERRUPT + if (aspeed_mbox_inb(mbox, ASPEED_MBOX_BMC_CTRL) & ASPEED_MBOX_CTRL_RECV) ++#endif + mask |= POLLIN; + + return mask; +@@ -206,6 +216,7 @@ static irqreturn_t aspeed_mbox_irq(int irq, void *arg) + { + struct aspeed_mbox *mbox = arg; + ++#if MBX_USE_INTERRUPT + if (!(aspeed_mbox_inb(mbox, ASPEED_MBOX_BMC_CTRL) & ASPEED_MBOX_CTRL_RECV)) + return IRQ_NONE; + +@@ -216,6 +227,7 @@ static irqreturn_t aspeed_mbox_irq(int irq, void *arg) + + /* Mask it off, we'll clear it when we the data gets read */ + aspeed_mbox_outb(mbox, ASPEED_MBOX_CTRL_MASK, ASPEED_MBOX_BMC_CTRL); ++#endif + + wake_up(&mbox->queue); + return IRQ_HANDLED; +@@ -248,7 +260,14 @@ static int aspeed_mbox_config_irq(struct aspeed_mbox *mbox, + aspeed_mbox_outb(mbox, 0xff, ASPEED_MBOX_STATUS_0); + aspeed_mbox_outb(mbox, 0xff, ASPEED_MBOX_STATUS_1); + +- aspeed_mbox_outb(mbox, ASPEED_MBOX_CTRL_RECV, ASPEED_MBOX_BMC_CTRL); ++ aspeed_mbox_outb(mbox, aspeed_mbox_inb(mbox, ASPEED_MBOX_BMC_CTRL) | ASPEED_MBOX_CTRL_MASK, ASPEED_MBOX_BMC_CTRL); ++ ++ /* ++ * Because mailbox data register init value is random, need to give a ++ * init value to mailbox data register. ++ */ ++ aspeed_mbox_outb(mbox, 0x00, ASPEED_MBOX_DATA_0); ++ + return 0; + } + +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0005-128MB-flashmap-for-PFR.patch b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0005-128MB-flashmap-for-PFR.patch new file mode 100644 index 000000000..03b4f4da4 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0005-128MB-flashmap-for-PFR.patch @@ -0,0 +1,30 @@ +From ddfbe1364c6ecf77f06990e6550dfe5a3791e6bf Mon Sep 17 00:00:00 2001 +From: Vikram Bodireddy <vikram.bodireddy@intel.com> +Date: Wed, 6 Feb 2019 15:59:34 +0530 +Subject: [PATCH] Selecting 128MB for PFR + +PFR platforms requires 128MB flash mapping. +This will override the existing 64MB flash map +and loads 128MB flash map. + +Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> +--- + arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +index 8aba46cdce46..6959a06d04e2 100644 +--- a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts ++++ b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts +@@ -90,7 +90,7 @@ + flash@0 { + status = "okay"; + m25p,fast-read; +-#include "openbmc-flash-layout-intel-64MB.dtsi" ++#include "openbmc-flash-layout-intel-128MB.dtsi" + }; + }; + +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0006-Allow-monitoring-of-power-control-input-GPIOs.patch b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0006-Allow-monitoring-of-power-control-input-GPIOs.patch new file mode 100644 index 000000000..d3b850efe --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0006-Allow-monitoring-of-power-control-input-GPIOs.patch @@ -0,0 +1,80 @@ +From 2e834ae04eba975066f80102c6f4656da314ca1e Mon Sep 17 00:00:00 2001 +From: "Jason M. Bills" <jason.m.bills@linux.intel.com> +Date: Fri, 24 May 2019 12:42:59 -0700 +Subject: [PATCH] Allow monitoring of power control input GPIOs + +The pass-through input GPIOs cannot be monitored because when +requested, pass-through is disabled which causes a change on the +pass-through output. + +The SIO GPIOs cannot be monitored because when requested, the +request is rejected based on the value of the ACPI strap. + +This change removes the register check condition from the pass- +through and desired SIO GPIOs so they can be requsted and +monitored from power control. + +Tested: +For pass-through, I used gpioset to hold a request on the input +GPIOs and confirmed that pass-through remained enabled. + +For SIO, I used gpioget to confirm that I can successfully request +and read the GPIO value. + +Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com> +--- + drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +index beb0729..05d1081 100644 +--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c ++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +@@ -250,7 +250,7 @@ FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); + + #define B20 32 + SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +-SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); ++SIG_EXPR_DECL(GPIE0IN, GPIE0); + SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); + SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); + MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); +@@ -270,7 +270,7 @@ FUNC_GROUP_DECL(GPIE0, B20, C20); + + #define F18 34 + SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +-SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); ++SIG_EXPR_DECL(GPIE2IN, GPIE2); + SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); + SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); + MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN); +@@ -1349,7 +1349,7 @@ FUNC_GROUP_DECL(ADC15, H4); + + #define R22 192 + SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +-SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); ++SIG_EXPR_DECL(SIOS3, ACPI); + SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); + SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); + MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22); +@@ -1357,7 +1357,7 @@ FUNC_GROUP_DECL(SIOS3, R22); + + #define R21 193 + SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +-SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); ++SIG_EXPR_DECL(SIOS5, ACPI); + SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); + SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); + MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21); +@@ -1373,7 +1373,7 @@ FUNC_GROUP_DECL(SIOPWREQ, P22); + + #define P21 195 + SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +-SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); ++SIG_EXPR_DECL(SIOONCTRL, ACPI); + SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); + SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); + MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21); +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/intel-ast2500.cfg b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/intel-ast2500.cfg new file mode 100644 index 000000000..480d4cc18 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/intel-ast2500.cfg @@ -0,0 +1,69 @@ +CONFIG_HWMON=y +CONFIG_SENSORS_ASPEED=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_IIO=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_ASPEED_ADC=y +CONFIG_SGPIO_ASPEED=y +CONFIG_CRC8=y +CONFIG_PECI=y +CONFIG_PECI_CHARDEV=y +CONFIG_PECI_ASPEED=y +CONFIG_SENSORS_PECI_CPUTEMP=y +CONFIG_SENSORS_PECI_DIMMTEMP=y +CONFIG_OF_CONFIGFS=y +CONFIG_CONFIGFS_FS=y +CONFIG_BLK_DEV_RAM_SIZE=49152 +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_ASPEED_ESPI_SLAVE=y +CONFIG_ASPEED_KCS_IPMI_BMC=y +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=n +CONFIG_I2C_SLAVE_MQUEUE=y +CONFIG_I2C_SLAVE_MQUEUE_MESSAGE_SIZE=256 +CONFIG_I2C_SLAVE_MQUEUE_QUEUE_SIZE=32 +CONFIG_ASPEED_LPC_SIO=y +CONFIG_JTAG=y +CONFIG_JTAG_ASPEED=y +CONFIG_FRAME_VECTOR=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_ASPEED=y +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_LIBCOMPOSITE=y +CONFIG_USB_F_HID=y +CONFIG_USB_GADGET=y +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_ASPEED_VHUB=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_ASPEED_UART_ROUTING=y +CONFIG_DEVMEM=y +CONFIG_ASPEED_VGA_SHAREDMEM=y +CONFIG_DEVMEM_BOOTPARAM=n +CONFIG_PWM=y +CONFIG_PWM_FTTMR010=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PWM_BEEPER=y +CONFIG_VFAT_FS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed_%.bbappend new file mode 100644 index 000000000..0ba716442 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed_%.bbappend @@ -0,0 +1,9 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/linux-aspeed:" +SRC_URI += "file://intel-ast2500.cfg \ + file://0001-arm-dts-add-DTS-for-Intel-platforms.patch \ + file://0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch \ + file://0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch \ + file://0004-Test-code-for-LPC-MBOX.patch \ + file://0006-Allow-monitoring-of-power-control-input-GPIOs.patch \ + " +SRC_URI += "${@bb.utils.contains('IMAGE_TYPE', 'pfr', 'file://0005-128MB-flashmap-for-PFR.patch', '', d)}" diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CYP-baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CYP-baseboard.json new file mode 100644 index 000000000..271881706 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/CYP-baseboard.json @@ -0,0 +1,1348 @@ +{ + "Exposes": [ + { + "Index": 0, + "Name": "P12V_PSU_RIGHT", + "PowerState": "On", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 1, + "Name": "P3V3", + "PowerState": "On", + "ScaleFactor": 0.4107, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 3.647 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 3.541 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 3.066 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 2.974 + } + ], + "Type": "ADC" + }, + { + "Index": 2, + "Name": "PVNN_PCH_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.081 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.049 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.807 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.783 + } + ], + "Type": "ADC" + }, + { + "Index": 3, + "Name": "P105_PCH_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.139 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.106 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.995 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.966 + } + ], + "Type": "ADC" + }, + { + "Index": 4, + "Name": "P12V_PSU_LEFT", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 5, + "Name": "P12V_AUX", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 6, + "Name": "P1V8_PCH", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.961 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.904 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.699 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.648 + } + ], + "Type": "ADC" + }, + { + "Index": 7, + "Name": "P3VBAT", + "ScaleFactor": 0.3333, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 3.296 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 3.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 2.457 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 2.138 + } + ], + "Type": "ADC" + }, + { + "Index": 8, + "Name": "PVCCIN_CPU0", + "PowerState": "On", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 2.151 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 2.088 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.418 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.376 + } + ], + "Type": "ADC" + }, + { + "Index": 9, + "Name": "PVCCIN_CPU1", + "PowerState": "On", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 2.151 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 2.088 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.418 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.376 + } + ], + "Type": "ADC" + }, + { + "Index": 10, + "Name": "PVDQ_ABCD_CPU0", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + 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"Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.19 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.155 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.752 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.729 + } + ], + "Type": "ADC" + }, + { + "Index": 15, + "Name": "PVCCIO_CPU1", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.19 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.155 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.752 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.729 + } + ], + "Type": "ADC" + }, + { + "BindGpioIntrusion": "Chassis Intrusion GPIO", + "Class": "Gpio", + "Name": "Chassis Intrusion Sensor", + "Type": "ChassisIntrusionSensor" + }, + { + "Direction": "In", + "Index": 0, + "Name": "Board REV ID0", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 3, + "Name": "Board REV ID1", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 8, + "Name": "Board SKU ID0", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 9, + "Name": "Board SKU ID1", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 10, + "Name": "Board SKU ID2", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 11, + "Name": "Board SKU ID3", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 12, + "Name": "Board SKU ID4", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 18, + "Name": "OCP3 PRSNTB0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 19, + "Name": "OCP3 PRSNTB1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 20, + "Name": "OCP3 PRSNTB2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 21, + "Name": "OCP3 PRSNTB3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 24, + "Name": "Force BMC Update", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 26, + "Name": "OCP PWRGD Aux", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 42, + "Name": "CPU1 Memhot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 43, + "Name": "CPU2 Memhot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 44, + "Name": "Cpu Err0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 45, + "Name": "Cpu Err1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 46, + "Name": "Platform Reset", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 47, + "Name": "CPU PRDY", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 48, + "Name": "Cpu Err2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 49, + "Name": "Cpu Caterr", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 50, + "Name": "PCH Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 51, + "Name": "Board REV ID2", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 52, + "Name": "NMI Event", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 53, + "Name": "Board SKU ID5", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 56, + "Name": "Rise1 PWRGD", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 57, + "Name": "Rise2 PWRGD", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 61, + "Name": "Rise3 PWRGD", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "In", + "Index": 62, + "Name": "Rise4 PWRGD", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 63, + "Name": "240VA OC", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 64, + "Name": "SYS FAN0 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 65, + "Name": "SYS FAN1 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 66, + "Name": "SYS FAN2 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 67, + "Name": "SYS FAN3 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 68, + "Name": "SASM ROC ID0", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 69, + "Name": "SASM ROC ID1", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 70, + "Name": "Midplane Switch ID0", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 71, + "Name": "Midplane Switch ID1", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 137, + "Name": "PCA9555 Intr", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 138, + "Name": "SYS FAN4 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 139, + "Name": "SYS FAN5 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 140, + "Name": "SYS FAN6 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 141, + "Name": "SYS FAN7 PRSNT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 143, + "Name": "Chassis Intrusion GPIO", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 144, + "Name": "Remote Debug Enable", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 146, + "Name": "RSMRST", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 214, + "Name": "SMI Active", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 218, + "Name": "ID Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 232, + "Name": "CPU1 Present", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 233, + "Name": "CPU1 Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 234, + "Name": "CPU1 VR Hot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 235, + "Name": "CPU1 FIVR Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 236, + "Name": "CPU1 Mem VR Hot1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 237, + "Name": "CPU1 Mem VR Hot2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 238, + "Name": "CPU1 ID0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 239, + "Name": "CPU1 ID1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 240, + "Name": "CPU1 Mismatch", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 241, + "Name": "CPU1 DIMM Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 242, + "Name": "CPU2 Present", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 243, + "Name": "CPU2 Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 244, + "Name": "CPU2 VR Hot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 245, + "Name": "CPU2 FIVR Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 246, + "Name": "CPU2 Mem VR Hot1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 247, + "Name": "CPU1 Mem VR Hot2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 248, + "Name": "CPU2 ID0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 249, + "Name": "CPU2 ID1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 250, + "Name": "CPU2 Mismatch", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 251, + "Name": "CPU2 DIMM Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 272, + "Name": "PLD Minor Revison Bit 0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 273, + "Name": "PLD Minor Revison Bit 1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 274, + "Name": "PLD Minor Revison Bit 2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 275, + "Name": "PLD Minor Revison Bit 3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 276, + "Name": "PLD Minor Revison Bit 4", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 277, + "Name": "PLD Minor Revison Bit 5", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 278, + "Name": "PLD Minor Revison Bit 6", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 279, + "Name": "PLD Minor Revison Bit 7", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 280, + "Name": "Main PLD Major Revison Bit 0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 281, + "Name": "Main PLD Major Revison Bit 1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 282, + "Name": "Main PLD Major Revison Bit 2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 283, + "Name": "Main PLD Major Revison Bit 3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 284, + "Name": "Main PLD Major Revison Bit 4", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 285, + "Name": "Main PLD Major Revison Bit 5", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 286, + "Name": "Main PLD Major Revison Bit 6", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 287, + "Name": "Main PLD Major Revison Bit 7", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 289, + "Name": "Memory Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 290, + "Name": "CPU Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 291, + "Name": "P3V3 Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 292, + "Name": "PSU Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 295, + "Name": "PCH Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Address": "0x4D", + "Bus": 6, + "Name": "CPU0 VR Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP421" + }, + { + "Address": "0x4F", + "Bus": 6, + "Name": "CPU1 Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP421" + }, + { + "Address": "0x4A", + "Bus": 6, + "Name": "BMC Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4B", + "Bus": 6, + "Name": "RightRear Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4E", + "Bus": 6, + "Name": "LeftRear Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4C", + "Bus": 6, + "Name": "PCH DS Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + } + ], + "Name": "CYP Baseboard", + "Probe": "xyz.openbmc_project.FruDevice({'PRODUCT_PRODUCT_NAME': '.*CYP'})", + "Type": "Board", + "ProductId": 152, + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "$PRODUCT_MANUFACTURER", + "Model": "$PRODUCT_PRODUCT_NAME", + "PartNumber": "$PRODUCT_PART_NUMBER", + "SerialNumber": "$PRODUCT_SERIAL_NUMBER" + } +} diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/FCXXPDBASSMBL_PDB.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/FCXXPDBASSMBL_PDB.json new file mode 100644 index 000000000..22f8b1c6d --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/FCXXPDBASSMBL_PDB.json @@ -0,0 +1,91 @@ +[ + { + "Exposes": [ + { + "Address": "$address", + "Bus": "$bus", + "Name": "FCXXPDBASSMBL Fru", + "Type": "24C01" + }, + { + "Address": "0x18", + "Bus": "$bus", + "Name": "Multi Node Presence Detector", + "Type": "MultiNode" + }, + { + "Address": "0x48", + "Bus": "$bus", + "Name": "PDB Temp1", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 80 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 75 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x49", + "Bus": "$bus", + "Name": "PDB Temp2", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 80 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 75 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + } + ], + "Name": "FCXXPDBASSMBL PDB", + "Probe": "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'FCXXPDBASSMBL', 'ADDRESS' : 85})", + "Type": "Board", + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "$BOARD_MANUFACTURER", + "Model": "$BOARD_PRODUCT_NAME", + "PartNumber": "$BOARD_PART_NUMBER", + "SerialNumber": "$BOARD_SERIAL_NUMBER" + } + } +]
\ No newline at end of file diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/MIDPLANE-2U2X12SWITCH.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/MIDPLANE-2U2X12SWITCH.json new file mode 100644 index 000000000..53edbfe87 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/MIDPLANE-2U2X12SWITCH.json @@ -0,0 +1,104 @@ +[ + { + "Exposes": [ + { + "Address": "$address", + "Bus": "$bus", + "Name": "Midplane 1 Fru", + "Type": "EEPROM" + }, + { + "Address": "0x4E", + "Bus": "$bus", + "Name": "Midplane 1 Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 80 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 75 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + } + ], + "Name": "Midplane 1", + "Probe": "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'F2U2X12SWITCH', 'ADDRESS' : 86})", + "Type": "Board", + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "$BOARD_MANUFACTURER", + "Model": "$BOARD_PRODUCT_NAME", + "PartNumber": "$BOARD_PART_NUMBER", + "SerialNumber": "$BOARD_SERIAL_NUMBER" + } + }, + { + "Exposes": [ + { + "Address": "$address", + "Bus": "$bus", + "Name": "Midplane 2 Fru", + "Type": "EEPROM" + }, + { + "Address": "0x4F", + "Bus": "$bus", + "Name": "Midplane 2 Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 80 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 75 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + } + ], + "Name": "Midplane 2", + "Probe": "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'F2U2X12SWITCH', 'ADDRESS' : 87})", + "Type": "Board", + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "$BOARD_MANUFACTURER", + "Model": "$BOARD_PRODUCT_NAME", + "PartNumber": "$BOARD_PART_NUMBER", + "SerialNumber": "$BOARD_SERIAL_NUMBER" + } + } +]
\ No newline at end of file diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/OPB2RH-Chassis.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/OPB2RH-Chassis.json new file mode 100644 index 000000000..7b86bfae0 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/OPB2RH-Chassis.json @@ -0,0 +1,19 @@ +{ + "Exposes": [ + { + "Name": "Multi Node Supported", + "Type": "MultiNode" + } + ], + "Name": "OPB2RH Chassis", + "Probe": [ + "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'FCXXPDBASSMBL'})" + ], + "Type": "Chassis", + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "Intel Corporation", + "Model": "OPB2RH", + "PartNumber": "R1234", + "SerialNumber": "12345" + } +}
\ No newline at end of file diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/TNP-baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/TNP-baseboard.json new file mode 100644 index 000000000..75cd39719 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/TNP-baseboard.json @@ -0,0 +1,1824 @@ +{ + "Exposes": [ + { + "Index": 0, + "Name": "Baseboard 12 Volt", + "PowerState": "On", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 4, + "Name": "P0V83_LAN_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 0.901 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 0.875 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.786 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.763 + } + ], + "Type": "ADC" + }, + { + "Index": 3, + "Name": "P105_PCH_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.139 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.106 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.995 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.966 + } + ], + "Type": "ADC" + }, + { + "Index": 5, + "Name": "P12V_AUX", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 6, + "Name": "P1V8_PCH", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.961 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.904 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.699 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.648 + } + ], + "Type": "ADC" + }, + { + "Index": 1, + "Name": "P3V3", + "PowerState": "On", + "ScaleFactor": 0.4107, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 3.647 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 3.541 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 3.066 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 2.974 + } + ], + "Type": "ADC" + }, + { + "Index": 7, + "Name": "P3VBAT", + "ScaleFactor": 0.3333, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 3.296 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 3.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 2.457 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 2.138 + } + ], + "Type": "ADC" + }, + { + "Index": 8, + "Name": "PVCCIN_CPU1", + "PowerState": "On", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 2.151 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 2.088 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.418 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.376 + } + ], + "Type": "ADC" + }, + { + "Index": 9, + "Name": "PVCCIN_CPU2", + "PowerState": "On", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 2.151 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 2.088 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.418 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.376 + } + ], + "Type": "ADC" + }, + { + "Index": 14, + "Name": "PVCCIO_CPU1", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.19 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.155 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.752 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.729 + } + ], + "Type": "ADC" + }, + { + "Index": 15, + "Name": "PVCCIO_CPU2", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.19 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.155 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.752 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.729 + } + ], + "Type": "ADC" + }, + { + "Index": 10, + "Name": "PVDQ_ABCD_CPU1", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 12, + "Name": "PVDQ_ABCD_CPU2", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 11, + "Name": "PVDQ_EFGH_CPU1", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 13, + "Name": "PVDQ_EFGH_CPU2", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 2, + "Name": "PVNN_PCH_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.081 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.049 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.807 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.783 + } + ], + "Type": "ADC" + }, + { + "Direction": "Input", + "Index": 40, + "Name": "NMI Out", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 50, + "Name": "PCH Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 51, + "Name": "Lcp Enter Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 52, + "Name": "Lcp Left Button", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 53, + "Name": "Lcp Right Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 49, + "Name": "Cpu Caterr", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 48, + "Name": "Cpu Err2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 63, + "Name": "PU 240VA Status", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 208, + "Name": "P3v3bat BridgeEn", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 214, + "Name": "Nmi Button", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 218, + "Name": "ID Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 232, + "Name": "Post Complete led0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 233, + "Name": "Post Complete led1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 233, + "Name": "CPU1 Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 234, + "Name": "Post Complete led2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 234, + "Name": "CPU1 VR Hot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 235, + "Name": "Post Complete led3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 236, + "Name": "Post Complete led4", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 236, + "Name": "CPU1 Mem VR Hot1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 237, + "Name": "Post Complete led5", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 237, + "Name": "CPU1 Mem VR Hot2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 238, + "Name": "Post Complete led6", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 239, + "Name": "Post Complete led7", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 232, + "Name": "CPU1 Present", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 235, + "Name": "CPU1 FIVR Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 238, + "Name": "CPU1 ID0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 240, + "Name": "CPU1 CH1 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 240, + "Name": "CPU1 Mismatch", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 241, + "Name": "CPU1 CH1 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 241, + "Name": "CPU1 DIMM Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 242, + "Name": "CPU1 CH2 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 242, + "Name": "CPU2 Present", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 243, + "Name": "CPU1 CH2 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 243, + "Name": "CPU2 Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 244, + "Name": "CPU1 CH3 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 244, + "Name": "CPU2 VR Hot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 245, + "Name": "CPU1 CH3 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 245, + "Name": "CPU2 FIVR Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 246, + "Name": "CPU1 CH4 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 246, + "Name": "CPU2 Mem VR Hot1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 247, + "Name": "CPU1 CH4 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 247, + "Name": "CPU1 Mem VR Hot2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 248, + "Name": "CPU1 CH5 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 248, + "Name": "CPU2 ID0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 249, + "Name": "CPU1 CH5 DIMM2 FAULT", + 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"Direction": "Input", + "Index": 289, + "Name": "Memory Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 290, + "Name": "CPU4 CH4 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 290, + "Name": "CPU Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 291, + "Name": "CPU4 CH4 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 291, + "Name": "P5V P3V3 Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 292, + "Name": "CPU4 CH5 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 292, + "Name": "PSU Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 293, + "Name": "CPU4 CH5 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 293, + "Name": "SAS Pwr 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"IntelFanConnector" + }, + { + "Address": "0x8", + "Class": "METemp", + "Name": "SSB Temp", + "PowerState": "BiosPost", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 103 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 98 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x7c", + "Class": "PxeBridgeTemp", + "Name": "CPU1 P12V PVCCIO VR Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": 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than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "BindGpioNodeID": "Node ID GPIO 0", + "Name": "Multi Node ID 0", + "Type": "MultiNode" + }, + { + "BindGpioNodeID": "Node ID GPIO 1", + "Name": "Multi Node ID 1", + "Type": "MultiNode" + }, + { + "Address": "0x71", + "Bus": 2, + "ChannelNames": [ + "M2_Slot1", + "M2_Slot2", + "", + "" + ], + "Name": "M.2 Mux", + "Type": "PCA9543Mux" + }, + { + "Address": "0x30", + "Bus": 0, + "CpuID": 1, + "Name": "Xeon CPU 1", + "Thresholds": [ + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper critical", + "Severity": 1, + "Value": 99 + }, + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper non critical", + "Severity": 0, + "Value": 89 + } + ], + "Type": "XeonCPU" + }, + { + "Address": "0x31", + "Bus": 0, + "CpuID": 2, + "Name": "Xeon CPU 2", + "Thresholds": [ + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper critical", + "Severity": 1, + "Value": 99 + }, + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper non critical", + "Severity": 0, + "Value": 89 + } + ], + "Type": "XeonCPU" + }, + { + "Address": "0x4E", + "Bus": 6, + "Name": "Exit Air Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4B", + "Bus": 6, + "Name": "Inlet Air Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + } + ], + "Name": "TNP Baseboard", + "Probe": "xyz.openbmc_project.FruDevice({'PRODUCT_PRODUCT_NAME': '.*TNP'})", + "Type": "Board", + "ProductId": 153, + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "$PRODUCT_MANUFACTURER", + "Model": "$PRODUCT_PRODUCT_NAME", + "PartNumber": "$PRODUCT_PART_NUMBER", + "SerialNumber": "$PRODUCT_SERIAL_NUMBER" + } +} diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json new file mode 100644 index 000000000..982dade40 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json @@ -0,0 +1,2040 @@ +{ + "Exposes": [ + { + "Index": 0, + "Name": "A_P12V_PSU_SCALED", + "PowerState": "On", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 3, + "Name": "P105_PCH_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + 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\ No newline at end of file diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json new file mode 100644 index 000000000..bdf6b7d9c --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WP-Baseboard.json @@ -0,0 +1,2033 @@ +{ + "Exposes": [ + { + "Index": 0, + "Name": "A_P12V_PSU_SCALED", + "PowerState": "On", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 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"IntelFanConnector" + }, + { + "Name": "System Fan connector 4", + "Pwm": 3, + "Tachs": [ + 6, + 7 + ], + "Type": "IntelFanConnector" + }, + { + "Name": "System Fan connector 5", + "Pwm": 4, + "Tachs": [ + 8, + 9 + ], + "Type": "IntelFanConnector" + }, + { + "Name": "System Fan connector 6", + "Pwm": 5, + "Tachs": [ + 10, + 11 + ], + "Type": "IntelFanConnector" + }, + { + "Name": "System Fan connector 7", + "Pwm": 6, + "Tachs": [ + 12, + 13 + ], + "Type": "IntelFanConnector" + }, + { + "Name": "System Fan connector 8", + "Pwm": 7, + "Tachs": [ + 14, + 15 + ], + "Type": "IntelFanConnector" + }, + { + "Address": "0x8", + "Class": "METemp", + "Name": "SSB Temp", + "PowerState": "BiosPost", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 103 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 98 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + 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"ICoefficient": 0.0, + "ILimitMax": 0.0, + "ILimitMin": 0.0, + "Inputs": [ + "Fan 8a", + "Fan 8b" + ], + "Name": "Fan 8", + "NegativeHysteresis": 0.0, + "OutLimitMax": 100.0, + "OutLimitMin": 30.0, + "Outputs": [ + "Pwm 8" + ], + "PCoefficient": 0.0, + "PositiveHysteresis": 0.0, + "SlewNeg": 0.0, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Right" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "BMC Temp" + ], + "Name": "BMC Temp", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "DIMM [ABC]\\d+ CPU1" + ], + "Name": "CPU1 DIMM ABC", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left", + "Right" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "DIMM [DEF]\\d+ CPU1" + ], + "Name": "CPU1 DIMM DEF", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "DIMM [ABC]\\d+ CPU2" + ], + "Name": "CPU2 DIMM ABC", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Right", + "PSU" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "DIMM [DEF]\\d+ CPU2" + ], + "Name": "CPU2 DIMM DEF", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left", + "Right" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "DTS CPU1" + ], + "Name": "DTS CPU1", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "DTS CPU2" + ], + "Name": "DTS CPU2", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Right", + "PSU" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "Left Rear Temp" + ], + "Name": "Left Rear Temp", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left", + "Right" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "Right Rear Board" + ], + "Name": "Right Rear Board", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "SSB Temp" + ], + "Name": "SSB Temp", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left", + "Right" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "VR 1 Temp" + ], + "Name": "VR 1 Temp", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Left" + ] + }, + { + "Class": "temp", + "FFGainCoefficient": 0.0, + "FFOffCoefficient": 0.0, + "ICoefficient": -1.0, + "ILimitMax": 100, + "ILimitMin": 30, + "Inputs": [ + "VR 2 Temp" + ], + "Name": "VR 2 Temp", + "NegativeHysteresis": 5.0, + "OutLimitMax": 100, + "OutLimitMin": 30, + "Outputs": [], + "PCoefficient": -0.15, + "PositiveHysteresis": 0.0, + "SetPoint": 60.0, + "SlewNeg": -1, + "SlewPos": 0.0, + "Type": "Pid", + "Zones": [ + "Right", + "PSU" + ] + }, + { + "FailSafePercent": 100, + "MinThermalOutput": 30, + "Name": "Left", + "Type": "Pid.Zone" + }, + { + "FailSafePercent": 100, + "MinThermalOutput": 30, + "Name": "Right", + "Type": "Pid.Zone" + }, + { + "FailSafePercent": 100, + "MinThermalOutput": 30, + "Name": "PSU", + "Type": "Pid.Zone" + }, + { + "Class": "Ceiling", + "Inputs": [ + "Front Panel Temp" + ], + "Name": "Front Panel UCC", + "NegativeHysteresis": 2, + "Output": [ + 70.0, + 80.0 + ], + "PositiveHysteresis": 0, + "Profiles": [ + "Acoustic" + ], + "Reading": [ + 22.0, + 32.0 + ], + "Type": "Stepwise", + "Zones": [ + "Left", + "Right" + ] + }, + { + "Class": "Floor", + "Inputs": [ + "Front Panel Temp" + ], + "Name": "Front Panel LCC", + "NegativeHysteresis": 2, + "Output": [ + 50.0, + 60.0 + ], + "PositiveHysteresis": 0, + "Reading": [ + 20.0, + 30.0 + ], + "Type": "Stepwise", + "Zones": [ + "Left", + "Right" + ] + }, + { + "Address": "0x4A", + "Bus": 6, + "Name": "BMC Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4B", + "Bus": 6, + "Name": "Right Rear Board Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x49", + "Bus": 6, + "Name": "Left Rear Board Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x48", + "Bus": 6, + "Name": "PCH M.2 Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4f", + "Bus": 6, + "Name": "Inlet BRD Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4D", + "Bus": "0x1", + "Name": "Front Panel Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 55 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 50 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x30", + "Bus": 0, + "CpuID": 1, + "Name": "CPU 1", + "PresenceGpio": 232, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 99, + "label": "DIMM" + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 89, + "label": "DIMM" + } + ], + "Type": "XeonCPU" + }, + { + "Address": "0x31", + "Bus": 0, + "CpuID": 2, + "Name": "CPU 2", + "PresenceGpio": 242, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 99, + "label": "DIMM" + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 89, + "label": "DIMM" + } + ], + "Type": "XeonCPU" + } + ], + "Name": "WP Baseboard", + "Probe": "xyz.openbmc_project.FruDevice({'PRODUCT_PRODUCT_NAME': '.*WP'})", + "ProductId": 154, + "Type": "Board", + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "$PRODUCT_MANUFACTURER", + "Model": "$PRODUCT_PRODUCT_NAME", + "PartNumber": "$PRODUCT_PART_NUMBER", + "SerialNumber": "$PRODUCT_SERIAL_NUMBER" + } +}
\ No newline at end of file diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager_%.bbappend new file mode 100644 index 000000000..b8b38ecff --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager_%.bbappend @@ -0,0 +1,15 @@ +FILESEXTRAPATHS_append := ":${THISDIR}/${PN}" +SRC_URI_append = " file://WC-Baseboard.json \ + file://WP-Baseboard.json \ + file://TNP-baseboard.json \ + file://FCXXPDBASSMBL_PDB.json \ + file://OPB2RH-Chassis.json \ + file://CYP-baseboard.json \ + file://MIDPLANE-2U2X12SWITCH.json" + +RDEPENDS_${PN} += " default-fru" + +do_install_append(){ + install -d ${D}/usr/share/entity-manager/configurations + install -m 0444 ${WORKDIR}/*.json ${D}/usr/share/entity-manager/configurations +} diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/obmc-console.conf b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/obmc-console.conf new file mode 100644 index 000000000..1d332e2a2 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/obmc-console.conf @@ -0,0 +1,3 @@ +baud = 921600 +local-tty = ttyS3 +local-tty-baud = 921600 diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/obmc-console@.service b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/obmc-console@.service new file mode 100644 index 000000000..7fb8f79d3 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/obmc-console@.service @@ -0,0 +1,21 @@ +[Unit] +Description=Phosphor Console Muxer listening on device /dev/%I +BindsTo=dev-%i.device +After=dev-%i.device + +[Service] +ExecStartPre=/usr/bin/sol-option-check.sh +ExecStartPre=/bin/sh -c 'echo -n "uart3" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/uart1' +ExecStartPre=/bin/sh -c 'echo -n "uart1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/uart3' +ExecStartPre=/bin/sh -c 'echo -n "io1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/uart4' +ExecStartPre=/bin/sh -c 'echo -n "uart4" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/io1' +ExecStart=/usr/bin/env obmc-console-server --config {sysconfdir}/obmc-console.conf %i +ExecStopPost=/bin/sh -c 'echo -n "io1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/uart1' +ExecStopPost=/bin/sh -c 'echo -n "io3" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/uart3' +ExecStopPost=/bin/sh -c 'echo -n "io4" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/uart4' +ExecStopPost=/bin/sh -c 'echo -n "uart1" > /sys/bus/platform/drivers/aspeed-uart-routing/1e78909c.uart_routing/io1' +SyslogIdentifier=obmc-console-server +Restart=always + +[Install] +WantedBy={SYSTEMD_DEFAULT_TARGET} diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/sol-option-check.sh b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/sol-option-check.sh new file mode 100755 index 000000000..ef32fcb9a --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console/sol-option-check.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +# Copyright 2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# + +if [ $(grep 192000000 /sys/class/tty/ttyS0/uartclk | wc -l) != 0 ]; then + echo "hs-uart" + sed -i -e 's/115200/921600/g' /etc/obmc-console.conf +else + echo "normal uart" + sed -i -e 's/921600/115200/g' /etc/obmc-console.conf +fi diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console_%.bbappend new file mode 100644 index 000000000..e808e4929 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/console/obmc-console_%.bbappend @@ -0,0 +1,8 @@ +FILESEXTRAPATHS_prepend_intel-ast2500 := "${THISDIR}/${PN}:" +OBMC_CONSOLE_HOST_TTY = "ttyS2" +SRC_URI += "file://sol-option-check.sh" + +do_install_append() { + install -d ${D}${bindir} + install -m 0755 ${WORKDIR}/sol-option-check.sh ${D}${bindir} +} diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed.bb b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed.bb new file mode 100644 index 000000000..9c10c5b3d --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed.bb @@ -0,0 +1,20 @@ +SUMMARY = "Set Wolfpass fan default speeds" +DESCRIPTION = "Sets all fans to a single speed" + +inherit allarch +inherit obmc-phosphor-systemd + +LICENSE = "Apache-2.0" +LIC_FILES_CHKSUM = "file://${INTELBASE}/COPYING.apache-2.0;md5=34400b68072d710fecd0a2940a0d1658" + +RDEPENDS_${PN} += "python" + +S = "${WORKDIR}" +SRC_URI += "file://set_fan_speeds.py" + +SYSTEMD_SERVICE_${PN} += "fan-default-speed.service" + +do_install() { + install -d ${D}/${bindir} + install -m 0755 ${WORKDIR}/set_fan_speeds.py ${D}/${bindir}/set_fan_speeds.py +} diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed/fan-default-speed.service b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed/fan-default-speed.service new file mode 100644 index 000000000..267fdee43 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed/fan-default-speed.service @@ -0,0 +1,10 @@ +[Unit] +Description=Set fans to a default speed +ConditionFileNotEmpty={bindir}/set_fan_speeds.py + +[Service] +ExecStart={bindir}/set_fan_speeds.py 150 +Type=oneshot + +[Install] +WantedBy=default.target diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed/set_fan_speeds.py b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed/set_fan_speeds.py new file mode 100644 index 000000000..70ba64799 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fans/fan-default-speed/set_fan_speeds.py @@ -0,0 +1,23 @@ +#!/usr/bin/python +import os +import glob +import time +import sys + +HWMON_DIR = "/sys/class/hwmon/hwmon0" + +count = 0 +inputs = None +while not inputs: + count += 1 + if count > 20: + print("pwm missing!") + sys.exit(0) + + inputs = glob.glob(os.path.join(HWMON_DIR, "pwm*")) + time.sleep(5) + +inputs = glob.glob(os.path.join(HWMON_DIR, "pwm*")) +for pwm in inputs: + with open(pwm, 'w') as f: + f.write(sys.argv[1]) diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru.bb b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru.bb new file mode 100644 index 000000000..1ae1680e0 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru.bb @@ -0,0 +1,27 @@ +SUMMARY = "Default Fru" +DESCRIPTION = "Installs a default fru file to image" + +inherit systemd + +SYSTEMD_SERVICE_${PN} = "SetBaseboardFru.service" + +S = "${WORKDIR}" +SRC_URI = "file://checkFru.sh \ + file://SetBaseboardFru.service \ + file://*.fru.bin" + +LICENSE = "Apache-2.0" +LIC_FILES_CHKSUM = "file://${INTELBASE}/COPYING.apache-2.0;md5=34400b68072d710fecd0a2940a0d1658" + +RDEPENDS_${PN} = "bash" + +do_install() { + install -d ${D}${bindir} + install -m 0755 ${S}/checkFru.sh ${D}/${bindir}/checkFru.sh + + install -d ${D}${sysconfdir}/fru + cp ${S}/*.fru.bin ${D}/${sysconfdir}/fru + + install -d ${D}${base_libdir}/systemd/system + install -m 0644 ${S}/SetBaseboardFru.service ${D}${base_libdir}/systemd/system +} diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600CYP.fru.bin b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600CYP.fru.bin Binary files differnew file mode 100644 index 000000000..ba5b96392 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600CYP.fru.bin diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600TNP.fru.bin b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600TNP.fru.bin Binary files differnew file mode 100644 index 000000000..afd58e6b9 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600TNP.fru.bin diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WC.fru.bin b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WC.fru.bin Binary files differnew file mode 100644 index 000000000..76c4b8d4b --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WC.fru.bin diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WFT.fru.bin b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WFT.fru.bin Binary files differnew file mode 100644 index 000000000..1b9f97ff4 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WFT.fru.bin diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WP.fru.bin b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WP.fru.bin Binary files differnew file mode 100644 index 000000000..fb219c0ce --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/S2600WP.fru.bin diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/SetBaseboardFru.service b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/SetBaseboardFru.service new file mode 100644 index 000000000..dec53725e --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/SetBaseboardFru.service @@ -0,0 +1,9 @@ +[Unit] +Description=Reads GPIO and Loads the FRU + +[Service] +ExecStart=/usr/bin/checkFru.sh +Type=oneshot + +[Install] +WantedBy=basic.target diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/checkFru.sh b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/checkFru.sh new file mode 100755 index 000000000..1eb79b299 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/fru/default-fru/checkFru.sh @@ -0,0 +1,38 @@ +#!/bin/bash + +# this script checks the gpio id and loads the correct baseboard fru +fruFile="/etc/fru/baseboard.fru.bin" +idGpio=( 8 9 10 11 12 53) +result=0 +idx=0 + +if [ -f $fruFile ]; then + exit 0 +fi + +cd /etc/fru +for gpio in "${idGpio[@]}" +do + echo $gpio > /sys/class/gpio/export + typeset -i value=$(cat /sys/class/gpio/gpio$gpio/value) + value=$((value << idx)) + result=$((result | value)) + idx=$((idx+1)) +done + +# wp +if (($result == 62)); then + cat S2600WP.fru.bin > $fruFile +# wc +elif (($result == 45)); then + cat S2600WC.fru.bin > $fruFile +# cyp +elif (($result == 60)); then + cat S2600CYP.fru.bin > $fruFile +# tnp +elif (($result == 12)); then + cat S2600TNP.fru.bin > $fruFile +# default to wft +else + cat S2600WFT.fru.bin > $fruFile +fi diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/workbook/wolfpass-config.bb b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/workbook/wolfpass-config.bb new file mode 100644 index 000000000..c91053536 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/workbook/wolfpass-config.bb @@ -0,0 +1,10 @@ +SUMMARY = "Wolfpass board wiring" +DESCRIPTION = "Board wiring information for the Wolfpass system." +PR = "r1" + +inherit config-in-skeleton + +LIC_FILES_CHKSUM = "file://${INTELBASE}/COPYING.apache-2.0;md5=34400b68072d710fecd0a2940a0d1658" + +SRCREV = "946064239016e38cd1cc346047b1d26960c06cdb" +SKELETON_URI = "git://git@github.com/Intel-BMC/skeleton.git;protocol=ssh;branch=intel" diff --git a/meta-openbmc-mods/meta-ast2500/recipes.txt b/meta-openbmc-mods/meta-ast2500/recipes.txt new file mode 100644 index 000000000..3ec3f4a42 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes.txt @@ -0,0 +1,2 @@ +recipes-kernel - The kernel and generic applications/libraries with strong kernel dependencies +recipes-phosphor - Phosphor OpenBMC applications and configuration |