diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2500')
9 files changed, 490 insertions, 163 deletions
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch index d52b1184a..4de12fd82 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch @@ -1,4 +1,4 @@ -From cc144438f78be5de8e9a67fd8cc898123e32d266 Mon Sep 17 00:00:00 2001 +From bd79f95696957ee1e63e4506e7f4d0693b7d1c6a Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Mon, 14 Sep 2020 17:38:28 -0700 Subject: [PATCH] Add WDT to u-boot to cover booting failures @@ -13,150 +13,69 @@ timeout is 100 seconds. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - arch/arm/mach-aspeed/platform_g5.S | 78 ++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-intel.c | 3 ++ - board/aspeed/ast-g5/ast-g5.c | 30 +++++++++++- - common/bootm_os.c | 5 ++ - 4 files changed, 114 insertions(+), 2 deletions(-) + arch/arm/mach-aspeed/flash.c | 7 +++++++ + arch/arm/mach-aspeed/platform_g5.S | 13 +++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 3 +++ + board/aspeed/ast-g5/ast-g5.c | 30 ++++++++++++++++++++++++++++-- + common/bootm_os.c | 5 +++++ + 5 files changed, 56 insertions(+), 2 deletions(-) +diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c +index d33fb9e0fe78..31bbf77e9e67 100644 +--- a/arch/arm/mach-aspeed/flash.c ++++ b/arch/arm/mach-aspeed/flash.c +@@ -30,6 +30,7 @@ + #include <asm/byteorder.h> + #include <asm/io.h> + #include <environment.h> ++#include <watchdog.h> + + #include <asm/arch/ast_scu.h> + #include <asm/arch/aspeed.h> +@@ -610,6 +611,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) + } + + putc ('.'); ++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) ++ WATCHDOG_RESET(); ++#endif + } + } + puts (" done\n"); +@@ -679,6 +683,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) + src += count; + cnt -= count; + printf("%c\b", pat[(patcnt++) & 0x03]); ++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) ++ WATCHDOG_RESET(); ++#endif + } + + reset_flash(info); diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S -index f221c97b19dc..e468ed68d687 100644 +index f221c97b19dc..3a06557fa99d 100644 --- a/arch/arm/mach-aspeed/platform_g5.S +++ b/arch/arm/mach-aspeed/platform_g5.S -@@ -582,6 +582,31 @@ espi_early_init_done: +@@ -582,6 +582,19 @@ espi_early_init_done: mov r1, #0xAE str r1, [r0] +#ifdef CONFIG_HW_WATCHDOG -+ /* Enable WDT1 to recover u-boot hang */ -+ ldr r0, =0x1e785004 ++ /* Enable WDT2 to recover u-boot hang */ ++ ldr r0, =0x1e785024 + ldr r1, =0x00500000 @ ~5 seconds + str r1, [r0] -+ ldr r0, =0x1e785008 ++ ldr r0, =0x1e785028 + ldr r1, =0x00004755 + str r1, [r0] -+ ldr r0, =0x1e78500c ++ ldr r0, =0x1e78502c + ldr r1, =0x00000033 + str r1, [r0] -+ -+ /* Clear Scratch register Bit 6 to do DDR training again on WDT1 reset */ -+ ldr r0, =0x1e6e203c -+ ldr r1, [r0] -+ tst r1, #(1<<2) -+ beq bypass_scratch_reg_clear -+ ldr r0, =0x1e6e2040 -+ ldr r1, [r0] -+ and r1, r1, #0xFFFFFFBF -+ str r1, [r0] -+ -+bypass_scratch_reg_clear: +#endif + /* Test - DRAM initial time */ ldr r0, =0x1e78203c ldr r1, =0x0000F000 -@@ -2335,6 +2360,13 @@ spi_checksum_wait_0: - ldr r1, [r0] - tst r1, r2 - beq spi_checksum_wait_0 -+ -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x31 @ '1' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - ldr r0, =0x1e620090 - ldr r5, [r0] @ record golden checksum - ldr r0, =0x1e620080 -@@ -2363,6 +2395,13 @@ spi_checksum_wait_1: - ldr r1, [r0] - tst r1, r2 - beq spi_checksum_wait_1 -+ -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - ldr r0, =0x1e620090 - ldr r2, [r0] @ read checksum - ldr r0, =0x1e620080 -@@ -2377,6 +2416,13 @@ spi_checksum_wait_2: - ldr r1, [r0] - tst r1, r2 - beq spi_checksum_wait_2 -+ -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - ldr r0, =0x1e620090 - ldr r2, [r0] @ read checksum - ldr r0, =0x1e620080 -@@ -2394,6 +2440,12 @@ spi_cbr_next_delay_e: - blt spi_cbr_next_delay_s - b spi_cbr_next_clkrate - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - spi_cbr_end: - ldr r0, =0x1e620094 - str r8, [r0] -@@ -2401,6 +2453,16 @@ spi_cbr_end: - mov r1, #0x0 - str r1, [r0] - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x32 @ '2' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - /****************************************************************************** - Miscellaneous Setting - ******************************************************************************/ -@@ -2447,6 +2509,16 @@ spi_cbr_end: - mov r1, #0 - str r1, [r0] - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x33 @ '3' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+ mov r1, #0x2E @ '.' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - /****************************************************************************** - Configure MAC timing - ******************************************************************************/ -@@ -2535,6 +2607,12 @@ set_D2PLL: - ldr r1, =0xEA - str r1, [r0] - -+/* Debug - UART console message */ -+ ldr r0, =0x1e784000 -+ mov r1, #0x34 @ '4' -+ str r1, [r0] -+/* Debug - UART console message */ -+ - /* restore lr */ - mov lr, r4 - diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c index c46bd70b71b2..92518a66fa67 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c @@ -192,25 +111,25 @@ index 00bd92ae5f94..3f27503bce62 100644 { - /* Restart WD2 timer */ - writel(0x4755, AST_WDT2_BASE + 0x08); -+ /* Restart WDT1 */ ++ /* Restart WDT2 */ + writel(AST_WDT_RESTART_VALUE, -+ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++ AST_WDT2_BASE + AST_WDT_COUNTER_RESTART_CTRL); +} + +void hw_watchdog_init(void) +{ -+ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); ++ writel(0, AST_WDT2_BASE + AST_WDT_CTRL); + writel(AST_WDT_TIMEOUT_DEFAULT, -+ AST_WDT1_BASE + AST_WDT_COUNTER_RELOAD_VALUE); ++ AST_WDT2_BASE + AST_WDT_COUNTER_RELOAD_VALUE); + writel(AST_WDT_RESTART_VALUE, -+ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++ AST_WDT2_BASE + AST_WDT_COUNTER_RESTART_CTRL); + writel(AST_WDT_EN_1MHZ_CLK | AST_WDT_SYS_RESET | AST_WDT_ENABLE, -+ AST_WDT1_BASE + AST_WDT_CTRL); ++ AST_WDT2_BASE + AST_WDT_CTRL); +} + +void hw_watchdog_disable(void) +{ -+ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); ++ writel(0, AST_WDT2_BASE + AST_WDT_CTRL); } #endif /* CONFIG_WATCHDOG */ diff --git a/common/bootm_os.c b/common/bootm_os.c diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch deleted file mode 100644 index d8309f32c..000000000 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch +++ /dev/null @@ -1,28 +0,0 @@ -From daa5fdb53f4ed5d40063daf3a3b8ee40115fe5bd Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> -Date: Fri, 11 Sep 2020 09:19:43 -0700 -Subject: [PATCH] Enable CONFIG_DDR4_SUPPORT_HYNIX - -This commit enables CONFIG_DDR4_SUPPORT_HYNIX for test. - -Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> ---- - arch/arm/mach-aspeed/platform_g5.S | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S -index f221c97b19dc..4276d6db3a9a 100644 ---- a/arch/arm/mach-aspeed/platform_g5.S -+++ b/arch/arm/mach-aspeed/platform_g5.S -@@ -149,7 +149,7 @@ - on the MB layout. Customer can find the appropriate frequency for their products. - Below are the new defined parameters for the Hynix DDR4 supporting. - ******************************************************************************/ --//#define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM -+#define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM - //#define CONFIG_DDR4_HYNIX_SET_1536 - //#define CONFIG_DDR4_HYNIX_SET_1488 - #define CONFIG_DDR4_HYNIX_SET_1440 --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0052-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0052-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch new file mode 100644 index 000000000..3c1705c05 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0052-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch @@ -0,0 +1,124 @@ +From b6f1f040f515a43d1903f4c4020032dfe436670d Mon Sep 17 00:00:00 2001 +From: Kuiying Wang <kuiying.wang@intel.com> +Date: Sun, 27 Sep 2020 17:45:56 +0800 +Subject: [PATCH] Fix issue on host console is broken due to BMC reset by + watchdog. + +obmc-console service changed uart routing to support SOL. +UART routing must be changed to normal, when BMC reset happens, +as BMC reset must be treated as SOL connection closure. +User needs to establish a new SOL connection after BMC reset, +and routing will be initialized for SOL at that time. +Which need several seconds (depends on BMC cycle time), +or even never been recoverred if stopped at u-boot shell. + +error situaton as below: +root@intel-obmc:~# devmem 0x1e78909c +0x03450003 +root@intel-obmc:~# /sbin/watchdog -T 0 -F /dev/watchdog1 + +U-Boot 2016.07 (Aug 25 2020 - 05:24:44 +0000) + +SOC : AST2500-A2 +RST : 0x08 (WDT2) +PLL : 24 MHz +CPU : 792 MHz +MEM : 792 MHz, EEC: Disable, Cache: Disable +VGA : 16 MiB +DRAM : init by SOC + Watchdog enabled +DRAM: 496 MiB +Flash: 64 MiB +In: serial +Out: serial +Err: serial +Un-Protected 1 sectors +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +Protected 1 sectors +Net: MAC0 : RMII/NCSI +MAC1 : RGMII +FTGMAC100#0, FTGMAC100#1 +ast# +ast# +ast# md 0x1e78909c +1e78909c: 03450003 ffceff00 19000000 00000000 + +Tested: +u-boot could reset HICRA 0x1e78909c + +correct situation as below: +root@intel-obmc:~# devmem 0x1e78909c +0x03450003 +root@intel-obmc:~# /sbin/watchdog -T 0 -F /dev/watchdog1 + +U-Boot 2016.07 (Sep 27 2020 - 09:34:20 +0000) + +SOC : AST2500-A2 +RST : 0x08 (WDT2) +PLL : 24 MHz +CPU : 792 MHz +MEM : 792 MHz, EEC: Disable, Cache: Disable +VGA : 16 MiB +DRAM : init by SOC + Watchdog enabled +DRAM: 496 MiB +Flash: 64 MiB +In: serial +Out: serial +Err: serial +Un-Protected 1 sectors +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +Protected 1 sectors +Net: MAC0 : RMII/NCSI +MAC1 : RGMII +FTGMAC100#0, FTGMAC100#1 +ast# +ast# +ast# md 0x1e78909c +1e78909c: 00000000 ffceff00 19000000 00000000 + +Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> +--- + arch/arm/include/asm/arch-aspeed/regs-lpc.h | 1 + + board/aspeed/ast-g5/ast-g5.c | 3 +++ + 2 files changed, 4 insertions(+) + +diff --git a/arch/arm/include/asm/arch-aspeed/regs-lpc.h b/arch/arm/include/asm/arch-aspeed/regs-lpc.h +index b0162ae4f3..b4d3da2906 100644 +--- a/arch/arm/include/asm/arch-aspeed/regs-lpc.h ++++ b/arch/arm/include/asm/arch-aspeed/regs-lpc.h +@@ -18,6 +18,7 @@ + */ + + #define AST_LPC_HICR5 0x80 ++#define AST_LPC_HICRA 0x9C + #define AST_LPC_HICRB 0x100 + + /* AST_LPC_HICR5 : 0x80 Host Interface Control Register 5 */ +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index 00bd92ae5f..4c5997ab8a 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -45,6 +45,9 @@ int board_init(void) + val |= LPC_HICRB_ILPC2AHB; + writel(val, AST_LPC_BASE + AST_LPC_HICRB); + ++ /* Reset UART routing */ ++ writel(0x0, AST_LPC_BASE + AST_LPC_HICRA); ++ + /* P2A, PCIe BMC */ + val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET); + val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend index fe150bf9d..a229bd969 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend @@ -47,8 +47,8 @@ SRC_URI_append_intel-ast2500 = " \ file://0046-Enable-FMC-DMA-for-memmove.patch \ file://0047-ast2500-parse-reset-reason.patch \ file://0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch \ - file://0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch \ file://0051-Add-Aspeed-DRAM-stress-test-command.patch \ + file://0052-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch \ " # CVE-2020-10648 vulnerability fix SRC_URI_append_intel-ast2500 = " \ diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0003-Fix-PSU-PWM-fan-control.patch b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0003-Fix-PSU-PWM-fan-control.patch new file mode 100644 index 000000000..49aaaf5f9 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0003-Fix-PSU-PWM-fan-control.patch @@ -0,0 +1,61 @@ +From ed3e946c02c89c389c0e28360692e51971734728 Mon Sep 17 00:00:00 2001 +From: James Feist <james.feist@linux.intel.com> +Date: Thu, 24 Sep 2020 15:31:03 -0700 +Subject: [PATCH 1/1] Fix PSU PWM fan control + +105a19754f003956def5934612b1de86225a4bc1 broke the control +interface range as the interface is supposed to accept 0-255 +fix it. + +Tested: +PSU PID control worked again + +Change-Id: I89c03c3382b221256353cc28b1f182c80a063249 +Signed-off-by: James Feist <james.feist@linux.intel.com> +--- + src/PwmSensor.cpp | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/src/PwmSensor.cpp b/src/PwmSensor.cpp +index 0c5d439..4824489 100644 +--- a/src/PwmSensor.cpp ++++ b/src/PwmSensor.cpp +@@ -27,6 +27,7 @@ + static constexpr size_t sysPwmMax = 255; + static constexpr size_t psuPwmMax = 100; + static constexpr double defaultPwm = 30.0; ++static constexpr size_t targetIfaceMax = 255; + + PwmSensor::PwmSensor(const std::string& name, const std::string& sysPath, + std::shared_ptr<sdbusplus::asio::connection>& conn, +@@ -99,7 +100,7 @@ PwmSensor::PwmSensor(const std::string& name, const std::string& sysPath, + controlInterface->register_property( + "Target", static_cast<uint64_t>(pwmValue), + [this](const uint64_t& req, uint64_t& resp) { +- if (req > pwmMax) ++ if (req > targetIfaceMax) + { + throw std::runtime_error("Value out of range"); + return -1; +@@ -108,7 +109,8 @@ PwmSensor::PwmSensor(const std::string& name, const std::string& sysPath, + { + return 1; + } +- setValue(req); ++ setValue( ++ std::round(pwmMax * static_cast<double>(req) / targetIfaceMax)); + resp = req; + + sensorInterface->signal_property("Value"); +@@ -117,6 +119,8 @@ PwmSensor::PwmSensor(const std::string& name, const std::string& sysPath, + }, + [this](uint64_t& curVal) { + uint64_t value = getValue(); ++ value = static_cast<uint64_t>(std::round( ++ (static_cast<double>(value) / pwmMax) * targetIfaceMax)); + if (curVal != value) + { + curVal = value; +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0004-Check-readingStateGood-before-updating-thresholds-pr.patch b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0004-Check-readingStateGood-before-updating-thresholds-pr.patch new file mode 100644 index 000000000..ae626661a --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0004-Check-readingStateGood-before-updating-thresholds-pr.patch @@ -0,0 +1,99 @@ +From 22a81c2898d6d3da1ba82cd9efead70b860b0acb Mon Sep 17 00:00:00 2001 +From: Zhikui Ren <zhikui.ren@intel.com> +Date: Thu, 1 Oct 2020 08:54:32 -0700 +Subject: [PATCH] Check readingStateGood before updating thresholds property + +Sensor read function checks for readingStateGood before +start. But if host resets while reading is in progress, +incorrect sensor value maybe returned. +Check readingStateGood before changing threshold. + +Add a timer async call for checkThresholds. This gives +power match callback a chance to run to update power state. +This change is only added for cpu sensors to minimize the +the impact and test needed. Change for other sensors or +in base class can be done as a follow up task. + +Tested: +Run host reset test for 500 cycles, no erronous sensor +events were reported. Before the change, same tests +never run more than 200 cycles. + +Signed-off-by: Zhikui Ren <zhikui.ren@intel.com> +--- + include/CPUSensor.hpp | 1 + + src/CPUSensor.cpp | 18 +++++++++++++++--- + src/Thresholds.cpp | 10 ++++++++++ + 3 files changed, 26 insertions(+), 3 deletions(-) + +diff --git a/include/CPUSensor.hpp b/include/CPUSensor.hpp +index 07f7ffd..4a56b21 100644 +--- a/include/CPUSensor.hpp ++++ b/include/CPUSensor.hpp +@@ -37,6 +37,7 @@ class CPUSensor : public Sensor + + private: + sdbusplus::asio::object_server& objServer; ++ std::shared_ptr<sdbusplus::asio::connection>& busConn; + boost::asio::posix::stream_descriptor inputDev; + boost::asio::deadline_timer waitTimer; + boost::asio::streambuf readBuf; +diff --git a/src/CPUSensor.cpp b/src/CPUSensor.cpp +index 127d68a..401412f 100644 +--- a/src/CPUSensor.cpp ++++ b/src/CPUSensor.cpp +@@ -45,8 +45,8 @@ CPUSensor::CPUSensor(const std::string& path, const std::string& objectType, + Sensor(boost::replace_all_copy(sensorName, " ", "_"), + std::move(_thresholds), sensorConfiguration, objectType, maxReading, + minReading, PowerState::on), +- objServer(objectServer), inputDev(io), waitTimer(io), path(path), +- privTcontrol(std::numeric_limits<double>::quiet_NaN()), ++ objServer(objectServer), busConn(conn), inputDev(io), waitTimer(io), ++ path(path), privTcontrol(std::numeric_limits<double>::quiet_NaN()), + dtsOffset(dtsOffset), show(show), pollTime(CPUSensor::sensorPollMs) + { + nameTcontrol = labelTcontrol; +@@ -288,6 +288,18 @@ void CPUSensor::checkThresholds(void) + { + if (show) + { +- thresholds::checkThresholds(this); ++ // give the power match callback to have a chance to run ++ // checkThresholds checks for host power state ++ auto timer = std::make_shared<boost::asio::steady_timer>( ++ busConn->get_io_context()); ++ timer->expires_after(std::chrono::milliseconds(100)); ++ timer->async_wait([this, timer](boost::system::error_code ec) { ++ if (ec) ++ { ++ // log the error but still check the thresholds ++ std::cerr << "Cpu sensor threshold timer error!\n"; ++ } ++ thresholds::checkThresholds(this); ++ }); + } + } +diff --git a/src/Thresholds.cpp b/src/Thresholds.cpp +index 025057e..ce1c759 100644 +--- a/src/Thresholds.cpp ++++ b/src/Thresholds.cpp +@@ -421,6 +421,16 @@ void assertThresholds(Sensor* sensor, double assertValue, + return; + } + ++ // readingState is verified before sensor read, ++ // but it can change during sensor read ++ // and return an incorrect value ++ if (assert && !sensor->readingStateGood()) ++ { ++ std::cout << "bad readingState, ignore theshold assert " << sensor->name ++ << " assert value " << assertValue << "\n"; ++ return; ++ } ++ + if (interface->set_property<bool, true>(property, assert)) + { + try +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0005-ExitAir-Move-to-GetSensorConfiguration.patch b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0005-ExitAir-Move-to-GetSensorConfiguration.patch new file mode 100644 index 000000000..a7533b88a --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0005-ExitAir-Move-to-GetSensorConfiguration.patch @@ -0,0 +1,75 @@ +From 655f376a240ce73f7c3fb6f37cd6da0cbce1693e Mon Sep 17 00:00:00 2001 +From: James Feist <james.feist@linux.intel.com> +Date: Mon, 5 Oct 2020 15:28:15 -0700 +Subject: [PATCH 1/1] ExitAir: Move to GetSensorConfiguration + +GetSensorConfiguration has improved to have retries +and avoid more expensive GetManagedOjects calls. Use +it. + +Tested: System Airflow still worked + +Change-Id: Icbbabb6ebda771b9cde563559a83f633ffc3769f +Signed-off-by: James Feist <james.feist@linux.intel.com> +--- + src/ExitAirTempSensor.cpp | 23 ++++++++++------------- + 1 file changed, 10 insertions(+), 13 deletions(-) + +diff --git a/src/ExitAirTempSensor.cpp b/src/ExitAirTempSensor.cpp +index 41d9a19..c667457 100644 +--- a/src/ExitAirTempSensor.cpp ++++ b/src/ExitAirTempSensor.cpp +@@ -61,6 +61,9 @@ static constexpr double cfmMinReading = 0; + + static constexpr size_t minSystemCfm = 50; + ++constexpr const std::array<const char*, 2> monitorIfaces = {exitAirIface, ++ cfmIface}; ++ + static std::vector<std::shared_ptr<CFMSensor>> cfmSensors; + + static void setupSensorMatch( +@@ -827,14 +830,10 @@ void createSensor(sdbusplus::asio::object_server& objectServer, + std::cerr << "Connection not created\n"; + return; + } +- dbusConnection->async_method_call( +- [&](boost::system::error_code ec, const ManagedObjectType& resp) { +- if (ec) +- { +- std::cerr << "Error contacting entity manager\n"; +- return; +- } +- ++ auto getter = std::make_shared<GetSensorConfiguration>( ++ dbusConnection, ++ std::move([&objectServer, &dbusConnection, ++ &exitAirSensor](const ManagedObjectType& resp) { + cfmSensors.clear(); + for (const auto& pathPair : resp) + { +@@ -908,9 +907,9 @@ void createSensor(sdbusplus::asio::object_server& objectServer, + exitAirSensor->setupMatches(); + exitAirSensor->updateReading(); + } +- }, +- entityManagerName, "/", "org.freedesktop.DBus.ObjectManager", +- "GetManagedObjects"); ++ })); ++ getter->getConfiguration( ++ std::vector<std::string>(monitorIfaces.begin(), monitorIfaces.end())); + } + + int main() +@@ -944,8 +943,6 @@ int main() + } + }); + }; +- constexpr const std::array<const char*, 2> monitorIfaces = {exitAirIface, +- cfmIface}; + for (const char* type : monitorIfaces) + { + auto match = std::make_unique<sdbusplus::bus::match::match>( +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0006-Treat-negative-temperatures-as-errors.patch b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0006-Treat-negative-temperatures-as-errors.patch new file mode 100644 index 000000000..13dc820d6 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0006-Treat-negative-temperatures-as-errors.patch @@ -0,0 +1,73 @@ +From 6f6b9cb68992e3493489d16b28bd0903e66ce587 Mon Sep 17 00:00:00 2001 +From: Zhikui Ren <zhikui.ren@intel.com> +Date: Tue, 6 Oct 2020 15:34:29 -0700 +Subject: [PATCH] Treat negative temperatures as errors + +During normal operations, temperature sensors are not expected to +read as zero or have negative values. +There might be some other root cause need to be identified +and addressed. Treat zeros and negative readings as errors +in temperatures as a workaround. + +Tested: +Valid temperature reading are being reported. +Negative readings are ignored. + +Signed-off-by: Zhikui Ren <zhikui.ren@intel.com> +--- + src/HwmonTempSensor.cpp | 13 +++++++++++-- + src/IpmbSensor.cpp | 7 ++++--- + 2 files changed, 15 insertions(+), 5 deletions(-) + +diff --git a/src/HwmonTempSensor.cpp b/src/HwmonTempSensor.cpp +index 649ca68..5514504 100644 +--- a/src/HwmonTempSensor.cpp ++++ b/src/HwmonTempSensor.cpp +@@ -116,8 +116,17 @@ void HwmonTempSensor::handleResponse(const boost::system::error_code& err) + try + { + double nvalue = std::stod(response); +- nvalue /= sensorScaleFactor; +- updateValue(nvalue); ++ if (nvalue < 0) ++ { ++ std::cerr << "Hwmon temp sensor " << name ++ << ": ignore negative rawValue " << nvalue << "\n"; ++ incrementError(); ++ } ++ else ++ { ++ nvalue /= sensorScaleFactor; ++ updateValue(nvalue); ++ } + } + catch (const std::invalid_argument&) + { +diff --git a/src/IpmbSensor.cpp b/src/IpmbSensor.cpp +index bc9d842..1855519 100644 +--- a/src/IpmbSensor.cpp ++++ b/src/IpmbSensor.cpp +@@ -241,7 +241,6 @@ bool IpmbSensor::processReading(const std::vector<uint8_t>& data, double& resp) + return false; + } + resp = data[0]; +- + return true; + } + case (ReadingFormat::byte3): +@@ -341,8 +340,10 @@ void IpmbSensor::read(void) + } + + double value = 0; +- +- if (!processReading(data, value)) ++ // Temperature sensors are not expected to read 0 ++ // treat them as errors ++ if (!processReading(data, value) || ++ (subType == IpmbSubType::temp && value == 0.0)) + { + incrementError(); + read(); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend index a8a74f3e0..a265f04df 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend @@ -1,4 +1,8 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" SRC_URI += "file://0001-Only-allow-drive-sensors-on-bus-2-for-ast2500.patch \ - file://0002-Fix-missing-threshold-de-assert-event-when-threshold.patch" + file://0002-Fix-missing-threshold-de-assert-event-when-threshold.patch \ + file://0003-Fix-PSU-PWM-fan-control.patch \ + file://0004-Check-readingStateGood-before-updating-thresholds-pr.patch \ + file://0005-ExitAir-Move-to-GetSensorConfiguration.patch \ + file://0006-Treat-negative-temperatures-as-errors.patch" |