diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2500')
11 files changed, 771 insertions, 26 deletions
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch index 40336d3dd..5e459b85d 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0007-Add-espi-support.patch @@ -1,7 +1,7 @@ -From dff3a123b0318f83ecd753eea8945ebdc15fd2f9 Mon Sep 17 00:00:00 2001 +From 1752e8b935996fe9359ba4990156d9b57d7a7b8e Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 10:21:40 -0800 -Subject: [PATCH 1/1] Add espi support +Subject: [PATCH] Add espi support This adds basic eSPI support for U-Boot. The eSPI driver works best with interrupts because the timing of the initialization with the PCH is not @@ -13,13 +13,15 @@ functions. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: James Feist <james.feist@linux.intel.com> +Signed-off-by: Saravanan Palanisamy <saravanan.palanisamy@intel.com> +Signed-off-by: Richard Marian Thomaiyar <richard.marian.thomaiyar@linux.intel.com> --- arch/arm/include/asm/arch-aspeed/regs-scu.h | 2 + board/aspeed/ast-g5/Makefile | 2 + - board/aspeed/ast-g5/ast-g5-espi.c | 248 ++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-espi.c | 264 ++++++++++++++++++++ board/aspeed/ast-g5/ast-g5-intel.c | 16 ++ board/aspeed/ast-g5/ast-g5.c | 3 + - 5 files changed, 271 insertions(+) + 5 files changed, 287 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-espi.c create mode 100644 board/aspeed/ast-g5/ast-g5-intel.c @@ -47,10 +49,10 @@ index df4e63966e..58e0c648f4 100644 obj-y += ast-g5-irq.o diff --git a/board/aspeed/ast-g5/ast-g5-espi.c b/board/aspeed/ast-g5/ast-g5-espi.c new file mode 100644 -index 0000000000..5a3ffe7bef +index 0000000000..3f169d4141 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-espi.c -@@ -0,0 +1,248 @@ +@@ -0,0 +1,264 @@ +/* + * Copyright 2018 Intel Corporation + * @@ -186,6 +188,22 @@ index 0000000000..5a3ffe7bef + uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; + writel(v, AST_ESPI_BASE + ESPI104); + } ++ ++ if (readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_HOST_RST_WARN) { ++ DBG_ESPI("Boot HOST_RST WARN set %08x\n", ++ readl(AST_ESPI_BASE + ESPI098)); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) ++ | AST_ESPI_HOST_RST_ACK; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ } ++ ++ if (readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_OOB_RST_WARN) { ++ DBG_ESPI("Boot OOB_RST WARN set %08x\n", ++ readl(AST_ESPI_BASE + ESPI098)); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) ++ | AST_ESPI_OOB_RST_ACK; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ } +} + +static int espi_irq_handler(struct pt_regs *regs) diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch index 392acb9ad..79d7ec60d 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch @@ -1,4 +1,4 @@ -From bd0d8af493387ab1602a0a40b4a548981c1e4d00 Mon Sep 17 00:00:00 2001 +From 4ae4e9e9cde04a76fe8052dbf69a8fe4e7d018c0 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Wed, 24 Jul 2019 20:11:30 +0530 Subject: [PATCH] PFR FW update and checkpoint support in u-boot @@ -45,7 +45,7 @@ index 0b2d936c23..9021d7fc08 100644 obj-y += fw-update.o +obj-y += pfr-mgr.o diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index dde5adbc70..6ef3ca9f73 100644 +index c46bd70b71..8d390b1ea1 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -16,6 +16,7 @@ @@ -56,7 +56,7 @@ index dde5adbc70..6ef3ca9f73 100644 /* Names to match the GPIOs */ enum gpio_names { -@@ -634,6 +635,10 @@ void ast_g5_intel(void) +@@ -687,6 +688,10 @@ void ast_g5_intel(void) ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); @@ -65,11 +65,11 @@ index dde5adbc70..6ef3ca9f73 100644 + set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, PFR_CPLD_CHKPOINT_START); + uart_init(); + mailbox_init(); pwm_init(); - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); -@@ -649,6 +654,11 @@ void ast_g5_intel(void) +@@ -708,6 +713,11 @@ void ast_g5_intel(void) kcs_init(); - if (intel_get_platform_id() == COOPER_CITY_BOARD_ID) + if (platform_id == COOPER_CITY_BOARD_ID) set_pwm_duty_cycle(ELEVATED_PWM_DUTY_VALUE); + /* Notify CPLD about FFUJ jumper set and pause + * of booting for indefinitely time. It will be @@ -77,8 +77,8 @@ index dde5adbc70..6ef3ca9f73 100644 + set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, + PFR_CPLD_CHKPOINT_FFUJ); /* TODO: need to stop the booting here. */ - } - } + } else { + /* diff --git a/board/aspeed/ast-g5/fw-update.c b/board/aspeed/ast-g5/fw-update.c index 99239938b5..89fe5fd4fd 100644 --- a/board/aspeed/ast-g5/fw-update.c diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch index f2d1ebdeb..99222f418 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch @@ -103,7 +103,7 @@ diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-int index 06c6708..e6dd2e6 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -661,6 +661,15 @@ extern void espi_init(void); +@@ -662,6 +662,15 @@ extern void espi_init(void); extern void kcs_init(void); void ast_g5_intel(void) { @@ -116,9 +116,9 @@ index 06c6708..e6dd2e6 100644 + */ + ast_scu_write(AST_WDT_RESET_MASK, AST_SCU_WDT_RESET); + - /* Disable uart port debug function */ - ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | - SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); + #ifdef USE_SOC_UART_DEBUG + /* Enable uart port debug function */ + ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) & -- 2.7.4 diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch index 3833d2a31..94c35be61 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch @@ -1,4 +1,4 @@ -From 51ae3c80f20be3b8e010aa57041fa9c38076cc76 Mon Sep 17 00:00:00 2001 +From 2dd6a0a9a6271bcb415349fdf5fbd5df3a44aeb6 Mon Sep 17 00:00:00 2001 From: Vikram Bodireddy <vikram.bodireddy@intel.com> Date: Wed, 18 Mar 2020 21:47:11 +0530 Subject: [PATCH] PFR- Skip counting WDT2 event when EXTRST# is set @@ -19,18 +19,18 @@ Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 575061ff88..872c7a843a 100644 +index 6a0d6556bc..c5aded759d 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -145,6 +145,7 @@ static const GPIOValue gpio_table[] = { +@@ -136,6 +136,7 @@ static const GPIOValue gpio_table[] = { #define HOST_SERIAL_B_HIGH_SPEED (1 << 1) #define WATCHDOG_RESET_BIT 0x8 +#define EXTRST_RESET_BIT 0x2 #define BOOT_FAILURE_LIMIT 0x3 - - #define BRIGHTON_CITY_BOARD_ID 0 -@@ -572,7 +573,8 @@ void ast_g5_intel_late_init(void) + + #define COOPER_CITY_BOARD_ID 40 +@@ -552,7 +553,8 @@ void ast_g5_intel_late_init(void) boot_failures = get_boot_failures(); diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch new file mode 100644 index 000000000..d52b1184a --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch @@ -0,0 +1,239 @@ +From cc144438f78be5de8e9a67fd8cc898123e32d266 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Mon, 14 Sep 2020 17:38:28 -0700 +Subject: [PATCH] Add WDT to u-boot to cover booting failures + +This commit enables WDT1 in early booting phase in u-boot to make BMC +reset to cover booting failures. If BMC meet any failure or if +systemd can't initiate watchdog timer service properly, BMC will +be reset by this watchdog. This watchdog will get feeding by +WATCHDOG_RESET macro calls from several points in u-boot loop +code. The early u-boot WD timeout is 5 seconds and kernel booting WD +timeout is 100 seconds. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/mach-aspeed/platform_g5.S | 78 ++++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 3 ++ + board/aspeed/ast-g5/ast-g5.c | 30 +++++++++++- + common/bootm_os.c | 5 ++ + 4 files changed, 114 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S +index f221c97b19dc..e468ed68d687 100644 +--- a/arch/arm/mach-aspeed/platform_g5.S ++++ b/arch/arm/mach-aspeed/platform_g5.S +@@ -582,6 +582,31 @@ espi_early_init_done: + mov r1, #0xAE + str r1, [r0] + ++#ifdef CONFIG_HW_WATCHDOG ++ /* Enable WDT1 to recover u-boot hang */ ++ ldr r0, =0x1e785004 ++ ldr r1, =0x00500000 @ ~5 seconds ++ str r1, [r0] ++ ldr r0, =0x1e785008 ++ ldr r1, =0x00004755 ++ str r1, [r0] ++ ldr r0, =0x1e78500c ++ ldr r1, =0x00000033 ++ str r1, [r0] ++ ++ /* Clear Scratch register Bit 6 to do DDR training again on WDT1 reset */ ++ ldr r0, =0x1e6e203c ++ ldr r1, [r0] ++ tst r1, #(1<<2) ++ beq bypass_scratch_reg_clear ++ ldr r0, =0x1e6e2040 ++ ldr r1, [r0] ++ and r1, r1, #0xFFFFFFBF ++ str r1, [r0] ++ ++bypass_scratch_reg_clear: ++#endif ++ + /* Test - DRAM initial time */ + ldr r0, =0x1e78203c + ldr r1, =0x0000F000 +@@ -2335,6 +2360,13 @@ spi_checksum_wait_0: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_0 ++ ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x31 @ '1' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + ldr r0, =0x1e620090 + ldr r5, [r0] @ record golden checksum + ldr r0, =0x1e620080 +@@ -2363,6 +2395,13 @@ spi_checksum_wait_1: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_1 ++ ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 +@@ -2377,6 +2416,13 @@ spi_checksum_wait_2: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_2 ++ ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 +@@ -2394,6 +2440,12 @@ spi_cbr_next_delay_e: + blt spi_cbr_next_delay_s + b spi_cbr_next_clkrate + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + spi_cbr_end: + ldr r0, =0x1e620094 + str r8, [r0] +@@ -2401,6 +2453,16 @@ spi_cbr_end: + mov r1, #0x0 + str r1, [r0] + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x32 @ '2' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + /****************************************************************************** + Miscellaneous Setting + ******************************************************************************/ +@@ -2447,6 +2509,16 @@ spi_cbr_end: + mov r1, #0 + str r1, [r0] + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x33 @ '3' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + /****************************************************************************** + Configure MAC timing + ******************************************************************************/ +@@ -2535,6 +2607,12 @@ set_D2PLL: + ldr r1, =0xEA + str r1, [r0] + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x34 @ '4' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + /* restore lr */ + mov lr, r4 + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index c46bd70b71b2..92518a66fa67 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -701,6 +701,9 @@ void ast_g5_intel(void) + timer8_init(); + enable_onboard_tpm(); + if (intel_force_firmware_jumper_enabled()) { ++#ifdef CONFIG_HW_WATCHDOG ++ hw_watchdog_disable(); ++#endif + /* FFUJ mode:- ChassisID: Solid Blue, StatusLED: Solid Amber */ + id_led_control(GPIO_ID_LED, EIDLED_On); + id_led_control(GPIO_GREEN_LED, EIDLED_Off); +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index 00bd92ae5f94..3f27503bce62 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -125,9 +125,35 @@ int board_eth_init(bd_t *bd) + + /* Called by macro WATCHDOG_RESET */ + #if defined(CONFIG_HW_WATCHDOG) ++#define AST_WDT_COUNTER_STATUS 0x00 ++#define AST_WDT_COUNTER_RELOAD_VALUE 0x04 ++#define AST_WDT_COUNTER_RESTART_CTRL 0x08 ++#define AST_WDT_RESTART_VALUE 0x4755 ++#define AST_WDT_CTRL 0x0c ++#define AST_WDT_EN_1MHZ_CLK BIT(4) ++#define AST_WDT_SYS_RESET BIT(1) ++#define AST_WDT_ENABLE BIT(0) ++#define AST_WDT_TIMEOUT_DEFAULT 0x6000000 /* ~100 seconds */ + void hw_watchdog_reset(void) + { +- /* Restart WD2 timer */ +- writel(0x4755, AST_WDT2_BASE + 0x08); ++ /* Restart WDT1 */ ++ writel(AST_WDT_RESTART_VALUE, ++ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++} ++ ++void hw_watchdog_init(void) ++{ ++ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); ++ writel(AST_WDT_TIMEOUT_DEFAULT, ++ AST_WDT1_BASE + AST_WDT_COUNTER_RELOAD_VALUE); ++ writel(AST_WDT_RESTART_VALUE, ++ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++ writel(AST_WDT_EN_1MHZ_CLK | AST_WDT_SYS_RESET | AST_WDT_ENABLE, ++ AST_WDT1_BASE + AST_WDT_CTRL); ++} ++ ++void hw_watchdog_disable(void) ++{ ++ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); + } + #endif /* CONFIG_WATCHDOG */ +diff --git a/common/bootm_os.c b/common/bootm_os.c +index b56eb39780e8..ec0e12ac84b9 100644 +--- a/common/bootm_os.c ++++ b/common/bootm_os.c +@@ -473,11 +473,16 @@ __weak void arch_preboot_os(void) + /* please define platform specific arch_preboot_os() */ + } + ++extern void hw_watchdog_init(void); ++ + int boot_selected_os(int argc, char * const argv[], int state, + bootm_headers_t *images, boot_os_fn *boot_fn) + { + disable_interrupts(); + arch_preboot_os(); ++#ifdef CONFIG_HW_WATCHDOG ++ hw_watchdog_init(); /* Re-init WDT with 100 seconds timeout */ ++#endif + boot_fn(state, argc, argv, images); + + /* Stand-alone may return when 'autostart' is 'no' */ +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch new file mode 100644 index 000000000..d8309f32c --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch @@ -0,0 +1,28 @@ +From daa5fdb53f4ed5d40063daf3a3b8ee40115fe5bd Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Fri, 11 Sep 2020 09:19:43 -0700 +Subject: [PATCH] Enable CONFIG_DDR4_SUPPORT_HYNIX + +This commit enables CONFIG_DDR4_SUPPORT_HYNIX for test. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/mach-aspeed/platform_g5.S | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S +index f221c97b19dc..4276d6db3a9a 100644 +--- a/arch/arm/mach-aspeed/platform_g5.S ++++ b/arch/arm/mach-aspeed/platform_g5.S +@@ -149,7 +149,7 @@ + on the MB layout. Customer can find the appropriate frequency for their products. + Below are the new defined parameters for the Hynix DDR4 supporting. + ******************************************************************************/ +-//#define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM ++#define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM + //#define CONFIG_DDR4_HYNIX_SET_1536 + //#define CONFIG_DDR4_HYNIX_SET_1488 + #define CONFIG_DDR4_HYNIX_SET_1440 +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0051-Add-Aspeed-DRAM-stress-test-command.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0051-Add-Aspeed-DRAM-stress-test-command.patch new file mode 100644 index 000000000..377be5e53 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0051-Add-Aspeed-DRAM-stress-test-command.patch @@ -0,0 +1,302 @@ +From 6ccd771297fdfc4dbb0571001e787a72f9348df9 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Wed, 16 Sep 2020 15:14:26 -0700 +Subject: [PATCH] Add Aspeed DRAM stress test command + +This commit adds DRAM stress test command. Also, it enables +SoC UART debug feature. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + board/aspeed/ast-g5/ast-g5-intel.c | 8 ++ + cmd/Kconfig | 4 + + cmd/Makefile | 2 + + cmd/dramtest.c | 219 +++++++++++++++++++++++++++++ + 4 files changed, 233 insertions(+) + create mode 100644 cmd/dramtest.c + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index c46bd70b71b2..91dae91d02e4 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -140,6 +140,8 @@ static const GPIOValue gpio_table[] = { + + #define COOPER_CITY_BOARD_ID 40 + ++#define USE_SOC_UART_DEBUG ++ + static int get_boot_failures(void) + { + return getenv_ulong("bootfailures", 10, 0); +@@ -660,9 +662,15 @@ extern void espi_init(void); + extern void kcs_init(void); + void ast_g5_intel(void) + { ++#ifdef USE_SOC_UART_DEBUG ++ /* Enable uart port debug function */ ++ ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) & ++ ~SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); ++#else + /* Disable uart port debug function */ + ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | + SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); ++#endif + + uart_init(); + mailbox_init(); +diff --git a/cmd/Kconfig b/cmd/Kconfig +index 33be2407d2ba..e7c7c4b67cef 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -605,6 +605,10 @@ config CMD_QFW + This provides access to the QEMU firmware interface. The main + feature is to allow easy loading of files passed to qemu-system + via -kernel / -initrd ++ ++config CMD_DRAMTEST ++ bool "ASPEED DRAM controller stress test" ++ default y + endmenu + + config CMD_BOOTSTAGE +diff --git a/cmd/Makefile b/cmd/Makefile +index c8ac0af55c05..eda5f91338ce 100644 +--- a/cmd/Makefile ++++ b/cmd/Makefile +@@ -152,6 +152,8 @@ obj-$(CONFIG_CMD_DFU) += dfu.o + obj-$(CONFIG_CMD_GPT) += gpt.o + obj-$(CONFIG_CMD_ETHSW) += ethsw.o + ++obj-$(CONFIG_CMD_DRAMTEST) += dramtest.o ++ + # Power + obj-$(CONFIG_CMD_PMIC) += pmic.o + obj-$(CONFIG_CMD_REGULATOR) += regulator.o +diff --git a/cmd/dramtest.c b/cmd/dramtest.c +new file mode 100644 +index 000000000000..cb2f0ea5ac35 +--- /dev/null ++++ b/cmd/dramtest.c +@@ -0,0 +1,219 @@ ++/* ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <console.h> ++#include <bootretry.h> ++#include <cli.h> ++#include <command.h> ++#include <console.h> ++ ++#include <inttypes.h> ++#include <mapmem.h> ++#include <asm/io.h> ++#include <linux/compiler.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define DRAM_BASE 0x80000000 ++#define TIMEOUT_DRAM 5000000 ++ ++#ifdef CONFIG_ASPEED_AST2600 ++#define BLK_SIZE_MB 64 ++#define N_BLK 32 ++#define MCR74_BLK_OFFSET 26 ++#define MCR74_LEN_OFFSET 4 ++#define MCR74_BLK_LEN_MASK GENMASK(30, 4) ++#else ++#define BLK_SIZE_MB 16 ++#define N_BLK 64 ++#define MCR74_BLK_OFFSET 24 ++#define MCR74_LEN_OFFSET 4 ++#define MCR74_BLK_LEN_MASK GENMASK(29, 4) ++#endif ++#define BLK_SIZE (BLK_SIZE_MB * 1024 * 1024) ++#define N_16B_IN_BLK (BLK_SIZE / 16) ++ ++/* ------------------------------------------------------------------------- */ ++int MMCTestBurst(unsigned int datagen) ++{ ++ unsigned int data; ++ unsigned int timeout = 0; ++ ++ writel(0x00000000, 0x1E6E0070); ++ writel((0x000000C1 | (datagen << 3)), 0x1E6E0070); ++ ++ do { ++ data = readl(0x1E6E0070) & 0x3000; ++ ++ if( data & 0x2000 ) ++ return(0); ++ ++ if( ++timeout > TIMEOUT_DRAM ) { ++ printf("Timeout!!\n"); ++ writel(0x00000000, 0x1E6E0070); ++ return(0); ++ } ++ } while (!data); ++ ++ writel(0x00000000, 0x1E6E0070); ++ ++ return(1); ++} ++ ++/* ------------------------------------------------------------------------- */ ++int MMCTestSingle(unsigned int datagen) ++{ ++ unsigned int data; ++ unsigned int timeout = 0; ++ ++ writel(0x00000000, 0x1E6E0070); ++ writel((0x00000085 | (datagen << 3)), 0x1E6E0070); ++ ++ do { ++ data = readl(0x1E6E0070) & 0x3000; ++ ++ if( data & 0x2000 ) ++ return(0); ++ ++ if( ++timeout > TIMEOUT_DRAM ){ ++ printf("Timeout!!\n"); ++ writel(0x00000000, 0x1E6E0070); ++ ++ return(0); ++ } ++ } while ( !data ); ++ ++ writel(0x00000000, 0x1E6E0070); ++ ++ return(1); ++} ++ ++/* ------------------------------------------------------------------------- */ ++int MMCTest(void) ++{ ++ unsigned int pattern; ++ ++ pattern = rand(); ++ writel(pattern, 0x1E6E007C); ++ printf("Pattern = %08X : ",pattern); ++ ++ if(!MMCTestBurst(0)) return(0); ++ if(!MMCTestBurst(1)) return(0); ++ if(!MMCTestBurst(2)) return(0); ++ if(!MMCTestBurst(3)) return(0); ++ if(!MMCTestBurst(4)) return(0); ++ if(!MMCTestBurst(5)) return(0); ++ if(!MMCTestBurst(6)) return(0); ++ if(!MMCTestBurst(7)) return(0); ++ if(!MMCTestSingle(0)) return(0); ++ if(!MMCTestSingle(1)) return(0); ++ if(!MMCTestSingle(2)) return(0); ++ if(!MMCTestSingle(3)) return(0); ++ if(!MMCTestSingle(4)) return(0); ++ if(!MMCTestSingle(5)) return(0); ++ if(!MMCTestSingle(6)) return(0); ++ if(!MMCTestSingle(7)) return(0); ++ ++ return(1); ++} ++ ++/* ------------------------------------------------------------------------- */ ++static void print_usage(void) ++{ ++ printf("\nASPEED DRAM BIST\n\n"); ++ printf("Usage: dramtest <count> <block> <length>\n\n"); ++ printf("count: how many iterations to run (mandatory, in decimal)\n"); ++ printf(" 0: infinite loop.\n"); ++ printf("block: index of the address block to test " ++ "(optional, in decimal, default: 0)\n"); ++ printf(" 0: [%08x, %08x)\n", DRAM_BASE + BLK_SIZE * 0, DRAM_BASE + BLK_SIZE * 1); ++ printf(" 1: [%08x, %08x)\n", DRAM_BASE + BLK_SIZE * 1, DRAM_BASE + BLK_SIZE * 2); ++ printf(" 2: [%08x, %08x)\n", DRAM_BASE + BLK_SIZE * 2, DRAM_BASE + BLK_SIZE * 3); ++ printf(" n: [80000000 + n*%dMB, 80000000 + (n+1)*%dMB)\n", BLK_SIZE_MB, BLK_SIZE_MB); ++ printf(" where n = [0, %d]\n", N_BLK - 1); ++ printf("length: size to test (optional, in hex, default: 0x10000)\n"); ++ printf(" 0x0: test the whole memory block %dMB\n", BLK_SIZE_MB); ++ printf(" 0x1: test the first 16 Bytes of the memory block\n"); ++ printf(" 0x2: test the first 2*16 Bytes of the memory block\n"); ++ printf(" n : test the first n*16 Bytes of the memory block\n"); ++ printf(" where n = [0x00000001, 0x%08x]\n", N_16B_IN_BLK - 1); ++ printf("\n\n"); ++} ++ ++static int ++do_ast_dramtest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ u32 PassCnt = 0; ++ unsigned long Testcounter = 0; ++ unsigned long block = 0; ++ unsigned long length = 0x10000; ++ int ret; ++ ++ if (argc < 2) { ++ ret = 0; ++ goto cmd_err; ++ } ++ ++ ret = CMD_RET_USAGE; ++ switch (argc) { ++ case 4: ++ if (strict_strtoul(argv[3], 16, &length) < 0 || ++ length > N_16B_IN_BLK - 1) ++ goto cmd_err; ++ if (length == 0) ++ length = N_16B_IN_BLK - 1; ++ /* fall through */ ++ case 3: ++ if (strict_strtoul(argv[2], 10, &block) < 0 || ++ block > N_BLK - 1) ++ goto cmd_err; ++ /* fall through */ ++ case 2: ++ if (strict_strtoul(argv[1], 10, &Testcounter) < 0) ++ goto cmd_err; ++ break; ++ default: ++ goto cmd_err; ++ } ++ ++ printf("Test range: 0x%08lx - 0x%08lx\n", DRAM_BASE + (block << MCR74_BLK_OFFSET), ++ DRAM_BASE + (block << MCR74_BLK_OFFSET) + (length << 4) + 15); ++ ++ ret = 1; ++ writel(0xFC600309, 0x1E6E0000); ++ while ((Testcounter > PassCnt) || (Testcounter == 0)) { ++ clrsetbits_le32(0x1E6E0074, MCR74_BLK_LEN_MASK, ++ (block << MCR74_BLK_OFFSET) | (length << MCR74_LEN_OFFSET)); ++ ++ if (!MMCTest()) { ++ printf("FAIL %d/%ld (fail DQ 0x%08x)\n", PassCnt, ++ Testcounter, readl(0x1E6E0078)); ++ ret = 0; ++ break; ++ } else { ++ PassCnt++; ++ printf("Pass %d/%ld\n", PassCnt, Testcounter); ++ } ++ } ++ ++ return (ret); ++ ++cmd_err: ++ print_usage(); ++ return (ret); ++} ++ ++U_BOOT_CMD( ++ dramtest, 5, 0, do_ast_dramtest, ++ "ASPEED DRAM BIST", ++ "" ++); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend index f5b54893f..fe150bf9d 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend @@ -46,6 +46,9 @@ SRC_URI_append_intel-ast2500 = " \ file://0045-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch \ file://0046-Enable-FMC-DMA-for-memmove.patch \ file://0047-ast2500-parse-reset-reason.patch \ + file://0049-Add-WDT-to-u-boot-to-cover-booting-failures.patch \ + file://0050-Enable-CONFIG_DDR4_SUPPORT_HYNIX.patch \ + file://0051-Add-Aspeed-DRAM-stress-test-command.patch \ " # CVE-2020-10648 vulnerability fix SRC_URI_append_intel-ast2500 = " \ diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json index 34a38489e..1d2048335 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json @@ -1684,7 +1684,7 @@ "Type": "PSUPresence" }, { - "RedundantCount": 1, + "RedundantCount": 2, "Name": "Power Unit Redundancy", "Type": "PURedundancy" }, diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0002-Fix-missing-threshold-de-assert-event-when-threshold.patch b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0002-Fix-missing-threshold-de-assert-event-when-threshold.patch new file mode 100644 index 000000000..13f9a157a --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0002-Fix-missing-threshold-de-assert-event-when-threshold.patch @@ -0,0 +1,154 @@ +From 8990f3d3d3d74c0bed2c0920073e1ecfd4ff422d Mon Sep 17 00:00:00 2001 +From: Zhikui Ren <zhikui.ren@intel.com> +Date: Thu, 24 Sep 2020 14:27:32 -0700 +Subject: [PATCH] Fix missing threshold de-assert event when threshold changes. + +Destructor can be called when sensor interface changes +like a new threshold value. Ensure adc sensor hresholds are de-asserted +on destruction. These events can be missed if the new threshold +value fixed the alarm because default state for new threshold +interface is de-asserted. + +Tested: +step1: +busctl set-property xyz.openbmc_project.ADCSensor /xyz/openbmc_project/sensors/voltage/P3VBAT xyz.openbmc_project.Sensor.Threshold.Warning WarningLow d 2.457 +ipmitool sel list +SEL has no entries +step2: +busctl set-property xyz.openbmc_project.ADCSensor /xyz/openbmc_project/sensors/voltage/P3VBAT xyz.openbmc_project.Sensor.Threshold.Warning WarningLow d 3.1 +ipmitool sel list + 1 | 09/24/20 | 21:30:15 UTC | Voltage #0x2d | Lower Non-critical going low | Asserted +step3: +busctl set-property xyz.openbmc_project.ADCSensor /xyz/openbmc_project/sensors/voltage/P3VBAT xyz.openbmc_project.Sensor.Threshold.Warning WarningLow d 2.457 +ipmitool sel list + 1 | 09/24/20 | 21:30:15 UTC | Voltage #0x2d | Lower Non-critical going low | Asserted + 2 | 09/24/20 | 21:30:33 UTC | Voltage #0x2d | Lower Non-critical going low | Deasserted + +Signed-off-by: Zhikui Ren <zhikui.ren@intel.com> +Change-Id: If28870ac1e0d09be4a631a3145408ec70390dfc5 +--- + include/Thresholds.hpp | 3 ++ + src/ADCSensor.cpp | 12 ++++++++ + src/Thresholds.cpp | 62 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 77 insertions(+) + +diff --git a/include/Thresholds.hpp b/include/Thresholds.hpp +index ca2b0a0..1d1b1b5 100644 +--- a/include/Thresholds.hpp ++++ b/include/Thresholds.hpp +@@ -47,6 +47,9 @@ void assertThresholds(Sensor* sensor, double assertValue, + thresholds::Level level, thresholds::Direction direction, + bool assert); + ++void forceDeassertThresholds(Sensor* sensor, thresholds::Level level, ++ thresholds::Direction direction); ++ + struct TimerUsed + { + bool used; +diff --git a/src/ADCSensor.cpp b/src/ADCSensor.cpp +index 7afb2ab..701c58e 100644 +--- a/src/ADCSensor.cpp ++++ b/src/ADCSensor.cpp +@@ -88,6 +88,18 @@ ADCSensor::~ADCSensor() + // close the input dev to cancel async operations + inputDev.close(); + waitTimer.cancel(); ++ ++ // Destructor can be called when sensor interface changes ++ // like a new threshold value. Ensure LOW thresholds are de-asserted ++ // on destruction. These events can be missed if the new threshold ++ // value fixed the alarm because default state for new threshold ++ // interface is de-asserted. ++ for (auto& threshold : thresholds) ++ { ++ thresholds::forceDeassertThresholds(this, threshold.level, ++ threshold.direction); ++ } ++ + objServer.remove_interface(thresholdInterfaceWarning); + objServer.remove_interface(thresholdInterfaceCritical); + objServer.remove_interface(sensorInterface); +diff --git a/src/Thresholds.cpp b/src/Thresholds.cpp +index 6aa077c..e480554 100644 +--- a/src/Thresholds.cpp ++++ b/src/Thresholds.cpp +@@ -344,6 +344,7 @@ bool checkThresholds(Sensor* sensor) + { + bool status = true; + std::vector<ChangeParam> changes = checkThresholds(sensor, sensor->value); ++ + for (const auto& change : changes) + { + assertThresholds(sensor, change.assertValue, change.threshold.level, +@@ -452,6 +453,67 @@ void assertThresholds(Sensor* sensor, double assertValue, + } + } + ++void forceDeassertThresholds(Sensor* sensor, thresholds::Level level, ++ thresholds::Direction direction) ++{ ++ std::string property; ++ std::shared_ptr<sdbusplus::asio::dbus_interface> interface; ++ if (level == thresholds::Level::WARNING && ++ direction == thresholds::Direction::HIGH) ++ { ++ property = "WarningAlarmHigh"; ++ interface = sensor->thresholdInterfaceWarning; ++ } ++ else if (level == thresholds::Level::WARNING && ++ direction == thresholds::Direction::LOW) ++ { ++ property = "WarningAlarmLow"; ++ interface = sensor->thresholdInterfaceWarning; ++ } ++ else if (level == thresholds::Level::CRITICAL && ++ direction == thresholds::Direction::HIGH) ++ { ++ property = "CriticalAlarmHigh"; ++ interface = sensor->thresholdInterfaceCritical; ++ } ++ else if (level == thresholds::Level::CRITICAL && ++ direction == thresholds::Direction::LOW) ++ { ++ property = "CriticalAlarmLow"; ++ interface = sensor->thresholdInterfaceCritical; ++ } ++ else ++ { ++ std::cerr << "Unknown threshold, level " << level << "direction " ++ << direction << "\n"; ++ return; ++ } ++ if (!interface) ++ { ++ std::cout << "trying to set uninitialized interface\n"; ++ return; ++ } ++ ++ if (interface->set_property<bool, true>(property, false)) ++ { ++ try ++ { ++ // msg.get_path() is interface->get_object_path() ++ sdbusplus::message::message msg = ++ interface->new_signal("ThresholdAsserted"); ++ ++ msg.append(sensor->name, interface->get_interface_name(), property, ++ false, sensor->value); ++ msg.signal_send(); ++ } ++ catch (const sdbusplus::exception::exception& e) ++ { ++ std::cerr << "Failed to send thresholdAsserted signal from forced " ++ "de-assert\n"; ++ } ++ } ++} ++ + bool parseThresholdsFromAttr( + std::vector<thresholds::Threshold>& thresholdVector, + const std::string& inputPath, const double& scaleFactor, +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend index 1c8817772..a8a74f3e0 100644 --- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend +++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend @@ -1,3 +1,4 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" -SRC_URI += "file://0001-Only-allow-drive-sensors-on-bus-2-for-ast2500.patch" +SRC_URI += "file://0001-Only-allow-drive-sensors-on-bus-2-for-ast2500.patch \ + file://0002-Fix-missing-threshold-de-assert-event-when-threshold.patch" |