diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0027-ast2600-Add-Mailbox-init-function.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0027-ast2600-Add-Mailbox-init-function.patch | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0027-ast2600-Add-Mailbox-init-function.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0027-ast2600-Add-Mailbox-init-function.patch new file mode 100644 index 000000000..8e3a17107 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0027-ast2600-Add-Mailbox-init-function.patch @@ -0,0 +1,127 @@ +From b41a5d9eb94bcaf40bc960d82f13cf41cb83c34e Mon Sep 17 00:00:00 2001 +From: Kuiying Wang <kuiying.wang@intel.com> +Date: Thu, 25 Feb 2021 14:45:12 +0800 +Subject: [PATCH] ast2600: Add Mailbox init function. + +Add Mailbox init function to make sure mailbox regs are reset +to expected values at reset. + +At power-on reset, 0x0c=0, 0x0d=2, 0x0e=5e, 0x0f=31 +as per the handshake definition with BIOS. + +At all other resets, 0x0c is preserved, 0x0d, 0x0e, 0x0f +are reset the same as power-on reset. + +Because the reset behavior depends on a flag set in the _f phase of +booting, the mailbox_init function must be called from the _r phase. + +AST2600 A0 has 16 mailboxes. +AST2600 A1 has 32 mailboxes. + +Tested: +BMC could boot correctly and all the mailboxes clear +ast# md 0x1e789200 +1e789200: 00000000 00000000 00000000 00000000 ................ +1e789210: 00000000 00000000 00000000 00000000 ................ +1e789220: 00000000 00000002 0000005e 00000031 .........^..1... +1e789230: 00000000 00000000 00000000 00000000 ................ +1e789240: 00000000 00000000 00000000 00000000 ................ + +Signed-off-by: Vernon Mauery <vernon.mauery@intel.com> +Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + board/aspeed/ast2600_intel/intel.c | 56 ++++++++++++++++++++++++++++-- + 1 file changed, 54 insertions(+), 2 deletions(-) + +diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c +index 17f9d6c8fbf6..c8b3cef70dd7 100644 +--- a/board/aspeed/ast2600_intel/intel.c ++++ b/board/aspeed/ast2600_intel/intel.c +@@ -13,6 +13,9 @@ + #define WATCHDOG_RESET_BIT BIT(20) + #define BOOT_FAILURE_LIMIT 3 + ++#define SCU_014 0x014 /* Silicon Revision ID */ ++#define REV_ID_AST2600A0 0x05000303 /* AST2600 A0 */ ++ + static int get_boot_failures(void) + { + return env_get_ulong("bootfailures", 10, 0); +@@ -374,6 +377,55 @@ static void timer_callback(void *cookie) + } + } + ++#define AST_MBX_BASE 0x1e789200 ++#define AST_MBX_COUNT_A0 16 ++#define AST_MBX_COUNT 32 ++#define MAILBOX_INIT_D 0x02 ++#define MAILBOX_INIT_E 0x5e ++#define MAILBOX_INIT_F 0x31 ++static void mailbox_init(void) ++{ ++ int i, mbx_count; ++ ++ if (readl(SCU_BASE + SCU_014) == REV_ID_AST2600A0) ++ mbx_count = AST_MBX_COUNT_A0; ++ else ++ mbx_count = AST_MBX_COUNT; ++ ++ if (gd->reset_reason & SYS_PWR_RESET_FLAG) ++ { ++ /* on AC-reset, clear all except special values to d/e/f */ ++ for (i = 0; i < mbx_count; i++) ++ { ++ long v; ++ if (i == 0x0d) ++ v = MAILBOX_INIT_D; ++ else if (i == 0x0e) ++ v = MAILBOX_INIT_E; ++ else if (i == 0x0f) ++ v = MAILBOX_INIT_F; ++ else ++ v = 0; ++ writel(v, AST_MBX_BASE + 4 * i); ++ } ++ } ++ else ++ { ++ /* on other resets, clear all except c/d/e/f */ ++ for (i = 0; i < mbx_count; i++) ++ { ++ long v; ++ if (i == 0x0d) ++ v = MAILBOX_INIT_D; ++ else if (i == 0x0c || i == 0x0e || i == 0x0f) ++ continue; ++ else ++ v = 0; ++ writel(v, AST_MBX_BASE + 4 * i); ++ } ++ } ++} ++ + int board_early_init_f(void) + { + /* This is called before relocation; beware! */ +@@ -396,6 +448,8 @@ int board_early_init_r(void) + + debug("board_early_init_r\n"); + ++ mailbox_init(); ++ + enable_onboard_tpm(); + + led_default_state(); +@@ -510,8 +564,6 @@ extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler, + void *cookie); + int board_late_init(void) + { +-#define SCU_014 0x014 /* Silicon Revision ID */ +-#define REV_ID_AST2600A0 0x05000303 /* AST2600 A0 */ + #define ONE_MSEC_IN_USEC 1000 + char value[11]; + u32 boot_failures; +-- +2.17.1 + |