diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch | 265 |
1 files changed, 265 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch new file mode 100644 index 000000000..2ec774144 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch @@ -0,0 +1,265 @@ +From 8c9e2fffa9ea72ddc8734ee74b30cc62ba06fd3a Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Mon, 2 Mar 2020 13:54:50 -0800 +Subject: [PATCH] AST2600: Add the latest chip initialization code + +This commit cherry picked the latest chip initialization code from +Aspped SDK v00.05.05 to support AST2600 A1 revision. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/mach-aspeed/ast2600/Makefile | 2 +- + arch/arm/mach-aspeed/ast2600/cache.c | 26 +++++++ + arch/arm/mach-aspeed/ast2600/platform.S | 132 +++++++++++++++++++++++++------- + 3 files changed, 130 insertions(+), 30 deletions(-) + create mode 100644 arch/arm/mach-aspeed/ast2600/cache.c + +diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile +index b074d4b70a14..2889388fab75 100644 +--- a/arch/arm/mach-aspeed/ast2600/Makefile ++++ b/arch/arm/mach-aspeed/ast2600/Makefile +@@ -1,2 +1,2 @@ +-obj-y += platform.o aspeed_scu_info.o ++obj-y += platform.o aspeed_scu_info.o cache.o + obj-$(CONFIG_SPL_BUILD) += spl.o +diff --git a/arch/arm/mach-aspeed/ast2600/cache.c b/arch/arm/mach-aspeed/ast2600/cache.c +new file mode 100644 +index 000000000000..82de0b0fda8a +--- /dev/null ++++ b/arch/arm/mach-aspeed/ast2600/cache.c +@@ -0,0 +1,26 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) ASPEED Technology Inc. ++ * Chia-Wei Wang <chiawei_wang@aspeedtech.com> ++ */ ++ ++#include <common.h> ++#include <asm/system.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++void enable_caches(void) ++{ ++#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) ++ enum dcache_option opt = DCACHE_WRITETHROUGH; ++#else ++ enum dcache_option opt = DCACHE_WRITEBACK; ++#endif ++ /* enable D-cache as well as MMU */ ++ dcache_enable(); ++ ++ /* setup cache attribute for DRAM region */ ++ mmu_set_region_dcache_behaviour(ASPEED_DRAM_BASE, ++ gd->ram_size, ++ opt); ++} +diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S +index de97cccc78b7..f1a1f057c09b 100644 +--- a/arch/arm/mach-aspeed/ast2600/platform.S ++++ b/arch/arm/mach-aspeed/ast2600/platform.S +@@ -26,39 +26,45 @@ + * +----------------------+ AST_SMP_MAILBOX_BASE + */ + +-#define AST_SMP_MAILBOX_BASE 0x1E6E2180 ++#define AST_SMP_MAILBOX_BASE (0x1E6E2180) + #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) + #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) + #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) + #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) + + /* AST2600 HW registers */ +-#define AST_SCU_BASE 0x1E6E2000 +-#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) +-#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) +-#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) +-#define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) +-#define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) +-#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) +-#define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) +-#define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) +- +-#define AST_FMC_BASE 0x1E620000 ++#define AST_SCU_BASE (0x1E6E2000) ++#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) ++#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) ++#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) ++#define AST_SCU_SYSRST_CTRL (AST_SCU_BASE + 0x040) ++#define AST_SCU_SYSRST_CTRL_CLR (AST_SCU_BASE + 0x044) ++#define AST_SCU_DEBUG_CTRL (AST_SCU_BASE + 0x0C8) ++#define AST_SCU_DEBUG_CTRL2 (AST_SCU_BASE + 0x0D8) ++#define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) ++#define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) ++#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) ++#define AST_SCU_HW_STRAP1_CLR (AST_SCU_BASE + 0x504) ++#define AST_SCU_HW_STRAP2 (AST_SCU_BASE + 0x510) ++#define AST_SCU_HW_STRAP2_CLR (AST_SCU_BASE + 0x514) ++#define AST_SCU_CA7_CTRL (AST_SCU_BASE + 0x800) ++#define AST_SCU_CA7_AXI_PREFETCH_START (AST_SCU_BASE + 0x808) ++#define AST_SCU_CA7_AXI_PREFETCH_END (AST_SCU_BASE + 0x80C) ++#define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) ++#define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) ++#define AST_SCU_MMIO_DEC_SET (AST_SCU_BASE + 0xC24) ++ ++#define AST_FMC_BASE (0x1E620000) ++#define AST_FMC_CE0_CTRL (AST_FMC_BASE + 0x010) + #define AST_FMC_WDT1_CTRL_MODE (AST_FMC_BASE + 0x060) + #define AST_FMC_WDT2_CTRL_MODE (AST_FMC_BASE + 0x064) + ++#define AST_GPIO_BASE (0x1E780000) ++#define AST_GPIOYZ_DATA_VALUE (AST_GPIO_BASE + 0x1E0) ++ + /* Revision ID */ + #define REV_ID_AST2600A0 0x05000303 + +-ENTRY(ast_bootmode) +- ldr r1, =AST_SCU_HW_STRAP1 +- ldr r0, [r1] +- tst r0, #0x4 +- moveq r0, #0x0 @; AST_BOOTMODE_SPI +- movne r0, #0x1 @; AST_BOOTMODE_EMMC +- mov pc, lr +-ENDPROC(ast_bootmode) +- + .macro scu_unlock + movw r0, #0xA8A8 + movt r0, #0x1688 @; magic key to unlock SCU +@@ -71,11 +77,19 @@ ENDPROC(ast_bootmode) + + .macro timer_init + #ifdef CONFIG_FPGA_ASPEED +- movw r0, #0x7840 +- movt r0, #0x17D ++ movw r0, #0xF080 ++ movt r0, #0x2FA + #else +- movw r0, #0x2340 +- movt r0, #0x430E ++ ldr r0, =AST_SCU_REV_ID ++ ldr r0, [r0] ++ ++ ldr r1, =REV_ID_AST2600A0 ++ cmp r0, r1 ++ ++ movweq r0, #0x32C0 ++ movteq r0, #0x4013 ++ movwne r0, #0x8C00 ++ movtne r0, #0x4786 + #endif + mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ + .endm +@@ -133,7 +147,7 @@ do_primary_core_setup: + /* unlock system control unit */ + scu_unlock + +- /* tune-up CPU clock for AST2600 A0 */ ++ /* identify AST2600 A0/A1 */ + ldr r0, =AST_SCU_REV_ID + ldr r0, [r0] + +@@ -142,7 +156,7 @@ do_primary_core_setup: + + bne 0f + +- /* setup CPU clocks */ ++ /* tune up CPU clocks (A0 only) */ + ldr r0, =AST_SCU_HW_STRAP1 + ldr r1, [r0] + bic r1, #0x1800 +@@ -150,7 +164,7 @@ do_primary_core_setup: + str r1, [r0] + + ldr r0, =AST_SCU_HPLL_PARAM +- movw r1, #0x4087 ++ movw r1, #0x4080 + movt r1, #0x1000 + str r1, [r0] + +@@ -163,13 +177,54 @@ wait_lock: + tst r1, #0x80000000 + beq wait_lock + ++ /* skip A1 only area */ ++ b 1f ++ + 0: ++ /* enable AXI prefetch (A1 only) */ ++ ldr r0, =AST_SCU_CA7_AXI_PREFETCH_START ++ ldr r1, =ASPEED_DRAM_BASE ++ str r1, [r0] ++ ++ ldr r0, =AST_SCU_CA7_AXI_PREFETCH_END ++ ldr r1, =0xFFFFFFFF ++ str r1, [r0] ++ ++ ldr r0, =AST_SCU_CA7_CTRL ++ ldr r1, [r0] ++ orr r1, #0x8000 ++ str r1, [r0] ++ ++ /* LPC/eSPI mode selection (A1 only) */ ++ ldr r0, =AST_GPIOYZ_DATA_VALUE ++ ldr r0, [r0] ++ tst r0, #0x1000 ++ beq 1f ++ ++ /* switch to LPC mode if GPIOZ[4]=1 */ ++ ldr r0, =AST_SCU_HW_STRAP2 ++ ldr r1, [r0] ++ orr r1, #0x40 ++ str r1, [r0] ++ ++1: ++ /* release display port reset */ ++ ldr r0, =AST_SCU_SYSRST_CTRL_CLR ++ movw r1, #0x0000 ++ movt r1, #0x3000 ++ str r1, [r0] ++ ++ /* MMIO decode setting */ ++ ldr r0, =AST_SCU_MMIO_DEC_SET ++ mov r1, #0x2000 ++ str r1, [r0] ++ + /* enable cache & SRAM parity check */ + mov r0, #0 + ldr r1, =AST_SCU_CA7_PARITY_CLR + str r0, [r1] + +- mov r0, #0x11 ++ mov r0, #0x1 + ldr r1, =AST_SCU_CA7_PARITY_CHK + str r0, [r1] + +@@ -177,8 +232,27 @@ wait_lock: + mov r0, #0 + ldr r1, =AST_FMC_WDT1_CTRL_MODE + str r0, [r1] ++#if 0 + ldr r1, =AST_FMC_WDT2_CTRL_MODE + str r0, [r1] ++#endif ++ /* tune up SPI clock */ ++ movw r0, #0x0641 ++ movt r0, #0x203B ++ ldr r1, =AST_FMC_CE0_CTRL ++ str r0, [r1] ++ ++ /* disable UART-based SoC Debug Interface UART5 and P2A bridge*/ ++ ldr r0, =AST_SCU_DEBUG_CTRL ++ ldr r1, [r0] ++ orr r1, #0x03 ++ str r1, [r0] ++ ++ /* disable UART-based SoC Debug Interface UART1 and LPC2AHB bridge */ ++ ldr r0, =AST_SCU_DEBUG_CTRL2 ++ ldr r1, [r0] ++ orr r1, #0x0A ++ str r1, [r0] + + /* relocate mailbox insn. for cpuN polling SMP go signal */ + adrl r0, mailbox_insn +-- +2.7.4 + |