diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch | 196 |
1 files changed, 123 insertions, 73 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch index e76c61a15..a084c4a8c 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch @@ -1,4 +1,4 @@ -From e02a837d388a45e4fb12c7d44eb0a1dc62140d29 Mon Sep 17 00:00:00 2001 +From 069a20560bf9efbd358503c76f043fcdd3a68a94 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@intel.com> Date: Thu, 24 Oct 2019 14:06:33 -0700 Subject: [PATCH] Add ast2600-intel as a new board @@ -13,7 +13,7 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c | 1 + board/aspeed/ast2600_intel/Kconfig | 13 + board/aspeed/ast2600_intel/Makefile | 4 + - board/aspeed/ast2600_intel/ast-espi.c | 232 ++++++++++++++ + board/aspeed/ast2600_intel/ast-espi.c | 282 +++++++++++++++++ board/aspeed/ast2600_intel/ast-irq.c | 399 +++++++++++++++++++++++++ board/aspeed/ast2600_intel/ast-irq.h | 8 + board/aspeed/ast2600_intel/ast-timer.c | 59 ++++ @@ -22,7 +22,7 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> common/autoboot.c | 10 + common/board_r.c | 8 +- include/configs/evb_ast2600.h | 2 +- - 16 files changed, 1090 insertions(+), 6 deletions(-) + 16 files changed, 1140 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/ast2600-intel.dts create mode 100644 board/aspeed/ast2600_intel/Kconfig create mode 100644 board/aspeed/ast2600_intel/Makefile @@ -322,10 +322,10 @@ index 000000000000..37d2f0064f38 +obj-y += ast-timer.o diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c new file mode 100644 -index 000000000000..2778d7b67d54 +index 000000000000..8dc12d7c9fe8 --- /dev/null +++ b/board/aspeed/ast2600_intel/ast-espi.c -@@ -0,0 +1,232 @@ +@@ -0,0 +1,282 @@ +/* + * Copyright 2018 Intel Corporation + * @@ -338,18 +338,20 @@ index 000000000000..2778d7b67d54 +#include <common.h> +#include <asm/io.h> + -+#define AST_LPC_BASE 0x1e6e9000 -+#define AST_ESPI_BASE 0x1e6ee000 -+#define AST_SCU_BASE 0x1e6e2000 -+#define AST_SCU_HW_STRAP1 0x510 -+#define SCU_HW_STRAP_ESPI_ENABLED 0x40 ++#define AST_LPC_BASE 0x1e6e9000 ++#define AST_ESPI_BASE 0x1e6ee000 ++#define AST_SCU_BASE 0x1e6e2000 ++#define AST_SCU_HW_STRAP1 0x510 ++#define SCU_HW_STRAP_ESPI_ENABLED 0x40 + -+#define DEBUG_ESPI_ENABLED 1 -+#ifdef DEBUG_ESPI_ENABLED -+#define DBG_ESPI debug ++#define USE_HW_HANDSHAKE 1 ++#define DEBUG_ESPI_ENABLED 1 ++#if DEBUG_ESPI_ENABLED ++#define DBG_ESPI printf +#else +#define DBG_ESPI(...) +#endif ++ +/* eSPI controller registers */ +#define ESPI000 0x000 /* Engine Control. */ +#define ESPI004 0x004 /* Engine Status. */ @@ -376,6 +378,7 @@ index 000000000000..2778d7b67d54 +#define ESPI070 0x070 /* DMA Addr of Flash Channel Tx pkt. */ +#define ESPI074 0x074 /* Control of Flash Channel Tx pkt. */ +#define ESPI078 0x078 /* Data port of Flash Channel Tx pkt. */ ++#define ESPI080 0x080 /* Engine Control 2. */ +#define ESPI084 0x084 /* Mapping Src Addr of Peripheral Channel Rx pkt. */ +#define ESPI088 0x088 /* Mapping Tgt Addr of Peripheral Channel Rx pkt. */ +#define ESPI08C 0x08C /* Mapping Addr Mask of Peripheral Channel Rx pkt. */ @@ -416,35 +419,63 @@ index 000000000000..2778d7b67d54 +#define ESPICFG818 0x818 /* Mapping Addr Mask of Peripheral Channel Rx pkt */ + +/* ESPI000 bits */ -+#define AST_ESPI_OOB_CHRDY (1 << 4) -+#define AST_ESPI_FLASH_SW_CHRDY (0x1 << 7) -+#define AST_ESPI_FLASH_SW_READ (0x1 << 10) ++#define AST_ESPI_OOB_CHRDY BIT(4) ++#define AST_ESPI_FLASH_SW_CHRDY BIT(7) ++#define AST_ESPI_FLASH_SW_READ BIT(10) + +/* ESPI00C bits (Interrupt Enable) */ -+#define AST_ESPI_IEN_SYS_EV (1 << 8) -+#define AST_ESPI_IEN_GPIO_EV (1 << 9) ++#define AST_ESPI_IEN_HW_RST BIT(31) ++#define AST_ESPI_IEN_SYS1_EV BIT(22) ++#define AST_ESPI_IEN_SYS_EV BIT(8) ++#define AST_ESPI_IEN_GPIO_EV BIT(9) + +/* ESPI008 bits ISR */ -+#define AST_ESPI_VW_SYS_EVT (1 << 8) -+#define AST_ESPI_VW_SYS_EV1 (1 << 22) ++#define AST_ESPI_VW_SYS_EVT BIT(8) ++#define AST_ESPI_VW_SYS_EV1 BIT(9) ++#define AST_ESPI_HW_RST BIT(31) ++ ++/* ESPI080 bits */ ++#define AST_ESPI_AUTO_ACK_HOST_RST_WARN BIT(2) ++#define AST_ESPI_AUTO_ACK_OOB_RST_WARN BIT(1) ++#define AST_ESPI_AUTO_ACK_SUS_WARN BIT(0) + +/* ESPI098 and ESPI11C bits */ -+#define AST_ESPI_OOB_RST_WARN (1 << 6) -+#define AST_ESPI_HOST_RST_WARN (1 << 8) -+#define AST_ESPI_OOB_RST_ACK (1 << 16) -+#define AST_ESPI_SL_BT_DONE (1 << 20) -+#define AST_ESPI_SL_BT_STATUS (1 << 23) -+#define AST_ESPI_HOST_RST_ACK (1 << 27) ++#define AST_ESPI_OOB_RST_WARN BIT(6) ++#define AST_ESPI_HOST_RST_WARN BIT(8) ++#define AST_ESPI_PLTRSTN BIT(5) ++#define AST_ESPI_OOB_RST_ACK BIT(16) ++#define AST_ESPI_SL_BT_DONE BIT(20) ++#define AST_ESPI_SL_BT_STATUS BIT(23) ++#define AST_ESPI_HOST_RST_ACK BIT(27) + +/* ESPI104 bits */ -+#define AST_ESPI_SUS_WARN (1 << 0) -+#define AST_ESPI_SUS_ACK (1 << 20) ++#define AST_ESPI_SUS_WARN BIT(0) ++#define AST_ESPI_SUS_ACK BIT(20) + +/* LPC chip ID */ -+#define SCR0SIO 0x170 -+#define IRQ_SRC_ESPI 74 /* IRQ 74 */ ++#define SCR0SIO 0x170 ++#define IRQ_SRC_ESPI 74 /* IRQ 74 */ + -+static int espi_irq_handler(struct pt_regs *regs) ++static void espi_handshake_ack(void) ++{ ++ /* IRQ only serviced if strapped, so no strap check */ ++ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { ++ DBG_ESPI("Setting espi slave boot done\n"); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ } ++ ++ uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104); ++ if (sys1_event & AST_ESPI_SUS_WARN && ++ !(sys1_event & AST_ESPI_SUS_ACK)) { ++ DBG_ESPI("Boot SUS_WARN, evt: 0x%08x\n", sys1_event); ++ writel(sys1_event | AST_ESPI_SUS_ACK, AST_ESPI_BASE + ESPI104); ++ DBG_ESPI("SUS_WARN sent ack\n"); ++ } ++} ++ ++int espi_irq_handler(struct pt_regs *regs) +{ + uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008); + @@ -456,22 +487,29 @@ index 000000000000..2778d7b67d54 + + DBG_ESPI("sys_status : 0x%08X\n", sys_status); + if (sys_status & AST_ESPI_HOST_RST_WARN) { -+ DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event); ++ DBG_ESPI("HOST_RST_WARN evt: 0x%08X\n", sys_event); + if (sys_event & AST_ESPI_HOST_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_HOST_RST_ACK; ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_HOST_RST_ACK; + writel(v, AST_ESPI_BASE + ESPI098); ++ DBG_ESPI("HOST_RST_WARN sent ack\n"); + } + } + if (sys_status & AST_ESPI_OOB_RST_WARN) { -+ DBG_ESPI("OOB_RST_WARN ev: %08X\n", sys_event); ++ DBG_ESPI("OOB_RST_WARN evt: 0x%08X\n", sys_event); + if (sys_event & AST_ESPI_OOB_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_OOB_RST_ACK; ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_OOB_RST_ACK; + writel(v, AST_ESPI_BASE + ESPI098); ++ DBG_ESPI("OOB_RST_WARN sent ack\n"); + } + } -+ writel(sys_status, AST_ESPI_BASE + ESPI11C); // clear status ++ if (sys_status & AST_ESPI_PLTRSTN) { ++ DBG_ESPI("PLTRSTN: %c, evt: 0x%08X\n", ++ (sys_event & AST_ESPI_PLTRSTN) ? '1' : '0', ++ sys_event); ++ } ++ writel(sys_status, AST_ESPI_BASE + ESPI11C); /* clear status */ + } + + if (irq_status & AST_ESPI_VW_SYS_EV1) { @@ -480,35 +518,31 @@ index 000000000000..2778d7b67d54 + + DBG_ESPI("sys1_status : 0x%08X\n", sys1_status); + if (sys1_status & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("SUS WARN ev: %08X\n", sys1_event); ++ DBG_ESPI("SUS WARN evt: 0x%08X\n", sys1_event); + if (sys1_event & AST_ESPI_SUS_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) -+ | AST_ESPI_SUS_ACK; ++ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | ++ AST_ESPI_SUS_ACK; + writel(v, AST_ESPI_BASE + ESPI104); ++ DBG_ESPI("SUS_WARN sent ack\n"); + } + } -+ writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status ++ writel(sys1_status, AST_ESPI_BASE + ESPI12C); /* clear status */ + } -+ writel(irq_status, AST_ESPI_BASE + ESPI008); // clear irq_status -+ return 0; -+} + -+static void espi_handshake_ack(void) -+{ -+ // IRQ only serviced if strapped, so no strap check -+ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { -+ DBG_ESPI("Setting espi slave boot done\n"); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } ++ if (irq_status & AST_ESPI_HW_RST) { ++ uint32_t v = readl(AST_ESPI_BASE + ESPI000) & 0x00ffffffff; ++ writel(v, AST_ESPI_BASE + ESPI000); ++ v |= 0xff000000; ++ writel(v, AST_ESPI_BASE + ESPI000); ++ ++ DBG_ESPI("HW_RESET\n"); + -+ if (readl(AST_ESPI_BASE + ESPI104) & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("Boot SUS WARN set %08x\n", -+ readl(AST_ESPI_BASE + ESPI104)); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; -+ writel(v, AST_ESPI_BASE + ESPI104); ++ espi_handshake_ack(); + } ++ ++ writel(irq_status, AST_ESPI_BASE + ESPI008); /* clear irq_status */ ++ ++ return 0; +} + +void espi_init(void) @@ -517,43 +551,59 @@ index 000000000000..2778d7b67d54 + & SCU_HW_STRAP_ESPI_ENABLED) { + uint32_t v; + ++ DBG_ESPI("espi init\n"); ++ ++ writel(0xff000000, AST_SCU_BASE + 0x454); /* driving strength */ ++ + /* Block flash access from Host */ + v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_FLASH_SW_CHRDY; + v |= AST_ESPI_FLASH_SW_READ | AST_ESPI_OOB_CHRDY; + writel(v, AST_ESPI_BASE + ESPI000); + -+ /* Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for -+ * BIOS using in eSPI mode */ ++ /* ++ * Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for ++ * BIOS using in eSPI mode. ++ */ + v = readl(AST_LPC_BASE + SCR0SIO) & ~0x000000ff; + writel(v, AST_LPC_BASE + SCR0SIO); + v = readl(AST_LPC_BASE + SCR0SIO) | 0xa8; + writel(v, AST_LPC_BASE + SCR0SIO); + -+ v = readl(AST_ESPI_BASE + ESPI000) | AST_ESPI_OOB_CHRDY; -+ writel(v, AST_ESPI_BASE + ESPI000); ++#if USE_HW_HANDSHAKE ++ v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ ++ return; ++#endif ++ ++ v = readl(AST_ESPI_BASE + ESPI080); ++ v &= ~(AST_ESPI_AUTO_ACK_HOST_RST_WARN | ++ AST_ESPI_AUTO_ACK_OOB_RST_WARN | ++ AST_ESPI_AUTO_ACK_SUS_WARN); ++ writel(v, AST_ESPI_BASE + ESPI080); /* Disable auto H/W ack */ + + writel(0, AST_ESPI_BASE + ESPI110); + writel(0, AST_ESPI_BASE + ESPI114); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN, -+ AST_ESPI_BASE + ESPI118); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN, -+ AST_ESPI_BASE + ESPI094); ++ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN | ++ AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI118); ++ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN | ++ AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI094); + + writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE + ESPI120); // int type 0 susp warn ++ AST_ESPI_BASE + ESPI120); /* int type 0 susp warn */ + writel(0, AST_ESPI_BASE + ESPI124); + writel(0, AST_ESPI_BASE + ESPI128); + writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE -+ + ESPI100); // Enable sysev1 ints for susp warn ++ AST_ESPI_BASE + ++ ESPI100); /* Enable sysev1 ints for susp warn */ + -+ writel(AST_ESPI_IEN_SYS_EV, -+ AST_ESPI_BASE + ESPI00C); // Enable only sys events ++ writel(AST_ESPI_IEN_HW_RST | AST_ESPI_IEN_SYS1_EV | ++ AST_ESPI_IEN_SYS_EV, AST_ESPI_BASE + ESPI00C); + + espi_handshake_ack(); + + irq_install_handler(IRQ_SRC_ESPI, espi_irq_handler, NULL); -+ + } else { + DBG_ESPI("No espi strap\n"); + } |