diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch | 63 |
1 files changed, 37 insertions, 26 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch index 10a45fa23..4714dd6cc 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch @@ -1,19 +1,19 @@ -From 34ccbd14d8f5caa66523a762e2030b6f105206cb Mon Sep 17 00:00:00 2001 +From 039b9a278a4d075e455a38ec93171dc812aec8b2 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Fri, 16 Nov 2018 15:57:57 -0800 -Subject: [PATCH] aspeed: add Pwm Driver +Subject: [PATCH 1/1] aspeed: add Pwm Driver Change-Id: Ia8b80212f7c70aafcc6a71782936ec95cf9b7f38 - +Signed-off-by: James Feist <james.feist@linux.intel.com> --- - board/aspeed/ast-g5/ast-g5-intel.c | 105 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 105 insertions(+) + board/aspeed/ast-g5/ast-g5-intel.c | 113 +++++++++++++++++++++++++++++ + 1 file changed, 113 insertions(+) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e53f5eb..c7ae566 100644 +index e74999223b..74e218dfd0 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -255,9 +255,114 @@ int intel_force_firmware_jumper_enabled(void) +@@ -257,9 +257,122 @@ int intel_force_firmware_jumper_enabled(void) return gpio_get_value(GPIO_FF_UPD_JUMPER); } @@ -35,7 +35,7 @@ index e53f5eb..c7ae566 100644 + +#define PWM_CLK_ENABLE BIT(0) +#define PWM_DUTY(PCT) (((PCT) * 128) / 100) -+#define PWM_DUTY_VALUE PWM_DUTY(57) ++#define DEFAULT_PWM_DUTY_VALUE PWM_DUTY(57) + + +static inline uint32_t ast_scu_read(uint32_t reg) @@ -57,10 +57,34 @@ index e53f5eb..c7ae566 100644 +#endif +} + ++static void set_pwm_duty_cycle(int duty) ++{ ++ uint32_t chan; ++ uint32_t val; ++ ++ /* enable pwm channels */ ++ for (chan = 0; chan < PWM_CHANNEL_COUNT; chan++) { ++ uint32_t base = chan < 4 ? PWM_BASE_ADDR : PWM_BASE_ADDR + 0x40; ++ uint8_t ch_duty_shift = 16 * (chan & 0x1); ++ uint8_t ch_pair = (chan & 0x3) / 2; ++ ++ /* enable pwm for the channel */ ++ val = readl(base); ++ val |= ((1 << (chan & 0x3)) << 8); ++ writel(val, base); ++ ++ /* set duty cycle */ ++ val = readl(base + PWM_DUTY_CYCLE + ch_pair * 4); ++ val &= ~(0xffff << ch_duty_shift); ++ val |= (((uint32_t)duty) << 8) << ch_duty_shift; ++ writel(val, base + PWM_DUTY_CYCLE + ch_pair * 4); ++ } ++ ++} ++ +static void pwm_init(void) +{ + uint32_t val; -+ uint32_t chan; + + /* select pwm 0-7 */ + val = ast_scu_read(AST_SCU_FUN_PIN_CTRL3); @@ -93,23 +117,7 @@ index e53f5eb..c7ae566 100644 + writel(0x1, PWM_BASE_ADDR + PWM_CONTROL); + writel(0x1, PWM_BASE_ADDR + PWM_CONTROL_EXT); + -+ /* enable pwm channels */ -+ for (chan = 0; chan < PWM_CHANNEL_COUNT; chan++) { -+ uint32_t base = chan < 4 ? PWM_BASE_ADDR : PWM_BASE_ADDR + 0x40; -+ uint8_t ch_duty_shift = 16 * (chan & 0x1); -+ uint8_t ch_pair = (chan & 0x3) / 2; -+ -+ /* enable pwm for the channel */ -+ val = readl(base); -+ val |= ((1 << (chan & 0x3)) << 8); -+ writel(val, base); -+ -+ /* set duty cycle */ -+ val = readl(base + PWM_DUTY_CYCLE + ch_pair * 4); -+ val &= ~(0xffff << ch_duty_shift); -+ val |= (((uint32_t)PWM_DUTY_VALUE) << 8) << ch_duty_shift; -+ writel(val, base + PWM_DUTY_CYCLE + ch_pair * 4); -+ } ++ set_pwm_duty_cycle(DEFAULT_PWM_DUTY_VALUE); + + /* set up clock type M: period = 127 units at 24MHz/8 (resulting ~23kHz period) */ + writel(0x7f30, PWM_BASE_ADDR + PWM_CLOCK_SELECTION); @@ -128,3 +136,6 @@ index e53f5eb..c7ae566 100644 gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); espi_init(); sgpio_init(); +-- +2.17.1 + |