diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch deleted file mode 100644 index 915b0197f..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch +++ /dev/null @@ -1,71 +0,0 @@ -From c2e2496dfd8cde56e32274b11968185a77f40736 Mon Sep 17 00:00:00 2001 -From: Kuiying Wang <kuiying.wang@intel.com> -Date: Tue, 10 Dec 2019 14:58:10 +0800 -Subject: [PATCH] AST2600: Enable host searial port clock configuration in - u-boot - -In u-boot could read env variable "hostsearialcfg" and set the corresponding -clock for host searail port. - -Tested: -setenv hostsearialcfg 1, speed is set to 192Mhz (baud rate 921600) -other value, speed is set to 24Mhz(baud rate 115200) -by default is 24Mhz. - -Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> ---- - board/aspeed/ast2600_intel/intel.c | 35 +++++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index a02e246d0d81..eb9b3959625e 100644 ---- a/board/aspeed/ast2600_intel/intel.c -+++ b/board/aspeed/ast2600_intel/intel.c -@@ -36,9 +36,44 @@ int gpio_abort(void) - } - - #define SCU_BASE 0x1E6E2000 -+#define SCU_338 0x338 //Generate UART 24 MHz Reference from UXCLK -+#define SCU_33C 0x33c //Generate UART 24 MHz Reference from HUXCLK -+#define SCU_338_R_VALUE_192MHZ 0x8e -+#define SCU_338_N_VALUE_192MHZ 0x3c3 -+#define SCU_338_R_VALUE_24MHZ 0x06 -+#define SCU_338_N_VALUE_24MHZ 0x145 -+#define HOST_SERIAL_HIGH_SPEED_192MHZ 1 -+#define R_VALUE_BITS 8 -+#define V_VALUE_BITS 10 -+#define R_V_VALUE_MASK (1 << (R_VALUE_BITS + V_VALUE_BITS)) -+ - int misc_init_r(void) - { - /* This is called near the end of the _r init sequence */ -+ /* By default host serail is set 24Mhz */ -+ uint32_t host_serial_cfg = 0; -+ char *host_serial_cfg_txt = NULL; -+ -+ /* Config the uart clock source based on environment configuration */ -+ host_serial_cfg_txt = env_get("hostserialcfg"); -+ -+ if (host_serial_cfg_txt != NULL) -+ host_serial_cfg = simple_strtoul(host_serial_cfg_txt, NULL, 16); -+ -+ if (host_serial_cfg > HOST_SERIAL_HIGH_SPEED_192MHZ || host_serial_cfg < 0) { -+ printf("Invalid hostserialcfg %x, 24Mhz is set by default!\n", host_serial_cfg); -+ host_serial_cfg = 0; -+ } -+ -+ if (host_serial_cfg & HOST_SERIAL_HIGH_SPEED_192MHZ) { -+ writel((readl(SCU_BASE | SCU_338) & R_V_VALUE_MASK) | -+ (SCU_338_N_VALUE_192MHZ << R_VALUE_BITS) | SCU_338_R_VALUE_192MHZ, -+ SCU_BASE | SCU_338); -+ } else { -+ writel((readl(SCU_BASE | SCU_338) & R_V_VALUE_MASK) | -+ (SCU_338_N_VALUE_24MHZ << R_VALUE_BITS) | SCU_338_R_VALUE_24MHZ, -+ SCU_BASE | SCU_338); -+ } - - return 0; - } --- -2.7.4 - |