diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch')
-rw-r--r-- | meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch new file mode 100644 index 000000000..b76a3dba0 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-Adding-PFR-boot-flow-checkpoint-in-u-boot.patch @@ -0,0 +1,102 @@ +From dda24946edd0a4ec54e3ecaa8bd493cce9bdfa15 Mon Sep 17 00:00:00 2001 +From: AppaRao Puli <apparao.puli@linux.intel.com> +Date: Mon, 22 Jul 2019 08:26:15 +0530 +Subject: [PATCH] Adding PFR boot flow checkpoint in u-boot + +Added two PFR boot flow check points in u-boot +1) Set the booting starts checkpoint(0x01) +2) Set FFUJ checkpoint(0x07) when jumper on. + +Tested: +Loaded the image, dumped all cpld registers and +cross verified the check-points properly set or not. + +Change-Id: I3c725b0e15c1fea5bdb7b085826bdabad19bda80 +Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> +--- + board/aspeed/ast-g5/ast-g5-intel.c | 46 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index e68ab85..9f0a64d 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -12,11 +12,21 @@ + #include <asm/arch/regs-scu.h> + #include <asm/arch/ast_scu.h> + #include <asm/arch/aspeed.h> ++#include <i2c.h> + + #include "ast-g5.h" + #include "ast-g5-gpio.h" + #include "ast-g5-timer.h" + ++/* PFR Specific defines */ ++#define PFR_CPLD_I2C_BUSNO 4 ++#define PFR_CPLD_SLAVE_ADDR 0xE0 ++#define PFR_CPLD_BOOT_CHECKPOINT_REG 0x13 ++ ++#define PFR_CPLD_CHKPOINT_START 0x01 ++#define PFR_CPLD_CHKPOINT_FFUJ 0x07 ++#define PFR_CPLD_CHKPOINT_FINISHED 0x09 ++ + /* Names to match the GPIOs */ + enum gpio_names { + GPIO_ID_LED = 0, +@@ -537,10 +547,42 @@ static void pwm_init(void) + writel(val, PWM_BASE_ADDR + PWM_CONTROL); + } + ++static void set_boot_checkpoint(u8 chk_point) ++{ ++ int ret = 0; ++ int chip = (PFR_CPLD_SLAVE_ADDR >> 1); ++ u32 reg_addr = PFR_CPLD_BOOT_CHECKPOINT_REG; ++ ++ /* Get current I2C bus number to restore later. */ ++ int current_bus_no = i2c_get_bus_num(); ++ ++ /* Set I2C bus number to PFR CPLD I2C bus. */ ++ ret = i2c_set_bus_num(PFR_CPLD_I2C_BUSNO); ++ if (ret) { ++ printf("Failed to change I2C bus number (%d)\n", ret); ++ goto done; ++ } ++ ++ ret = i2c_write(chip, reg_addr, 1, &chk_point, 1); ++ if (ret) { ++ printf("Error writing the chip: %d\n", ret); ++ goto done; ++ } ++ ++done: ++ /* Restore I2C bus number */ ++ if (i2c_set_bus_num(current_bus_no)) ++ printf("Failed to restore I2C bus number.\n"); ++} ++ + extern void espi_init(void); + extern void kcs_init(void); + void ast_g5_intel(void) + { ++ /* To notify the CPLD about the start of bootloader ++ * and hardware initialization */ ++ set_boot_checkpoint(PFR_CPLD_CHKPOINT_START); ++ + uart_init(); + pwm_init(); + gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); +@@ -551,6 +593,10 @@ void ast_g5_intel(void) + if (intel_force_firmware_jumper_enabled()) { + id_led_control(GPIO_AMBER_LED, EIDLED_On); + kcs_init(); ++ /* Notify CPLD about FFUJ jumper set and pause ++ * of booting for indefinitely time. It will be ++ * resumed once reset is done. */ ++ set_boot_checkpoint(PFR_CPLD_CHKPOINT_FFUJ); + /* TODO: need to stop the booting here. */ + } else { + id_led_control(GPIO_GREEN_LED, EIDLED_On); +-- +2.7.4 + |