diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files')
7 files changed, 352 insertions, 49 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch index 16eb31250..e376001b3 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch @@ -1,4 +1,4 @@ -From bc6ea87d8213ecdc5ab7cced8b2fc4284fdef019 Mon Sep 17 00:00:00 2001 +From 2db86017f1cd48da9f6c102665d5ae3d1efe48cc Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 12:16:53 -0800 Subject: [PATCH] Add status and ID LED support @@ -8,17 +8,18 @@ bootloader phase, the LEDs should be blinking. When booting linux, they should turn to a fixed state. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> +Signed-off-by: James Feist <james.feist@linux.intel.com> +Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> Change-Id: Ic9595621b21000ef465ff57ed2047855296e2714 - --- - board/aspeed/ast-g5/ast-g5-intel.c | 110 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 110 insertions(+) + board/aspeed/ast-g5/ast-g5-intel.c | 113 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 113 insertions(+) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 6e45cb4..e53f5eb 100644 +index 6e45cb4..e749992 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -146,6 +146,110 @@ static void sgpio_init(void) +@@ -146,6 +146,112 @@ static void sgpio_init(void) writel(value, AST_GPIO_BASE + GPIO254); } @@ -51,8 +52,10 @@ index 6e45cb4..e53f5eb 100644 +}; + +static struct led_info s_led_info[] = { ++ /* BMC Executing bootloader (Default) :- ++ * ChassisID: Blinking Blue 3Hz, StatusLED: Blinking Green 1Hz */ + [GPIO_ID_LED] = {GPIO_ID_LED, EIDLED_Blink_3HZ, 1, 0}, -+ [GPIO_GREEN_LED] = {GPIO_GREEN_LED, EIDLED_Off, 0, 0}, ++ [GPIO_GREEN_LED] = {GPIO_GREEN_LED, EIDLED_Blink_1HZ, 0, 0}, + [GPIO_AMBER_LED] = {GPIO_AMBER_LED, EIDLED_Off, 0, 0}, +}; + @@ -129,14 +132,18 @@ index 6e45cb4..e53f5eb 100644 int intel_force_firmware_jumper_enabled(void) { return gpio_get_value(GPIO_FF_UPD_JUMPER); -@@ -157,4 +261,10 @@ void ast_g5_intel(void) +@@ -157,4 +263,11 @@ void ast_g5_intel(void) gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); espi_init(); sgpio_init(); + timer8_init(); + if (intel_force_firmware_jumper_enabled()) { ++ /* FFUJ mode:- ChassisID: Solid Blue, StatusLED: Solid Amber */ ++ id_led_control(GPIO_ID_LED, EIDLED_On); ++ id_led_control(GPIO_GREEN_LED, EIDLED_Off); + id_led_control(GPIO_AMBER_LED, EIDLED_On); -+ } else { -+ id_led_control(GPIO_GREEN_LED, EIDLED_On); + } } +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch index 63eebe56b..2b6382967 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch @@ -1,7 +1,7 @@ -From 1264c57a485a238b715c489b7ca14982af396442 Mon Sep 17 00:00:00 2001 +From 6d8db23becf9665193023e350adcad00b75195b0 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Wed, 13 Mar 2019 14:28:05 +0530 -Subject: [PATCH] KCS driver support in uBoot +Subject: [PATCH 1/1] KCS driver support in uBoot Added KCS support in uBoot. This will enable KCS channels and set the specified registers @@ -25,18 +25,18 @@ via KCS interfaces using cmdtool.efi. Res: C1 (Invalid). Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> - +Signed-off-by: James Feist <james.feist@linux.intel.com> --- board/aspeed/ast-g5/Makefile | 1 + board/aspeed/ast-g5/ast-g5-intel.c | 3 + - board/aspeed/ast-g5/ast-g5-kcs.c | 420 +++++++++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-kcs.h | 112 ++++++++++ + board/aspeed/ast-g5/ast-g5-kcs.c | 420 +++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-kcs.h | 112 ++++++++ 4 files changed, 536 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-kcs.c create mode 100644 board/aspeed/ast-g5/ast-g5-kcs.h diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 9022433..05972b9 100644 +index 90224333c4..05972b9d17 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -4,3 +4,4 @@ obj-y += ast-g5-espi.o @@ -45,29 +45,28 @@ index 9022433..05972b9 100644 obj-y += ast-g5-timer.o +obj-y += ast-g5-kcs.o diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e19df03..adc6d10 100644 +index 032f716722..c149426947 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -480,6 +480,7 @@ static void pwm_init(void) +@@ -256,6 +256,7 @@ int intel_force_firmware_jumper_enabled(void) } extern void espi_init(void); +extern void kcs_init(void); void ast_g5_intel(void) { - pwm_init(); -@@ -489,6 +490,8 @@ void ast_g5_intel(void) + gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); +@@ -264,5 +265,7 @@ void ast_g5_intel(void) timer8_init(); if (intel_force_firmware_jumper_enabled()) { id_led_control(GPIO_AMBER_LED, EIDLED_On); + kcs_init(); + /* TODO: need to stop the booting here. */ - } else { - id_led_control(GPIO_GREEN_LED, EIDLED_On); } + } diff --git a/board/aspeed/ast-g5/ast-g5-kcs.c b/board/aspeed/ast-g5/ast-g5-kcs.c new file mode 100644 -index 0000000..7bff26f +index 0000000000..7bff26f9db --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-kcs.c @@ -0,0 +1,420 @@ @@ -493,7 +492,7 @@ index 0000000..7bff26f +} diff --git a/board/aspeed/ast-g5/ast-g5-kcs.h b/board/aspeed/ast-g5/ast-g5-kcs.h new file mode 100644 -index 0000000..bb697c4 +index 0000000000..bb697c455d --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-kcs.h @@ -0,0 +1,112 @@ @@ -609,3 +608,6 @@ index 0000000..bb697c4 + u16 data_out_idx; + u8 data_out[MAX_KCS_PKT_SIZE]; +}; +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch index 7700e067f..b41403fe3 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch @@ -1,7 +1,7 @@ -From 0c975e64ca8bd5fdaf12f15b4dbc9ceaa942c36c Mon Sep 17 00:00:00 2001 +From 2c5ae4ff71edda4d2d9cc0d289f61635409c3be4 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Wed, 24 Jul 2019 20:11:30 +0530 -Subject: [PATCH] PFR FW update and checkpoint support in u-boot +Subject: [PATCH 2/2] PFR FW update and checkpoint support in u-boot 1) Added firmware update ipmi commands support for PFR images. This enables PFR based firmware @@ -21,21 +21,22 @@ BMC image update via KCS ( In FFUJ mode). cross verified the check-points properly set or not. Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> +Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> --- board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 10 ++++ - board/aspeed/ast-g5/fw-update.c | 112 +++++++++++++++++++------------------ - board/aspeed/ast-g5/fw-update.h | 7 +++ - board/aspeed/ast-g5/ipmi-fwupd.c | 37 ++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 10 +++ + board/aspeed/ast-g5/fw-update.c | 112 +++++++++++++++-------------- + board/aspeed/ast-g5/fw-update.h | 7 ++ + board/aspeed/ast-g5/ipmi-fwupd.c | 37 ++++++++++ board/aspeed/ast-g5/ipmi-fwupd.h | 6 -- - board/aspeed/ast-g5/pfr-mgr.c | 73 ++++++++++++++++++++++++ - board/aspeed/ast-g5/pfr-mgr.h | 73 ++++++++++++++++++++++++ + board/aspeed/ast-g5/pfr-mgr.c | 73 +++++++++++++++++++ + board/aspeed/ast-g5/pfr-mgr.h | 73 +++++++++++++++++++ 8 files changed, 258 insertions(+), 61 deletions(-) create mode 100644 board/aspeed/ast-g5/pfr-mgr.c create mode 100644 board/aspeed/ast-g5/pfr-mgr.h diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 0b2d936..9021d7f 100644 +index 0b2d936c23..9021d7fc08 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -8,3 +8,4 @@ obj-y += ast-g5-kcs.o @@ -44,7 +45,7 @@ index 0b2d936..9021d7f 100644 obj-y += fw-update.o +obj-y += pfr-mgr.o diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e68ab85..cd359ce 100644 +index c58fd3591b..13889594bf 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -16,6 +16,7 @@ @@ -55,10 +56,10 @@ index e68ab85..cd359ce 100644 /* Names to match the GPIOs */ enum gpio_names { -@@ -541,6 +542,10 @@ extern void espi_init(void); - extern void kcs_init(void); - void ast_g5_intel(void) - { +@@ -582,6 +583,10 @@ void ast_g5_intel(void) + ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | + SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); + + /* To notify the CPLD about the start of bootloader + * and hardware initialization */ + set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, PFR_CPLD_CHKPOINT_START); @@ -66,8 +67,8 @@ index e68ab85..cd359ce 100644 uart_init(); pwm_init(); gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); -@@ -551,6 +556,11 @@ void ast_g5_intel(void) - if (intel_force_firmware_jumper_enabled()) { +@@ -595,6 +600,11 @@ void ast_g5_intel(void) + id_led_control(GPIO_GREEN_LED, EIDLED_Off); id_led_control(GPIO_AMBER_LED, EIDLED_On); kcs_init(); + /* Notify CPLD about FFUJ jumper set and pause @@ -76,10 +77,10 @@ index e68ab85..cd359ce 100644 + set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, + PFR_CPLD_CHKPOINT_FFUJ); /* TODO: need to stop the booting here. */ - } else { - id_led_control(GPIO_GREEN_LED, EIDLED_On); + } + } diff --git a/board/aspeed/ast-g5/fw-update.c b/board/aspeed/ast-g5/fw-update.c -index 9923993..89fe5fd 100644 +index 99239938b5..89fe5fd4fd 100644 --- a/board/aspeed/ast-g5/fw-update.c +++ b/board/aspeed/ast-g5/fw-update.c @@ -6,6 +6,7 @@ @@ -269,7 +270,7 @@ index 9923993..89fe5fd 100644 mdelay(WAIT_STATE_TIMEOUT); } diff --git a/board/aspeed/ast-g5/fw-update.h b/board/aspeed/ast-g5/fw-update.h -index ed033ad..45e46ba 100644 +index ed033adfed..45e46ba596 100644 --- a/board/aspeed/ast-g5/fw-update.h +++ b/board/aspeed/ast-g5/fw-update.h @@ -28,6 +28,12 @@ enum update_status { @@ -291,7 +292,7 @@ index ed033ad..45e46ba 100644 int generate_random_number(void); + diff --git a/board/aspeed/ast-g5/ipmi-fwupd.c b/board/aspeed/ast-g5/ipmi-fwupd.c -index 3eba056..6afc8d6 100644 +index 3eba056e7f..6afc8d66b7 100644 --- a/board/aspeed/ast-g5/ipmi-fwupd.c +++ b/board/aspeed/ast-g5/ipmi-fwupd.c @@ -2,10 +2,14 @@ @@ -350,7 +351,7 @@ index 3eba056..6afc8d6 100644 result->no_of_bytes_written = (u8)req_len; diff --git a/board/aspeed/ast-g5/ipmi-fwupd.h b/board/aspeed/ast-g5/ipmi-fwupd.h -index e490f6b..7409d2e 100644 +index e490f6b527..7409d2e2f9 100644 --- a/board/aspeed/ast-g5/ipmi-fwupd.h +++ b/board/aspeed/ast-g5/ipmi-fwupd.h @@ -19,12 +19,6 @@ enum control_state_bit { @@ -368,7 +369,7 @@ index e490f6b..7409d2e 100644 u8 completion_code; diff --git a/board/aspeed/ast-g5/pfr-mgr.c b/board/aspeed/ast-g5/pfr-mgr.c new file mode 100644 -index 0000000..7713168 +index 0000000000..77131688e7 --- /dev/null +++ b/board/aspeed/ast-g5/pfr-mgr.c @@ -0,0 +1,73 @@ @@ -447,7 +448,7 @@ index 0000000..7713168 + diff --git a/board/aspeed/ast-g5/pfr-mgr.h b/board/aspeed/ast-g5/pfr-mgr.h new file mode 100644 -index 0000000..6cf8c6d +index 0000000000..6cf8c6d5b9 --- /dev/null +++ b/board/aspeed/ast-g5/pfr-mgr.h @@ -0,0 +1,73 @@ @@ -525,5 +526,5 @@ index 0000000..6cf8c6d +ulong get_flash_region_offset(u32 type); +ulong get_image_max_size(u32 type); -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0034-Disable-uart-debug-interface.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0034-Disable-uart-debug-interface.patch new file mode 100644 index 000000000..941dc7d0d --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0034-Disable-uart-debug-interface.patch @@ -0,0 +1,54 @@ +From 961561c437c8a3f3de1753c502a20c334966354e Mon Sep 17 00:00:00 2001 +From: Yong Li <yong.b.li@linux.intel.com> +Date: Tue, 20 Aug 2019 16:10:03 +0800 +Subject: [PATCH 1/2] Disable uart debug interface + +AST2500 SOC integrates a UART debug interface which can +input commands to AST2500 by using simple terminal +program without the assistance of CPU. + +For security requirements, we need to disable this feature, +set SCU2C[]10 = 1 to disable it. + +Tested: +Flash the u-boot.bin and dump SCU2C as below: +md 0x1e6e202c +1e6e202c: 00200400 + +Signed-off-by: Yong Li <yong.b.li@linux.intel.com> +Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> +--- + arch/arm/include/asm/arch-aspeed/regs-scu.h | 1 + + board/aspeed/ast-g5/ast-g5-intel.c | 4 ++++ + 2 files changed, 5 insertions(+) + +diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h +index 8a596ceafc..8333ba1c59 100644 +--- a/arch/arm/include/asm/arch-aspeed/regs-scu.h ++++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h +@@ -467,6 +467,7 @@ + #define SCU_MISC_VUART_TO_CTRL (0x1 << 13) + #define SCU_MISC_DIV13_EN (0x1 << 12) + #define SCU_MISC_Y_CLK_INVERT (0x1 << 11) ++#define SCU_MISC_UART_DEBUG_DIS (0x1 << 10) + #define SCU_MISC_OUT_DELAY (0x1 << 9) + #define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8) + #define SCU_MISC_2D_CRT_EN (0x1 << 7) +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index 324387a4bc..c58fd3591b 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -578,6 +578,10 @@ extern void espi_init(void); + extern void kcs_init(void); + void ast_g5_intel(void) + { ++ /* Disable uart port debug function */ ++ ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | ++ SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); ++ + uart_init(); + pwm_init(); + gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch new file mode 100644 index 000000000..193101370 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch @@ -0,0 +1,124 @@ +From c15d982a36e34f3d3cc69efff7b56a5157be9a5c Mon Sep 17 00:00:00 2001 +From: Vikram Bodireddy <vikram.bodireddy@intel.com> +Date: Thu, 5 Sep 2019 15:03:21 +0530 +Subject: [PATCH] PFR platform - EXTRST# reset mask selection + +This is a fix taken from Purely PFR. +This commit will enable specific reset mask for EXTRST# signal. +On PFR platforms, EXTRST# signal is used by PFR CPLD to put BMC +in reset during firmware authentications, recovery and firmware +update flow, during which certain modules of BMC should be chosen +to be reset so that Host functionality would be intact. + +Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> + + .../include/asm/arch-aspeed/ast-g5-intel.h | 31 +++++++++++++++++++ + arch/arm/include/asm/arch-aspeed/regs-scu.h | 29 +++++++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 9 ++++++ + 3 files changed, 69 insertions(+) + +diff --git a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h +index 64f4ed17bf..b9386b2cf6 100644 +--- a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h ++++ b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h +@@ -12,6 +12,37 @@ + + #define AST_G5_INTEL 1 + ++/* EXTRST# mask for PFR platform ++ * EXTRST# is used by PFR CPLD to keep BMC in ++ * reset during firmware authentication, updates and recovery ++ * this mask selects the modules to be reset along with BMC so that ++ * Host functions are intact. ++ * (this is fix from Purley PFR ) ++ */ ++#define AST_WDT_RESET_MASK ( \ ++ WDT_RESET_MASK_SPI | \ ++ WDT_RESET_MASK_XDMA | \ ++ WDT_RESET_MASK_MCTP | \ ++ WDT_RESET_MASK_ADC | \ ++ WDT_RESET_MASK_JTAG | \ ++ WDT_RESET_MASK_PECI | \ ++ WDT_RESET_MASK_CRT | \ ++ WDT_RESET_MASK_MIC | \ ++ WDT_RESET_MASK_SDIO | \ ++ WDT_RESET_MASK_HAC | \ ++ WDT_RESET_MASK_VIDEO | \ ++ WDT_RESET_MASK_HID11 | \ ++ WDT_RESET_MASK_USB11 | \ ++ WDT_RESET_MASK_USB20 | \ ++ WDT_RESET_MASK_GRAPHICS | \ ++ WDT_RESET_MASK_MAC2 | \ ++ WDT_RESET_MASK_MAC1 | \ ++ WDT_RESET_MASK_I2C | \ ++ WDT_RESET_MASK_AHB | \ ++ WDT_RESET_MASK_COPROC | \ ++ WDT_RESET_MASK_ARM | \ ++ 0) ++ + #ifndef __ASSEMBLY__ + int intel_force_firmware_jumper_enabled(void); + int intel_failed_boot(void); +diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h +index 8333ba1c59..98895a47bf 100644 +--- a/arch/arm/include/asm/arch-aspeed/regs-scu.h ++++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h +@@ -144,6 +144,35 @@ + #define SCU_RESET_AHB (0x1 << 1) + #define SCU_RESET_SRAM_CTRL (0x1 << 0) + ++/* AST_WDT/EXTRST - 0x9C selection masks */ ++#define WDT_RESET_MASK_MISC (1 << 25) /* Misc. SOC controller (WDT, RTC, Timer, UART, SRAM.) */ ++#define WDT_RESET_MASK_SPI (1 << 24) /* SPI controller */ ++#define WDT_RESET_MASK_XDMA (1 << 23) /* X-DMA controller */ ++#define WDT_RESET_MASK_MCTP (1 << 22) /* MCTP controller */ ++#define WDT_RESET_MASK_GPIO (1 << 21) /* GPIO controller */ ++#define WDT_RESET_MASK_ADC (1 << 20) /* ADC controller */ ++#define WDT_RESET_MASK_JTAG (1 << 19) /* JTAG master controller */ ++#define WDT_RESET_MASK_PECI (1 << 18) /* PECI controller */ ++#define WDT_RESET_MASK_PWM (1 << 17) /* PWM controller */ ++#define WDT_RESET_MASK_CRT (1 << 16) /* CRT mode 2D engine */ ++#define WDT_RESET_MASK_MIC (1 << 15) /* MIC controller */ ++#define WDT_RESET_MASK_SDIO (1 << 14) /* SD/SDIO controller */ ++#define WDT_RESET_MASK_LPC (1 << 13) /* LPC controller */ ++#define WDT_RESET_MASK_HAC (1 << 12) /* HAC engine */ ++#define WDT_RESET_MASK_VIDEO (1 << 11) /* Video engine */ ++#define WDT_RESET_MASK_HID11 (1 << 10) /* USB1.1 HID/USB2.0 Host EHCI2 controller */ ++#define WDT_RESET_MASK_USB11 (1 << 9) /* USB1.1 Host controller */ ++#define WDT_RESET_MASK_USB20 (1 << 8) /* USB2.0 Host/Hub controller */ ++#define WDT_RESET_MASK_GRAPHICS (1 << 7) /* Graphics CRT controller */ ++#define WDT_RESET_MASK_MAC2 (1 << 6) /* MAC#2 controller */ ++#define WDT_RESET_MASK_MAC1 (1 << 5) /* MAC#1 controller */ ++#define WDT_RESET_MASK_I2C (1 << 4) /* I2C controller */ ++#define WDT_RESET_MASK_AHB (1 << 3) /* AHB bridges */ ++#define WDT_RESET_MASK_SDRAM (1 << 2) /* SDRAM controller */ ++#define WDT_RESET_MASK_COPROC (1 << 1) /* Coprocessor */ ++#define WDT_RESET_MASK_ARM (1 << 0) /* ARM */ ++#define WDT_RESET_MASK_ALL 0x03ffffff /* all the bits above: 0-25*/ ++ + /* AST_SCU_RESET2 0xD4 - Reset Control register set 2 */ + #define SCU_RESET_CRT3 (0x1 << 8) + #define SCU_RESET_CRT2 (0x1 << 7) +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index 13889594bf..ce87a46cd1 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -579,6 +579,15 @@ extern void espi_init(void); + extern void kcs_init(void); + void ast_g5_intel(void) + { ++ /* EXTRST# mask for PFR platform ++ * EXTRST# is used by PFR CPLD to keep BMC in ++ * reset during firmware authentication, updates and recovery ++ * this mask selects the modules to be reset along with BMC so that ++ * Host functions are intact. ++ * (this is fix from Purley PFR ) ++ */ ++ ast_scu_write(AST_WDT_RESET_MASK, AST_SCU_WDT_RESET); ++ + /* Disable uart port debug function */ + ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | + SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0036-Re-Enable-KCS.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0036-Re-Enable-KCS.patch new file mode 100644 index 000000000..976277f9e --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0036-Re-Enable-KCS.patch @@ -0,0 +1,35 @@ +From 6bd4135cd2b8e3a95f5c29e7edaa678e0ca6eded Mon Sep 17 00:00:00 2001 +From: James Feist <james.feist@linux.intel.com> +Date: Thu, 19 Sep 2019 10:15:19 -0700 +Subject: [PATCH 1/1] Re-Enable KCS + +Phosphor-isolation isolates too much and seems to +make KCS not work. This removes the lines from that +patch that seem to be of question. + +Tested: AC/Cycled, cmdtool.efi 20 18 1 works + +Signed-off-by: James Feist <james.feist@linux.intel.com> +--- + board/aspeed/ast-g5/ast-g5.c | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index ead2e1bb63..00bd92ae5f 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -41,11 +41,6 @@ int board_init(void) + bool sdmc_unlocked; + u32 val; + +- /* iLPC2AHB */ +- val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1); +- val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO; +- writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1); +- + val = readl(AST_LPC_BASE + AST_LPC_HICRB); + val |= LPC_HICRB_ILPC2AHB; + writel(val, AST_LPC_BASE + AST_LPC_HICRB); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch new file mode 100644 index 000000000..9c176e998 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch @@ -0,0 +1,80 @@ +From 4b96a19bdde82d7fed24cb70e0bcaef16d8711c3 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Fri, 4 Oct 2019 15:54:43 -0700 +Subject: [PATCH] aspeed/ast-scu.c: fix MAC1LINK and MAC2LINK pin pads setting + +Intel platforms don't use these pins as PHY link monitoring inputs +so this commit disables them in SCU pin control register so that +the pins can be used as GPIOs. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/mach-aspeed/ast-scu.c | 37 +++++++++---------------------------- + 1 file changed, 9 insertions(+), 28 deletions(-) + +diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c +index 537cd4b3e1c7..28c48c115406 100644 +--- a/arch/arm/mach-aspeed/ast-scu.c ++++ b/arch/arm/mach-aspeed/ast-scu.c +@@ -419,49 +419,30 @@ void ast_scu_multi_func_eth(u8 num) + { + switch (num) { + case 0: +- if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC0_RGMII) { ++ if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC0_RGMII) + printf("MAC0 : RGMII\n"); +- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | +- SCU_FUN_PIN_MAC0_PHY_LINK, +- AST_SCU_FUN_PIN_CTRL1); +- } else { ++ else + printf("MAC0 : RMII/NCSI\n"); +- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & +- ~SCU_FUN_PIN_MAC0_PHY_LINK, +- AST_SCU_FUN_PIN_CTRL1); +- } +- +-#ifdef AST_SOC_G5 +- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | +- SCU_FUN_PIN_MAC0_PHY_LINK, AST_SCU_FUN_PIN_CTRL1); + +-#endif ++ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & ++ ~SCU_FUN_PIN_MAC0_PHY_LINK, ++ AST_SCU_FUN_PIN_CTRL1); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | + SCU_FUN_PIN_MAC0_MDIO | SCU_FUN_PIN_MAC0_MDC, + AST_SCU_FUN_PIN_CTRL3); +- + break; + case 1: +- if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC1_RGMII) { ++ if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC1_RGMII) + printf("MAC1 : RGMII\n"); +- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | +- SCU_FUN_PIN_MAC1_PHY_LINK, +- AST_SCU_FUN_PIN_CTRL1); +- } else { ++ else + printf("MAC1 : RMII/NCSI\n"); +- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & +- ~SCU_FUN_PIN_MAC1_PHY_LINK, +- AST_SCU_FUN_PIN_CTRL1); +- } + +- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | +- SCU_FUN_PIN_MAC1_PHY_LINK, ++ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & ++ ~SCU_FUN_PIN_MAC1_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); +- + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | + SCU_FUC_PIN_MAC1_MDIO, + AST_SCU_FUN_PIN_CTRL5); +- + break; + } + } +-- +2.7.4 + |