diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot')
15 files changed, 928 insertions, 180 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch index a084c4a8c..f1505b8cd 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch @@ -1,28 +1,29 @@ -From 069a20560bf9efbd358503c76f043fcdd3a68a94 Mon Sep 17 00:00:00 2001 +From efa949f82a1dd32b83eafe3fe58038abc04ecdbf Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@intel.com> Date: Thu, 24 Oct 2019 14:06:33 -0700 Subject: [PATCH] Add ast2600-intel as a new board Signed-off-by: Vernon Mauery <vernon.mauery@intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> --- arch/arm/dts/Makefile | 3 + - arch/arm/dts/ast2600-intel.dts | 170 +++++++++++ + arch/arm/dts/ast2600-intel.dts | 157 ++++++++++ arch/arm/lib/interrupts.c | 5 + arch/arm/mach-aspeed/ast2600/Kconfig | 9 + arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c | 1 + board/aspeed/ast2600_intel/Kconfig | 13 + board/aspeed/ast2600_intel/Makefile | 4 + - board/aspeed/ast2600_intel/ast-espi.c | 282 +++++++++++++++++ + board/aspeed/ast2600_intel/ast-espi.c | 298 ++++++++++++++++++ board/aspeed/ast2600_intel/ast-irq.c | 399 +++++++++++++++++++++++++ board/aspeed/ast2600_intel/ast-irq.h | 8 + board/aspeed/ast2600_intel/ast-timer.c | 59 ++++ - board/aspeed/ast2600_intel/intel.c | 171 +++++++++++ + board/aspeed/ast2600_intel/intel.c | 176 +++++++++++ cmd/Kconfig | 2 +- common/autoboot.c | 10 + common/board_r.c | 8 +- include/configs/evb_ast2600.h | 2 +- - 16 files changed, 1140 insertions(+), 6 deletions(-) + 16 files changed, 1148 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/ast2600-intel.dts create mode 100644 board/aspeed/ast2600_intel/Kconfig create mode 100644 board/aspeed/ast2600_intel/Makefile @@ -48,10 +49,10 @@ index d1d4dca340f8..38fe8113469e 100644 diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts new file mode 100644 -index 000000000000..0d362ac7c150 +index 000000000000..99788b21e444 --- /dev/null +++ b/arch/arm/dts/ast2600-intel.dts -@@ -0,0 +1,170 @@ +@@ -0,0 +1,157 @@ +/dts-v1/; + +#include "ast2600-u-boot.dtsi" @@ -209,19 +210,6 @@ index 000000000000..0d362ac7c150 + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; +}; -+ -+#if 0 -+&pcie_bridge0 { -+ status = "okay"; -+}; -+#else -+&pcie_bridge1 { -+ status = "okay"; -+}; -+#endif -+&h2x { -+ status = "okay"; -+}; diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index ee775ce5d264..8c985532afb4 100644 --- a/arch/arm/lib/interrupts.c @@ -322,10 +310,10 @@ index 000000000000..37d2f0064f38 +obj-y += ast-timer.o diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c new file mode 100644 -index 000000000000..8dc12d7c9fe8 +index 000000000000..1852dd3d86e2 --- /dev/null +++ b/board/aspeed/ast2600_intel/ast-espi.c -@@ -0,0 +1,282 @@ +@@ -0,0 +1,298 @@ +/* + * Copyright 2018 Intel Corporation + * @@ -341,11 +329,11 @@ index 000000000000..8dc12d7c9fe8 +#define AST_LPC_BASE 0x1e6e9000 +#define AST_ESPI_BASE 0x1e6ee000 +#define AST_SCU_BASE 0x1e6e2000 -+#define AST_SCU_HW_STRAP1 0x510 ++#define AST_SCU_HW_STRAP2 0x510 +#define SCU_HW_STRAP_ESPI_ENABLED 0x40 + -+#define USE_HW_HANDSHAKE 1 -+#define DEBUG_ESPI_ENABLED 1 ++#define USE_HW_HANDSHAKE 0 ++#define DEBUG_ESPI_ENABLED 0 +#if DEBUG_ESPI_ENABLED +#define DBG_ESPI printf +#else @@ -431,7 +419,8 @@ index 000000000000..8dc12d7c9fe8 + +/* ESPI008 bits ISR */ +#define AST_ESPI_VW_SYS_EVT BIT(8) -+#define AST_ESPI_VW_SYS_EV1 BIT(9) ++#define AST_ESPI_VW_GPIO_EVT BIT(9) ++#define AST_ESPI_VW_SYS_EV1 BIT(22) +#define AST_ESPI_HW_RST BIT(31) + +/* ESPI080 bits */ @@ -479,7 +468,15 @@ index 000000000000..8dc12d7c9fe8 +{ + uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008); + -+ DBG_ESPI("ISR irq_status : 0x%08X\n", irq_status); ++ DBG_ESPI("espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x,\ ++ ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x,\ ++ ESPI12c=0X%x, irq_status=0x%x\n", ++ readl(AST_ESPI_BASE + ESPI008), ++ readl(AST_ESPI_BASE + ESPI00C), ++ readl(AST_ESPI_BASE + ESPI100), ++ readl(AST_ESPI_BASE + ESPI11C), ++ readl(AST_ESPI_BASE + ESPI094), ++ readl(AST_ESPI_BASE + ESPI12C), irq_status); + + if (irq_status & AST_ESPI_VW_SYS_EVT) { + uint32_t sys_status = readl(AST_ESPI_BASE + ESPI11C); @@ -542,13 +539,22 @@ index 000000000000..8dc12d7c9fe8 + + writel(irq_status, AST_ESPI_BASE + ESPI008); /* clear irq_status */ + ++ DBG_ESPI("end espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x,\ ++ ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x,\ ++ ESPI12c=0X%x, irq_status=0X%x\n", ++ readl(AST_ESPI_BASE + ESPI008), ++ readl(AST_ESPI_BASE + ESPI00C), ++ readl(AST_ESPI_BASE + ESPI100), ++ readl(AST_ESPI_BASE + ESPI11C), ++ readl(AST_ESPI_BASE + ESPI094), ++ readl(AST_ESPI_BASE + ESPI12C), irq_status); + return 0; +} + +void espi_init(void) +{ -+ if (1 || !readl(AST_SCU_BASE + AST_SCU_HW_STRAP1) -+ & SCU_HW_STRAP_ESPI_ENABLED) { ++ if (!readl(AST_SCU_BASE + AST_SCU_HW_STRAP2) & ++ SCU_HW_STRAP_ESPI_ENABLED) { + uint32_t v; + + DBG_ESPI("espi init\n"); @@ -601,8 +607,6 @@ index 000000000000..8dc12d7c9fe8 + writel(AST_ESPI_IEN_HW_RST | AST_ESPI_IEN_SYS1_EV | + AST_ESPI_IEN_SYS_EV, AST_ESPI_BASE + ESPI00C); + -+ espi_handshake_ack(); -+ + irq_install_handler(IRQ_SRC_ESPI, espi_irq_handler, NULL); + } else { + DBG_ESPI("No espi strap\n"); @@ -1094,10 +1098,10 @@ index 000000000000..cf8c69aba5d3 +} diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c new file mode 100644 -index 000000000000..100eb1ec5d21 +index 000000000000..b5d8dd36d20b --- /dev/null +++ b/board/aspeed/ast2600_intel/intel.c -@@ -0,0 +1,171 @@ +@@ -0,0 +1,176 @@ +/* Intel customizations of Das U-Boot */ +#include <common.h> +#include <asm/gpio.h> @@ -1196,18 +1200,23 @@ index 000000000000..100eb1ec5d21 + writel(value, AST_LPC_BASE + HICRB); +} + -+#define AST_GPIO_BASE 0x1e780000 -+#define SGPIO_CLK_DIV(N) ((N) << 16) -+#define SGPIO_BYTES(N) ((N) << 6) -+#define SGPIO_ENABLE 1 -+#define GPIO254 0x554 ++#define AST_GPIO_BASE 0x1e780000 + +static void sgpio_init(void) +{ ++#define SGPIO_CLK_DIV(N) ((N) << 16) ++#define SGPIO_BYTES(N) ((N) << 6) ++#define SGPIO_ENABLE 1 ++#define GPIO554 0x554 ++#define SCU_414 0x414 /* Multi-function Pin Control #5 */ ++#define SCU_414_SGPM_MASK GENMASK(27, 24) ++ + uint32_t value; -+ /* set the gpio clock to pclk/(2*(5+1)) or ~2 MHz */ ++ /* set the sgpio clock to pclk/(2*(5+1)) or ~2 MHz */ + value = SGPIO_CLK_DIV(256) | SGPIO_BYTES(10) | SGPIO_ENABLE; -+ writel(value, AST_GPIO_BASE + GPIO254); ++ writel(value, AST_GPIO_BASE + GPIO554); ++ writel(readl(SCU_BASE | SCU_414) | SCU_414_SGPM_MASK, ++ SCU_BASE | SCU_414); +} + +void espi_init(void); @@ -1238,8 +1247,8 @@ index 000000000000..100eb1ec5d21 + +int board_early_init_r(void) +{ -+ printf("board_early_init_r\n"); -+ timer_enable(0, 1, timer_handler); ++ debug("board_early_init_r\n"); ++ /* timer_enable(0, 1, timer_handler); */ + + espi_init(); + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Disable-crashdump-trigger-gpio.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Disable-crashdump-trigger-gpio.patch index 6ffdbc702..d9c40fea0 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Disable-crashdump-trigger-gpio.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Disable-crashdump-trigger-gpio.patch @@ -1,4 +1,4 @@ -From aae3bab86f19784cbe0767ea0973527ce217bf89 Mon Sep 17 00:00:00 2001 +From b203aee347f6b4104a7dfbc061b195c99795451e Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Fri, 3 Jan 2020 15:14:09 -0800 Subject: [PATCH] Disable crashdump trigger gpio @@ -12,11 +12,11 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 1 file changed, 23 insertions(+) diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index eb6fbaf77e66..7daf1b83305a 100644 +index b6a11132448f..f095f1ecd696 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c -@@ -146,6 +146,27 @@ static void sgpio_init(void) - writel(value, AST_GPIO_BASE + GPIO254); +@@ -151,6 +151,27 @@ static void sgpio_init(void) + SCU_BASE | SCU_414); } +static void disable_crashlog_trigger(void) @@ -43,7 +43,7 @@ index eb6fbaf77e66..7daf1b83305a 100644 void espi_init(void); int arch_interrupt_init_early(void); -@@ -162,6 +183,8 @@ int board_early_init_f(void) +@@ -167,6 +188,8 @@ int board_early_init_f(void) * I am not sure if it actually does anything... */ arch_interrupt_init_early(); diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch new file mode 100644 index 000000000..ce9aa668a --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch @@ -0,0 +1,458 @@ +From 959b75b846aa25168fe9e3d04ceb0e0778f89992 Mon Sep 17 00:00:00 2001 +From: Kuiying Wang <kuiying.wang@intel.com> +Date: Fri, 3 Jan 2020 12:52:29 +0800 +Subject: [PATCH] Enable interrupt in u-boot. + +Ast2600 is Cortex-A7 +GIC V2 is used as the interrupt controller +GIC includes GICD and GICC + +Testedby: +1. Enable interrupt based SW handshake for ESPI +2. Both ArcherCity and Ast2600 EVB are working well. + +Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> +--- + arch/arm/lib/vectors.S | 31 ++++++- + board/aspeed/ast2600_intel/ast-irq.c | 154 +++++++++++++++++------------------ + configs/evb-ast2600_defconfig | 1 + + include/configs/evb_ast2600.h | 1 + + 4 files changed, 107 insertions(+), 80 deletions(-) + +diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S +index 2ca6e2494a7a..e2ed04a204de 100644 +--- a/arch/arm/lib/vectors.S ++++ b/arch/arm/lib/vectors.S +@@ -13,7 +13,7 @@ + */ + + #include <config.h> +- ++#define CONFIG_USE_IRQ + /* + * A macro to allow insertion of an ARM exception vector either + * for the non-boot0 case or by a boot0-header. +@@ -145,6 +145,17 @@ fiq: + + #else /* !CONFIG_SPL_BUILD */ + ++#ifdef CONFIG_USE_IRQ ++/* IRQ stack memory (calculated at run-time) */ ++.globl IRQ_STACK_START ++IRQ_STACK_START: ++ .word 0x0badc0de ++/* IRQ stack memory (calculated at run-time) */ ++.globl FIQ_STACK_START ++FIQ_STACK_START: ++ .word 0x0badc0de ++#endif ++ + /* IRQ stack memory (calculated at run-time) + 8 bytes */ + .globl IRQ_STACK_START_IN + IRQ_STACK_START_IN: +@@ -277,17 +288,31 @@ not_used: + bad_save_user_regs + bl do_not_used + ++ .align 5 ++#ifdef CONFIG_USE_IRQ ++irq: ++ get_irq_stack ++ irq_save_user_regs ++ bl do_irq ++ irq_restore_user_regs ++ .align 5 ++fiq: ++ get_fiq_stack ++ /* someone ought to write a more effective fiq_save_user_regs */ ++ irq_save_user_regs ++ bl do_fiq ++ irq_restore_user_regs + + .align 5 ++#else + irq: + get_bad_stack + bad_save_user_regs + bl do_irq +- + .align 5 + fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq +- ++#endif /* CONFIG_USE_IRQ */ + #endif /* CONFIG_SPL_BUILD */ +diff --git a/board/aspeed/ast2600_intel/ast-irq.c b/board/aspeed/ast2600_intel/ast-irq.c +index f817f8cd7c81..6e91b17ab186 100644 +--- a/board/aspeed/ast2600_intel/ast-irq.c ++++ b/board/aspeed/ast2600_intel/ast-irq.c +@@ -18,19 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; + #define GIC_INTERFACE_OFFSET 0x4000 + #define GIC_VIRT_OFFSET 0x6000 + +-#define VIC_STATUS_L 0x80 +-#define VIC_STATUS_H 0x84 +-#define VIC_IRQ_SELECTION_L 0x98 +-#define VIC_IRQ_SELECTION_H 0x9C +-#define VIC_ENABLE_L 0xA0 +-#define VIC_ENABLE_H 0xA4 +-#define VIC_ENABLE_CLEAR_L 0xA8 +-#define VIC_ENABLE_CLEAR_H 0xAC +-#define VIC_INTERRUPT_CLEAR_L 0xD8 +-#define VIC_INTERRUPT_CLEAR_H 0xDC +- +-#define VIC_CLEAR_ALL (~0) +- + /* GIC_DISTRIBUTOR_OFFSET register offsets */ + #define GICD_CTLR 0x000 + #define GICD_TYPER 0x004 +@@ -82,7 +69,9 @@ DECLARE_GLOBAL_DATA_PTR; + #define GICC_IIDR 0x00fc + #define GICC_DIR 0x1000 + +-#define GIC_CPU_IMPLEMENTER_MAGIC 0x0102143b ++#define GIC_CPU_IMPLEMENTER_MAGIC 0x0102143b ++#define GICC_IAR_INT_ID_MASK 0x3ff ++#define GIC_CPU_DEACTIVATE 0x1000 + + /* GIC_INTERFACE_OFFSET register offsets */ + #define GICH_HCR 0x000 +@@ -116,9 +105,10 @@ DECLARE_GLOBAL_DATA_PTR; + + #define GIC_VIRT_CPU_IMPLEMENTER_MAGIC 0x0102143b + +-#define GICD_CTLR_ENABLE 0x03 +- +-#define GICD_INT_DEF_PRI 0xa0 ++#define GICD_CTLR_ENABLE 0x03 /*enable group 0 and 1*/ ++#define GICC_CTLR_ENABLE 0x03 ++#define GICD_ITARGET_ALL 0xffffffff ++#define GICD_INT_DEF_PRI 0xa0 + #define GICD_INT_DEF_PRI_X4 (\ + (GICD_INT_DEF_PRI << 24) |\ + (GICD_INT_DEF_PRI << 16) |\ +@@ -129,20 +119,30 @@ DECLARE_GLOBAL_DATA_PTR; + #define GICD_INT_EN_CLR_X32 0xffffffff + #define GICD_INT_EN_CLR_PPI 0xffff0000 + #define GICD_INT_EN_SET_SGI 0x0000ffff ++#define GICD_ICFG_LEVEL_TRIGGER 0x55555555 ++#define GICC_UNMASK_ALL_PRIORITY 0xff + + #define gicd_readl(OFFSET) readl(gbase + GIC_DISTRIBUTOR_OFFSET + (OFFSET)) + #define gicd_writel(VALUE, OFFSET) \ + writel((VALUE), gbase + GIC_DISTRIBUTOR_OFFSET + (OFFSET)) + #define gicc_readl(OFFSET) readl(gbase + GIC_CPU_OFFSET + (OFFSET)) ++#define gicc_writel(VALUE, OFFSET) \ ++ writel((VALUE), gbase + GIC_CPU_OFFSET + (OFFSET)) + #define gich_readl(OFFSET) readl(gbase + GIC_INTERFACE_OFFSET + (OFFSET)) + #define gicv_readl(OFFSET) readl(gbase + GIC_VIRT_OFFSET + (OFFSET)) +- +-static size_t max_irq = 0; +- + #define ITLINES_MASK 0x1f + #define ITLINES_SHIFT 5 +- + #define GIC_MAX_IRQ 1020 ++#define SPI_INT_NUM_MIN 32 ++#define MAX_IRQ 0xfffffffe ++#define DEBUG_IRQ_ENABLED 0 ++#if DEBUG_IRQ_ENABLED ++#define DBG_IRQ printf ++#else ++#define DBG_IRQ(...) ++#endif ++ ++static size_t max_irq = 0; + static interrupt_handler_t *handlers[GIC_MAX_IRQ] = {NULL}; + static unsigned long irq_total = 0; + static unsigned long irq_counts[GIC_MAX_IRQ] = {0}; +@@ -159,31 +159,40 @@ static inline uint32_t gic_base(void) + + static void enable_gic(void) + { +- uint32_t gicd_ctlr; ++ uint32_t gicd_ctlr, gicc_ctlr; + ++ DBG_IRQ(" %s()\n", __FUNCTION__); + /* add GIC offset ref table 1-3 for interrupt distributor address */ + gicd_ctlr = gicd_readl(GICD_CTLR); ++ gicc_ctlr = gicc_readl(GICC_CTLR); + gicd_writel(gicd_ctlr | GICD_CTLR_ENABLE, GICD_CTLR); ++ gicc_writel(gicc_ctlr | GICC_CTLR_ENABLE, GICC_CTLR); + } + + static void disable_gic(void) + { +- uint32_t gicd_ctlr; +- ++ uint32_t gicd_ctlr, gicc_ctlr; ++ DBG_IRQ(" %s()\n", __FUNCTION__); + /* add GIC offset ref table 1-3 for interrupt distributor address */ + gicd_ctlr = gicd_readl(GICD_CTLR); + gicd_writel(gicd_ctlr & ~GICD_CTLR_ENABLE, GICD_CTLR); ++ gicc_ctlr = gicc_readl(GICC_CTLR); ++ gicc_writel(gicc_ctlr & ~GICC_CTLR_ENABLE, GICC_CTLR); + } + + static void enable_irq_id(unsigned int id) + { ++ DBG_IRQ(" %s()\n", __FUNCTION__); ++ + uint32_t grp = id >> ITLINES_SHIFT; + uint32_t grp_bit = 1 << (id & ITLINES_MASK); + gicd_writel(grp_bit, GICD_ISENABLERn + grp * sizeof(uint32_t)); ++ gicd_writel(GICD_ITARGET_ALL, GICD_ITARGETSRn + id / 4 * 4); + } + + static void disable_irq_id(unsigned int id) + { ++ DBG_IRQ(" %s()\n", __FUNCTION__); + uint32_t grp = id >> ITLINES_SHIFT; + uint32_t grp_bit = 1 << (id & ITLINES_MASK); + gicd_writel(grp_bit, GICD_ICENABLERn + grp * sizeof(uint32_t)); +@@ -193,22 +202,29 @@ static int gic_probe(void) + { + int i; + gbase = gic_base(); ++ DBG_IRQ("gic_probe GIC base = 0x%x, magicd=0x%x\n", ++ gbase, gicd_readl(GICD_IIDR)); + enable_gic(); + + if (gicd_readl(GICD_IIDR) != GIC_DISTRIBUTOR_IMPLEMENTER_MAGIC && + gicc_readl(GICC_IIDR) != GIC_CPU_IMPLEMENTER_MAGIC && + gicv_readl(GICV_IIDR) != GIC_VIRT_CPU_IMPLEMENTER_MAGIC) + { ++ printf("error: magic check \n"); + return 0; + } + /* GIC supports up to 1020 lines */ +- max_irq = ((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) << ITLINES_SHIFT; ++ max_irq = (((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) * 32) - 1; + if (max_irq > GIC_MAX_IRQ) + max_irq = GIC_MAX_IRQ; + /* set all lines to be level triggered N-N */ + for (i = 32; i < max_irq; i += 16) +- gicd_writel(0, GICD_ICFGRn + i / 4); ++ gicd_writel(GICD_ICFG_LEVEL_TRIGGER, GICD_ICFGRn + i / 4); + ++ DBG_IRQ("max_irq = 0x%x, typer=0x%x, config=0x%x, maxirq=0x%x\n", max_irq, ++ (gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1, ++ gicd_readl(GICD_ICFGRn + 0x8), ++ ((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) * 0x20); + /* Set priority on all interrupts. */ + for (i = 0; i < max_irq; i += 4) + gicd_writel(GICD_INT_DEF_PRI_X4, GICD_IPRIORITYRn + i); +@@ -218,9 +234,11 @@ static int gic_probe(void) + gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn + i / 8); + gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICENABLERn + i / 8); + } +- gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn); +- gicd_writel(GICD_INT_EN_CLR_PPI, GICD_ICENABLERn); ++ gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn); ++ gicd_writel(GICD_INT_EN_CLR_PPI, GICD_ICENABLERn); + gicd_writel(GICD_INT_EN_SET_SGI, GICD_ISENABLERn); ++ /* unmask all priority */ ++ gicc_writel(GICC_UNMASK_ALL_PRIORITY, GICC_PMRn); + + return 0; + } +@@ -228,6 +246,7 @@ static int gic_probe(void) + void irq_free_handler (int irq); + static void gic_shutdown(void) + { ++ DBG_IRQ(" %s()\n", __FUNCTION__); + int i; + for (i = 0; i < max_irq; i++) + { +@@ -238,6 +257,7 @@ static void gic_shutdown(void) + + int arch_interrupt_init_early(void) + { ++ DBG_IRQ(" %s()\n", __FUNCTION__); + return 0; + } + +@@ -249,11 +269,13 @@ int arch_interrupt_init(void) + handlers[i] = NULL; + irq_counts[i] = 0; + } ++ DBG_IRQ("arch_interrupt_init\n"); + return gic_probe(); + } + + int arch_interrupt_fini(void) + { ++ DBG_IRQ(" %s()\n", __FUNCTION__); + gic_shutdown(); + return 0; + } +@@ -261,14 +283,12 @@ int arch_interrupt_fini(void) + int interrupt_init (void) + { + /* +- * setup up stacks if necessary +- */ ++ * setup up stacks if necessary*/ ++ IRQ_STACK_START = gd->irq_sp + 8; + IRQ_STACK_START_IN = gd->irq_sp + 8; + +- printf("%s()\n", __FUNCTION__); ++ DBG_IRQ(" %s()\n", __FUNCTION__); + return arch_interrupt_init(); +- +- return 0; + } + + int global_interrupts_enabled (void) +@@ -286,12 +306,12 @@ void enable_interrupts (void) + { + unsigned long cpsr; + __asm__ __volatile__("mrs %0, cpsr\n" +- "bic %0, %0, #0x80\n" ++ "bic %0, %0, #0x1c0\n" + "msr cpsr_c, %0" + : "=r" (cpsr) + : + : "memory"); +- ++ DBG_IRQ(" %s()\n", __FUNCTION__); + return; + } + +@@ -304,11 +324,13 @@ int disable_interrupts (void) + : "=r" (cpsr), "=r" (temp) + : + : "memory"); ++ DBG_IRQ(" %s()\n", __FUNCTION__); + return (cpsr & 0x80) == 0; + } + + void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx) + { ++ DBG_IRQ(" %s()\n", __FUNCTION__); + if (irq > max_irq) { + printf("irq %d out of range\n", irq); + return; +@@ -317,13 +339,14 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx) + printf("irq %d already in use (%p)\n", irq, handlers[irq]); + return; + } +- printf("registering handler for irq %d\n", irq); ++ DBG_IRQ("registering handler for irq %d\n", irq); + handlers[irq] = handler; + enable_irq_id(irq); + } + + void irq_free_handler (int irq) + { ++ DBG_IRQ(" %s()\n", __FUNCTION__); + if (irq >= max_irq) { + printf("irq %d out of range\n", irq); + return; +@@ -338,9 +361,10 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) + { + int i; + int enabled = global_interrupts_enabled(); +- printf("GIC base = 0x%x\n", gbase); +- printf("interrupts %sabled\n", (enabled ? "en" : "dis")); ++ DBG_IRQ("GIC base = 0x%x\n", gbase); ++ DBG_IRQ("interrupts %sabled\n", (enabled ? "en" : "dis")); + uint32_t grp_en = 0; ++ + for (i = 0; i < max_irq; i++) { + if ((i & ITLINES_MASK) == 0) + grp_en = gicd_readl(GICD_ISENABLERn + +@@ -348,52 +372,28 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) + int irq_enabled = grp_en & (1 << (i & ITLINES_MASK)); + if (!irq_enabled) + continue; +- printf("% 2i (% 3s): %lu\n", i, ++ DBG_IRQ("%2d (%3s): %lu\n", i, + (irq_enabled ? "on" : "off"), irq_counts[i]); + } +- printf("total: %lu\n", irq_total); ++ DBG_IRQ("total: %lu\n", irq_total); + return 0; + } + + void do_irq(struct pt_regs *pt_regs) + { +- int i; +- if (!gbase) { +- static int printed_msg = 0; +- if (!printed_msg) +- { +- printed_msg = 1; +- printf("interrupt before configured!\n"); +- } +- return; +- } +- irq_total++; +- uint32_t grp_pend = 0; +- for (i = 0; i < max_irq; i++) { +- /* limit reads of the pending register to once in 32 */ +- if ((i & ITLINES_MASK) == 0) +- grp_pend = gicd_readl(GICD_ISPENDRn + +- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); +- uint32_t pending = grp_pend & (1 << (i & ITLINES_MASK)); +- if (pending) { +- irq_counts[i]++; +- /* mask via GICD_ICENABLERn */ +- gicd_writel(pending, GICD_ICENABLERn + +- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); +- if (handlers[i]) { +- handlers[i](pt_regs); +- /* unmask via GICD_ISENABLERn */ +- gicd_writel(pending, GICD_ISENABLERn + +- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); +- /* clear pending via GICD_ICPENDRn */ +- gicd_writel(pending, GICD_ICPENDRn + +- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); +- } else { +- printf("unexpected interrupt %i; masking\n", i); +- /* clear pending via GICD_ICPENDRn */ +- gicd_writel(pending, GICD_ISPENDRn + +- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); +- } ++ uint32_t irqstat = 0, irqnr = 0; ++ ++ if (irq_total < MAX_IRQ) ++ irq_total++; ++ irqstat = gicc_readl(GICC_IAR); ++ irqnr = irqstat & GICC_IAR_INT_ID_MASK; ++ ++ if (irqnr > SPI_INT_NUM_MIN && irqnr < GIC_MAX_IRQ) { ++ gicc_writel(irqnr, GICC_EOIR); ++ if (irq_counts[irqnr] < MAX_IRQ) ++ irq_counts[irqnr]++; ++ if (handlers[irqnr]) { ++ handlers[irqnr](NULL); + } + } + } +diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig +index 517d59adaf11..9cd7aea98e8d 100644 +--- a/configs/evb-ast2600_defconfig ++++ b/configs/evb-ast2600_defconfig +@@ -72,3 +72,4 @@ CONFIG_SPI=y + CONFIG_DM_SPI=y + CONFIG_SYSRESET=y + CONFIG_WDT=y ++CONFIG_USE_IRQ=y +diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h +index 91a42f2522e2..15061b25d872 100644 +--- a/include/configs/evb_ast2600.h ++++ b/include/configs/evb_ast2600.h +@@ -8,6 +8,7 @@ + + #include <configs/aspeed-common.h> + ++#define CONFIG_USE_IRQ + #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000) + #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000) + +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch new file mode 100644 index 000000000..ca5846416 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch @@ -0,0 +1,158 @@ +From 8c953c7f1d512cf4acd9ce000d65e46094d61597 Mon Sep 17 00:00:00 2001 +From: arun-pm <arun.p.m@linux.intel.com> +Date: Fri, 29 Nov 2019 00:19:09 +0530 +Subject: [PATCH] SPI Quad IO Mode + +This commit adds quad IO mode in SPI driver for AST2600. + +Note:- Removed n25q00 Quad I/O support for the time being due to clock issue + with chip 'Micron 8UA15 - rw182 (128MB)' while enabling Quad I/O mode. +--- + arch/arm/dts/ast2600-intel.dts | 6 ++--- + drivers/mtd/spi/spi-nor-ids.c | 7 +++++- + drivers/spi/aspeed_spi.c | 46 ++++++++++++++++++++++++---------- + 3 files changed, 41 insertions(+), 18 deletions(-) + +diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts +index 0d362ac7c1..2a74bbd30a 100644 +--- a/arch/arm/dts/ast2600-intel.dts ++++ b/arch/arm/dts/ast2600-intel.dts +@@ -101,16 +101,14 @@ + + &fmc { + status = "okay"; +-#if 0 + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fmcquad_default>; +-#endif + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <40000000>; +- spi-tx-bus-width = <2>; +- spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; + }; + }; + +diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c +index c77987f1ff..d679238562 100644 +--- a/drivers/mtd/spi/spi-nor-ids.c ++++ b/drivers/mtd/spi/spi-nor-ids.c +@@ -164,7 +164,12 @@ const struct flash_info spi_nor_ids[] = { + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, +- { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, ++ /* Removed n25q00 Quad I/O support for the time being due to clock issue with chip 'Micron 8UA15 - rw182 (128MB)' ++ * while enabling Quad I/O mode. As this chip is default shipped in platforms, marking it ++ * as Not supported for the time being. Once all chips are replaced with the new model, this can be enabled ++ * back(Note:- Certain other chips having same name(n25q00) but different part number has no issues). ++ */ ++ { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | NO_CHIP_ERASE) }, + { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + #endif +diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c +index a8c2b3de2b..ae5edaee9f 100644 +--- a/drivers/spi/aspeed_spi.c ++++ b/drivers/spi/aspeed_spi.c +@@ -16,6 +16,9 @@ + #include <linux/ioport.h> + + #define ASPEED_SPI_MAX_CS 3 ++#define AST2600A0 0x05000303 ++#define AST2600A0_MAX_FREQ 40000000 ++#define AST_MAX_FREQ 100000000 + + struct aspeed_spi_regs { + u32 conf; /* 0x00 CE Type Setting */ +@@ -593,6 +596,7 @@ static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, + aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); + aspeed_spi_stop_user(priv, flash); + ++ debug("=== write opcode [%x] ==== \n", opcode); + switch(opcode) { + case SPINOR_OP_EN4B: + writel(readl(&priv->regs->ctrl) | BIT(flash->cs), &priv->regs->ctrl); +@@ -615,6 +619,8 @@ static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, + /* First, send the opcode */ + aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); + ++ if(flash->iomode == CE_CTRL_IO_QUAD_ADDR_DATA) ++ writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); + /* + * The controller is configured for 4BYTE address mode. Fix + * the address width and send an extra byte if the SPI Flash +@@ -664,9 +670,6 @@ static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, + { + aspeed_spi_start_user(priv, flash); + +- if(flash->iomode == CE_CTRL_IO_QPI_DATA) +- writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); +- + /* cmd buffer = cmd + addr : normally cmd is use signle mode*/ + aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); + +@@ -872,15 +875,19 @@ static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, + else + read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); + +- if (slave->mode & (SPI_RX_DUAL | SPI_TX_DUAL)) { +- debug("CS%u: setting dual data mode\n", flash->cs); +- flash->iomode = CE_CTRL_IO_DUAL_DATA; +- flash->spi->read_opcode = SPINOR_OP_READ_1_1_2; +- } else if (slave->mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { +- flash->iomode = CE_CTRL_IO_QUAD_DATA; +- flash->spi->read_opcode = SPINOR_OP_READ_1_4_4; +- } else { +- debug("normal read \n"); ++ switch(flash->spi->read_opcode) { ++ case SPINOR_OP_READ_1_1_2: ++ case SPINOR_OP_READ_1_1_2_4B: ++ flash->iomode = CE_CTRL_IO_DUAL_DATA; ++ break; ++ case SPINOR_OP_READ_1_1_4: ++ case SPINOR_OP_READ_1_1_4_4B: ++ flash->iomode = CE_CTRL_IO_QUAD_DATA; ++ break; ++ case SPINOR_OP_READ_1_4_4: ++ case SPINOR_OP_READ_1_4_4_4B: ++ flash->iomode = CE_CTRL_IO_QUAD_ADDR_DATA; ++ break; + } + + if(priv->new_ver) { +@@ -986,6 +993,19 @@ static int aspeed_spi_bind(struct udevice *bus) + return 0; + } + ++static int aspeed_get_max_freq(void) ++{ ++ u32 rev_id = readl(ASPEED_REVISION_ID); ++ ++ /*Limit max spi frequency less than 50MHz on AST2600-A0 due ++ * to FWSPICLK signal quality issue. ++ */ ++ if(rev_id == AST2600A0) ++ return AST2600A0_MAX_FREQ; ++ else ++ return AST_MAX_FREQ; ++} ++ + static int aspeed_spi_probe(struct udevice *bus) + { + struct resource res_regs, res_ahb; +@@ -1016,7 +1036,7 @@ static int aspeed_spi_probe(struct udevice *bus) + clk_free(&hclk); + + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", +- 100000000); ++ aspeed_get_max_freq()); + + priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); + +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch index b37aee7e6..fac5a64ef 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch @@ -1,7 +1,7 @@ -From c46cb2dd703f55ca63ed9c5cf2a97868a7e6c209 Mon Sep 17 00:00:00 2001 +From 74a1399befdb0f7604d116ac8578e7e4004728d8 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Wed, 14 Nov 2018 10:21:40 -0800 -Subject: [PATCH] Add espi support +Subject: [PATCH 1/1] Add espi support This adds basic eSPI support for U-Boot. The eSPI driver works best with interrupts because the timing of the initialization with the PCH is not @@ -12,23 +12,22 @@ host to boot. In the future it may be expanded to have further functions. Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> -Change-Id: Id7072f1408dcf364968b1b74f2192e50a22a82f0 - +Signed-off-by: James Feist <james.feist@linux.intel.com> --- arch/arm/include/asm/arch-aspeed/regs-scu.h | 2 + board/aspeed/ast-g5/Makefile | 2 + - board/aspeed/ast-g5/ast-g5-espi.c | 231 ++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-espi.c | 242 ++++++++++++++++++++ board/aspeed/ast-g5/ast-g5-intel.c | 16 ++ board/aspeed/ast-g5/ast-g5.c | 3 + - 5 files changed, 254 insertions(+) + 5 files changed, 265 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-espi.c create mode 100644 board/aspeed/ast-g5/ast-g5-intel.c diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h -index b714fa9..10b983a 100644 +index c9b91795d1..019c00036a 100644 --- a/arch/arm/include/asm/arch-aspeed/regs-scu.h +++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h -@@ -552,6 +552,8 @@ +@@ -554,6 +554,8 @@ #define CLK_25M_IN (0x1 << 23) @@ -38,7 +37,7 @@ index b714fa9..10b983a 100644 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index df4e639..58e0c64 100644 +index df4e63966e..58e0c648f4 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -1,2 +1,4 @@ @@ -48,10 +47,10 @@ index df4e639..58e0c64 100644 obj-y += ast-g5-irq.o diff --git a/board/aspeed/ast-g5/ast-g5-espi.c b/board/aspeed/ast-g5/ast-g5-espi.c new file mode 100644 -index 0000000..79ef253 +index 0000000000..dda7ac7cd5 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-espi.c -@@ -0,0 +1,231 @@ +@@ -0,0 +1,242 @@ +/* + * Copyright 2018 Intel Corporation + * @@ -144,10 +143,12 @@ index 0000000..79ef253 +#define AST_ESPI_OOB_CHRDY (1 << 4) +#define AST_ESPI_FLASH_SW_CHRDY (0x1 << 7) +#define AST_ESPI_FLASH_SW_READ (0x1 << 10) ++#define ASPEED_ESPI_CTRL_SW_RESET GENMASK(31, 24) + +/* ESPI00C bits (Interrupt Enable) */ +#define AST_ESPI_IEN_SYS_EV (1 << 8) +#define AST_ESPI_IEN_GPIO_EV (1 << 9) ++#define AST_ESPI_IEN_HW_RST (1 << 31) + +/* ESPI008 bits ISR */ +#define AST_ESPI_VW_SYS_EVT (1 << 8) @@ -169,12 +170,38 @@ index 0000000..79ef253 +#define SCR0SIO 0x170 +#define IRQ_SRC_ESPI 23 /* IRQ 23 */ + ++static void espi_handshake_ack(void) ++{ ++ // IRQ only serviced if strapped, so no strap check ++ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { ++ DBG_ESPI("Setting espi slave boot done\n"); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) ++ | AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ } ++ ++ if (readl(AST_ESPI_BASE + ESPI104) & AST_ESPI_SUS_WARN) { ++ DBG_ESPI("Boot SUS WARN set %08x\n", ++ readl(AST_ESPI_BASE + ESPI104)); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; ++ writel(v, AST_ESPI_BASE + ESPI104); ++ } ++} ++ +static int espi_irq_handler(struct pt_regs *regs) +{ + uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008); + + DBG_ESPI("ISR irq_status : 0x%08X\n", irq_status); + ++ ++ if (irq_status & AST_ESPI_IEN_HW_RST) { ++ uint32_t v = readl(AST_ESPI_BASE + ESPI000); ++ writel(v & ~ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000); ++ writel(v | ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000); ++ espi_handshake_ack(); ++ } ++ + if (irq_status & AST_ESPI_VW_SYS_EVT) { + uint32_t sys_status = readl(AST_ESPI_BASE + ESPI11C); + uint32_t sys_event = readl(AST_ESPI_BASE + ESPI098); @@ -214,28 +241,11 @@ index 0000000..79ef253 + } + writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status + } ++ + writel(irq_status, AST_ESPI_BASE + ESPI008); // clear irq_status + return 0; +} + -+static void espi_handshake_ack(void) -+{ -+ // IRQ only serviced if strapped, so no strap check -+ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { -+ DBG_ESPI("Setting espi slave boot done\n"); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } -+ -+ if (readl(AST_ESPI_BASE + ESPI104) & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("Boot SUS WARN set %08x\n", -+ readl(AST_ESPI_BASE + ESPI104)); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; -+ writel(v, AST_ESPI_BASE + ESPI104); -+ } -+} -+ +void espi_init(void) +{ + if (readl(AST_SCU_BASE + AST_SCU_HW_STRAP1) @@ -273,8 +283,8 @@ index 0000000..79ef253 + AST_ESPI_BASE + + ESPI100); // Enable sysev1 ints for susp warn + -+ writel(AST_ESPI_IEN_SYS_EV, -+ AST_ESPI_BASE + ESPI00C); // Enable only sys events ++ writel(AST_ESPI_IEN_SYS_EV | AST_ESPI_IEN_HW_RST, ++ AST_ESPI_BASE + ESPI00C); // Enable events + + espi_handshake_ack(); + @@ -285,7 +295,7 @@ index 0000000..79ef253 +} diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c new file mode 100644 -index 0000000..e79235c +index 0000000000..e79235c8d0 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -0,0 +1,16 @@ @@ -306,10 +316,10 @@ index 0000000..e79235c + espi_init(); +} diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index 2472aa3..d41ef9c 100644 +index ca25348178..cab5fabcef 100644 --- a/board/aspeed/ast-g5/ast-g5.c +++ b/board/aspeed/ast-g5/ast-g5.c -@@ -18,6 +18,8 @@ +@@ -21,6 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; @@ -318,7 +328,7 @@ index 2472aa3..d41ef9c 100644 int board_early_init_f(void) { /* make sure uart5 is using 24MHz clock */ -@@ -34,6 +36,7 @@ int board_init(void) +@@ -84,6 +86,7 @@ int board_init(void) gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gd->flags = 0; @@ -326,3 +336,6 @@ index 2472aa3..d41ef9c 100644 return 0; } +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch new file mode 100644 index 000000000..e309f6a98 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch @@ -0,0 +1,41 @@ +From 899934a036171eb9174e800ba6367b8b8a3e70c4 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Wed, 29 Jan 2020 14:55:44 -0800 +Subject: [PATCH] Override OTP strap settings + +This commit adds settings to override OTP strap. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/mach-aspeed/ast2600/platform.S | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S +index de97cccc78b7..ab8d10b70b9a 100644 +--- a/arch/arm/mach-aspeed/ast2600/platform.S ++++ b/arch/arm/mach-aspeed/ast2600/platform.S +@@ -40,6 +40,7 @@ + #define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) + #define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) + #define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) ++#define AST_SCU_HW_STRAP2 (AST_SCU_BASE + 0x510) + #define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) + #define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) + +@@ -133,6 +134,13 @@ do_primary_core_setup: + /* unlock system control unit */ + scu_unlock + ++ /* enable eSPI and ACPI */ ++ ldr r0, =AST_SCU_HW_STRAP2 ++ ldr r1, [r0] ++ bic r1, #0x40 @; Select eSPI ++ orr r1, #0x20 @; Enable ACPI ++ str r1, [r0] ++ + /* tune-up CPU clock for AST2600 A0 */ + ldr r0, =AST_SCU_REV_ID + ldr r0, [r0] +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch index f7dd80504..e11f15870 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch @@ -1,7 +1,7 @@ -From 0fbd5fe6fa08f709b64bdbad6440ea77b422fc4b Mon Sep 17 00:00:00 2001 +From 15d04184a94aca6db889d77c2cc5a800b280da4b Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@linux.intel.com> Date: Fri, 16 Nov 2018 09:58:01 -0800 -Subject: [PATCH] Add basic GPIO support +Subject: [PATCH 01/30] Add basic GPIO support Add a table of well-known gpios (such as FP LEDs and FF UPD jumper) and initialize them at boot. @@ -11,18 +11,19 @@ Add a mechanism to get/set well known gpios from command line. Change-Id: I4136a5ccb048b3604f13b17ea0c18a4bc596c249 Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com> +%% original patch: 0009-Add-basic-GPIO-support.patch --- board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-gpio.c | 195 +++++++++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-gpio.h | 102 +++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-intel.c | 42 ++++++++ + board/aspeed/ast-g5/ast-g5-gpio.c | 202 +++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-gpio.h | 103 +++++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 45 +++++++ board/aspeed/ast-g5/ast-g5.h | 1 + - 5 files changed, 341 insertions(+) + 5 files changed, 352 insertions(+) create mode 100644 board/aspeed/ast-g5/ast-g5-gpio.c create mode 100644 board/aspeed/ast-g5/ast-g5-gpio.h diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 58e0c64..2970ae5 100644 +index 58e0c648f4..2970ae5741 100644 --- a/board/aspeed/ast-g5/Makefile +++ b/board/aspeed/ast-g5/Makefile @@ -2,3 +2,4 @@ obj-y += ast-g5.o @@ -32,10 +33,10 @@ index 58e0c64..2970ae5 100644 +obj-y += ast-g5-gpio.o diff --git a/board/aspeed/ast-g5/ast-g5-gpio.c b/board/aspeed/ast-g5/ast-g5-gpio.c new file mode 100644 -index 0000000..d596c15 +index 0000000000..dc6962f4ba --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-gpio.c -@@ -0,0 +1,195 @@ +@@ -0,0 +1,202 @@ +/* + * Copyright 2018 Intel Corporation + * @@ -104,13 +105,13 @@ index 0000000..d596c15 + return; + } + port = GPIO_PORT(gpio_table[n].u8PortPin); -+ assert = GPIO_PORT(gpio_table[n].u8Value); ++ assert = GPIO_ASSERT(gpio_table[n].u8PinCFG); + pin = GPIO_PIN(gpio_table[n].u8PortPin); + base = GPIO_BASES[GPIO_GROUP(port)].u32ddr; + shift = GPIO_SHIFT(port, pin); + + gpio_value = readl(base + GPIO_DATA_VALUE); -+ if ((assert &&asserted) || !(assert || asserted)) { ++ if ((assert && asserted) || !(assert || asserted)) { + // set the bit + gpio_value |= (1 << shift); + } else { @@ -133,7 +134,7 @@ index 0000000..d596c15 + return -1; + } + port = GPIO_PORT(gpio_table[n].u8PortPin); -+ assert = GPIO_PORT(gpio_table[n].u8Value); ++ assert = GPIO_ASSERT(gpio_table[n].u8PinCFG); + pin = GPIO_PIN(gpio_table[n].u8PortPin); + base = GPIO_BASES[GPIO_GROUP(port)].u32ddr; + shift = GPIO_SHIFT(port, pin); @@ -141,6 +142,9 @@ index 0000000..d596c15 + gpio_value = readl(base + GPIO_DATA_VALUE); + gpio_value >>= shift; + gpio_value &= 1; ++ // the output here is the logical output, which is ++ // NOT (value XOR assert) ++ // This just gets there without a conditional + gpio_value ^= assert; + return !gpio_value; +} @@ -166,6 +170,8 @@ index 0000000..d596c15 + uint8_t pin; + uint32_t base; + uint8_t shift; ++ uint8_t assert; ++ uint8_t init_val; + + port = GPIO_PORT(gpio_table[i].u8PortPin); + pin = GPIO_PIN(gpio_table[i].u8PortPin); @@ -182,7 +188,9 @@ index 0000000..d596c15 + + /* set data value */ + value = readl(base + GPIO_DATA_VALUE); -+ if (gpio_table[i].u8Value) ++ assert = GPIO_ASSERT(gpio_table[i].u8PinCFG); ++ init_val = gpio_table[i].u8Value; ++ if ((assert && init_val) || !(assert || init_val)) + value |= (1 << shift); + else + value &= ~(1 << shift); @@ -211,7 +219,7 @@ index 0000000..d596c15 + if (argc < 3) { + return 1; + } -+ n = simple_strtoul(argv[2], NULL, 16); ++ n = simple_strtoul(argv[2], NULL, 0); + if (argv[1][0] == 'g') { + printf("%d\n", gpio_get_value(n)); + return 0; @@ -221,7 +229,7 @@ index 0000000..d596c15 + } + if (argv[1][0] == 's') { + int value; -+ value = simple_strtoul(argv[3], NULL, 16); ++ value = simple_strtoul(argv[3], NULL, 0); + gpio_set_value(n, value); + return 0; + } @@ -233,10 +241,10 @@ index 0000000..d596c15 + ""); diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h new file mode 100644 -index 0000000..a820c0f +index 0000000000..54b7388a22 --- /dev/null +++ b/board/aspeed/ast-g5/ast-g5-gpio.h -@@ -0,0 +1,102 @@ +@@ -0,0 +1,103 @@ +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + @@ -305,6 +313,7 @@ index 0000000..a820c0f +#define GPIO_PORT(N) (N >> 3) +#define GPIO_SHIFT(PORT, PIN) ((PIN) + (((PORT) % 4) * 8)) +#define GPIO_GROUP(PORT) ((PORT) / 4) ++#define GPIO_ASSERT(N) (((N) >> 4) & 0x01) + +#define ID_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_6) +#define GRN_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_4) @@ -340,10 +349,10 @@ index 0000000..a820c0f + +#endif /* __HW_GPIO_H__ */ diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index c2a8b33..069e7a3 100644 +index c2a8b33aec..1868c230eb 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -14,6 +14,47 @@ +@@ -14,6 +14,50 @@ #include <asm/arch/aspeed.h> #include "ast-g5.h" @@ -361,8 +370,11 @@ index c2a8b33..069e7a3 100644 +#define GPIO_CFG_DEFAULT (GPCFG_ACTIVE_HIGH | GPCFG_LEVEL_TRIG) +// Active High, Level, Output Disabled + ++#define GPIO_CFG_LOW_INPUT (GPCFG_LEVEL_TRIG) ++// Active Low, Level, Output Disabled ++ +#define GPIO_CFG_FP_LED (GPCFG_OUTPUT_EN) -+// Active High, Pull-up, Level, Output Disabled ++// Active High, Pull-up, Level, Output Enabled + +// Format is: +// GPIO PORT, GPIO PIN Number, GPIO PIN Configuration, GPIO PIN Value, GPIO @@ -381,7 +393,7 @@ index c2a8b33..069e7a3 100644 + GPIO_DEBOUNCE_NONE}, + + /* Force Update Jumper -- pin D0 */ -+ [GPIO_FF_UPD_JUMPER] = {FORCE_BMC_UPDATE_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ [GPIO_FF_UPD_JUMPER] = {FORCE_BMC_UPDATE_PORT_PIN, GPIO_CFG_LOW_INPUT, 0, + GPIO_DEBOUNCE_8MS}, + + /* Enable Pulse -- pin D6 */ @@ -391,7 +403,7 @@ index c2a8b33..069e7a3 100644 #define LPC_SNOOP_ADDR 0x80 #define HICR5 0x080 /* Host Interface Control Register 5 */ -@@ -107,6 +148,7 @@ static void sgpio_init(void) +@@ -107,6 +151,7 @@ static void sgpio_init(void) extern void espi_init(void); void ast_g5_intel(void) { @@ -400,7 +412,7 @@ index c2a8b33..069e7a3 100644 sgpio_init(); } diff --git a/board/aspeed/ast-g5/ast-g5.h b/board/aspeed/ast-g5/ast-g5.h -index 9fd10ec..908db14 100644 +index 9fd10eccb3..908db1477b 100644 --- a/board/aspeed/ast-g5/ast-g5.h +++ b/board/aspeed/ast-g5/ast-g5.h @@ -3,5 +3,6 @@ @@ -410,3 +422,6 @@ index 9fd10ec..908db14 100644 +#include "ast-g5-gpio.h" #endif /* _AST_G5_H_ */ +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch index 2d63314af..065f890bc 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch @@ -1,7 +1,7 @@ -From 4c87d6074fb36d423f135392983d225785abf43a Mon Sep 17 00:00:00 2001 +From b6f898ef15eede75700e9e13a8e0b69d88b12fd4 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Thu, 20 Jun 2019 18:11:43 +0530 -Subject: [PATCH] Manufacturing mode physical presence detection +Subject: [PATCH 15/30] Manufacturing mode physical presence detection Support for physical presence of manufacturing mode added. Front panel power button press for 15 seconds will be detected @@ -23,16 +23,17 @@ Change-Id: Id7e7c7e7860c7ef3ae8e3a7a7cfda7ff506c0f2b Signed-off-by: Richard Marian Thomaiyar <richard.marian.thomaiyar@linux.intel.com> Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> +%% original patch: 0025-Manufacturing-mode-physical-presence-detection.patch --- board/aspeed/ast-g5/ast-g5-gpio.h | 2 +- - board/aspeed/ast-g5/ast-g5-intel.c | 35 +++++++++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 35 ++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h -index a820c0f..ed2499f 100644 +index 54b7388a22..8ccf437346 100644 --- a/board/aspeed/ast-g5/ast-g5-gpio.h +++ b/board/aspeed/ast-g5/ast-g5-gpio.h -@@ -72,7 +72,7 @@ +@@ -73,7 +73,7 @@ #define AMB_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_5) #define FORCE_BMC_UPDATE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_0) #define TPM_EN_PULSE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_6) @@ -42,7 +43,7 @@ index a820c0f..ed2499f 100644 // GPIO Configuration Register bits #define GPCFG_EVENT_TO_SMI (1 << 7) // 1 == enabled diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 55afa09..452cb5c 100644 +index 45ecd83fd3..efc3315caf 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -24,6 +24,7 @@ enum gpio_names { @@ -53,18 +54,18 @@ index 55afa09..452cb5c 100644 }; #define GPIO_CFG_DEFAULT (GPCFG_ACTIVE_HIGH | GPCFG_LEVEL_TRIG) -@@ -55,6 +56,10 @@ static const GPIOValue gpio_table[] = { +@@ -58,6 +59,10 @@ static const GPIOValue gpio_table[] = { /* Enable Pulse -- pin D6 */ [GPIO_ENABLE_TPM_PULSE] = {TPM_EN_PULSE_PORT_PIN, GPCFG_OUTPUT_EN, 0, GPIO_DEBOUNCE_NONE}, + /* Front Panel Power Button -- pin E2 */ -+ [GPIO_FP_PWR_BTN] = {FP_PWR_BTN_PORT_PIN, GPIO_CFG_DEFAULT, 0, ++ [GPIO_FP_PWR_BTN] = {FP_PWR_BTN_PORT_PIN, GPIO_CFG_LOW_INPUT, 0, + GPIO_DEBOUNCE_8MS}, + }; #define LPC_SNOOP_ADDR 0x80 -@@ -373,6 +378,30 @@ static void update_bootargs_cmd(const char *key, const char *value) +@@ -403,6 +408,30 @@ static void update_bootargs_cmd(const char *key, const char *value) free(buf); } @@ -95,7 +96,7 @@ index 55afa09..452cb5c 100644 void ast_g5_intel_late_init(void) { char value[32]; -@@ -420,6 +449,12 @@ void ast_g5_intel_late_init(void) +@@ -450,6 +479,12 @@ void ast_g5_intel_late_init(void) ast_scu_write(0, AST_SCU_SYS_CTRL); update_bootargs_cmd("resetreason", value); @@ -109,5 +110,5 @@ index 55afa09..452cb5c 100644 static void pwm_init(void) -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch index f91ab8fea..3c21a7c0a 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch @@ -1,4 +1,4 @@ -From 513ff559cd6fedd29412fb59b6f436f617620511 Mon Sep 17 00:00:00 2001 +From 0f64b0e0c0a122ce23b5ccc518f514ec296bc7f5 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Tue, 21 May 2019 00:53:04 +0530 Subject: [PATCH] FFUJ: FW IPMI commands and flash support in u-boot @@ -28,7 +28,6 @@ Tested: image transfer via KCS and flashing. Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> - --- arch/arm/include/asm/arch-aspeed/ast-g5-intel.h | 1 + board/aspeed/ast-g5/Makefile | 2 + @@ -38,9 +37,9 @@ Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> board/aspeed/ast-g5/ipmi-fwupd.h | 81 ++++ board/aspeed/ast-g5/ipmi-handler.c | 66 +++- board/aspeed/ast-g5/ipmi-handler.h | 3 +- - common/autoboot.c | 11 + + common/autoboot.c | 13 + configs/ast_g5_phy_defconfig | 1 + - 10 files changed, 1091 insertions(+), 12 deletions(-) + 10 files changed, 1093 insertions(+), 12 deletions(-) create mode 100644 board/aspeed/ast-g5/fw-update.c create mode 100644 board/aspeed/ast-g5/fw-update.h create mode 100644 board/aspeed/ast-g5/ipmi-fwupd.c @@ -1237,10 +1236,10 @@ index 9d46d9b..8eea930 100644 /* BMC IPMB LUNs */ diff --git a/common/autoboot.c b/common/autoboot.c -index d66c0fa..45a600e 100644 +index d66c0fa..3647d5f 100644 --- a/common/autoboot.c +++ b/common/autoboot.c -@@ -349,6 +349,17 @@ void autoboot_command(const char *s) +@@ -349,6 +349,19 @@ void autoboot_command(const char *s) { debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>"); @@ -1251,6 +1250,8 @@ index d66c0fa..45a600e 100644 + * This will make sure debug mode intact during FFUJ. + */ + if (intel_force_firmware_jumper_enabled()) { ++ printf("#### Force firmware update mode is enabled, " ++ "Serial console is disabled. ####\n"); + start_fw_update_loop(); + } +#endif @@ -1267,3 +1268,6 @@ index 1b96ab7..5965a9b 100644 CONFIG_CMD_I2C=y CONFIG_SYS_I2C_AST=y +CONFIG_LIB_RAND=y +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch index 193101370..85cf0cc5e 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch @@ -1,4 +1,4 @@ -From c15d982a36e34f3d3cc69efff7b56a5157be9a5c Mon Sep 17 00:00:00 2001 +From 3886bca377525ca9a70a6e04403606e456c535ad Mon Sep 17 00:00:00 2001 From: Vikram Bodireddy <vikram.bodireddy@intel.com> Date: Thu, 5 Sep 2019 15:03:21 +0530 Subject: [PATCH] PFR platform - EXTRST# reset mask selection @@ -11,7 +11,7 @@ update flow, during which certain modules of BMC should be chosen to be reset so that Host functionality would be intact. Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> - +--- .../include/asm/arch-aspeed/ast-g5-intel.h | 31 +++++++++++++++++++ arch/arm/include/asm/arch-aspeed/regs-scu.h | 29 +++++++++++++++++ board/aspeed/ast-g5/ast-g5-intel.c | 9 ++++++ @@ -60,7 +60,7 @@ index 64f4ed17bf..b9386b2cf6 100644 int intel_force_firmware_jumper_enabled(void); int intel_failed_boot(void); diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h -index 8333ba1c59..98895a47bf 100644 +index 1bdb1d8574..0a4fb6f773 100644 --- a/arch/arm/include/asm/arch-aspeed/regs-scu.h +++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h @@ -144,6 +144,35 @@ @@ -100,13 +100,13 @@ index 8333ba1c59..98895a47bf 100644 #define SCU_RESET_CRT3 (0x1 << 8) #define SCU_RESET_CRT2 (0x1 << 7) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 13889594bf..ce87a46cd1 100644 +index f8dbae8163..e697bd17e5 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -579,6 +579,15 @@ extern void espi_init(void); - extern void kcs_init(void); - void ast_g5_intel(void) +@@ -684,6 +684,15 @@ void ast_g5_intel(void) { + int platform_id; + + /* EXTRST# mask for PFR platform + * EXTRST# is used by PFR CPLD to keep BMC in + * reset during firmware authentication, updates and recovery diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0039-AST2500-increase-boot-speed.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0039-AST2500-increase-boot-speed.patch deleted file mode 100644 index d8ac50dbd..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0039-AST2500-increase-boot-speed.patch +++ /dev/null @@ -1,50 +0,0 @@ -From b571713f51beb467eefae8e56bfea6e5eab48f8c Mon Sep 17 00:00:00 2001 -From: James Feist <james.feist@linux.intel.com> -Date: Tue, 10 Dec 2019 16:21:24 -0800 -Subject: [PATCH 1/1] AST2500 increase boot speed - -Enable CONFIG_FLASH_SPIx2_Dummy and add it to known -good SPI flashes. - -Signed-off-by: James Feist <james.feist@linux.intel.com> ---- - arch/arm/mach-aspeed/flash.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c -index d33fb9e0fe..95fc46dd76 100644 ---- a/arch/arm/mach-aspeed/flash.c -+++ b/arch/arm/mach-aspeed/flash.c -@@ -34,6 +34,7 @@ - #include <asm/arch/ast_scu.h> - #include <asm/arch/aspeed.h> - -+#define CONFIG_FLASH_SPIx2_Dummy 1 - - /* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. -@@ -730,7 +731,7 @@ static ulong flash_get_size (ulong base, flash_info_t *info) - ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ; - info->flash_id = ulID; - --// printf("SPI Flash ID: %x \n", ulID); -+ printf("SPI Flash ID: %x \n", ulID); - - /* init default */ - info->iomode = IOMODEx1; -@@ -1035,6 +1036,12 @@ static ulong flash_get_size (ulong base, flash_info_t *info) - EraseClk = 25; - ReadClk = 50; - info->address32 = 1; -+#if defined(CONFIG_FLASH_SPIx2_Dummy) -+ info->readcmd = 0xbb; -+ info->dummybyte = 1; -+ info->dualport = 1; -+ info->iomode = IOMODEx2_dummy; -+#endif - break; - - case SST25VF016B: --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch new file mode 100644 index 000000000..b36627d17 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch @@ -0,0 +1,65 @@ +From 933d80ac82dbe1f74c653b0ac505fde406e2553c Mon Sep 17 00:00:00 2001 +From: Vernon Mauery <vernon.mauery@intel.com> +Date: Mon, 27 Jan 2020 15:13:10 -0800 +Subject: [PATCH] Initialize the BMC/host mailbox at reset time + +When the BMC comes out of reset, the mailbox registers need to be set so +the communications with the host can start properly. + +Tested: boot the BMC and take note that the mailbox registers are no + longer random garbage. + +Signed-off-by: Vernon Mauery <vernon.mauery@intel.com> +--- + board/aspeed/ast-g5/ast-g5-intel.c | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index ce87a46cd1..1086742045 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -575,6 +575,33 @@ static void pwm_init(void) + writel(val, PWM_BASE_ADDR + PWM_CONTROL); + } + ++#define AST_MBX_COUNT 16 ++#define MB_HINIT_BP_REG1 (0) ++#define MB_HINIT_BP_REG2 (1) // reserved for future bit definition. ++#define MB_FW_MJ_VER_REG (2) ++#define MB_FW_MN_VER_REG (3) ++#define MB_HINIT_ERR_REG (4) ++#define MB_BOOTL_BP_REG1 (5) ++#define MB_BOOTL_BP_REG2 (6) // tracks which image selected ++#define MB_BOOTL_ERR_REG (7) ++#define MB_RUNTM_BP_REG1 (8) ++#define MB_RUNTM_BP_REG2 (9) // reserved for future bit definition. ++#define MB_RUNTM_ERR_REG (10) ++static void mailbox_init(void) ++{ ++ /* clear out default mbox values */ ++ int i; ++ for (i = 0; i < AST_MBX_COUNT; i++) ++ { ++ writel(0, AST_MBX_BASE + 4 * i); ++ } ++ /* by the time this is called, all the hardware init is done ++ * so we can mark that as complete */ ++ writel(0xff, AST_MBX_BASE + 4 * MB_HINIT_BP_REG1); ++ /* mark progress up through booting linux */ ++ writel(0x1f, AST_MBX_BASE + 4 * MB_BOOTL_BP_REG1); ++} ++ + extern void espi_init(void); + extern void kcs_init(void); + void ast_g5_intel(void) +@@ -597,6 +624,7 @@ void ast_g5_intel(void) + set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, PFR_CPLD_CHKPOINT_START); + + uart_init(); ++ mailbox_init(); + pwm_init(); + gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); + espi_init(); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0041-Disabling-boot-delay.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0041-Disabling-boot-delay.patch new file mode 100644 index 000000000..69ec33a17 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0041-Disabling-boot-delay.patch @@ -0,0 +1,27 @@ +From e21ee4b456addc93a9afed0cb52ac2a53d3b785a Mon Sep 17 00:00:00 2001 +From: arun-pm <arun.p.m@linux.intel.com> +Date: Thu, 30 Jan 2020 10:32:13 +0530 +Subject: [PATCH] Disabling boot delay + +Boot delay is changed to -2 so that BMC will not stop in u-boot by pressing +ESC key. +--- + include/configs/ast-common.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h +index 0bc7f2d75f..dce6bbf5aa 100644 +--- a/include/configs/ast-common.h ++++ b/include/configs/ast-common.h +@@ -70,7 +70,7 @@ + /* + * Environment Config + */ +-#define CONFIG_BOOTDELAY 2 ++#define CONFIG_BOOTDELAY -2 + + /* + * Miscellaneous configurable options +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend index b5ea27dae..bc5d2f415 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend @@ -10,6 +10,9 @@ SRC_URI_append_intel-ast2600 = " \ file://0021-AST2600-Enable-host-searial-port-clock-configuration.patch \ file://0003-ast2600-intel-layout-environment-addr.patch \ file://0004-Disable-crashdump-trigger-gpio.patch \ + file://0005-Ast2600-Enable-interrupt-in-u-boot.patch \ + file://0006-SPI-Quad-IO-Mode.patch \ + file://0007-ast2600-Override-OTP-strap-settings.patch \ " do_install_append () { install -m 0644 ${WORKDIR}/fw_env.config ${S}/tools/env/fw_env.config diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend index 8e35c468b..170e84846 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend @@ -39,14 +39,18 @@ SRC_URI_append_intel-ast2500 = " \ file://0036-Re-Enable-KCS.patch \ file://0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch \ file://0038-Increase-default-fan-speed-for-cooper-city.patch \ - file://0039-AST2500-increase-boot-speed.patch \ + file://0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch \ " PFR_SRC_URI = " \ file://0022-u-boot-env-change-for-PFR-image.patch \ file://0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch \ file://0035-PFR-platform-EXTRST-reset-mask-selection.patch \ " +AUTOBOOT_SRC_URI = " \ + file://0041-Disabling-boot-delay.patch \ + " SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" +SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'debug-tweaks', '', AUTOBOOT_SRC_URI, d)}" do_install_append () { install -m 0644 ${WORKDIR}/fw_env.config ${S}/tools/env/fw_env.config } |