diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0039-Add-Aspeed-PWM-driver-which-uses-FTTMR010-timer-IP.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0039-Add-Aspeed-PWM-driver-which-uses-FTTMR010-timer-IP.patch | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0039-Add-Aspeed-PWM-driver-which-uses-FTTMR010-timer-IP.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0039-Add-Aspeed-PWM-driver-which-uses-FTTMR010-timer-IP.patch index 3e8f86666..c115d23d0 100644 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0039-Add-Aspeed-PWM-driver-which-uses-FTTMR010-timer-IP.patch +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0039-Add-Aspeed-PWM-driver-which-uses-FTTMR010-timer-IP.patch @@ -1,4 +1,4 @@ -From ef2e1d9d2e8c97daf806f4da74738a84de054116 Mon Sep 17 00:00:00 2001 +From 7ac4709dd92c608ca4c8ff0046a434c8f465a80c Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Mon, 11 Feb 2019 17:02:35 -0800 Subject: [PATCH] Add Aspeed PWM driver which uses FTTMR010 timer IP @@ -13,15 +13,15 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> arch/arm/boot/dts/aspeed-g5.dtsi | 2 +- drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + - drivers/pwm/pwm-fttmr010.c | 437 +++++++++++++++++++++++++++++++++++++++ - 4 files changed, 448 insertions(+), 1 deletion(-) + drivers/pwm/pwm-fttmr010.c | 441 +++++++++++++++++++++++++++++++++++++++ + 4 files changed, 452 insertions(+), 1 deletion(-) create mode 100644 drivers/pwm/pwm-fttmr010.c diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi -index 8a7c4257b917..c24197232385 100644 +index b8c85fad2a39..88ac8e08b6ae 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi -@@ -300,7 +300,7 @@ +@@ -312,7 +312,7 @@ timer: timer@1e782000 { /* This timer is a Faraday FTTMR010 derivative */ @@ -31,10 +31,10 @@ index 8a7c4257b917..c24197232385 100644 interrupts = <16 17 18 35 36 37 38 39>; clocks = <&syscon ASPEED_CLK_APB>; diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig -index a8f47df0655a..92a8fbebe2d9 100644 +index dff5a93f7daa..5759439a3947 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig -@@ -170,6 +170,15 @@ config PWM_FSL_FTM +@@ -171,6 +171,15 @@ config PWM_FSL_FTM To compile this driver as a module, choose M here: the module will be called pwm-fsl-ftm. @@ -51,7 +51,7 @@ index a8f47df0655a..92a8fbebe2d9 100644 tristate "HiSilicon BVT PWM support" depends on ARCH_HISI || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile -index 9c676a0dadf5..13b7b20ad5ab 100644 +index c368599d36c0..937d212bb02a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CRC) += pwm-crc.o @@ -61,13 +61,13 @@ index 9c676a0dadf5..13b7b20ad5ab 100644 +obj-$(CONFIG_PWM_FTTMR010) += pwm-fttmr010.o obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o obj-$(CONFIG_PWM_IMG) += pwm-img.o - obj-$(CONFIG_PWM_IMX) += pwm-imx.o + obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o diff --git a/drivers/pwm/pwm-fttmr010.c b/drivers/pwm/pwm-fttmr010.c new file mode 100644 -index 000000000000..32e508c962dc +index 000000000000..4c929a25e27c --- /dev/null +++ b/drivers/pwm/pwm-fttmr010.c -@@ -0,0 +1,437 @@ +@@ -0,0 +1,441 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Intel Corporation + @@ -192,7 +192,6 @@ index 000000000000..32e508c962dc +static int pwm_fttmr010_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pwm_fttmr010 *priv = to_pwm_fttmr010(chip); -+ ulong flags; + u32 cr; + + cr = readl(priv->base + TIMER_CR); @@ -210,6 +209,8 @@ index 000000000000..32e508c962dc + case 8: + cr |= (TIMER_8_CR_ASPEED_ENABLE | TIMER_8_CR_ASPEED_PULSE_OUT); + break; ++ default: ++ return -ERANGE; + } + + writel(cr, priv->base + TIMER_CR); @@ -221,7 +222,6 @@ index 000000000000..32e508c962dc +static void pwm_fttmr010_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct pwm_fttmr010 *priv = to_pwm_fttmr010(chip); -+ ulong flags; + u32 cr; + + cr = readl(priv->base + TIMER_CR); @@ -239,6 +239,8 @@ index 000000000000..32e508c962dc + case 8: + cr &= ~(TIMER_8_CR_ASPEED_ENABLE | TIMER_8_CR_ASPEED_PULSE_OUT); + break; ++ default: ++ return; + } + + writel(cr, priv->base + TIMER_CR); @@ -309,6 +311,8 @@ index 000000000000..32e508c962dc + lreg_offset = TIMER8_ASPEED_LOAD; + mreg_offset = TIMER8_ASPEED_MATCH1; + break; ++ default: ++ return -ERANGE; + } + + writel(tload, priv->base + creg_offset); |