diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0074-media-aspeed-refine-HSYNC-VSYNC-polarity-setting-log.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0074-media-aspeed-refine-HSYNC-VSYNC-polarity-setting-log.patch | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0074-media-aspeed-refine-HSYNC-VSYNC-polarity-setting-log.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0074-media-aspeed-refine-HSYNC-VSYNC-polarity-setting-log.patch new file mode 100644 index 000000000..4118e366c --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0074-media-aspeed-refine-HSYNC-VSYNC-polarity-setting-log.patch @@ -0,0 +1,93 @@ +From 1032b062669b7ee041d2f5a9f4729953655efe61 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Wed, 4 Sep 2019 14:52:40 -0700 +Subject: [PATCH] media: aspeed: refine HSYNC/VSYNC polarity setting logic + +Sometimes it detects weird resolutions such as 1024x287 when the +actual resolution is 1280x768. To resolve this issue, this commit +refines HSYNC/VSYNC polarity setting code for mode detection by +clearing the bits as normal polarity at the beginning of the first +mode detection like datasheet suggested, and refines polarity +setting logic so that the bits can be set or cleared properly. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + drivers/media/platform/aspeed-video.c | 45 ++++++++++++++++++----------------- + 1 file changed, 23 insertions(+), 22 deletions(-) + +diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c +index 4ef37cfc8446..455c6af81236 100644 +--- a/drivers/media/platform/aspeed-video.c ++++ b/drivers/media/platform/aspeed-video.c +@@ -614,7 +614,7 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video) + int i; + int hsync_counter = 0; + int vsync_counter = 0; +- u32 sts; ++ u32 sts, ctrl; + + for (i = 0; i < NUM_POLARITY_CHECKS; ++i) { + sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS); +@@ -629,30 +629,29 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video) + hsync_counter++; + } + +- if (hsync_counter < 0 || vsync_counter < 0) { +- u32 ctrl = 0; ++ ctrl = aspeed_video_read(video, VE_CTRL); + +- if (hsync_counter < 0) { +- ctrl = VE_CTRL_HSYNC_POL; +- video->detected_timings.polarities &= +- ~V4L2_DV_HSYNC_POS_POL; +- } else { +- video->detected_timings.polarities |= +- V4L2_DV_HSYNC_POS_POL; +- } +- +- if (vsync_counter < 0) { +- ctrl = VE_CTRL_VSYNC_POL; +- video->detected_timings.polarities &= +- ~V4L2_DV_VSYNC_POS_POL; +- } else { +- video->detected_timings.polarities |= +- V4L2_DV_VSYNC_POS_POL; +- } ++ if (hsync_counter < 0) { ++ ctrl |= VE_CTRL_HSYNC_POL; ++ video->detected_timings.polarities &= ++ ~V4L2_DV_HSYNC_POS_POL; ++ } else { ++ ctrl &= ~VE_CTRL_HSYNC_POL; ++ video->detected_timings.polarities |= ++ V4L2_DV_HSYNC_POS_POL; ++ } + +- if (ctrl) +- aspeed_video_update(video, VE_CTRL, 0, ctrl); ++ if (vsync_counter < 0) { ++ ctrl |= VE_CTRL_VSYNC_POL; ++ video->detected_timings.polarities &= ++ ~V4L2_DV_VSYNC_POS_POL; ++ } else { ++ ctrl &= ~VE_CTRL_VSYNC_POL; ++ video->detected_timings.polarities |= ++ V4L2_DV_VSYNC_POS_POL; + } ++ ++ aspeed_video_write(video, VE_CTRL, ctrl); + } + + static bool aspeed_video_alloc_buf(struct aspeed_video *video, +@@ -741,6 +740,8 @@ static void aspeed_video_get_resolution(struct aspeed_video *video) + } + + set_bit(VIDEO_RES_DETECT, &video->flags); ++ aspeed_video_update(video, VE_CTRL, ++ VE_CTRL_VSYNC_POL | VE_CTRL_HSYNC_POL, 0); + aspeed_video_enable_mode_detect(video); + + rc = wait_event_interruptible_timeout(video->wait, +-- +2.7.4 + |