diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch')
| -rw-r--r-- | meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch | 129 |
1 files changed, 0 insertions, 129 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch deleted file mode 100644 index ef234fffe..000000000 --- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 9fc2343bac42db2432f96db1bbfc6979822a7154 Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> -Date: Thu, 26 Mar 2020 14:20:19 -0700 -Subject: [PATCH] Refine clock settings - -This commit refines clock settings with cherry picking the latest -code from Aspeed SDK v00.05.05 - -Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> ---- - drivers/clk/clk-ast2600.c | 60 +++++++++++++++++++++++++++++++++++++++++------ - 1 file changed, 53 insertions(+), 7 deletions(-) - -diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c -index fb6b11440b97..e07326544fdc 100644 ---- a/drivers/clk/clk-ast2600.c -+++ b/drivers/clk/clk-ast2600.c -@@ -31,6 +31,24 @@ - #define ASPEED_G6_CLK_SELECTION1 0x300 - #define ASPEED_G6_CLK_SELECTION2 0x304 - #define ASPEED_G6_CLK_SELECTION4 0x310 -+#define ASPEED_G6_CLK_SELECTION5 0x314 -+ -+#define ASPEED_G6_MAC12_CLK_CTRL0 0x340 -+#define ASPEED_G6_MAC12_CLK_CTRL1 0x348 -+#define ASPEED_G6_MAC12_CLK_CTRL2 0x34C -+ -+#define ASPEED_G6_MAC34_CLK_CTRL0 0x350 -+#define ASPEED_G6_MAC34_CLK_CTRL1 0x358 -+#define ASPEED_G6_MAC34_CLK_CTRL2 0x35C -+ -+#define ASPEED_G6_MAC34_DRIVING_CTRL 0x458 -+ -+#define ASPEED_G6_DEF_MAC12_DELAY_1G 0x0041b410 -+#define ASPEED_G6_DEF_MAC12_DELAY_100M 0x00417410 -+#define ASPEED_G6_DEF_MAC12_DELAY_10M 0x00417410 -+#define ASPEED_G6_DEF_MAC34_DELAY_1G 0x00104208 -+#define ASPEED_G6_DEF_MAC34_DELAY_100M 0x00104208 -+#define ASPEED_G6_DEF_MAC34_DELAY_10M 0x00104208 - - #define ASPEED_HPLL_PARAM 0x200 - #define ASPEED_APLL_PARAM 0x210 -@@ -40,9 +58,6 @@ - - #define ASPEED_G6_STRAP1 0x500 - --#define ASPEED_MAC12_CLK_DLY 0x340 --#define ASPEED_MAC34_CLK_DLY 0x350 -- - #define ASPEED_G6_GEN_UART_REF 0x338 - #define UART_192MHZ_R_N_VALUE 0x3c38e - -@@ -515,7 +530,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) - - /* RMII1 50MHz (RCLK) output enable */ - hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, -- scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0, -+ scu_g6_base + ASPEED_G6_MAC12_CLK_CTRL0, 29, 0, - &aspeed_g6_clk_lock); - if (IS_ERR(hw)) - return PTR_ERR(hw); -@@ -523,7 +538,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) - - /* RMII2 50MHz (RCLK) output enable */ - hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, -- scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0, -+ scu_g6_base + ASPEED_G6_MAC12_CLK_CTRL0, 30, 0, - &aspeed_g6_clk_lock); - if (IS_ERR(hw)) - return PTR_ERR(hw); -@@ -545,7 +560,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) - - /* RMII3 50MHz (RCLK) output enable */ - hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0, -- scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0, -+ scu_g6_base + ASPEED_G6_MAC34_CLK_CTRL0, 29, 0, - &aspeed_g6_clk_lock); - if (IS_ERR(hw)) - return PTR_ERR(hw); -@@ -553,7 +568,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) - - /* RMII4 50MHz (RCLK) output enable */ - hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0, -- scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0, -+ scu_g6_base + ASPEED_G6_MAC34_CLK_CTRL0, 30, 0, - &aspeed_g6_clk_lock); - if (IS_ERR(hw)) - return PTR_ERR(hw); -@@ -770,6 +785,37 @@ static void __init aspeed_g6_cc_init(struct device_node *np) - return; - } - -+ /* fixed settings for RGMII/RMII clock generator */ -+ /* MAC1/2 RGMII 125MHz = EPLL / 8 */ -+ regmap_update_bits(map, ASPEED_G6_CLK_SELECTION2, GENMASK(23, 20), -+ (0x7 << 20)); -+ -+ /* MAC3/4 RMII 50MHz = HCLK / 4 */ -+ regmap_update_bits(map, ASPEED_G6_CLK_SELECTION4, GENMASK(18, 16), -+ (0x3 << 16)); -+ -+ /* -+ * BIT[31]: MAC1/2 RGMII 125M source = internal PLL -+ * BIT[28]: RGMIICK pad direction = output -+ */ -+ regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL0, -+ BIT(31) | BIT(28) | ASPEED_G6_DEF_MAC12_DELAY_1G); -+ regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL1, -+ ASPEED_G6_DEF_MAC12_DELAY_100M); -+ regmap_write(map, ASPEED_G6_MAC12_CLK_CTRL2, -+ ASPEED_G6_DEF_MAC12_DELAY_10M); -+ -+ /* MAC3/4 RGMII 125M source = RGMIICK pad */ -+ regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL0, -+ ASPEED_G6_DEF_MAC34_DELAY_1G); -+ regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL1, -+ ASPEED_G6_DEF_MAC34_DELAY_100M); -+ regmap_write(map, ASPEED_G6_MAC34_CLK_CTRL2, -+ ASPEED_G6_DEF_MAC34_DELAY_10M); -+ -+ /* MAC3/4 default pad driving strength */ -+ regmap_write(map, ASPEED_G6_MAC34_DRIVING_CTRL, 0x0000000a); -+ - aspeed_g6_cc(map); - aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data); --- -2.7.4 - |