diff options
Diffstat (limited to 'meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils')
46 files changed, 12678 insertions, 0 deletions
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch new file mode 100644 index 000000000..e0de79fd2 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch @@ -0,0 +1,65 @@ +From 247ead894f7079a4ededf2b48a65ffa6e78e2222 Mon Sep 17 00:00:00 2001 +From: David Holsgrove <david.holsgrove@xilinx.com> +Date: Wed, 8 May 2013 11:03:36 +1000 +Subject: [PATCH 01/43] Add wdc.ext.clear and wdc.ext.flush insns + +Added two new instructions, wdc.ext.clear and wdc.ext.flush, +to enable MicroBlaze to flush an external cache, which is +used with the new coherency support for multiprocessing. + +Signed-off-by:nagaraju <nmekala@xilix.com> +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + opcodes/microblaze-opc.h | 5 ++++- + opcodes/microblaze-opcm.h | 4 ++-- + 2 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 62ee3c9a4d..865151f95b 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -91,6 +91,7 @@ + #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ + #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ + #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ ++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ + + /* New Mask for msrset, msrclr insns. */ +@@ -101,7 +102,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 289 ++#define MAX_OPCODES 291 + + struct op_code_struct + { +@@ -174,7 +175,9 @@ struct op_code_struct + {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, + {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, + {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, ++ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }, + {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, ++ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst }, + {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, + {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, + {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 5a2d3b0c8b..42f3dd3be5 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -33,8 +33,8 @@ enum microblaze_instr + /* 'or/and/xor' are C++ keywords. */ + microblaze_or, microblaze_and, microblaze_xor, + andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, +- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd, +- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, ++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br, ++ brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, + bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch new file mode 100644 index 000000000..98e40c0ea --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch @@ -0,0 +1,64 @@ +From 7163824e07ade3ad2dc24e888265d27e0bc87869 Mon Sep 17 00:00:00 2001 +From: nagaraju <nmekala@xilix.com> +Date: Tue, 19 Mar 2013 17:18:23 +0530 +Subject: [PATCH 02/43] Add mlittle-endian and mbig-endian flags + +Added support in gas for mlittle-endian and mbig-endian flags +as options. + +Updated show usage for MicroBlaze specific assembler options +to include new entries. + +Signed-off-by:nagaraju <nmekala@xilix.com> +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + gas/config/tc-microblaze.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index ab90c6b20f..c92e9ce563 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -37,6 +37,8 @@ + + #define OPTION_EB (OPTION_MD_BASE + 0) + #define OPTION_EL (OPTION_MD_BASE + 1) ++#define OPTION_LITTLE (OPTION_MD_BASE + 2) ++#define OPTION_BIG (OPTION_MD_BASE + 3) + + void microblaze_generate_symbol (char *sym); + static bfd_boolean check_spl_reg (unsigned *); +@@ -1845,6 +1847,8 @@ struct option md_longopts[] = + { + {"EB", no_argument, NULL, OPTION_EB}, + {"EL", no_argument, NULL, OPTION_EL}, ++ {"mlittle-endian", no_argument, NULL, OPTION_LITTLE}, ++ {"mbig-endian", no_argument, NULL, OPTION_BIG}, + { NULL, no_argument, NULL, 0} + }; + +@@ -2498,9 +2502,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + switch (c) + { + case OPTION_EB: ++ case OPTION_BIG: + target_big_endian = 1; + break; + case OPTION_EL: ++ case OPTION_LITTLE: + target_big_endian = 0; + break; + default: +@@ -2515,6 +2521,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED) + /* fprintf(stream, _("\ + MicroBlaze options:\n\ + -noSmall Data in the comm and data sections do not go into the small data section\n")); */ ++ fprintf (stream, _(" MicroBlaze specific assembler options:\n")); ++ fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu")); ++ fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu")); + } + + +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch new file mode 100644 index 000000000..445f5dd87 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch @@ -0,0 +1,31 @@ +From 2b9eec7fdfae66c5500baef444559976d1b20e0b Mon Sep 17 00:00:00 2001 +From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> +Date: Fri, 22 Jun 2012 01:20:20 +0200 +Subject: [PATCH 03/43] Disable the warning message for eh_frame_hdr + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> +--- + bfd/elf-eh-frame.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c +index a13e81ebb8..1824ba6e5b 100644 +--- a/bfd/elf-eh-frame.c ++++ b/bfd/elf-eh-frame.c +@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info, + goto success; + + free_no_table: ++/* FIXME: Remove the microblaze specifics when relaxing gets fixed. */ ++if (bfd_get_arch(abfd) != bfd_arch_microblaze) { + _bfd_error_handler + /* xgettext:c-format */ + (_("error in %pB(%pA); no .eh_frame_hdr table will be created"), + abfd, sec); ++} + hdr_info->u.dwarf.table = FALSE; + if (sec_info) + free (sec_info); +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0004-Fix-relaxation-of-assembler-resolved-references.patch new file mode 100644 index 000000000..d1b754c37 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0004-Fix-relaxation-of-assembler-resolved-references.patch @@ -0,0 +1,74 @@ +From ababe1df64146c616455eb1af4cf8fd21eb6f42c Mon Sep 17 00:00:00 2001 +From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> +Date: Tue, 14 Feb 2012 01:00:22 +0100 +Subject: [PATCH 04/43] Fix relaxation of assembler resolved references + +--- + bfd/elf32-microblaze.c | 38 ++++++++++++++++++++++++++++++++++++++ + gas/config/tc-microblaze.c | 1 + + 2 files changed, 39 insertions(+) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index e3c8027248..359484dd5e 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -1973,6 +1973,44 @@ microblaze_elf_relax_section (bfd *abfd, + irelscanend = irelocs + o->reloc_count; + for (irelscan = irelocs; irelscan < irelscanend; irelscan++) + { ++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE) ++ { ++ unsigned int val; ++ ++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); ++ ++ /* This was a PC-relative instruction that was completely resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend ++ + isym->st_value, sec); ++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) { ++ fprintf(stderr, "Unhandled NONE 64\n"); ++ } + if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) + { + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index c92e9ce563..3e728400b7 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -2205,6 +2205,7 @@ md_apply_fix (fixS * fixP, + else + fixP->fx_r_type = BFD_RELOC_NONE; + fixP->fx_addsy = section_symbol (absolute_section); ++ fixP->fx_done = 0; + } + return; + } +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch new file mode 100644 index 000000000..ac13e6e39 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch @@ -0,0 +1,247 @@ +From e9837b5aec42b084c93868095b409f9a6a81b570 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 6 Feb 2017 15:53:08 +0530 +Subject: [PATCH 05/43] [LOCAL]: Fixup debug_loc sections after linker + relaxation Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing reloc + info from the assembler to the linker when the linker manages to fully + resolve a local symbol reference. + +This is a workaround for design flaws in the assembler to +linker interface with regards to linker relaxation. + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> +Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com> +--- + bfd/bfd-in2.h | 9 +++++-- + bfd/elf32-microblaze.c | 53 ++++++++++++++++++++++++++++---------- + bfd/libbfd.h | 1 + + bfd/reloc.c | 6 +++++ + binutils/readelf.c | 4 +++ + gas/config/tc-microblaze.c | 5 +++- + include/elf/microblaze.h | 2 ++ + 7 files changed, 64 insertions(+), 16 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index e25da50aaf..721531886a 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5866,10 +5866,15 @@ value relative to the read-write small data area anchor */ + expressions of the form "Symbol Op Symbol" */ + BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative ++/* This is a 32 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_NONE, ++ BFD_RELOC_MICROBLAZE_32_NONE, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imm instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 359484dd5e..1c69c269c7 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -176,7 +176,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + +- /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_32_NONE",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ + HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ + 0, /* Rightshift. */ + 3, /* Size (0 = byte, 1 = short, 2 = long). */ +@@ -562,6 +576,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_NONE: + microblaze_reloc = R_MICROBLAZE_NONE; + break; ++ case BFD_RELOC_MICROBLAZE_32_NONE: ++ microblaze_reloc = R_MICROBLAZE_32_NONE; ++ break; + case BFD_RELOC_MICROBLAZE_64_NONE: + microblaze_reloc = R_MICROBLAZE_64_NONE; + break; +@@ -1918,6 +1935,7 @@ microblaze_elf_relax_section (bfd *abfd, + } + break; + case R_MICROBLAZE_NONE: ++ case R_MICROBLAZE_32_NONE: + { + /* This was a PC-relative instruction that was + completely resolved. */ +@@ -1926,12 +1944,18 @@ microblaze_elf_relax_section (bfd *abfd, + target_address = irel->r_addend + irel->r_offset; + sfix = calc_fixup (irel->r_offset, 0, sec); + efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } + irel->r_addend -= (efix - sfix); + /* Should use HOWTO. */ + microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, + irel->r_addend); +- } +- break; ++ } ++ break; + case R_MICROBLAZE_64_NONE: + { + /* This was a PC-relative 64-bit instruction that was +@@ -1973,12 +1997,16 @@ microblaze_elf_relax_section (bfd *abfd, + irelscanend = irelocs + o->reloc_count; + for (irelscan = irelocs; irelscan < irelscanend; irelscan++) + { +- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE) ++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) + { + unsigned int val; + + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + ++ /* hax: We only do the following fixup for debug location lists. */ ++ if (strcmp(".debug_loc", o->name)) ++ continue; ++ + /* This was a PC-relative instruction that was completely resolved. */ + if (ocontents == NULL) + { +@@ -1999,18 +2027,17 @@ microblaze_elf_relax_section (bfd *abfd, + (file_ptr) 0, + o->rawsize)) + goto error_return; +- elf_section_data (o)->this_hdr.contents = ocontents; +- } +- } +- irelscan->r_addend -= calc_fixup (irelscan->r_addend +- + isym->st_value, sec); ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } + val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ if (val != irelscan->r_addend) { ++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); + microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, + irelscan->r_addend); + } +- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) { +- fprintf(stderr, "Unhandled NONE 64\n"); +- } + if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) + { + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); +@@ -2070,7 +2097,7 @@ microblaze_elf_relax_section (bfd *abfd, + elf_section_data (o)->this_hdr.contents = ocontents; + } + } +- irelscan->r_addend -= calc_fixup (irel->r_addend ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend + + isym->st_value, + 0, + sec); +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index 36284d71a9..feb9fada1e 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -2901,6 +2901,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_ROSDA", + "BFD_RELOC_MICROBLAZE_32_RWSDA", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", ++ "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", + "BFD_RELOC_MICROBLAZE_64_GOTPC", + "BFD_RELOC_MICROBLAZE_64_GOT", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index e6446a7809..87753ae4f0 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6795,6 +6795,12 @@ ENUM + ENUMDOC + This is a 32 bit reloc for the microblaze to handle + expressions of the form "Symbol Op Symbol" ++ENUM ++ BFD_RELOC_MICROBLAZE_32_NONE ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC +diff --git a/binutils/readelf.c b/binutils/readelf.c +index b13eb6a43b..da6252c128 100644 +--- a/binutils/readelf.c ++++ b/binutils/readelf.c +@@ -13019,6 +13019,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type) + || reloc_type == 32 /* R_AVR_DIFF32. */); + case EM_METAG: + return reloc_type == 3; /* R_METAG_NONE. */ ++ case EM_MICROBLAZE: ++ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */ ++ || reloc_type == 0 /* R_MICROBLAZE_NONE. */ ++ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */ + case EM_NDS32: + return (reloc_type == 0 /* R_XTENSA_NONE. */ + || reloc_type == 204 /* R_NDS32_DIFF8. */ +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 3e728400b7..fa665b4e25 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -2201,7 +2201,9 @@ md_apply_fix (fixS * fixP, + /* This fixup has been resolved. Create a reloc in case the linker + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) +- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; ++ else if (fixP->fx_r_type == BFD_RELOC_32) ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; + else + fixP->fx_r_type = BFD_RELOC_NONE; + fixP->fx_addsy = section_symbol (absolute_section); +@@ -2426,6 +2428,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + switch (fixp->fx_r_type) + { + case BFD_RELOC_NONE: ++ case BFD_RELOC_MICROBLAZE_32_NONE: + case BFD_RELOC_MICROBLAZE_64_NONE: + case BFD_RELOC_32: + case BFD_RELOC_MICROBLAZE_32_LO: +diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h +index 830b5ad446..6ee0966444 100644 +--- a/include/elf/microblaze.h ++++ b/include/elf/microblaze.h +@@ -61,6 +61,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type) + RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30) /* PC-relative TEXT offset. */ + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */ + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */ ++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33) ++ + END_RELOC_NUMBERS (R_MICROBLAZE_max) + + /* Global base address names. */ +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch new file mode 100644 index 000000000..97d692c7a --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch @@ -0,0 +1,39 @@ +From 403d6e82742452be4e3f3010c8d9989f0a490c0b Mon Sep 17 00:00:00 2001 +From: David Holsgrove <david.holsgrove@xilinx.com> +Date: Wed, 27 Feb 2013 13:56:11 +1000 +Subject: [PATCH 06/43] upstream change to garbage collection sweep causes mb + regression + +Upstream change for PR13177 now clears the def_regular during gc_sweep of a +section. (All other archs in binutils/bfd/elf32-*.c received an update +to a warning about unresolvable relocations - this warning is not present +in binutils/bfd/elf32-microblaze.c, but this warning check would not +prevent the error being seen) + +The visible issue with this change is when running a c++ application +in Petalinux which links libstdc++.so for exception handling it segfaults +on execution. + +This does not occur if static linking libstdc++.a, so its during the +relocations for a shared lib with garbage collection this occurs + +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + bfd/elflink.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/bfd/elflink.c b/bfd/elflink.c +index e50c0e4b38..09d43e3ca5 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -6187,7 +6187,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data) + + inf = (struct elf_gc_sweep_symbol_info *) data; + (*inf->hide_symbol) (inf->info, h, TRUE); +- h->def_regular = 0; + h->ref_regular = 0; + h->ref_regular_nonweak = 0; + } +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0007-Fix-bug-in-TLSTPREL-Relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0007-Fix-bug-in-TLSTPREL-Relocation.patch new file mode 100644 index 000000000..49534b4ec --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0007-Fix-bug-in-TLSTPREL-Relocation.patch @@ -0,0 +1,33 @@ +From 072a8968c50b2ebd93e225a6b959916f9d60b493 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 15 Jun 2015 16:50:30 +0530 +Subject: [PATCH 07/43] Fix bug in TLSTPREL Relocation + +Fixed the problem related to the fixup/relocations TLSTPREL. +When the fixup is applied the addend is not added at the correct offset +of the instruction. The offset is hard coded considering its big endian +and it fails for Little endian. This patch allows support for both +big & little-endian compilers +--- + bfd/elf32-microblaze.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 1c69c269c7..d19a6dca84 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -1451,9 +1451,9 @@ microblaze_elf_relocate_section (bfd *output_bfd, + relocation += addend; + relocation -= dtprel_base(info); + bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, +- contents + offset + 2); ++ contents + offset + endian); + bfd_put_16 (input_bfd, relocation & 0xffff, +- contents + offset + 2 + INST_WORD_SIZE); ++ contents + offset + endian + INST_WORD_SIZE); + break; + case (int) R_MICROBLAZE_TEXTREL_64: + case (int) R_MICROBLAZE_TEXTREL_32_LO: +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0008-Added-Address-extension-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0008-Added-Address-extension-instructions.patch new file mode 100644 index 000000000..51fcee905 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0008-Added-Address-extension-instructions.patch @@ -0,0 +1,98 @@ +From 4674056da6bafa8168c0a680498b958f3a39be94 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 18 Jan 2016 12:28:21 +0530 +Subject: [PATCH 08/43] Added Address extension instructions + +This patch adds the support of new instructions which are required +for supporting Address extension feature. + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + +ChangeLog: + 2016-01-18 Nagaraju Mekala <nmekala@xilix.com> + + *microblaze-opc.h (op_code_struct): Update + Added new instructions + *microblaze-opcm.h (microblaze_instr): Update + Added new instructions +--- + opcodes/microblaze-opc.h | 11 +++++++++++ + opcodes/microblaze-opcm.h | 10 +++++----- + 2 files changed, 16 insertions(+), 5 deletions(-) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 865151f95b..330f1040e7 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -178,8 +178,11 @@ struct op_code_struct + {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }, + {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, + {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst }, ++ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst }, + {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, ++ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst }, + {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, ++ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst }, + {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, + {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst }, + {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst }, +@@ -229,18 +232,24 @@ struct op_code_struct + {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst }, + {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst }, + {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst }, ++ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst }, + {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst }, + {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst }, ++ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst }, + {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst }, + {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst }, + {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst }, ++ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst }, + {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst }, + {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst }, ++ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst }, + {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst }, + {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst }, ++ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst }, + {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst }, + {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst }, + {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst }, ++ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst }, + {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst }, + {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst }, + {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst }, +@@ -405,6 +414,8 @@ struct op_code_struct + {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst }, + {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst }, + {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */ ++ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */ ++ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */ + {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst }, + {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, + {"", 0, 0, 0, 0, 0, 0, 0, 0}, +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 42f3dd3be5..1c39dbf50b 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -33,13 +33,13 @@ enum microblaze_instr + /* 'or/and/xor' are C++ keywords. */ + microblaze_or, microblaze_and, microblaze_xor, + andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, +- wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br, +- brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, +- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, ++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse, ++ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, ++ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, +- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, +- shr, sw, swr, swx, lbui, lhui, lwi, ++ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, ++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, + sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, + fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, + fint, fsqrt, +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0009-fixing-the-MAX_OPCODES-to-correct-value.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0009-fixing-the-MAX_OPCODES-to-correct-value.patch new file mode 100644 index 000000000..d93ccd205 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0009-fixing-the-MAX_OPCODES-to-correct-value.patch @@ -0,0 +1,25 @@ +From 7651a2f7ab486e26981cb5e032bf578d0951ff4a Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 28 Jan 2016 14:07:34 +0530 +Subject: [PATCH 09/43] fixing the MAX_OPCODES to correct value + +--- + opcodes/microblaze-opc.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 330f1040e7..2a6b841232 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -102,7 +102,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 291 ++#define MAX_OPCODES 299 + + struct op_code_struct + { +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0010-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0010-Add-new-bit-field-instructions.patch new file mode 100644 index 000000000..901c53e67 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0010-Add-new-bit-field-instructions.patch @@ -0,0 +1,230 @@ +From 7e9e123337f2d441b213ea9d0be07e9049241f64 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 18 Jul 2016 12:24:28 +0530 +Subject: [PATCH 10/43] Add new bit-field instructions + +This patches adds new bsefi and bsifi instructions. +BSEFI- The instruction shall extract a bit field from a +register and place it right-adjusted in the destination register. +The other bits in the destination register shall be set to zero +BSIFI- The instruction shall insert a right-adjusted bit field +from a register at another position in the destination register. +The rest of the bits in the destination register shall be unchanged + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> +--- + gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++- + opcodes/microblaze-dis.c | 16 +++++++++ + opcodes/microblaze-opc.h | 12 ++++++- + opcodes/microblaze-opcm.h | 6 +++- + 4 files changed, 102 insertions(+), 3 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index fa665b4e25..71bb888ab8 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -917,7 +917,7 @@ md_assemble (char * str) + unsigned reg2; + unsigned reg3; + unsigned isize; +- unsigned int immed, temp; ++ unsigned int immed, immed2, temp; + expressionS exp; + char name[20]; + +@@ -1172,7 +1172,76 @@ md_assemble (char * str) + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (immed << IMM_LOW) & IMM5_MASK; + break; ++ case INST_TYPE_RD_R1_IMM5_IMM5: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg2 = 0; ++ } ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (®1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ if (check_spl_reg (®2)) ++ as_fatal (_("Cannot use special register with this instruction")); + ++ /* Width immediate value. */ ++ if (strcmp (op_end, "")) ++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH); ++ else ++ as_fatal (_("Error in statement syntax")); ++ if (exp.X_op != O_constant) ++ { ++ as_warn (_("Symbol used as immediate width value for bit field instruction")); ++ immed = 1; ++ } ++ else ++ immed = exp.X_add_number; ++ if (opcode->instr == bsefi && immed > 31) ++ as_fatal (_("Width value must be less than 32")); ++ ++ /* Shift immediate value. */ ++ if (strcmp (op_end, "")) ++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM); ++ else ++ as_fatal (_("Error in statement syntax")); ++ if (exp.X_op != O_constant) ++ { ++ as_warn (_("Symbol used as immediate shift value for bit field instruction")); ++ immed2 = 0; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immed2 = exp.X_add_number; ++ } ++ if (immed2 != (immed2 % 32)) ++ { ++ as_warn (_("Shift value greater than 32. using <value %% 32>")); ++ immed2 = immed2 % 32; ++ } ++ ++ /* Check combined value. */ ++ if (immed + immed2 > 32) ++ as_fatal (_("Width value + shift value must not be greater than 32")); ++ ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ if (opcode->instr == bsefi) ++ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */ ++ else ++ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */ ++ inst |= (immed2 << IMM_LOW) & IMM5_MASK; ++ break; + case INST_TYPE_R1_R2: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index f691740dfd..f8aaf27873 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr) + return(strdup(tmpstr)); + } + ++static char * ++get_field_imm5width (long instr) ++{ ++ char tmpstr[25]; ++ ++ if (instr & 0x00004000) ++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ ++ else ++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */ ++ return (strdup (tmpstr)); ++} ++ + static char * + get_field_rfsl (long instr) + { +@@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + /* For mbar 16 or sleep insn. */ + case INST_TYPE_NONE: + break; ++ /* For bit field insns. */ ++ case INST_TYPE_RD_R1_IMM5_IMM5: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst)); ++ break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (inst)); +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 2a6b841232..ce8ac351b5 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -59,6 +59,9 @@ + /* For mbar. */ + #define INST_TYPE_IMM5 20 + ++/* For bsefi and bsifi */ ++#define INST_TYPE_RD_R1_IMM5_IMM5 21 ++ + #define INST_TYPE_NONE 25 + + +@@ -89,7 +92,9 @@ + #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ + #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ + #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ ++#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */ + #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ ++#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */ + #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ + #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ +@@ -102,7 +107,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 299 ++#define MAX_OPCODES 301 + + struct op_code_struct + { +@@ -159,6 +164,8 @@ struct op_code_struct + {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, + {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, + {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, ++ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, ++ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, + {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst }, + {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst }, +@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM5 ((int) 0x00000000) + #define MAX_IMM5 ((int) 0x0000001f) + ++#define MIN_IMM_WIDTH ((int) 0x00000001) ++#define MAX_IMM_WIDTH ((int) 0x00000020) ++ + #endif /* MICROBLAZE_OPC */ + +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 1c39dbf50b..28662694cd 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -29,7 +29,7 @@ enum microblaze_instr + addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, + mulh, mulhu, mulhsu,swapb,swaph, + idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, +- ncget, ncput, muli, bslli, bsrai, bsrli, mului, ++ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului, + /* 'or/and/xor' are C++ keywords. */ + microblaze_or, microblaze_and, microblaze_xor, + andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, +@@ -129,6 +129,7 @@ enum microblaze_instr_type + #define RB_LOW 11 /* Low bit for RB. */ + #define IMM_LOW 0 /* Low bit for immediate. */ + #define IMM_MBAR 21 /* low bit for mbar instruction. */ ++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */ + + #define RD_MASK 0x03E00000 + #define RA_MASK 0x001F0000 +@@ -141,6 +142,9 @@ enum microblaze_instr_type + /* Imm mask for mbar. */ + #define IMM5_MBAR_MASK 0x03E00000 + ++/* Imm mask for extract/insert width. */ ++#define IMM5_WIDTH_MASK 0x000007C0 ++ + /* FSL imm mask for get, put instructions. */ + #define RFSL_MASK 0x000000F + +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0011-fixing-the-imm-bug.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0011-fixing-the-imm-bug.patch new file mode 100644 index 000000000..4c1b0c251 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0011-fixing-the-imm-bug.patch @@ -0,0 +1,27 @@ +From 8b2e8fe916066bb1caa99abc67f8cde3ebd41c70 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 10 Jul 2017 16:07:28 +0530 +Subject: [PATCH 11/43] fixing the imm bug. with relax option imm -1 is also + getting removed this is corrected now. + +--- + bfd/elf32-microblaze.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index d19a6dca84..d001437b3f 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -1869,8 +1869,7 @@ microblaze_elf_relax_section (bfd *abfd, + else + symval += irel->r_addend; + +- if ((symval & 0xffff8000) == 0 +- || (symval & 0xffff8000) == 0xffff8000) ++ if ((symval & 0xffff8000) == 0) + { + /* We can delete this instruction. */ + sec->relax[sec->relax_count].addr = irel->r_offset; +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch new file mode 100644 index 000000000..ad4db430f --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch @@ -0,0 +1,33 @@ +From 2a7b66bbc0473c6cbe6653a48818962b5b411ef2 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Fri, 29 Sep 2017 18:00:23 +0530 +Subject: [PATCH 12/43] [Patch,Microblaze]: fixed bug in GCC so that It will + support .long 0U and .long 0u + +--- + gas/expr.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/gas/expr.c b/gas/expr.c +index ee85bda1cc..b502418b71 100644 +--- a/gas/expr.c ++++ b/gas/expr.c +@@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode) + break; + } + } ++ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u')) ++ { ++ input_line_pointer--; ++ ++ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri) ++ ? 0 : 10, ++ expressionP); ++ break; ++ } + c = *input_line_pointer; + switch (c) + { +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch new file mode 100644 index 000000000..323b7bdea --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch @@ -0,0 +1,26 @@ +From 59a9a1a913b7dfa424792c907001413c1ddd320c Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 16 Oct 2017 15:44:23 +0530 +Subject: [PATCH 13/43] fixing the constant range check issue sample error: not + in range ffffffff80000000..7fffffff, not ffffffff70000000 + +--- + gas/config/tc-microblaze.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 71bb888ab8..16b10d00a9 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -757,7 +757,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) + if ((e->X_add_number >> 31) == 1) + e->X_add_number |= -((addressT) (1U << 31)); + +- if (e->X_add_number < min || e->X_add_number > max) ++ if ((int)e->X_add_number < min || (int)e->X_add_number > max) + { + as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"), + (long) min, (long) max, (long) e->X_add_number); +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch new file mode 100644 index 000000000..1a3e01301 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch @@ -0,0 +1,36 @@ +From 00b7561a868b08dab952b9b9f4a01118195aeb29 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 21 Feb 2018 12:32:02 +0530 +Subject: [PATCH 14/43] [Patch,Microblaze]: Compiler will give error messages + in more detail for mxl-gp-opt flag.. + +--- + ld/ldmain.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/ld/ldmain.c b/ld/ldmain.c +index 77cdbd0dd2..517d85baef 100644 +--- a/ld/ldmain.c ++++ b/ld/ldmain.c +@@ -1446,6 +1446,18 @@ reloc_overflow (struct bfd_link_info *info, + break; + case bfd_link_hash_defined: + case bfd_link_hash_defweak: ++ ++ if((strcmp(reloc_name,"R_MICROBLAZE_SRW32") == 0) && entry->type == bfd_link_hash_defined) ++ { ++ einfo (_(" relocation truncated to fit: don't enable small data pointer optimizations[mxl-gp-opt] if extern or multiple declarations used: " ++ "%s against symbol `%T' defined in %A section in %B"), ++ reloc_name, entry->root.string, ++ entry->u.def.section, ++ entry->u.def.section == bfd_abs_section_ptr ++ ? info->output_bfd : entry->u.def.section->owner); ++ break; ++ } ++ + einfo (_(" relocation truncated to fit: " + "%s against symbol `%pT' defined in %pA section in %pB"), + reloc_name, entry->root.string, +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch new file mode 100644 index 000000000..d0f96eca8 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch @@ -0,0 +1,4738 @@ +From 9aeae734291f8aaeb449c1403561b71de1ea3bea Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sun, 30 Sep 2018 16:28:28 +0530 +Subject: [PATCH 15/43] intial commit of MB 64-bit + +--- + bfd/Makefile.am | 2 + + bfd/Makefile.in | 3 + + bfd/config.bfd | 4 + + bfd/configure | 2 + + bfd/configure.ac | 2 + + bfd/cpu-microblaze.c | 52 +- + bfd/elf64-microblaze.c | 3584 ++++++++++++++++++++++++++++ + bfd/targets.c | 6 + + gas/config/tc-microblaze.c | 274 ++- + gas/config/tc-microblaze.h | 4 +- + include/elf/common.h | 1 + + ld/Makefile.am | 8 + + ld/Makefile.in | 10 + + ld/configure.tgt | 3 + + ld/emulparams/elf64microblaze.sh | 23 + + ld/emulparams/elf64microblazeel.sh | 23 + + opcodes/microblaze-dis.c | 39 +- + opcodes/microblaze-opc.h | 162 +- + opcodes/microblaze-opcm.h | 20 +- + 19 files changed, 4181 insertions(+), 41 deletions(-) + create mode 100644 bfd/elf64-microblaze.c + create mode 100644 ld/emulparams/elf64microblaze.sh + create mode 100644 ld/emulparams/elf64microblazeel.sh + +diff --git a/bfd/Makefile.am b/bfd/Makefile.am +index a9191555ad..c5fd250812 100644 +--- a/bfd/Makefile.am ++++ b/bfd/Makefile.am +@@ -570,6 +570,7 @@ BFD64_BACKENDS = \ + elf64-riscv.lo \ + elfxx-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -603,6 +604,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +diff --git a/bfd/Makefile.in b/bfd/Makefile.in +index 896df52042..fd457cba1e 100644 +--- a/bfd/Makefile.in ++++ b/bfd/Makefile.in +@@ -995,6 +995,7 @@ BFD64_BACKENDS = \ + elf64-riscv.lo \ + elfxx-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -1028,6 +1029,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +@@ -1494,6 +1496,7 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@ +diff --git a/bfd/config.bfd b/bfd/config.bfd +index 0e1ddb659c..93d210643d 100644 +--- a/bfd/config.bfd ++++ b/bfd/config.bfd +@@ -850,11 +850,15 @@ case "${targ}" in + microblazeel*-*) + targ_defvec=microblaze_elf32_le_vec + targ_selvecs=microblaze_elf32_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + microblaze*-*) + targ_defvec=microblaze_elf32_vec + targ_selvecs=microblaze_elf32_le_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + #ifdef BFD64 +diff --git a/bfd/configure b/bfd/configure +index 04786696dc..d455abe7c5 100755 +--- a/bfd/configure ++++ b/bfd/configure +@@ -14847,6 +14847,8 @@ do + rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; + s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; + score_elf32_be_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + sh_coff_vec) tb="$tb coff-sh.lo $coff" ;; +diff --git a/bfd/configure.ac b/bfd/configure.ac +index eda38ea086..f01c3362fe 100644 +--- a/bfd/configure.ac ++++ b/bfd/configure.ac +@@ -615,6 +615,8 @@ do + rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; + s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; + score_elf32_be_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + sh_coff_vec) tb="$tb coff-sh.lo $coff" ;; +diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c +index 9bc2eb3de9..c91ba46f75 100644 +--- a/bfd/cpu-microblaze.c ++++ b/bfd/cpu-microblaze.c +@@ -23,7 +23,24 @@ + #include "bfd.h" + #include "libbfd.h" + +-const bfd_arch_info_type bfd_microblaze_arch = ++const bfd_arch_info_type bfd_microblaze_arch[] = ++{ ++#if BFD_DEFAULT_TARGET_SIZE == 64 ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ 0, /* Machine number - 0 for now. */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ FALSE, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ +@@ -38,4 +55,37 @@ const bfd_arch_info_type bfd_microblaze_arch = + bfd_default_scan, /* String to architecture conversion. */ + bfd_arch_default_fill, /* Default fill. */ + NULL /* Next in list. */ ++} ++#else ++{ ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ 0, /* Machine number - 0 for now. */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ TRUE, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ 0, /* Machine number - 0 for now. */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ FALSE, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ NULL /* Next in list. */ ++} ++#endif + }; +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +new file mode 100644 +index 0000000000..0f43ae6ea8 +--- /dev/null ++++ b/bfd/elf64-microblaze.c +@@ -0,0 +1,3584 @@ ++/* Xilinx MicroBlaze-specific support for 32-bit ELF ++ ++ Copyright (C) 2009-2016 Free Software Foundation, Inc. ++ ++ This file is part of BFD, the Binary File Descriptor library. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the ++ Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, ++ Boston, MA 02110-1301, USA. */ ++ ++ ++int dbg1 = 0; ++ ++#include "sysdep.h" ++#include "bfd.h" ++#include "bfdlink.h" ++#include "libbfd.h" ++#include "elf-bfd.h" ++#include "elf/microblaze.h" ++#include <assert.h> ++ ++#define USE_RELA /* Only USE_REL is actually significant, but this is ++ here are a reminder... */ ++#define INST_WORD_SIZE 4 ++ ++static int ro_small_data_pointer = 0; ++static int rw_small_data_pointer = 0; ++ ++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max]; ++ ++static reloc_howto_type microblaze_elf_howto_raw[] = ++{ ++ /* This reloc does nothing. */ ++ HOWTO (R_MICROBLAZE_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 3, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_NONE", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A standard 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A standard PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_PCREL", /* Name. */ ++ TRUE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit PCREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_64_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 64, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64_PCREL", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* The low half of a PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_32_PCREL_LO", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit relocation. Table entry not really used. */ ++ HOWTO (R_MICROBLAZE_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* The low half of a 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_LO", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Read-only small data section relocation. */ ++ HOWTO (R_MICROBLAZE_SRO32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRO32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Read-write small data area relocation. */ ++ HOWTO (R_MICROBLAZE_SRW32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRW32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_32_NONE",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 3, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_64_NONE",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Symbol Op Symbol relocation. */ ++ HOWTO (R_MICROBLAZE_32_SYM_OP_SYM, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_SYM_OP_SYM", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable hierarchy. */ ++ HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTINHERIT", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable member usage. */ ++ HOWTO (R_MICROBLAZE_GNU_VTENTRY, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ _bfd_elf_rel_vtable_reloc_fn, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTENTRY", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTPC_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOT_64",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A 64 bit PLT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_PLT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_PLT_64",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_REL, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_REL", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_JUMP_SLOT", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GLOB_DAT", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A 32 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* COPY relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_COPY, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_COPY", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Marker relocs for TLS. */ ++ HOWTO (R_MICROBLAZE_TLS, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLS", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSGD, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGD", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSLD, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSLD", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes the load module index of the load module that contains the ++ definition of its TLS sym. */ ++ HOWTO (R_MICROBLAZE_TLSDTPMOD32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPMOD32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. Used for initializing GOT */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL64, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL64", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSGOTTPREL32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGOTTPREL32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSTPREL32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSTPREL32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++}; ++ ++#ifndef NUM_ELEM ++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) ++#endif ++ ++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done. */ ++ ++static void ++microblaze_elf_howto_init (void) ++{ ++ unsigned int i; ++ ++ for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;) ++ { ++ unsigned int type; ++ ++ type = microblaze_elf_howto_raw[i].type; ++ ++ BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table)); ++ ++ microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i]; ++ } ++} ++ ++static reloc_howto_type * ++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, ++ bfd_reloc_code_real_type code) ++{ ++ enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE; ++ ++ switch (code) ++ { ++ case BFD_RELOC_NONE: ++ microblaze_reloc = R_MICROBLAZE_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_NONE: ++ microblaze_reloc = R_MICROBLAZE_32_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_NONE: ++ microblaze_reloc = R_MICROBLAZE_64_NONE; ++ break; ++ case BFD_RELOC_32: ++ microblaze_reloc = R_MICROBLAZE_32; ++ break; ++ /* RVA is treated the same as 32 */ ++ case BFD_RELOC_RVA: ++ microblaze_reloc = R_MICROBLAZE_32; ++ break; ++ case BFD_RELOC_32_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL; ++ break; ++ case BFD_RELOC_64_PCREL: ++ microblaze_reloc = R_MICROBLAZE_64_PCREL; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL_LO; ++ break; ++ case BFD_RELOC_64: ++ microblaze_reloc = R_MICROBLAZE_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO: ++ microblaze_reloc = R_MICROBLAZE_32_LO; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_ROSDA: ++ microblaze_reloc = R_MICROBLAZE_SRO32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_RWSDA: ++ microblaze_reloc = R_MICROBLAZE_SRW32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: ++ microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM; ++ break; ++ case BFD_RELOC_VTABLE_INHERIT: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT; ++ break; ++ case BFD_RELOC_VTABLE_ENTRY: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ microblaze_reloc = R_MICROBLAZE_GOTPC_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOT: ++ microblaze_reloc = R_MICROBLAZE_GOT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_PLT: ++ microblaze_reloc = R_MICROBLAZE_PLT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGD: ++ microblaze_reloc = R_MICROBLAZE_TLSGD; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSLD: ++ microblaze_reloc = R_MICROBLAZE_TLSLD; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_COPY: ++ microblaze_reloc = R_MICROBLAZE_COPY; ++ break; ++ default: ++ return (reloc_howto_type *) NULL; ++ } ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ return microblaze_elf_howto_table [(int) microblaze_reloc]; ++}; ++ ++static reloc_howto_type * ++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, ++ const char *r_name) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++) ++ if (microblaze_elf_howto_raw[i].name != NULL ++ && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0) ++ return µblaze_elf_howto_raw[i]; ++ ++ return NULL; ++} ++ ++/* Set the howto pointer for a RCE ELF reloc. */ ++ ++static void ++microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, ++ arelent * cache_ptr, ++ Elf_Internal_Rela * dst) ++{ ++ unsigned int r_type; ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ r_type = ELF64_R_TYPE (dst->r_info); ++ if (r_type >= R_MICROBLAZE_max) ++ { ++ (*_bfd_error_handler) (_("%B: unrecognised MicroBlaze reloc number: %d"), ++ abfd, r_type); ++ bfd_set_error (bfd_error_bad_value); ++ r_type = R_MICROBLAZE_NONE; ++ } ++ ++ cache_ptr->howto = microblaze_elf_howto_table [r_type]; ++} ++ ++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */ ++ ++static bfd_boolean ++microblaze_elf_is_local_label_name (bfd *abfd, const char *name) ++{ ++ if (name[0] == 'L' && name[1] == '.') ++ return TRUE; ++ ++ if (name[0] == '$' && name[1] == 'L') ++ return TRUE; ++ ++ /* With gcc, the labels go back to starting with '.', so we accept ++ the generic ELF local label syntax as well. */ ++ return _bfd_elf_is_local_label_name (abfd, name); ++} ++ ++/* The microblaze linker (like many others) needs to keep track of ++ the number of relocs that it decides to copy as dynamic relocs in ++ check_relocs for each symbol. This is so that it can later discard ++ them if they are found to be unnecessary. We store the information ++ in a field extending the regular ELF linker hash table. */ ++ ++struct elf64_mb_dyn_relocs ++{ ++ struct elf64_mb_dyn_relocs *next; ++ ++ /* The input section of the reloc. */ ++ asection *sec; ++ ++ /* Total number of relocs copied for the input section. */ ++ bfd_size_type count; ++ ++ /* Number of pc-relative relocs copied for the input section. */ ++ bfd_size_type pc_count; ++}; ++ ++/* ELF linker hash entry. */ ++ ++struct elf64_mb_link_hash_entry ++{ ++ struct elf_link_hash_entry elf; ++ ++ /* Track dynamic relocs copied for this symbol. */ ++ struct elf64_mb_dyn_relocs *dyn_relocs; ++ ++ /* TLS Reference Types for the symbol; Updated by check_relocs */ ++#define TLS_GD 1 /* GD reloc. */ ++#define TLS_LD 2 /* LD reloc. */ ++#define TLS_TPREL 4 /* TPREL reloc, => IE. */ ++#define TLS_DTPREL 8 /* DTPREL reloc, => LD. */ ++#define TLS_TLS 16 /* Any TLS reloc. */ ++ unsigned char tls_mask; ++ ++}; ++ ++#define IS_TLS_GD(x) (x == (TLS_TLS | TLS_GD)) ++#define IS_TLS_LD(x) (x == (TLS_TLS | TLS_LD)) ++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL)) ++#define IS_TLS_NONE(x) (x == 0) ++ ++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent)) ++ ++/* ELF linker hash table. */ ++ ++struct elf64_mb_link_hash_table ++{ ++ struct elf_link_hash_table elf; ++ ++ /* Short-cuts to get to dynamic linker sections. */ ++ asection *sgot; ++ asection *sgotplt; ++ asection *srelgot; ++ asection *splt; ++ asection *srelplt; ++ asection *sdynbss; ++ asection *srelbss; ++ ++ /* Small local sym to section mapping cache. */ ++ struct sym_cache sym_sec; ++ ++ /* TLS Local Dynamic GOT Entry */ ++ union { ++ bfd_signed_vma refcount; ++ bfd_vma offset; ++ } tlsld_got; ++}; ++ ++/* Nonzero if this section has TLS related relocations. */ ++#define has_tls_reloc sec_flg0 ++ ++/* Get the ELF linker hash table from a link_info structure. */ ++ ++#define elf64_mb_hash_table(p) \ ++ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \ ++ == MICROBLAZE_ELF_DATA ? ((struct elf64_mb_link_hash_table *) ((p)->hash)) : NULL) ++ ++/* Create an entry in a microblaze ELF linker hash table. */ ++ ++static struct bfd_hash_entry * ++link_hash_newfunc (struct bfd_hash_entry *entry, ++ struct bfd_hash_table *table, ++ const char *string) ++{ ++ /* Allocate the structure if it has not already been allocated by a ++ subclass. */ ++ if (entry == NULL) ++ { ++ entry = bfd_hash_allocate (table, ++ sizeof (struct elf64_mb_link_hash_entry)); ++ if (entry == NULL) ++ return entry; ++ } ++ ++ /* Call the allocation method of the superclass. */ ++ entry = _bfd_elf_link_hash_newfunc (entry, table, string); ++ if (entry != NULL) ++ { ++ struct elf64_mb_link_hash_entry *eh; ++ ++ eh = (struct elf64_mb_link_hash_entry *) entry; ++ eh->dyn_relocs = NULL; ++ eh->tls_mask = 0; ++ } ++ ++ return entry; ++} ++ ++/* Create a mb ELF linker hash table. */ ++ ++static struct bfd_link_hash_table * ++microblaze_elf_link_hash_table_create (bfd *abfd) ++{ ++ struct elf64_mb_link_hash_table *ret; ++ bfd_size_type amt = sizeof (struct elf64_mb_link_hash_table); ++ ++ ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt); ++ if (ret == NULL) ++ return NULL; ++ ++ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, ++ sizeof (struct elf64_mb_link_hash_entry), ++ MICROBLAZE_ELF_DATA)) ++ { ++ free (ret); ++ return NULL; ++ } ++ ++ return &ret->elf.root; ++} ++ ++/* Set the values of the small data pointers. */ ++ ++static void ++microblaze_elf_final_sdp (struct bfd_link_info *info) ++{ ++ struct bfd_link_hash_entry *h; ++ ++ h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ ro_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++ ++ h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ rw_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++} ++ ++static bfd_vma ++dtprel_base (struct bfd_link_info *info) ++{ ++ /* If tls_sec is NULL, we should have signalled an error already. */ ++ if (elf_hash_table (info)->tls_sec == NULL) ++ return 0; ++ return elf_hash_table (info)->tls_sec->vma; ++} ++ ++/* The size of the thread control block. */ ++#define TCB_SIZE 8 ++ ++/* Output a simple dynamic relocation into SRELOC. */ ++ ++static void ++microblaze_elf_output_dynamic_relocation (bfd *output_bfd, ++ asection *sreloc, ++ unsigned long reloc_index, ++ unsigned long indx, ++ int r_type, ++ bfd_vma offset, ++ bfd_vma addend) ++{ ++ ++ Elf_Internal_Rela rel; ++ ++ rel.r_info = ELF64_R_INFO (indx, r_type); ++ rel.r_offset = offset; ++ rel.r_addend = addend; ++ ++ bfd_elf64_swap_reloca_out (output_bfd, &rel, ++ (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela))); ++} ++ ++/* This code is taken from elf64-m32r.c ++ There is some attempt to make this function usable for many architectures, ++ both USE_REL and USE_RELA ['twould be nice if such a critter existed], ++ if only to serve as a learning tool. ++ ++ The RELOCATE_SECTION function is called by the new ELF backend linker ++ to handle the relocations for a section. ++ ++ The relocs are always passed as Rela structures; if the section ++ actually uses Rel structures, the r_addend field will always be ++ zero. ++ ++ This function is responsible for adjust the section contents as ++ necessary, and (if using Rela relocs and generating a ++ relocatable output file) adjusting the reloc addend as ++ necessary. ++ ++ This function does not have to worry about setting the reloc ++ address or the reloc symbol index. ++ ++ LOCAL_SYMS is a pointer to the swapped in local symbols. ++ ++ LOCAL_SECTIONS is an array giving the section in the input file ++ corresponding to the st_shndx field of each local symbol. ++ ++ The global hash table entry for the global symbols can be found ++ via elf_sym_hashes (input_bfd). ++ ++ When generating relocatable output, this function must handle ++ STB_LOCAL/STT_SECTION symbols specially. The output symbol is ++ going to be the section symbol corresponding to the output ++ section, which means that the addend must be adjusted ++ accordingly. */ ++ ++static bfd_boolean ++microblaze_elf_relocate_section (bfd *output_bfd, ++ struct bfd_link_info *info, ++ bfd *input_bfd, ++ asection *input_section, ++ bfd_byte *contents, ++ Elf_Internal_Rela *relocs, ++ Elf_Internal_Sym *local_syms, ++ asection **local_sections) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; ++ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); ++ Elf_Internal_Rela *rel, *relend; ++ int endian = (bfd_little_endian (output_bfd)) ? 0 : 2; ++ /* Assume success. */ ++ bfd_boolean ret = TRUE; ++ asection *sreloc; ++ bfd_vma *local_got_offsets; ++ unsigned int tls_type; ++ ++ if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1]) ++ microblaze_elf_howto_init (); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ local_got_offsets = elf_local_got_offsets (input_bfd); ++ ++ sreloc = elf_section_data (input_section)->sreloc; ++ ++ rel = relocs; ++ relend = relocs + input_section->reloc_count; ++ for (; rel < relend; rel++) ++ { ++ int r_type; ++ reloc_howto_type *howto; ++ unsigned long r_symndx; ++ bfd_vma addend = rel->r_addend; ++ bfd_vma offset = rel->r_offset; ++ struct elf_link_hash_entry *h; ++ Elf_Internal_Sym *sym; ++ asection *sec; ++ const char *sym_name; ++ bfd_reloc_status_type r = bfd_reloc_ok; ++ const char *errmsg = NULL; ++ bfd_boolean unresolved_reloc = FALSE; ++ ++ h = NULL; ++ r_type = ELF64_R_TYPE (rel->r_info); ++ tls_type = 0; ++ ++ if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max) ++ { ++ (*_bfd_error_handler) (_("%s: unknown relocation type %d"), ++ bfd_get_filename (input_bfd), (int) r_type); ++ bfd_set_error (bfd_error_bad_value); ++ ret = FALSE; ++ continue; ++ } ++ ++ howto = microblaze_elf_howto_table[r_type]; ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ ++ if (bfd_link_relocatable (info)) ++ { ++ /* This is a relocatable link. We don't have to change ++ anything, unless the reloc is against a section symbol, ++ in which case we have to adjust according to where the ++ section symbol winds up in the output section. */ ++ sec = NULL; ++ if (r_symndx >= symtab_hdr->sh_info) ++ /* External symbol. */ ++ continue; ++ ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sym_name = "<local symbol>"; ++ /* STT_SECTION: symbol is associated with a section. */ ++ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) ++ /* Symbol isn't associated with a section. Nothing to do. */ ++ continue; ++ ++ sec = local_sections[r_symndx]; ++ addend += sec->output_offset + sym->st_value; ++#ifndef USE_REL ++ /* This can't be done for USE_REL because it doesn't mean anything ++ and elf_link_input_bfd asserts this stays zero. */ ++ /* rel->r_addend = addend; */ ++#endif ++ ++#ifndef USE_REL ++ /* Addends are stored with relocs. We're done. */ ++ continue; ++#else /* USE_REL */ ++ /* If partial_inplace, we need to store any additional addend ++ back in the section. */ ++ if (!howto->partial_inplace) ++ continue; ++ /* ??? Here is a nice place to call a special_function like handler. */ ++ r = _bfd_relocate_contents (howto, input_bfd, addend, ++ contents + offset); ++#endif /* USE_REL */ ++ } ++ else ++ { ++ bfd_vma relocation; ++ ++ /* This is a final link. */ ++ sym = NULL; ++ sec = NULL; ++ unresolved_reloc = FALSE; ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ { ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sec = local_sections[r_symndx]; ++ if (sec == 0) ++ continue; ++ sym_name = "<local symbol>"; ++ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); ++ /* r_addend may have changed if the reference section was ++ a merge section. */ ++ addend = rel->r_addend; ++ } ++ else ++ { ++ /* External symbol. */ ++ bfd_boolean warned ATTRIBUTE_UNUSED; ++ bfd_boolean ignored ATTRIBUTE_UNUSED; ++ ++ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, ++ r_symndx, symtab_hdr, sym_hashes, ++ h, sec, relocation, ++ unresolved_reloc, warned, ignored); ++ sym_name = h->root.root.string; ++ } ++ ++ /* Sanity check the address. */ ++ if (offset > bfd_get_section_limit (input_bfd, input_section)) ++ { ++ r = bfd_reloc_outofrange; ++ goto check_reloc; ++ } ++ ++ switch ((int) r_type) ++ { ++ case (int) R_MICROBLAZE_SRO32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_get_section_name (sec->owner, sec); ++ ++ if (strcmp (name, ".sdata2") == 0 ++ || strcmp (name, ".sbss2") == 0) ++ { ++ if (ro_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (ro_small_data_pointer == 0) ++ { ++ ret = FALSE; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= ro_small_data_pointer; ++ /* Now it contains the offset from _SDA2_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"), ++ bfd_get_filename (input_bfd), ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ bfd_get_section_name (sec->owner, sec)); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = FALSE; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_SRW32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_get_section_name (sec->owner, sec); ++ ++ if (strcmp (name, ".sdata") == 0 ++ || strcmp (name, ".sbss") == 0) ++ { ++ if (rw_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (rw_small_data_pointer == 0) ++ { ++ ret = FALSE; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= rw_small_data_pointer; ++ /* Now it contains the offset from _SDA_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"), ++ bfd_get_filename (input_bfd), ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ bfd_get_section_name (sec->owner, sec)); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = FALSE; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_32_SYM_OP_SYM: ++ break; /* Do nothing. */ ++ ++ case (int) R_MICROBLAZE_GOTPC_64: ++ relocation = htab->sgotplt->output_section->vma ++ + htab->sgotplt->output_offset; ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ relocation += addend; ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ ++ case (int) R_MICROBLAZE_PLT_64: ++ { ++ bfd_vma immediate; ++ if (htab->splt != NULL && h != NULL ++ && h->plt.offset != (bfd_vma) -1) ++ { ++ relocation = (htab->splt->output_section->vma ++ + htab->splt->output_offset ++ + h->plt.offset); ++ unresolved_reloc = FALSE; ++ immediate = relocation - (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ else ++ { ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ immediate = relocation; ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSGD: ++ tls_type = (TLS_TLS | TLS_GD); ++ goto dogot; ++ case (int) R_MICROBLAZE_TLSLD: ++ tls_type = (TLS_TLS | TLS_LD); ++ dogot: ++ case (int) R_MICROBLAZE_GOT_64: ++ { ++ bfd_vma *offp; ++ bfd_vma off, off2; ++ unsigned long indx; ++ bfd_vma static_value; ++ ++ bfd_boolean need_relocs = FALSE; ++ if (htab->sgot == NULL) ++ abort (); ++ ++ indx = 0; ++ offp = NULL; ++ ++ /* 1. Identify GOT Offset; ++ 2. Compute Static Values ++ 3. Process Module Id, Process Offset ++ 4. Fixup Relocation with GOT offset value. */ ++ ++ /* 1. Determine GOT Offset to use : TLS_LD, global, local */ ++ if (IS_TLS_LD (tls_type)) ++ offp = &htab->tlsld_got.offset; ++ else if (h != NULL) ++ { ++ if (htab->sgotplt != NULL && h->got.offset != (bfd_vma) -1) ++ offp = &h->got.offset; ++ else ++ abort (); ++ } ++ else ++ { ++ if (local_got_offsets == NULL) ++ abort (); ++ offp = &local_got_offsets[r_symndx]; ++ } ++ ++ if (!offp) ++ abort (); ++ ++ off = (*offp) & ~1; ++ off2 = off; ++ ++ if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type)) ++ off2 = off + 4; ++ ++ /* Symbol index to use for relocs */ ++ if (h != NULL) ++ { ++ bfd_boolean dyn = ++ elf_hash_table (info)->dynamic_sections_created; ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, ++ bfd_link_pic (info), ++ h) ++ && (!bfd_link_pic (info) ++ || !SYMBOL_REFERENCES_LOCAL (info, h))) ++ indx = h->dynindx; ++ } ++ ++ /* Need to generate relocs ? */ ++ if ((bfd_link_pic (info) || indx != 0) ++ && (h == NULL ++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ || h->root.type != bfd_link_hash_undefweak)) ++ need_relocs = TRUE; ++ ++ /* 2. Compute/Emit Static value of r-expression */ ++ static_value = relocation + addend; ++ ++ /* 3. Process module-id and offset */ ++ if (! ((*offp) & 1) ) ++ { ++ bfd_vma got_offset; ++ ++ got_offset = (htab->sgot->output_section->vma ++ + htab->sgot->output_offset ++ + off); ++ ++ /* Process module-id */ ++ if (IS_TLS_LD(tls_type)) ++ { ++ if (! bfd_link_pic (info)) ++ { ++ bfd_put_32 (output_bfd, 1, htab->sgot->contents + off); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, htab->srelgot->reloc_count++, ++ /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, 0); ++ } ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ if (! need_relocs) ++ { ++ bfd_put_32 (output_bfd, 1, htab->sgot->contents + off); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, ++ htab->srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, indx ? 0 : static_value); ++ } ++ } ++ ++ /* Process Offset */ ++ if (htab->srelgot == NULL) ++ abort (); ++ ++ got_offset = (htab->sgot->output_section->vma ++ + htab->sgot->output_offset ++ + off2); ++ if (IS_TLS_LD(tls_type)) ++ { ++ /* For LD, offset should be 0 */ ++ *offp |= 1; ++ bfd_put_32 (output_bfd, 0, htab->sgot->contents + off2); ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ *offp |= 1; ++ static_value -= dtprel_base(info); ++ if (need_relocs) ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, htab->srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32, ++ got_offset, indx ? 0 : static_value); ++ } ++ else ++ { ++ bfd_put_32 (output_bfd, static_value, ++ htab->sgot->contents + off2); ++ } ++ } ++ else ++ { ++ bfd_put_32 (output_bfd, static_value, ++ htab->sgot->contents + off2); ++ ++ /* Relocs for dyn symbols generated by ++ finish_dynamic_symbols */ ++ if (bfd_link_pic (info) && h == NULL) ++ { ++ *offp |= 1; ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, htab->srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_REL, ++ got_offset, static_value); ++ } ++ } ++ } ++ ++ /* 4. Fixup Relocation with GOT offset value ++ Compute relative address of GOT entry for applying ++ the current relocation */ ++ relocation = htab->sgot->output_section->vma ++ + htab->sgot->output_offset ++ + off ++ - htab->sgotplt->output_section->vma ++ - htab->sgotplt->output_offset; ++ ++ /* Apply Current Relocation */ ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ ++ unresolved_reloc = FALSE; ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_64: ++ { ++ bfd_vma immediate; ++ unsigned short lo, high; ++ relocation += addend; ++ relocation -= htab->sgotplt->output_section->vma ++ + htab->sgotplt->output_offset; ++ /* Write this value into correct location. */ ++ immediate = relocation; ++ lo = immediate & 0x0000ffff; ++ high = (immediate >> 16) & 0x0000ffff; ++ bfd_put_16 (input_bfd, high, contents + offset + endian); ++ bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + endian); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_32: ++ { ++ relocation += addend; ++ relocation -= htab->sgotplt->output_section->vma ++ + htab->sgotplt->output_offset; ++ /* Write this value into correct location. */ ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSDTPREL64: ++ relocation += addend; ++ relocation -= dtprel_base(info); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ case (int) R_MICROBLAZE_64_PCREL : ++ case (int) R_MICROBLAZE_64: ++ case (int) R_MICROBLAZE_32: ++ { ++ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols ++ from removed linkonce sections, or sections discarded by ++ a linker script. */ ++ if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ if ((bfd_link_pic (info) ++ && (h == NULL ++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ || h->root.type != bfd_link_hash_undefweak) ++ && (!howto->pc_relative ++ || (h != NULL ++ && h->dynindx != -1 ++ && (!info->symbolic ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && h != NULL ++ && h->dynindx != -1 ++ && !h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined))) ++ { ++ Elf_Internal_Rela outrel; ++ bfd_byte *loc; ++ bfd_boolean skip; ++ ++ /* When generating a shared object, these relocations ++ are copied into the output file to be resolved at run ++ time. */ ++ ++ BFD_ASSERT (sreloc != NULL); ++ ++ skip = FALSE; ++ ++ outrel.r_offset = ++ _bfd_elf_section_offset (output_bfd, info, input_section, ++ rel->r_offset); ++ if (outrel.r_offset == (bfd_vma) -1) ++ skip = TRUE; ++ else if (outrel.r_offset == (bfd_vma) -2) ++ skip = TRUE; ++ outrel.r_offset += (input_section->output_section->vma ++ + input_section->output_offset); ++ ++ if (skip) ++ memset (&outrel, 0, sizeof outrel); ++ /* h->dynindx may be -1 if the symbol was marked to ++ become local. */ ++ else if (h != NULL ++ && ((! info->symbolic && h->dynindx != -1) ++ || !h->def_regular)) ++ { ++ BFD_ASSERT (h->dynindx != -1); ++ outrel.r_info = ELF64_R_INFO (h->dynindx, r_type); ++ outrel.r_addend = addend; ++ } ++ else ++ { ++ if (r_type == R_MICROBLAZE_32) ++ { ++ outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); ++ outrel.r_addend = relocation + addend; ++ } ++ else ++ { ++ BFD_FAIL (); ++ (*_bfd_error_handler) ++ (_("%B: probably compiled without -fPIC?"), ++ input_bfd); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; ++ } ++ } ++ ++ loc = sreloc->contents; ++ loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc); ++ break; ++ } ++ else ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ } ++ ++ default : ++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, ++ contents, offset, ++ relocation, addend); ++ break; ++ } ++ } ++ ++ check_reloc: ++ ++ if (r != bfd_reloc_ok) ++ { ++ /* FIXME: This should be generic enough to go in a utility. */ ++ const char *name; ++ ++ if (h != NULL) ++ name = h->root.root.string; ++ else ++ { ++ name = (bfd_elf_string_from_elf_section ++ (input_bfd, symtab_hdr->sh_link, sym->st_name)); ++ if (name == NULL || *name == '\0') ++ name = bfd_section_name (input_bfd, sec); ++ } ++ ++ if (errmsg != NULL) ++ goto common_error; ++ ++ switch (r) ++ { ++ case bfd_reloc_overflow: ++ (*info->callbacks->reloc_overflow) ++ (info, (h ? &h->root : NULL), name, howto->name, ++ (bfd_vma) 0, input_bfd, input_section, offset); ++ break; ++ ++ case bfd_reloc_undefined: ++ (*info->callbacks->undefined_symbol) ++ (info, name, input_bfd, input_section, offset, TRUE); ++ break; ++ ++ case bfd_reloc_outofrange: ++ errmsg = _("internal error: out of range error"); ++ goto common_error; ++ ++ case bfd_reloc_notsupported: ++ errmsg = _("internal error: unsupported relocation error"); ++ goto common_error; ++ ++ case bfd_reloc_dangerous: ++ errmsg = _("internal error: dangerous error"); ++ goto common_error; ++ ++ default: ++ errmsg = _("internal error: unknown error"); ++ /* Fall through. */ ++ common_error: ++ (*info->callbacks->warning) (info, errmsg, name, input_bfd, ++ input_section, offset); ++ break; ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++/* Merge backend specific data from an object file to the output ++ object file when linking. ++ ++ Note: We only use this hook to catch endian mismatches. */ ++static bfd_boolean ++microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) ++{ ++ /* Check if we have the same endianess. */ ++ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) ++ return FALSE; ++ ++ return TRUE; ++} ++ ++ ++/* Calculate fixup value for reference. */ ++ ++static int ++calc_fixup (bfd_vma start, bfd_vma size, asection *sec) ++{ ++ bfd_vma end = start + size; ++ int i, fixup = 0; ++ ++ if (sec == NULL || sec->relax == NULL) ++ return 0; ++ ++ /* Look for addr in relax table, total fixup value. */ ++ for (i = 0; i < sec->relax_count; i++) ++ { ++ if (end <= sec->relax[i].addr) ++ break; ++ if ((end != start) && (start > sec->relax[i].addr)) ++ continue; ++ fixup += sec->relax[i].size; ++ } ++ return fixup; ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ a 32-bit instruction. */ ++static void ++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr = bfd_get_32 (abfd, bfd_addr); ++ instr &= ~0x0000ffff; ++ instr |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ two consecutive 32-bit instructions. */ ++static void ++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr_hi; ++ unsigned long instr_lo; ++ ++ instr_hi = bfd_get_32 (abfd, bfd_addr); ++ instr_hi &= ~0x0000ffff; ++ instr_hi |= ((val >> 16) & 0x0000ffff); ++ bfd_put_32 (abfd, instr_hi, bfd_addr); ++ ++ instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE); ++ instr_lo &= ~0x0000ffff; ++ instr_lo |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE); ++} ++ ++static bfd_boolean ++microblaze_elf_relax_section (bfd *abfd, ++ asection *sec, ++ struct bfd_link_info *link_info, ++ bfd_boolean *again) ++{ ++ Elf_Internal_Shdr *symtab_hdr; ++ Elf_Internal_Rela *internal_relocs; ++ Elf_Internal_Rela *free_relocs = NULL; ++ Elf_Internal_Rela *irel, *irelend; ++ bfd_byte *contents = NULL; ++ bfd_byte *free_contents = NULL; ++ int rel_count; ++ unsigned int shndx; ++ int i, sym_index; ++ asection *o; ++ struct elf_link_hash_entry *sym_hash; ++ Elf_Internal_Sym *isymbuf, *isymend; ++ Elf_Internal_Sym *isym; ++ int symcount; ++ int offset; ++ bfd_vma src, dest; ++ ++ /* We only do this once per section. We may be able to delete some code ++ by running multiple passes, but it is not worth it. */ ++ *again = FALSE; ++ ++ /* Only do this for a text section. */ ++ if (bfd_link_relocatable (link_info) ++ || (sec->flags & SEC_RELOC) == 0 ++ || (sec->reloc_count == 0) ++ || (sec->flags & SEC_CODE) == 0) ++ return TRUE; ++ ++ BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0)); ++ ++ /* If this is the first time we have been called for this section, ++ initialize the cooked size. */ ++ if (sec->size == 0) ++ sec->size = sec->rawsize; ++ ++ /* Get symbols for this section. */ ++ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; ++ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; ++ symcount = symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (isymbuf == NULL) ++ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount, ++ 0, NULL, NULL, NULL); ++ BFD_ASSERT (isymbuf != NULL); ++ ++ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); ++ if (internal_relocs == NULL) ++ goto error_return; ++ if (! link_info->keep_memory) ++ free_relocs = internal_relocs; ++ ++ sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) ++ * sizeof (struct relax_table)); ++ if (sec->relax == NULL) ++ goto error_return; ++ sec->relax_count = 0; ++ ++ irelend = internal_relocs + sec->reloc_count; ++ rel_count = 0; ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma symval; ++ if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL) ++ && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 )) ++ continue; /* Can't delete this reloc. */ ++ ++ /* Get the section contents. */ ++ if (contents == NULL) ++ { ++ if (elf_section_data (sec)->this_hdr.contents != NULL) ++ contents = elf_section_data (sec)->this_hdr.contents; ++ else ++ { ++ contents = (bfd_byte *) bfd_malloc (sec->size); ++ if (contents == NULL) ++ goto error_return; ++ free_contents = contents; ++ ++ if (!bfd_get_section_contents (abfd, sec, contents, ++ (file_ptr) 0, sec->size)) ++ goto error_return; ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } ++ } ++ ++ /* Get the value of the symbol referred to by the reloc. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ /* A local symbol. */ ++ asection *sym_sec; ++ ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ if (isym->st_shndx == SHN_UNDEF) ++ sym_sec = bfd_und_section_ptr; ++ else if (isym->st_shndx == SHN_ABS) ++ sym_sec = bfd_abs_section_ptr; ++ else if (isym->st_shndx == SHN_COMMON) ++ sym_sec = bfd_com_section_ptr; ++ else ++ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ ++ symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel); ++ } ++ else ++ { ++ unsigned long indx; ++ struct elf_link_hash_entry *h; ++ ++ indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info; ++ h = elf_sym_hashes (abfd)[indx]; ++ BFD_ASSERT (h != NULL); ++ ++ if (h->root.type != bfd_link_hash_defined ++ && h->root.type != bfd_link_hash_defweak) ++ /* This appears to be a reference to an undefined ++ symbol. Just ignore it--it will be caught by the ++ regular reloc processing. */ ++ continue; ++ ++ symval = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ } ++ ++ /* If this is a PC-relative reloc, subtract the instr offset from ++ the symbol value. */ ++ if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ symval = symval + irel->r_addend ++ - (irel->r_offset ++ + sec->output_section->vma ++ + sec->output_offset); ++ } ++ else ++ symval += irel->r_addend; ++ ++ if ((symval & 0xffff8000) == 0) ++ { ++ /* We can delete this instruction. */ ++ sec->relax[sec->relax_count].addr = irel->r_offset; ++ sec->relax[sec->relax_count].size = INST_WORD_SIZE; ++ sec->relax_count++; ++ ++ /* Rewrite relocation type. */ ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ case R_MICROBLAZE_64_PCREL: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_PCREL_LO); ++ break; ++ case R_MICROBLAZE_64: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_LO); ++ break; ++ default: ++ /* Cannot happen. */ ++ BFD_ASSERT (FALSE); ++ } ++ } ++ } /* Loop through all relocations. */ ++ ++ /* Loop through the relocs again, and see if anything needs to change. */ ++ if (sec->relax_count > 0) ++ { ++ shndx = _bfd_elf_section_from_bfd_section (abfd, sec); ++ rel_count = 0; ++ sec->relax[sec->relax_count].addr = sec->size; ++ ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma nraddr; ++ ++ /* Get the new reloc address. */ ++ nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec); ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ default: ++ break; ++ case R_MICROBLAZE_64_PCREL: ++ break; ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_32_LO: ++ /* If this reloc is against a symbol defined in this ++ section, we must check the addend to see it will put the value in ++ range to be adjusted, and hence must be changed. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ /* Only handle relocs against .text. */ ++ if (isym->st_shndx == shndx ++ && ELF64_ST_TYPE (isym->st_info) == STT_SECTION) ++ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); ++ } ++ break; ++ case R_MICROBLAZE_NONE: ++ case R_MICROBLAZE_32_NONE: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ case R_MICROBLAZE_64_NONE: ++ { ++ /* This was a PC-relative 64-bit instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE; ++ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ irel->r_addend -= (efix - sfix); ++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset ++ + INST_WORD_SIZE, irel->r_addend); ++ } ++ break; ++ } ++ irel->r_offset = nraddr; ++ } /* Change all relocs in this section. */ ++ ++ /* Look through all other sections. */ ++ for (o = abfd->sections; o != NULL; o = o->next) ++ { ++ Elf_Internal_Rela *irelocs; ++ Elf_Internal_Rela *irelscan, *irelscanend; ++ bfd_byte *ocontents; ++ ++ if (o == sec ++ || (o->flags & SEC_RELOC) == 0 ++ || o->reloc_count == 0) ++ continue; ++ ++ /* We always cache the relocs. Perhaps, if info->keep_memory is ++ FALSE, we should free them, if we are permitted to. */ ++ ++ irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE); ++ if (irelocs == NULL) ++ goto error_return; ++ ++ ocontents = NULL; ++ irelscanend = irelocs + o->reloc_count; ++ for (irelscan = irelocs; irelscan < irelscanend; irelscan++) ++ { ++ if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) ++ { ++ unsigned int val; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* hax: We only do the following fixup for debug location lists. */ ++ if (strcmp(".debug_loc", o->name)) ++ continue; ++ ++ /* This was a PC-relative instruction that was completely resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ if (val != irelscan->r_addend) { ++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend ++ + isym->st_value, ++ 0, ++ sec); ++ } ++ } ++ else if ((ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO) ++ || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO)) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ immediate = instr & 0x0000ffff; ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ } ++ ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ offset = calc_fixup (irelscan->r_addend, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ } ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_64 (abfd, ocontents ++ + irelscan->r_offset, immediate); ++ } ++ } ++ } ++ } ++ ++ /* Adjust the local symbols defined in this section. */ ++ isymend = isymbuf + symtab_hdr->sh_info; ++ for (isym = isymbuf; isym < isymend; isym++) ++ { ++ if (isym->st_shndx == shndx) ++ { ++ isym->st_value -= calc_fixup (isym->st_value, 0, sec); ++ if (isym->st_size) ++ isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec); ++ } ++ } ++ ++ /* Now adjust the global symbols defined in this section. */ ++ isym = isymbuf + symtab_hdr->sh_info; ++ symcount = (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info; ++ for (sym_index = 0; sym_index < symcount; sym_index++) ++ { ++ sym_hash = elf_sym_hashes (abfd)[sym_index]; ++ if ((sym_hash->root.type == bfd_link_hash_defined ++ || sym_hash->root.type == bfd_link_hash_defweak) ++ && sym_hash->root.u.def.section == sec) ++ { ++ sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value, ++ 0, sec); ++ if (sym_hash->size) ++ sym_hash->size -= calc_fixup (sym_hash->root.u.def.value, ++ sym_hash->size, sec); ++ } ++ } ++ ++ /* Physically move the code and change the cooked size. */ ++ dest = sec->relax[0].addr; ++ for (i = 0; i < sec->relax_count; i++) ++ { ++ int len; ++ src = sec->relax[i].addr + sec->relax[i].size; ++ len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size; ++ ++ memmove (contents + dest, contents + src, len); ++ sec->size -= sec->relax[i].size; ++ dest += len; ++ } ++ ++ elf_section_data (sec)->relocs = internal_relocs; ++ free_relocs = NULL; ++ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ free_contents = NULL; ++ ++ symtab_hdr->contents = (bfd_byte *) isymbuf; ++ } ++ ++ if (free_relocs != NULL) ++ { ++ free (free_relocs); ++ free_relocs = NULL; ++ } ++ ++ if (free_contents != NULL) ++ { ++ if (!link_info->keep_memory) ++ free (free_contents); ++ else ++ /* Cache the section contents for elf_link_input_bfd. */ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ free_contents = NULL; ++ } ++ ++ if (sec->relax_count == 0) ++ { ++ *again = FALSE; ++ free (sec->relax); ++ sec->relax = NULL; ++ } ++ else ++ *again = TRUE; ++ return TRUE; ++ ++ error_return: ++ if (free_relocs != NULL) ++ free (free_relocs); ++ if (free_contents != NULL) ++ free (free_contents); ++ if (sec->relax != NULL) ++ { ++ free (sec->relax); ++ sec->relax = NULL; ++ sec->relax_count = 0; ++ } ++ return FALSE; ++} ++ ++/* Return the section that should be marked against GC for a given ++ relocation. */ ++ ++static asection * ++microblaze_elf_gc_mark_hook (asection *sec, ++ struct bfd_link_info * info, ++ Elf_Internal_Rela * rel, ++ struct elf_link_hash_entry * h, ++ Elf_Internal_Sym * sym) ++{ ++ if (h != NULL) ++ switch (ELF64_R_TYPE (rel->r_info)) ++ { ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ case R_MICROBLAZE_GNU_VTENTRY: ++ return NULL; ++ } ++ ++ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); ++} ++ ++/* Update the got entry reference counts for the section being removed. */ ++ ++static bfd_boolean ++microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info * info ATTRIBUTE_UNUSED, ++ asection * sec ATTRIBUTE_UNUSED, ++ const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) ++{ ++ return TRUE; ++} ++ ++/* PIC support. */ ++ ++#define PLT_ENTRY_SIZE 16 ++ ++#define PLT_ENTRY_WORD_0 0xb0000000 /* "imm 0". */ ++#define PLT_ENTRY_WORD_1 0xe9940000 /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT. */ ++#define PLT_ENTRY_WORD_1_NOPIC 0xe9800000 /* "lwi r12,r0,0" - non-PIC object. */ ++#define PLT_ENTRY_WORD_2 0x98186000 /* "brad r12". */ ++#define PLT_ENTRY_WORD_3 0x80000000 /* "nop". */ ++ ++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up ++ shortcuts to them in our hash table. */ ++ ++static bfd_boolean ++create_got_section (bfd *dynobj, struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ ++ if (! _bfd_elf_create_got_section (dynobj, info)) ++ return FALSE; ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ htab->sgot = bfd_get_linker_section (dynobj, ".got"); ++ htab->sgotplt = bfd_get_linker_section (dynobj, ".got.plt"); ++ if (!htab->sgot || !htab->sgotplt) ++ return FALSE; ++ ++ if ((htab->srelgot = bfd_get_linker_section (dynobj, ".rela.got")) == NULL) ++ htab->srelgot = bfd_make_section_anyway (dynobj, ".rela.got"); ++ if (htab->srelgot == NULL ++ || ! bfd_set_section_flags (dynobj, htab->srelgot, SEC_ALLOC ++ | SEC_LOAD ++ | SEC_HAS_CONTENTS ++ | SEC_IN_MEMORY ++ | SEC_LINKER_CREATED ++ | SEC_READONLY) ++ || ! bfd_set_section_alignment (dynobj, htab->srelgot, 2)) ++ return FALSE; ++ return TRUE; ++} ++ ++static bfd_boolean ++update_local_sym_info (bfd *abfd, ++ Elf_Internal_Shdr *symtab_hdr, ++ unsigned long r_symndx, ++ unsigned int tls_type) ++{ ++ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd); ++ unsigned char *local_got_tls_masks; ++ ++ if (local_got_refcounts == NULL) ++ { ++ bfd_size_type size = symtab_hdr->sh_info; ++ ++ size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks)); ++ local_got_refcounts = bfd_zalloc (abfd, size); ++ if (local_got_refcounts == NULL) ++ return FALSE; ++ elf_local_got_refcounts (abfd) = local_got_refcounts; ++ } ++ ++ local_got_tls_masks = ++ (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info); ++ local_got_tls_masks[r_symndx] |= tls_type; ++ local_got_refcounts[r_symndx] += 1; ++ ++ return TRUE; ++} ++/* Look through the relocs for a section during the first phase. */ ++ ++static bfd_boolean ++microblaze_elf_check_relocs (bfd * abfd, ++ struct bfd_link_info * info, ++ asection * sec, ++ const Elf_Internal_Rela * relocs) ++{ ++ Elf_Internal_Shdr * symtab_hdr; ++ struct elf_link_hash_entry ** sym_hashes; ++ struct elf_link_hash_entry ** sym_hashes_end; ++ const Elf_Internal_Rela * rel; ++ const Elf_Internal_Rela * rel_end; ++ struct elf64_mb_link_hash_table *htab; ++ asection *sreloc = NULL; ++ ++ if (bfd_link_relocatable (info)) ++ return TRUE; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ symtab_hdr = & elf_tdata (abfd)->symtab_hdr; ++ sym_hashes = elf_sym_hashes (abfd); ++ sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (!elf_bad_symtab (abfd)) ++ sym_hashes_end -= symtab_hdr->sh_info; ++ ++ rel_end = relocs + sec->reloc_count; ++ ++ for (rel = relocs; rel < rel_end; rel++) ++ { ++ unsigned int r_type; ++ struct elf_link_hash_entry * h; ++ unsigned long r_symndx; ++ unsigned char tls_type = 0; ++ ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ r_type = ELF64_R_TYPE (rel->r_info); ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ h = NULL; ++ else ++ { ++ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; ++ ++ /* PR15323, ref flags aren't set for references in the same ++ object. */ ++ h->root.non_ir_ref = 1; ++ } ++ ++ switch (r_type) ++ { ++ /* This relocation describes the C++ object vtable hierarchy. ++ Reconstruct it for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) ++ return FALSE; ++ break; ++ ++ /* This relocation describes which C++ vtable entries are actually ++ used. Record for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTENTRY: ++ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) ++ return FALSE; ++ break; ++ ++ /* This relocation requires .plt entry. */ ++ case R_MICROBLAZE_PLT_64: ++ if (h != NULL) ++ { ++ h->needs_plt = 1; ++ h->plt.refcount += 1; ++ } ++ break; ++ ++ /* This relocation requires .got entry. */ ++ case R_MICROBLAZE_TLSGD: ++ tls_type |= (TLS_TLS | TLS_GD); ++ goto dogottls; ++ case R_MICROBLAZE_TLSLD: ++ tls_type |= (TLS_TLS | TLS_LD); ++ dogottls: ++ sec->has_tls_reloc = 1; ++ case R_MICROBLAZE_GOT_64: ++ if (htab->sgot == NULL) ++ { ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ if (!create_got_section (htab->elf.dynobj, info)) ++ return FALSE; ++ } ++ if (h != NULL) ++ { ++ h->got.refcount += 1; ++ elf64_mb_hash_entry (h)->tls_mask |= tls_type; ++ } ++ else ++ { ++ if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) ) ++ return FALSE; ++ } ++ break; ++ ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_64_PCREL: ++ case R_MICROBLAZE_32: ++ { ++ if (h != NULL && !bfd_link_pic (info)) ++ { ++ /* we may need a copy reloc. */ ++ h->non_got_ref = 1; ++ ++ /* we may also need a .plt entry. */ ++ h->plt.refcount += 1; ++ if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL) ++ h->pointer_equality_needed = 1; ++ } ++ ++ ++ /* If we are creating a shared library, and this is a reloc ++ against a global symbol, or a non PC relative reloc ++ against a local symbol, then we need to copy the reloc ++ into the shared library. However, if we are linking with ++ -Bsymbolic, we do not need to copy a reloc against a ++ global symbol which is defined in an object we are ++ including in the link (i.e., DEF_REGULAR is set). At ++ this point we have not seen all the input files, so it is ++ possible that DEF_REGULAR is not set now but will be set ++ later (it is never cleared). In case of a weak definition, ++ DEF_REGULAR may be cleared later by a strong definition in ++ a shared library. We account for that possibility below by ++ storing information in the relocs_copied field of the hash ++ table entry. A similar situation occurs when creating ++ shared libraries and symbol visibility changes render the ++ symbol local. ++ ++ If on the other hand, we are creating an executable, we ++ may need to keep relocations for symbols satisfied by a ++ dynamic library if we manage to avoid copy relocs for the ++ symbol. */ ++ ++ if ((bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && (r_type != R_MICROBLAZE_64_PCREL ++ || (h != NULL ++ && (! info->symbolic ++ || h->root.type == bfd_link_hash_defweak ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && h != NULL ++ && (h->root.type == bfd_link_hash_defweak ++ || !h->def_regular))) ++ { ++ struct elf64_mb_dyn_relocs *p; ++ struct elf64_mb_dyn_relocs **head; ++ ++ /* When creating a shared object, we must copy these ++ relocs into the output file. We create a reloc ++ section in dynobj and make room for the reloc. */ ++ ++ if (sreloc == NULL) ++ { ++ bfd *dynobj; ++ ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ dynobj = htab->elf.dynobj; ++ ++ sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, ++ 2, abfd, 1); ++ if (sreloc == NULL) ++ return FALSE; ++ } ++ ++ /* If this is a global symbol, we count the number of ++ relocations we need for this symbol. */ ++ if (h != NULL) ++ head = &((struct elf64_mb_link_hash_entry *) h)->dyn_relocs; ++ else ++ { ++ /* Track dynamic relocs needed for local syms too. ++ We really need local syms available to do this ++ easily. Oh well. */ ++ ++ asection *s; ++ Elf_Internal_Sym *isym; ++ void *vpp; ++ ++ isym = bfd_sym_from_r_symndx (&htab->sym_sec, ++ abfd, r_symndx); ++ if (isym == NULL) ++ return FALSE; ++ ++ s = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ if (s == NULL) ++ return FALSE; ++ ++ vpp = &elf_section_data (s)->local_dynrel; ++ head = (struct elf64_mb_dyn_relocs **) vpp; ++ } ++ ++ p = *head; ++ if (p == NULL || p->sec != sec) ++ { ++ bfd_size_type amt = sizeof *p; ++ p = ((struct elf64_mb_dyn_relocs *) ++ bfd_alloc (htab->elf.dynobj, amt)); ++ if (p == NULL) ++ return FALSE; ++ p->next = *head; ++ *head = p; ++ p->sec = sec; ++ p->count = 0; ++ p->pc_count = 0; ++ } ++ ++ p->count += 1; ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ p->pc_count += 1; ++ } ++ } ++ break; ++ } ++ } ++ ++ return TRUE; ++} ++ ++static bfd_boolean ++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ if (!htab->sgot && !create_got_section (dynobj, info)) ++ return FALSE; ++ ++ if (!_bfd_elf_create_dynamic_sections (dynobj, info)) ++ return FALSE; ++ ++ htab->splt = bfd_get_linker_section (dynobj, ".plt"); ++ htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt"); ++ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss"); ++ if (!bfd_link_pic (info)) ++ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss"); ++ ++ if (!htab->splt || !htab->srelplt || !htab->sdynbss ++ || (!bfd_link_pic (info) && !htab->srelbss)) ++ abort (); ++ ++ return TRUE; ++} ++ ++/* Copy the extra info we tack onto an elf_link_hash_entry. */ ++ ++static void ++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *dir, ++ struct elf_link_hash_entry *ind) ++{ ++ struct elf64_mb_link_hash_entry *edir, *eind; ++ ++ edir = (struct elf64_mb_link_hash_entry *) dir; ++ eind = (struct elf64_mb_link_hash_entry *) ind; ++ ++ if (eind->dyn_relocs != NULL) ++ { ++ if (edir->dyn_relocs != NULL) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (ind->root.type == bfd_link_hash_indirect) ++ abort (); ++ ++ /* Add reloc counts against the weak sym to the strong sym ++ list. Merge any entries against the same section. */ ++ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ struct elf64_mb_dyn_relocs *q; ++ ++ for (q = edir->dyn_relocs; q != NULL; q = q->next) ++ if (q->sec == p->sec) ++ { ++ q->pc_count += p->pc_count; ++ q->count += p->count; ++ *pp = p->next; ++ break; ++ } ++ if (q == NULL) ++ pp = &p->next; ++ } ++ *pp = edir->dyn_relocs; ++ } ++ ++ edir->dyn_relocs = eind->dyn_relocs; ++ eind->dyn_relocs = NULL; ++ } ++ ++ edir->tls_mask |= eind->tls_mask; ++ ++ _bfd_elf_link_hash_copy_indirect (info, dir, ind); ++} ++ ++static bfd_boolean ++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *h) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry * eh; ++ struct elf64_mb_dyn_relocs *p; ++ asection *sdynbss, *s; ++ unsigned int power_of_two; ++ bfd *dynobj; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ /* If this is a function, put it in the procedure linkage table. We ++ will fill in the contents of the procedure linkage table later, ++ when we know the address of the .got section. */ ++ if (h->type == STT_FUNC ++ || h->needs_plt) ++ { ++ if (h->plt.refcount <= 0 ++ || SYMBOL_CALLS_LOCAL (info, h) ++ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT ++ && h->root.type == bfd_link_hash_undefweak)) ++ { ++ /* This case can occur if we saw a PLT reloc in an input ++ file, but the symbol was never referred to by a dynamic ++ object, or if all references were garbage collected. In ++ such a case, we don't actually need to build a procedure ++ linkage table, and we can just do a PC32 reloc instead. */ ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ return TRUE; ++ } ++ else ++ /* It's possible that we incorrectly decided a .plt reloc was ++ needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in ++ check_relocs. We can't decide accurately between function and ++ non-function syms in check-relocs; Objects loaded later in ++ the link may change h->type. So fix it now. */ ++ h->plt.offset = (bfd_vma) -1; ++ ++ /* If this is a weak symbol, and there is a real definition, the ++ processor independent code will have arranged for us to see the ++ real definition first, and we can just use the same value. */ ++ if (h->u.weakdef != NULL) ++ { ++ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined ++ || h->u.weakdef->root.type == bfd_link_hash_defweak); ++ h->root.u.def.section = h->u.weakdef->root.u.def.section; ++ h->root.u.def.value = h->u.weakdef->root.u.def.value; ++ return TRUE; ++ } ++ ++ /* This is a reference to a symbol defined by a dynamic object which ++ is not a function. */ ++ ++ /* If we are creating a shared library, we must presume that the ++ only references to the symbol are via the global offset table. ++ For such cases we need not do anything here; the relocations will ++ be handled correctly by relocate_section. */ ++ if (bfd_link_pic (info)) ++ return TRUE; ++ ++ /* If there are no references to this symbol that do not use the ++ GOT, we don't need to generate a copy reloc. */ ++ if (!h->non_got_ref) ++ return TRUE; ++ ++ /* If -z nocopyreloc was given, we won't generate them either. */ ++ if (info->nocopyreloc) ++ { ++ h->non_got_ref = 0; ++ return TRUE; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ for (p = eh->dyn_relocs; p != NULL; p = p->next) ++ { ++ s = p->sec->output_section; ++ if (s != NULL && (s->flags & SEC_READONLY) != 0) ++ break; ++ } ++ ++ /* If we didn't find any dynamic relocs in read-only sections, then ++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ ++ if (p == NULL) ++ { ++ h->non_got_ref = 0; ++ return TRUE; ++ } ++ ++ /* We must allocate the symbol in our .dynbss section, which will ++ become part of the .bss section of the executable. There will be ++ an entry for this symbol in the .dynsym section. The dynamic ++ object will contain position independent code, so all references ++ from the dynamic object to this symbol will go through the global ++ offset table. The dynamic linker will use the .dynsym entry to ++ determine the address it must put in the global offset table, so ++ both the dynamic object and the regular object will refer to the ++ same memory location for the variable. */ ++ ++ /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker ++ to copy the initial value out of the dynamic object and into the ++ runtime process image. */ ++ dynobj = elf_hash_table (info)->dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) ++ { ++ htab->srelbss->size += sizeof (Elf64_External_Rela); ++ h->needs_copy = 1; ++ } ++ ++ /* We need to figure out the alignment required for this symbol. I ++ have no idea how ELF linkers handle this. */ ++ power_of_two = bfd_log2 (h->size); ++ if (power_of_two > 3) ++ power_of_two = 3; ++ ++ sdynbss = htab->sdynbss; ++ /* Apply the required alignment. */ ++ sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two)); ++ if (power_of_two > bfd_get_section_alignment (dynobj, sdynbss)) ++ { ++ if (! bfd_set_section_alignment (dynobj, sdynbss, power_of_two)) ++ return FALSE; ++ } ++ ++ /* Define the symbol as being at this point in the section. */ ++ h->root.u.def.section = sdynbss; ++ h->root.u.def.value = sdynbss->size; ++ ++ /* Increment the section size to make room for the symbol. */ ++ sdynbss->size += h->size; ++ return TRUE; ++} ++ ++/* Allocate space in .plt, .got and associated reloc sections for ++ dynamic relocs. */ ++ ++static bfd_boolean ++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat) ++{ ++ struct bfd_link_info *info; ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (h->root.type == bfd_link_hash_indirect) ++ return TRUE; ++ ++ info = (struct bfd_link_info *) dat; ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ if (htab->elf.dynamic_sections_created ++ && h->plt.refcount > 0) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return FALSE; ++ } ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h)) ++ { ++ asection *s = htab->splt; ++ ++ /* The first entry in .plt is reserved. */ ++ if (s->size == 0) ++ s->size = PLT_ENTRY_SIZE; ++ ++ h->plt.offset = s->size; ++ ++ /* If this symbol is not defined in a regular file, and we are ++ not generating a shared library, then set the symbol to this ++ location in the .plt. This is required to make function ++ pointers compare as equal between the normal executable and ++ the shared library. */ ++ if (! bfd_link_pic (info) ++ && !h->def_regular) ++ { ++ h->root.u.def.section = s; ++ h->root.u.def.value = h->plt.offset; ++ } ++ ++ /* Make room for this entry. */ ++ s->size += PLT_ENTRY_SIZE; ++ ++ /* We also need to make an entry in the .got.plt section, which ++ will be placed in the .got section by the linker script. */ ++ htab->sgotplt->size += 4; ++ ++ /* We also need to make an entry in the .rel.plt section. */ ++ htab->srelplt->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ if (h->got.refcount > 0) ++ { ++ unsigned int need; ++ asection *s; ++ ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return FALSE; ++ } ++ ++ need = 0; ++ if ((eh->tls_mask & TLS_TLS) != 0) ++ { ++ /* Handle TLS Symbol */ ++ if ((eh->tls_mask & TLS_LD) != 0) ++ { ++ if (!eh->elf.def_dynamic) ++ /* We'll just use htab->tlsld_got.offset. This should ++ always be the case. It's a little odd if we have ++ a local dynamic reloc against a non-local symbol. */ ++ htab->tlsld_got.refcount += 1; ++ else ++ need += 8; ++ } ++ if ((eh->tls_mask & TLS_GD) != 0) ++ need += 8; ++ } ++ else ++ { ++ /* Regular (non-TLS) symbol */ ++ need += 4; ++ } ++ if (need == 0) ++ { ++ h->got.offset = (bfd_vma) -1; ++ } ++ else ++ { ++ s = htab->sgot; ++ h->got.offset = s->size; ++ s->size += need; ++ htab->srelgot->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ h->got.offset = (bfd_vma) -1; ++ ++ if (eh->dyn_relocs == NULL) ++ return TRUE; ++ ++ /* In the shared -Bsymbolic case, discard space allocated for ++ dynamic pc-relative relocs against symbols which turn out to be ++ defined in regular objects. For the normal shared case, discard ++ space for pc-relative relocs that have become local due to symbol ++ visibility changes. */ ++ ++ if (bfd_link_pic (info)) ++ { ++ if (h->def_regular ++ && (h->forced_local ++ || info->symbolic)) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ ++ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ p->count -= p->pc_count; ++ p->pc_count = 0; ++ if (p->count == 0) ++ *pp = p->next; ++ else ++ pp = &p->next; ++ } ++ } ++ } ++ else ++ { ++ /* For the non-shared case, discard space for relocs against ++ symbols which turn out to need copy relocs or are not ++ dynamic. */ ++ ++ if (!h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || (htab->elf.dynamic_sections_created ++ && (h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined)))) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return FALSE; ++ } ++ ++ /* If that succeeded, we know we'll be keeping all the ++ relocs. */ ++ if (h->dynindx != -1) ++ goto keep; ++ } ++ ++ eh->dyn_relocs = NULL; ++ ++ keep: ; ++ } ++ ++ /* Finally, allocate space. */ ++ for (p = eh->dyn_relocs; p != NULL; p = p->next) ++ { ++ asection *sreloc = elf_section_data (p->sec)->sreloc; ++ sreloc->size += p->count * sizeof (Elf64_External_Rela); ++ } ++ ++ return TRUE; ++} ++ ++/* Set the sizes of the dynamic sections. */ ++ ++static bfd_boolean ++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ bfd *dynobj; ++ asection *s; ++ bfd *ibfd; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ dynobj = htab->elf.dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ ++ /* Set up .got offsets for local syms, and space for local dynamic ++ relocs. */ ++ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) ++ { ++ bfd_signed_vma *local_got; ++ bfd_signed_vma *end_local_got; ++ bfd_size_type locsymcount; ++ Elf_Internal_Shdr *symtab_hdr; ++ unsigned char *lgot_masks; ++ asection *srel; ++ ++ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) ++ continue; ++ ++ for (s = ibfd->sections; s != NULL; s = s->next) ++ { ++ struct elf64_mb_dyn_relocs *p; ++ ++ for (p = ((struct elf64_mb_dyn_relocs *) ++ elf_section_data (s)->local_dynrel); ++ p != NULL; ++ p = p->next) ++ { ++ if (!bfd_is_abs_section (p->sec) ++ && bfd_is_abs_section (p->sec->output_section)) ++ { ++ /* Input section has been discarded, either because ++ it is a copy of a linkonce section or due to ++ linker script /DISCARD/, so we'll be discarding ++ the relocs too. */ ++ } ++ else if (p->count != 0) ++ { ++ srel = elf_section_data (p->sec)->sreloc; ++ srel->size += p->count * sizeof (Elf64_External_Rela); ++ if ((p->sec->output_section->flags & SEC_READONLY) != 0) ++ info->flags |= DF_TEXTREL; ++ } ++ } ++ } ++ ++ local_got = elf_local_got_refcounts (ibfd); ++ if (!local_got) ++ continue; ++ ++ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; ++ locsymcount = symtab_hdr->sh_info; ++ end_local_got = local_got + locsymcount; ++ lgot_masks = (unsigned char *) end_local_got; ++ s = htab->sgot; ++ srel = htab->srelgot; ++ ++ for (; local_got < end_local_got; ++local_got, ++lgot_masks) ++ { ++ if (*local_got > 0) ++ { ++ unsigned int need = 0; ++ if ((*lgot_masks & TLS_TLS) != 0) ++ { ++ if ((*lgot_masks & TLS_GD) != 0) ++ need += 8; ++ if ((*lgot_masks & TLS_LD) != 0) ++ htab->tlsld_got.refcount += 1; ++ } ++ else ++ need += 4; ++ ++ if (need == 0) ++ { ++ *local_got = (bfd_vma) -1; ++ } ++ else ++ { ++ *local_got = s->size; ++ s->size += need; ++ if (bfd_link_pic (info)) ++ srel->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ *local_got = (bfd_vma) -1; ++ } ++ } ++ ++ /* Allocate global sym .plt and .got entries, and space for global ++ sym dynamic relocs. */ ++ elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info); ++ ++ if (htab->tlsld_got.refcount > 0) ++ { ++ htab->tlsld_got.offset = htab->sgot->size; ++ htab->sgot->size += 8; ++ if (bfd_link_pic (info)) ++ htab->srelgot->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ htab->tlsld_got.offset = (bfd_vma) -1; ++ ++ if (elf_hash_table (info)->dynamic_sections_created) ++ { ++ /* Make space for the trailing nop in .plt. */ ++ if (htab->splt->size > 0) ++ htab->splt->size += 4; ++ } ++ ++ /* The check_relocs and adjust_dynamic_symbol entry points have ++ determined the sizes of the various dynamic sections. Allocate ++ memory for them. */ ++ for (s = dynobj->sections; s != NULL; s = s->next) ++ { ++ const char *name; ++ bfd_boolean strip = FALSE; ++ ++ if ((s->flags & SEC_LINKER_CREATED) == 0) ++ continue; ++ ++ /* It's OK to base decisions on the section name, because none ++ of the dynobj section names depend upon the input files. */ ++ name = bfd_get_section_name (dynobj, s); ++ ++ if (strncmp (name, ".rela", 5) == 0) ++ { ++ if (s->size == 0) ++ { ++ /* If we don't need this section, strip it from the ++ output file. This is to handle .rela.bss and ++ .rela.plt. We must create it in ++ create_dynamic_sections, because it must be created ++ before the linker maps input sections to output ++ sections. The linker does that before ++ adjust_dynamic_symbol is called, and it is that ++ function which decides whether anything needs to go ++ into these sections. */ ++ strip = TRUE; ++ } ++ else ++ { ++ /* We use the reloc_count field as a counter if we need ++ to copy relocs into the output file. */ ++ s->reloc_count = 0; ++ } ++ } ++ else if (s != htab->splt && s != htab->sgot && s != htab->sgotplt) ++ { ++ /* It's not one of our sections, so don't allocate space. */ ++ continue; ++ } ++ ++ if (strip) ++ { ++ s->flags |= SEC_EXCLUDE; ++ continue; ++ } ++ ++ /* Allocate memory for the section contents. */ ++ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. ++ Unused entries should be reclaimed before the section's contents ++ are written out, but at the moment this does not happen. Thus in ++ order to prevent writing out garbage, we initialise the section's ++ contents to zero. */ ++ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); ++ if (s->contents == NULL && s->size != 0) ++ return FALSE; ++ } ++ ++ if (elf_hash_table (info)->dynamic_sections_created) ++ { ++ /* Add some entries to the .dynamic section. We fill in the ++ values later, in microblaze_elf_finish_dynamic_sections, but we ++ must add the entries now so that we get the correct size for ++ the .dynamic section. The DT_DEBUG entry is filled in by the ++ dynamic linker and used by the debugger. */ ++#define add_dynamic_entry(TAG, VAL) \ ++ _bfd_elf_add_dynamic_entry (info, TAG, VAL) ++ ++ if (bfd_link_executable (info)) ++ { ++ if (!add_dynamic_entry (DT_DEBUG, 0)) ++ return FALSE; ++ } ++ ++ if (!add_dynamic_entry (DT_RELA, 0) ++ || !add_dynamic_entry (DT_RELASZ, 0) ++ || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela))) ++ return FALSE; ++ ++ if (htab->splt->size != 0) ++ { ++ if (!add_dynamic_entry (DT_PLTGOT, 0) ++ || !add_dynamic_entry (DT_PLTRELSZ, 0) ++ || !add_dynamic_entry (DT_PLTREL, DT_RELA) ++ || !add_dynamic_entry (DT_JMPREL, 0) ++ || !add_dynamic_entry (DT_BIND_NOW, 1)) ++ return FALSE; ++ } ++ ++ if (info->flags & DF_TEXTREL) ++ { ++ if (!add_dynamic_entry (DT_TEXTREL, 0)) ++ return FALSE; ++ } ++ } ++#undef add_dynamic_entry ++ return TRUE; ++} ++ ++/* Finish up dynamic symbol handling. We set the contents of various ++ dynamic sections here. */ ++ ++static bfd_boolean ++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd, ++ struct bfd_link_info *info, ++ struct elf_link_hash_entry *h, ++ Elf_Internal_Sym *sym) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ if (h->plt.offset != (bfd_vma) -1) ++ { ++ asection *splt; ++ asection *srela; ++ asection *sgotplt; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ bfd_vma plt_index; ++ bfd_vma got_offset; ++ bfd_vma got_addr; ++ ++ /* This symbol has an entry in the procedure linkage table. Set ++ it up. */ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ splt = htab->splt; ++ srela = htab->srelplt; ++ sgotplt = htab->sgotplt; ++ BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL); ++ ++ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved. */ ++ got_offset = (plt_index + 3) * 4; /* 3 reserved ??? */ ++ got_addr = got_offset; ++ ++ /* For non-PIC objects we need absolute address of the GOT entry. */ ++ if (!bfd_link_pic (info)) ++ got_addr += htab->sgotplt->output_section->vma + sgotplt->output_offset; ++ ++ /* Fill in the entry in the procedure linkage table. */ ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff), ++ splt->contents + h->plt.offset); ++ if (bfd_link_pic (info)) ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ else ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2, ++ splt->contents + h->plt.offset + 8); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3, ++ splt->contents + h->plt.offset + 12); ++ ++ /* Any additions to the .got section??? */ ++ /* bfd_put_32 (output_bfd, ++ splt->output_section->vma + splt->output_offset + h->plt.offset + 4, ++ sgotplt->contents + got_offset); */ ++ ++ /* Fill in the entry in the .rela.plt section. */ ++ rela.r_offset = (sgotplt->output_section->vma ++ + sgotplt->output_offset ++ + got_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT); ++ rela.r_addend = 0; ++ loc = srela->contents; ++ loc += plt_index * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); ++ ++ if (!h->def_regular) ++ { ++ /* Mark the symbol as undefined, rather than as defined in ++ the .plt section. Zero the value. */ ++ sym->st_shndx = SHN_UNDEF; ++ sym->st_value = 0; ++ } ++ } ++ ++ /* h->got.refcount to be checked ? */ ++ if (h->got.offset != (bfd_vma) -1 && ++ ! ((h->got.offset & 1) || ++ IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask))) ++ { ++ asection *sgot; ++ asection *srela; ++ bfd_vma offset; ++ ++ /* This symbol has an entry in the global offset table. Set it ++ up. */ ++ ++ sgot = htab->sgot; ++ srela = htab->srelgot; ++ BFD_ASSERT (sgot != NULL && srela != NULL); ++ ++ offset = (sgot->output_section->vma + sgot->output_offset ++ + (h->got.offset &~ (bfd_vma) 1)); ++ ++ /* If this is a -Bsymbolic link, and the symbol is defined ++ locally, we just want to emit a RELATIVE reloc. Likewise if ++ the symbol was forced to be local because of a version file. ++ The entry in the global offset table will already have been ++ initialized in the relocate_section function. */ ++ if (bfd_link_pic (info) ++ && ((info->symbolic && h->def_regular) ++ || h->dynindx == -1)) ++ { ++ asection *sec = h->root.u.def.section; ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ /* symindex= */ 0, ++ R_MICROBLAZE_REL, offset, ++ h->root.u.def.value ++ + sec->output_section->vma ++ + sec->output_offset); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ h->dynindx, ++ R_MICROBLAZE_GLOB_DAT, ++ offset, 0); ++ } ++ ++ bfd_put_32 (output_bfd, (bfd_vma) 0, ++ sgot->contents + (h->got.offset &~ (bfd_vma) 1)); ++ } ++ ++ if (h->needs_copy) ++ { ++ asection *s; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ ++ /* This symbols needs a copy reloc. Set it up. */ ++ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ s = bfd_get_linker_section (htab->elf.dynobj, ".rela.bss"); ++ BFD_ASSERT (s != NULL); ++ ++ rela.r_offset = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY); ++ rela.r_addend = 0; ++ loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); ++ } ++ ++ /* Mark some specially defined symbols as absolute. */ ++ if (h == htab->elf.hdynamic ++ || h == htab->elf.hgot ++ || h == htab->elf.hplt) ++ sym->st_shndx = SHN_ABS; ++ ++ return TRUE; ++} ++ ++ ++/* Finish up the dynamic sections. */ ++ ++static bfd_boolean ++microblaze_elf_finish_dynamic_sections (bfd *output_bfd, ++ struct bfd_link_info *info) ++{ ++ bfd *dynobj; ++ asection *sdyn, *sgot; ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ dynobj = htab->elf.dynobj; ++ ++ sdyn = bfd_get_linker_section (dynobj, ".dynamic"); ++ ++ if (htab->elf.dynamic_sections_created) ++ { ++ asection *splt; ++ Elf64_External_Dyn *dyncon, *dynconend; ++ ++ splt = bfd_get_linker_section (dynobj, ".plt"); ++ BFD_ASSERT (splt != NULL && sdyn != NULL); ++ ++ dyncon = (Elf64_External_Dyn *) sdyn->contents; ++ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size); ++ for (; dyncon < dynconend; dyncon++) ++ { ++ Elf_Internal_Dyn dyn; ++ const char *name; ++ bfd_boolean size; ++ ++ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn); ++ ++ switch (dyn.d_tag) ++ { ++ case DT_PLTGOT: name = ".got.plt"; size = FALSE; break; ++ case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break; ++ case DT_JMPREL: name = ".rela.plt"; size = FALSE; break; ++ case DT_RELA: name = ".rela.dyn"; size = FALSE; break; ++ case DT_RELASZ: name = ".rela.dyn"; size = TRUE; break; ++ default: name = NULL; size = FALSE; break; ++ } ++ ++ if (name != NULL) ++ { ++ asection *s; ++ ++ s = bfd_get_section_by_name (output_bfd, name); ++ if (s == NULL) ++ dyn.d_un.d_val = 0; ++ else ++ { ++ if (! size) ++ dyn.d_un.d_ptr = s->vma; ++ else ++ dyn.d_un.d_val = s->size; ++ } ++ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon); ++ } ++ } ++ ++ /* Clear the first entry in the procedure linkage table, ++ and put a nop in the last four bytes. */ ++ if (splt->size > 0) ++ { ++ memset (splt->contents, 0, PLT_ENTRY_SIZE); ++ bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop. */, ++ splt->contents + splt->size - 4); ++ } ++ ++ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; ++ } ++ ++ /* Set the first entry in the global offset table to the address of ++ the dynamic section. */ ++ sgot = bfd_get_linker_section (dynobj, ".got.plt"); ++ if (sgot && sgot->size > 0) ++ { ++ if (sdyn == NULL) ++ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); ++ else ++ bfd_put_32 (output_bfd, ++ sdyn->output_section->vma + sdyn->output_offset, ++ sgot->contents); ++ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; ++ } ++ ++ if (htab->sgot && htab->sgot->size > 0) ++ elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4; ++ ++ return TRUE; ++} ++ ++/* Hook called by the linker routine which adds symbols from an object ++ file. We use it to put .comm items in .sbss, and not .bss. */ ++ ++static bfd_boolean ++microblaze_elf_add_symbol_hook (bfd *abfd, ++ struct bfd_link_info *info, ++ Elf_Internal_Sym *sym, ++ const char **namep ATTRIBUTE_UNUSED, ++ flagword *flagsp ATTRIBUTE_UNUSED, ++ asection **secp, ++ bfd_vma *valp) ++{ ++ if (sym->st_shndx == SHN_COMMON ++ && !bfd_link_relocatable (info) ++ && sym->st_size <= elf_gp_size (abfd)) ++ { ++ /* Common symbols less than or equal to -G nn bytes are automatically ++ put into .sbss. */ ++ *secp = bfd_make_section_old_way (abfd, ".sbss"); ++ if (*secp == NULL ++ || ! bfd_set_section_flags (abfd, *secp, SEC_IS_COMMON)) ++ return FALSE; ++ ++ *valp = sym->st_size; ++ } ++ ++ return TRUE; ++} ++ ++#define TARGET_LITTLE_SYM microblaze_elf64_le_vec ++#define TARGET_LITTLE_NAME "elf64-microblazeel" ++ ++#define TARGET_BIG_SYM microblaze_elf64_vec ++#define TARGET_BIG_NAME "elf64-microblaze" ++ ++#define ELF_ARCH bfd_arch_microblaze ++#define ELF_TARGET_ID MICROBLAZE_ELF_DATA ++#define ELF_MACHINE_CODE EM_MICROBLAZE ++#define ELF_MACHINE_ALT1 EM_MICROBLAZE_OLD ++#define ELF_MAXPAGESIZE 0x1000 ++#define elf_info_to_howto microblaze_elf_info_to_howto ++#define elf_info_to_howto_rel NULL ++ ++#define bfd_elf64_bfd_reloc_type_lookup microblaze_elf_reloc_type_lookup ++#define bfd_elf64_bfd_is_local_label_name microblaze_elf_is_local_label_name ++#define elf_backend_relocate_section microblaze_elf_relocate_section ++#define bfd_elf64_bfd_relax_section microblaze_elf_relax_section ++#define bfd_elf64_bfd_merge_private_bfd_data microblaze_elf_merge_private_bfd_data ++#define bfd_elf64_bfd_reloc_name_lookup microblaze_elf_reloc_name_lookup ++ ++#define elf_backend_gc_mark_hook microblaze_elf_gc_mark_hook ++#define elf_backend_gc_sweep_hook microblaze_elf_gc_sweep_hook ++#define elf_backend_check_relocs microblaze_elf_check_relocs ++#define elf_backend_copy_indirect_symbol microblaze_elf_copy_indirect_symbol ++#define bfd_elf64_bfd_link_hash_table_create microblaze_elf_link_hash_table_create ++#define elf_backend_can_gc_sections 1 ++#define elf_backend_can_refcount 1 ++#define elf_backend_want_got_plt 1 ++#define elf_backend_plt_readonly 1 ++#define elf_backend_got_header_size 12 ++#define elf_backend_rela_normal 1 ++ ++#define elf_backend_adjust_dynamic_symbol microblaze_elf_adjust_dynamic_symbol ++#define elf_backend_create_dynamic_sections microblaze_elf_create_dynamic_sections ++#define elf_backend_finish_dynamic_sections microblaze_elf_finish_dynamic_sections ++#define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol ++#define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections ++#define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook ++ ++#include "elf64-target.h" +diff --git a/bfd/targets.c b/bfd/targets.c +index 158168cb3b..ef567a30c8 100644 +--- a/bfd/targets.c ++++ b/bfd/targets.c +@@ -706,6 +706,8 @@ extern const bfd_target mep_elf32_le_vec; + extern const bfd_target metag_elf32_vec; + extern const bfd_target microblaze_elf32_vec; + extern const bfd_target microblaze_elf32_le_vec; ++extern const bfd_target microblaze_elf64_vec; ++extern const bfd_target microblaze_elf64_le_vec; + extern const bfd_target mips_ecoff_be_vec; + extern const bfd_target mips_ecoff_le_vec; + extern const bfd_target mips_ecoff_bele_vec; +@@ -1073,6 +1075,10 @@ static const bfd_target * const _bfd_target_vector[] = + + &metag_elf32_vec, + ++#ifdef BFD64 ++ µblaze_elf64_vec, ++ µblaze_elf64_le_vec, ++#endif + µblaze_elf32_vec, + + &mips_ecoff_be_vec, +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 16b10d00a9..c79434785a 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -35,10 +35,13 @@ + #define streq(a,b) (strcmp (a, b) == 0) + #endif + ++static int microblaze_arch_size = 0; ++ + #define OPTION_EB (OPTION_MD_BASE + 0) + #define OPTION_EL (OPTION_MD_BASE + 1) + #define OPTION_LITTLE (OPTION_MD_BASE + 2) + #define OPTION_BIG (OPTION_MD_BASE + 3) ++#define OPTION_M64 (OPTION_MD_BASE + 4) + + void microblaze_generate_symbol (char *sym); + static bfd_boolean check_spl_reg (unsigned *); +@@ -773,6 +776,74 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) + return new_pointer; + } + ++ static char * ++parse_imml (char * s, expressionS * e, long min, long max) ++{ ++ char *new_pointer; ++ char *atp; ++ int itype, ilen; ++ ++ ilen = 0; ++ ++ /* Find the start of "@GOT" or "@PLT" suffix (if any) */ ++ for (atp = s; *atp != '@'; atp++) ++ if (is_end_of_line[(unsigned char) *atp]) ++ break; ++ ++ if (*atp == '@') ++ { ++ itype = match_imm (atp + 1, &ilen); ++ if (itype != 0) ++ { ++ *atp = 0; ++ e->X_md = itype; ++ } ++ else ++ { ++ atp = NULL; ++ e->X_md = 0; ++ ilen = 0; ++ } ++ *atp = 0; ++ } ++ else ++ { ++ atp = NULL; ++ e->X_md = 0; ++ } ++ ++ if (atp && !GOT_symbol) ++ { ++ GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); ++ } ++ ++ new_pointer = parse_exp (s, e); ++ ++ if (!GOT_symbol && ! strncmp (s, GOT_SYMBOL_NAME, 20)) ++ { ++ GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); ++ } ++ ++ if (e->X_op == O_absent) ++ ; /* An error message has already been emitted. */ ++ else if ((e->X_op != O_constant && e->X_op != O_symbol) ) ++ as_fatal (_("operand must be a constant or a label")); ++ else if ((e->X_op == O_constant) && ((long) e->X_add_number < min ++ || (long) e->X_add_number > max)) ++ { ++ as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"), ++ min, max, (long) e->X_add_number); ++ } ++ ++ if (atp) ++ { ++ *atp = '@'; /* restore back (needed?) */ ++ if (new_pointer >= atp) ++ new_pointer += ilen + 1; /* sizeof (imm_suffix) + 1 for '@' */ ++ } ++ return new_pointer; ++} ++ + static char * + check_got (int * got_type, int * got_len) + { +@@ -920,6 +991,7 @@ md_assemble (char * str) + unsigned int immed, immed2, temp; + expressionS exp; + char name[20]; ++ long immedl; + + /* Drop leading whitespace. */ + while (ISSPACE (* str)) +@@ -1129,7 +1201,7 @@ md_assemble (char * str) + } + break; + +- case INST_TYPE_RD_R1_IMM5: ++ case INST_TYPE_RD_R1_IMMS: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else +@@ -1163,16 +1235,22 @@ md_assemble (char * str) + immed = exp.X_add_number; + } + +- if (immed != (immed % 32)) ++ if ((immed != (immed % 32)) && ++ (opcode->instr == bslli || opcode->instr == bsrai || opcode->instr == bsrli)) + { + as_warn (_("Shift value > 32. using <value %% 32>")); + immed = immed % 32; + } ++ else if (immed != (immed % 64)) ++ { ++ as_warn (_("Shift value > 64. using <value %% 64>")); ++ immed = immed % 64; ++ } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM5_MASK; ++ inst |= (immed << IMM_LOW) & IMM6_MASK; + break; +- case INST_TYPE_RD_R1_IMM5_IMM5: ++ case INST_TYPE_RD_R1_IMMW_IMMS: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else +@@ -1196,7 +1274,7 @@ md_assemble (char * str) + + /* Width immediate value. */ + if (strcmp (op_end, "")) +- op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH); ++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM); + else + as_fatal (_("Error in statement syntax")); + if (exp.X_op != O_constant) +@@ -1208,6 +1286,8 @@ md_assemble (char * str) + immed = exp.X_add_number; + if (opcode->instr == bsefi && immed > 31) + as_fatal (_("Width value must be less than 32")); ++ else if (opcode->instr == bslefi && immed > 63) ++ as_fatal (_("Width value must be less than 64")); + + /* Shift immediate value. */ + if (strcmp (op_end, "")) +@@ -1215,32 +1295,40 @@ md_assemble (char * str) + else + as_fatal (_("Error in statement syntax")); + if (exp.X_op != O_constant) +- { ++ { + as_warn (_("Symbol used as immediate shift value for bit field instruction")); + immed2 = 0; + } + else +- { ++ { + output = frag_more (isize); + immed2 = exp.X_add_number; +- } +- if (immed2 != (immed2 % 32)) +- { +- as_warn (_("Shift value greater than 32. using <value %% 32>")); ++ } ++ if ((immed2 != (immed2 % 32)) && (opcode->instr == bsefi || opcode->instr == bsifi)) ++ { ++ ++ as_warn (_("Shift value greater than 32. using <value %% 32>")); + immed2 = immed2 % 32; + } ++ else if (immed2 != (immed2 % 64)) ++ { ++ as_warn (_("Shift value greater than 64. using <value %% 64>")); ++ immed2 = immed2 % 64; ++ } + + /* Check combined value. */ +- if (immed + immed2 > 32) ++ if ((immed + immed2 > 32) && (opcode->instr == bsefi || opcode->instr == bsifi)) + as_fatal (_("Width value + shift value must not be greater than 32")); + ++ else if (immed + immed2 > 64) ++ as_fatal (_("Width value + shift value must not be greater than 64")); + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; +- if (opcode->instr == bsefi) +- inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */ ++ if (opcode->instr == bsefi || opcode->instr == bslefi) ++ inst |= (immed & IMM6_MASK) << IMM_WIDTH_LOW; /* bsefi or bslefi */ + else +- inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */ +- inst |= (immed2 << IMM_LOW) & IMM5_MASK; ++ inst |= ((immed + immed2 - 1) & IMM6_MASK) << IMM_WIDTH_LOW; /* bsifi or bslifi */ ++ inst |= (immed2 << IMM_LOW) & IMM6_MASK; + break; + case INST_TYPE_R1_R2: + if (strcmp (op_end, "")) +@@ -1808,6 +1896,142 @@ md_assemble (char * str) + } + inst |= (immed << IMM_MBAR); + break; ++ /* For 64-bit instructions */ ++ case INST_TYPE_RD_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg2 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (& reg1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ if (check_spl_reg (& reg2)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (®1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ ++ inst |= (reg1 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_IMML: ++ as_fatal (_("An IMML instruction should not be present in the .s file")); ++ break; + + default: + as_fatal (_("unimplemented opcode \"%s\""), name); +@@ -1918,6 +2142,7 @@ struct option md_longopts[] = + {"EL", no_argument, NULL, OPTION_EL}, + {"mlittle-endian", no_argument, NULL, OPTION_LITTLE}, + {"mbig-endian", no_argument, NULL, OPTION_BIG}, ++ {"m64", no_argument, NULL, OPTION_M64}, + { NULL, no_argument, NULL, 0} + }; + +@@ -2569,6 +2794,18 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + return rel; + } + ++/* Called by TARGET_FORMAT. */ ++const char * ++microblaze_target_format (void) ++{ ++ ++ if (microblaze_arch_size == 64) ++ return "elf64-microblazeel"; ++ else ++ return target_big_endian ? "elf32-microblaze" : "elf32-microblazeel"; ++} ++ ++ + int + md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + { +@@ -2582,6 +2819,10 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + case OPTION_LITTLE: + target_big_endian = 0; + break; ++ case OPTION_M64: ++ //if (arg != NULL && strcmp (arg, "64") == 0) ++ microblaze_arch_size = 64; ++ break; + default: + return 0; + } +@@ -2597,6 +2838,7 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED) + fprintf (stream, _(" MicroBlaze specific assembler options:\n")); + fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu")); + fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu")); ++ fprintf (stream, " -%-23s%s\n", "m64", N_("generate 64-bit elf")); + } + + +diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h +index ca9dbb861f..9d38d2ced5 100644 +--- a/gas/config/tc-microblaze.h ++++ b/gas/config/tc-microblaze.h +@@ -78,7 +78,9 @@ extern const struct relax_type md_relax_table[]; + + #ifdef OBJ_ELF + +-#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel") ++#define TARGET_FORMAT microblaze_target_format() ++extern const char *microblaze_target_format (void); ++//#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel") + + #define ELF_TC_SPECIAL_SECTIONS \ + { ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, \ +diff --git a/include/elf/common.h b/include/elf/common.h +index 996acf9703..2f1e5be366 100644 +--- a/include/elf/common.h ++++ b/include/elf/common.h +@@ -339,6 +339,7 @@ + #define EM_RISCV 243 /* RISC-V */ + #define EM_LANAI 244 /* Lanai 32-bit processor. */ + #define EM_BPF 247 /* Linux BPF – in-kernel virtual machine. */ ++#define EM_MB_64 248 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ + #define EM_NFP 250 /* Netronome Flow Processor. */ + #define EM_CSKY 252 /* C-SKY processor family. */ + +diff --git a/ld/Makefile.am b/ld/Makefile.am +index c2c798b4fe..b272f537e4 100644 +--- a/ld/Makefile.am ++++ b/ld/Makefile.am +@@ -422,6 +422,8 @@ ALL_64_EMULATION_SOURCES = \ + eelf32ltsmipn32.c \ + eelf32ltsmipn32_fbsd.c \ + eelf32mipswindiss.c \ ++ eelf64microblazeel.c \ ++ eelf64microblaze.c \ + eelf64_aix.c \ + eelf64_ia64.c \ + eelf64_ia64_fbsd.c \ +@@ -1702,6 +1704,12 @@ eelf32_x86_64_nacl.c: $(srcdir)/emulparams/elf32_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ++eelf64microblazeel.c: $(srcdir)/emulparams/elf64microblazeel.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ ++eelf64microblaze.c: $(srcdir)/emulparams/elf64microblaze.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ + eelf64_aix.c: $(srcdir)/emulparams/elf64_aix.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + +diff --git a/ld/Makefile.in b/ld/Makefile.in +index fc687fc516..1a530ad729 100644 +--- a/ld/Makefile.in ++++ b/ld/Makefile.in +@@ -907,6 +907,8 @@ ALL_64_EMULATION_SOURCES = \ + eelf32ltsmipn32.c \ + eelf32ltsmipn32_fbsd.c \ + eelf32mipswindiss.c \ ++ eelf64microblazeel.c \ ++ eelf64microblaze.c \ + eelf64_aix.c \ + eelf64_ia64.c \ + eelf64_ia64_fbsd.c \ +@@ -1355,6 +1357,8 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_fbsd.Po@am__quote@ +@@ -3306,6 +3310,12 @@ eelf32_x86_64_nacl.c: $(srcdir)/emulparams/elf32_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ++eelf64microblazeel.c: $(srcdir)/emulparams/elf64microblazeel.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ ++eelf64microblaze.c: $(srcdir)/emulparams/elf64microblaze.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ + eelf64_aix.c: $(srcdir)/emulparams/elf64_aix.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + +diff --git a/ld/configure.tgt b/ld/configure.tgt +index beba17ef51..5109799f2b 100644 +--- a/ld/configure.tgt ++++ b/ld/configure.tgt +@@ -423,6 +423,9 @@ microblaze*-linux*) targ_emul="elf32mb_linux" + microblazeel*) targ_emul=elf32microblazeel + targ_extra_emuls=elf32microblaze + ;; ++microblazeel64*) targ_emul=elf64microblazeel ++ targ_extra_emuls=elf64microblaze ++ ;; + microblaze*) targ_emul=elf32microblaze + targ_extra_emuls=elf32microblazeel + ;; +diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh +new file mode 100644 +index 0000000000..9c7b0eb708 +--- /dev/null ++++ b/ld/emulparams/elf64microblaze.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh +new file mode 100644 +index 0000000000..9c7b0eb708 +--- /dev/null ++++ b/ld/emulparams/elf64microblazeel.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index f8aaf27873..20ea6a885a 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -33,6 +33,7 @@ + #define get_field_r1(instr) get_field (instr, RA_MASK, RA_LOW) + #define get_field_r2(instr) get_field (instr, RB_MASK, RB_LOW) + #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) ++#define get_int_field_imml(instr) ((instr & IMML_MASK) >> IMM_LOW) + #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) + + +@@ -56,11 +57,20 @@ get_field_imm (long instr) + } + + static char * +-get_field_imm5 (long instr) ++get_field_imml (long instr) + { + char tmpstr[25]; + +- sprintf (tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); ++ sprintf (tmpstr, "%d", (short)((instr & IMML_MASK) >> IMM_LOW)); ++ return (strdup (tmpstr)); ++} ++ ++static char * ++get_field_imms (long instr) ++{ ++ char tmpstr[25]; ++ ++ sprintf (tmpstr, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); + } + +@@ -74,14 +84,14 @@ get_field_imm5_mbar (long instr) + } + + static char * +-get_field_imm5width (long instr) ++get_field_immw (long instr) + { + char tmpstr[25]; + + if (instr & 0x00004000) +- sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ ++ sprintf (tmpstr, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ + else +- sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */ ++ sprintf (tmpstr, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */ + return (strdup (tmpstr)); + } + +@@ -286,9 +296,13 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; +- case INST_TYPE_RD_R1_IMM5: ++ case INST_TYPE_RD_R1_IMML: ++ print_func (stream, "\t%s, %s, %s", get_field_rd (inst), ++ get_field_r1(inst), get_field_imm (inst)); ++ /* TODO: Also print symbol */ ++ case INST_TYPE_RD_R1_IMMS: + print_func (stream, "\t%s, %s, %s", get_field_rd (inst), +- get_field_r1(inst), get_field_imm5 (inst)); ++ get_field_r1(inst), get_field_imms (inst)); + break; + case INST_TYPE_RD_RFSL: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst)); +@@ -386,6 +400,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; ++ case INST_TYPE_IMML: ++ print_func (stream, "\t%s", get_field_imml (inst)); ++ /* TODO: Also print symbol */ ++ break; + case INST_TYPE_RD_R2: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); + break; +@@ -409,9 +427,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_NONE: + break; + /* For bit field insns. */ +- case INST_TYPE_RD_R1_IMM5_IMM5: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst)); +- break; ++ case INST_TYPE_RD_R1_IMMW_IMMS: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst), get_field_r1(inst), ++ get_field_immw (inst), get_field_imms (inst)); ++ break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (inst)); +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index ce8ac351b5..985834b8df 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -40,7 +40,7 @@ + #define INST_TYPE_RD_SPECIAL 11 + #define INST_TYPE_R1 12 + /* New instn type for barrel shift imms. */ +-#define INST_TYPE_RD_R1_IMM5 13 ++#define INST_TYPE_RD_R1_IMMS 13 + #define INST_TYPE_RD_RFSL 14 + #define INST_TYPE_R1_RFSL 15 + +@@ -60,7 +60,13 @@ + #define INST_TYPE_IMM5 20 + + /* For bsefi and bsifi */ +-#define INST_TYPE_RD_R1_IMM5_IMM5 21 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 ++ ++/* For 64-bit instructions */ ++#define INST_TYPE_IMML 22 ++#define INST_TYPE_RD_R1_IMML 23 ++#define INST_TYPE_R1_IMML 24 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 + + #define INST_TYPE_NONE 25 + +@@ -91,13 +97,14 @@ + #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ + #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ + #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ +-#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ +-#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */ ++#define OPCODE_MASK_H3 0xFC000700 /* High 6 bits and bits 21, 22, 23. */ ++#define OPCODE_MASK_H3B 0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22. */ + #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ +-#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */ ++#define OPCODE_MASK_H32B 0xFC00E000 /* High 6 bits and bit 16, 17, 18. */ + #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ + #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ ++#define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ + + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ +@@ -107,7 +114,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 301 ++#define MAX_OPCODES 412 + + struct op_code_struct + { +@@ -125,6 +132,7 @@ struct op_code_struct + /* More info about output format here. */ + } opcodes[MAX_OPCODES] = + { ++ /* 32-bit instructions */ + {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, + {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, + {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, +@@ -161,11 +169,11 @@ struct op_code_struct + {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, + {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, + {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, +- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, +- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, +- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, +- {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, +- {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, ++ {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, ++ {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, ++ {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, ++ {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, ++ {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, + {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst }, + {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst }, +@@ -425,6 +433,129 @@ struct op_code_struct + {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */ + {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst }, + {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, ++ ++ /* 64-bit instructions */ ++ {"addl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst }, ++ {"rsubl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst }, ++ {"addlc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst }, ++ {"rsublc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst }, ++ {"addlk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst }, ++ {"rsublk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst }, ++ {"addlkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst }, ++ {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst }, ++ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, ++ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, ++ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, ++ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, ++ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, ++ {"bslrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst }, ++ {"bsllli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst }, ++ {"bslrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst }, ++ {"bslrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst }, ++ {"bslefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst }, ++ {"bslifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst }, ++ {"orl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst }, ++ {"andl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst }, ++ {"xorl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst }, ++ {"andnl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst }, ++ {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst }, ++ {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst }, ++ {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst }, ++ {"srla", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst }, ++ {"srlc", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst }, ++ {"srll", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst }, ++ {"sextl8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst }, ++ {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst }, ++ {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst }, ++ {"brea", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst }, ++ {"bread", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst }, ++ {"breald", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst }, ++ {"beaeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst }, ++ {"bealeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst }, ++ {"beaeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst }, ++ {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst }, ++ {"beane", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst }, ++ {"bealne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst }, ++ {"beaned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst }, ++ {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst }, ++ {"bealt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst }, ++ {"beallt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst }, ++ {"bealtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst }, ++ {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst }, ++ {"beale", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst }, ++ {"bealle", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst }, ++ {"bealed", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst }, ++ {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst }, ++ {"beagt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst }, ++ {"bealgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst }, ++ {"beagtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst }, ++ {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst }, ++ {"beage", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst }, ++ {"bealge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst }, ++ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, ++ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, ++ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, ++ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, ++ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, ++ {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst }, ++ {"beaeqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst }, ++ {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */ ++ {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst }, ++ {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqid */ ++ {"beanei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst }, ++ {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */ ++ {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst }, ++ {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaneid */ ++ {"bealti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst }, ++ {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */ ++ {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst }, ++ {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealtid */ ++ {"bealei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst }, ++ {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */ ++ {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst }, ++ {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealeid */ ++ {"beagti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst }, ++ {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */ ++ {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst }, ++ {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagtid */ ++ {"beagei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst }, ++ {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */ ++ {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst }, ++ {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beageid */ ++ {"ll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst }, ++ {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst }, ++ {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst }, ++ {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst }, ++ {"lli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ ++ {"sli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ ++ {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */ ++ {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst }, ++ {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst }, ++ {"dmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst }, ++ {"ddiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst }, ++ {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst }, ++ {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst }, ++ {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst }, ++ {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst }, ++ {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst }, ++ {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst }, ++ {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst }, ++ {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst }, ++ {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst }, ++ {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst }, ++ + {"", 0, 0, 0, 0, 0, 0, 0, 0}, + }; + +@@ -445,8 +576,17 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM5 ((int) 0x00000000) + #define MAX_IMM5 ((int) 0x0000001f) + ++#define MIN_IMM6 ((int) 0x00000000) ++#define MAX_IMM6 ((int) 0x0000003f) ++ + #define MIN_IMM_WIDTH ((int) 0x00000001) + #define MAX_IMM_WIDTH ((int) 0x00000020) + ++#define MIN_IMM6_WIDTH ((int) 0x00000001) ++#define MAX_IMM6_WIDTH ((int) 0x00000040) ++ ++#define MIN_IMML ((long) 0xffffff8000000000L) ++#define MAX_IMML ((long) 0x0000007fffffffffL) ++ + #endif /* MICROBLAZE_OPC */ + +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 28662694cd..076dbcd0b3 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -25,6 +25,7 @@ + + enum microblaze_instr + { ++ /* 32-bit instructions */ + add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, + addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, + mulh, mulhu, mulhsu,swapb,swaph, +@@ -58,6 +59,18 @@ enum microblaze_instr + aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, + eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, ++ ++ /* 64-bit instructions */ ++ addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, ++ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, ++ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, ++ bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt, ++ bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid, ++ beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti, ++ beagtid, beagei, beageid, imml, ll, llr, sl, slr, ++ dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge, ++ dcmp_un, dbl, dlong, dsqrt, + invalid_inst + }; + +@@ -135,15 +148,18 @@ enum microblaze_instr_type + #define RA_MASK 0x001F0000 + #define RB_MASK 0x0000F800 + #define IMM_MASK 0x0000FFFF ++#define IMML_MASK 0x00FFFFFF + +-/* Imm mask for barrel shifts. */ ++/* Imm masks for barrel shifts. */ + #define IMM5_MASK 0x0000001F ++#define IMM6_MASK 0x0000003F + + /* Imm mask for mbar. */ + #define IMM5_MBAR_MASK 0x03E00000 + +-/* Imm mask for extract/insert width. */ ++/* Imm masks for extract/insert width. */ + #define IMM5_WIDTH_MASK 0x000007C0 ++#define IMM6_WIDTH_MASK 0x00000FC0 + + /* FSL imm mask for get, put instructions. */ + #define RFSL_MASK 0x000000F +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0016-MB-X-initial-commit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0016-MB-X-initial-commit.patch new file mode 100644 index 000000000..0c3da95a1 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0016-MB-X-initial-commit.patch @@ -0,0 +1,691 @@ +From bcd4263219c9756b9c1c1df64c6fef1311057fac Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sun, 30 Sep 2018 16:31:26 +0530 +Subject: [PATCH 16/43] MB-X initial commit code cleanup is needed. + +--- + bfd/bfd-in2.h | 10 +++ + bfd/elf32-microblaze.c | 65 +++++++++++++++- + bfd/elf64-microblaze.c | 61 ++++++++++++++- + bfd/libbfd.h | 2 + + bfd/reloc.c | 12 +++ + gas/config/tc-microblaze.c | 152 ++++++++++++++++++++++++++++++------- + include/elf/microblaze.h | 2 + + opcodes/microblaze-opc.h | 4 +- + opcodes/microblaze-opcm.h | 4 +- + 9 files changed, 277 insertions(+), 35 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 721531886a..4f777059d8 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5876,11 +5876,21 @@ done here - only used for relaxing */ + * +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_NONE, + ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). The relocation is ++PC-relative GOT offset */ ++ BFD_RELOC_MICROBLAZE_64_GPC, ++ + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + GOT offset */ +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index d001437b3f..035e71f311 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ + 0, /* Rightshift. */ +@@ -280,6 +294,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ + /* A 64 bit GOT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ + 0, /* Rightshift. */ +@@ -619,9 +648,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; ++ case BFD_RELOC_MICROBLAZE_64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: + microblaze_reloc = R_MICROBLAZE_GOTPC_64; + break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOT: + microblaze_reloc = R_MICROBLAZE_GOT_64; + break; +@@ -1467,7 +1502,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) + { + relocation += addend; +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { +@@ -1933,6 +1968,28 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); + } + break; ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; + case R_MICROBLAZE_NONE: + case R_MICROBLAZE_32_NONE: + { +@@ -2037,9 +2094,9 @@ microblaze_elf_relax_section (bfd *abfd, + microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, + irelscan->r_addend); + } +- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) +- { +- isym = isymbuf + ELF32_R_SYM (irelscan->r_info); ++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) ++ { ++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 0f43ae6ea8..56a45f2a05 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -116,6 +116,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + ++ /* A 64 bit relocation. Table entry not really used. */ ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 64, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ + 0, /* Rightshift. */ +@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ + /* A 64 bit GOT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ + 0, /* Rightshift. */ +@@ -589,9 +619,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; ++ case BFD_RELOC_MICROBLAZE_64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: + microblaze_reloc = R_MICROBLAZE_GOTPC_64; + break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOT: + microblaze_reloc = R_MICROBLAZE_GOT_64; + break; +@@ -1161,6 +1197,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + break; /* Do nothing. */ + + case (int) R_MICROBLAZE_GOTPC_64: ++ case (int) R_MICROBLAZE_GPC_64: + relocation = htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset; + relocation -= (input_section->output_section->vma +@@ -1431,7 +1468,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) + { + relocation += addend; +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { +@@ -1876,6 +1913,28 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); + } + break; ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; + case R_MICROBLAZE_NONE: + case R_MICROBLAZE_32_NONE: + { +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index feb9fada1e..450653f2d8 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -2903,7 +2903,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", ++ "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", ++ "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index 87753ae4f0..ccf29f54cf 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6803,12 +6803,24 @@ ENUMDOC + done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_NONE ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64 + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC ++ENUMDOC ++ This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64_GPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index c79434785a..3f90b7c892 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -94,6 +94,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; + #define TLSTPREL_OFFSET 16 + #define TEXT_OFFSET 17 + #define TEXT_PC_OFFSET 18 ++#define DEFINED_64_OFFSET 19 + + /* Initialize the relax table. */ + const relax_typeS md_relax_table[] = +@@ -117,6 +118,8 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 16: TLSTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ ++// { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 16: TLSTPREL_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 17: DEFINED_64_OFFSET. */ + }; + + static struct hash_control * opcode_hash_control; /* Opcode mnemonics. */ +@@ -396,7 +399,8 @@ const pseudo_typeS md_pseudo_table[] = + {"data32", cons, 4}, /* Same as word. */ + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ +- {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ ++ {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ ++ {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, +@@ -405,6 +409,7 @@ const pseudo_typeS md_pseudo_table[] = + {"sbss", microblaze_s_bss, 1}, + {"text", microblaze_s_text, 0}, + {"word", cons, 4}, ++ {"dword", cons, 8}, + {"frame", s_ignore, 0}, + {"mask", s_ignore, 0}, /* Emitted by gcc. */ + {NULL, NULL, 0} +@@ -898,7 +903,7 @@ check_got (int * got_type, int * got_len) + extern bfd_reloc_code_real_type + parse_cons_expression_microblaze (expressionS *exp, int size) + { +- if (size == 4) ++ if (size == 4 || (microblaze_arch_size == 64 && size == 8)) + { + /* Handle @GOTOFF et.al. */ + char *save, *gotfree_copy; +@@ -930,6 +935,7 @@ parse_cons_expression_microblaze (expressionS *exp, int size) + + static const char * str_microblaze_ro_anchor = "RO"; + static const char * str_microblaze_rw_anchor = "RW"; ++static const char * str_microblaze_64 = "64"; + + static bfd_boolean + check_spl_reg (unsigned * reg) +@@ -1174,6 +1180,33 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } ++#if 0 //revisit ++ else if (streq (name, "lli") || streq (name, "sli")) ++ { ++ temp = immed & 0xFFFFFFFFFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++#endif + else + { + temp = immed & 0xFFFF8000; +@@ -1926,6 +1959,7 @@ md_assemble (char * str) + if (exp.X_op != O_constant) + { + char *opc = NULL; ++ //char *opc = str_microblaze_64; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -1939,7 +1973,7 @@ md_assemble (char * str) + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, +- opc); ++ (char *) opc); + immedl = 0L; + } + else +@@ -1977,7 +2011,7 @@ md_assemble (char * str) + reg1 = 0; + } + if (strcmp (op_end, "")) +- op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); + else + as_fatal (_("Error in statement syntax")); + +@@ -1987,7 +2021,8 @@ md_assemble (char * str) + + if (exp.X_op != O_constant) + { +- char *opc = NULL; ++ //char *opc = NULL; ++ char *opc = str_microblaze_64; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -2001,14 +2036,13 @@ md_assemble (char * str) + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, +- opc); ++ (char *) opc); + immedl = 0L; + } + else + { + output = frag_more (isize); + immedl = exp.X_add_number; +- + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { +@@ -2187,13 +2221,23 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; ++ case DEFINED_64_OFFSET: ++ if (fragP->fr_symbol == GOT_symbol) ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC); ++ else ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64); ++ fragP->fr_fix += INST_WORD_SIZE * 2; ++ fragP->fr_var = 0; ++ break; + case DEFINED_ABS_SEGMENT: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, +- fragP->fr_offset, FALSE, BFD_RELOC_64); ++ fragP->fr_offset, TRUE, BFD_RELOC_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2416,22 +2460,38 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_64_PCREL: + case BFD_RELOC_64: + case BFD_RELOC_MICROBLAZE_64_TEXTREL: ++ case BFD_RELOC_MICROBLAZE_64: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ { ++ /* Generate the imm instruction. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + +- /* Generate the imm instruction. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imm"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; +- ++ inst1 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ } ++ else ++ { ++ /* Generate the imm instruction. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; ++ } + buf[0] = INST_BYTE0 (inst1); + buf[1] = INST_BYTE1 (inst1); + buf[2] = INST_BYTE2 (inst1); +@@ -2460,6 +2520,7 @@ md_apply_fix (fixS * fixP, + /* Fall through. */ + + case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ case BFD_RELOC_MICROBLAZE_64_GPC: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +@@ -2467,12 +2528,16 @@ md_apply_fix (fixS * fixP, + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; +- +- /* Generate the imm instruction. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ else ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { +- as_bad (_("unknown opcode \"%s\""), "imm"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ else ++ as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + +@@ -2496,6 +2561,8 @@ md_apply_fix (fixS * fixP, + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; + else +@@ -2539,6 +2606,32 @@ md_estimate_size_before_relax (fragS * fragP, + as_bad (_("Absolute PC-relative value in relaxation code. Assembler error.....")); + abort (); + } ++ else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type ++ && !S_IS_WEAK (fragP->fr_symbol)) ++ { ++ if (fragP->fr_opcode != NULL) { ++ if(streq (fragP->fr_opcode, str_microblaze_64)) ++ { ++ /* Used as an absolute value. */ ++ fragP->fr_subtype = DEFINED_64_OFFSET; ++ /* Variable part does not change. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ else ++ { ++ fragP->fr_subtype = DEFINED_PC_OFFSET; ++ /* Don't know now whether we need an imm instruction. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ } ++ else ++ { ++ fragP->fr_subtype = DEFINED_PC_OFFSET; ++ /* Don't know now whether we need an imm instruction. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ } ++ #if 0 + else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type && + !S_IS_WEAK (fragP->fr_symbol)) + { +@@ -2546,6 +2639,7 @@ md_estimate_size_before_relax (fragS * fragP, + /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } ++#endif + else if (S_IS_DEFINED (fragP->fr_symbol) + && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0)) + { +@@ -2648,6 +2742,7 @@ md_estimate_size_before_relax (fragS * fragP, + case TLSLD_OFFSET: + case TLSTPREL_OFFSET: + case TLSDTPREL_OFFSET: ++ case DEFINED_64_OFFSET: + fragP->fr_var = INST_WORD_SIZE*2; + break; + case DEFINED_RO_SEGMENT: +@@ -2701,7 +2796,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) + else + { + /* The case where we are going to resolve things... */ +- if (fixp->fx_r_type == BFD_RELOC_64_PCREL) ++ if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64) + return fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE; + else + return fixp->fx_where + fixp->fx_frag->fr_address; +@@ -2734,6 +2829,8 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_32_RWSDA: + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +@@ -2876,7 +2973,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- r = BFD_RELOC_64; ++ if (microblaze_arch_size == 64) ++ r = BFD_RELOC_32; ++ else ++ r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h +index 6ee0966444..16b2736577 100644 +--- a/include/elf/microblaze.h ++++ b/include/elf/microblaze.h +@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type) + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */ + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */ + RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33) ++ RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34) ++ RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35) /* GOT entry offset. */ + + END_RELOC_NUMBERS (R_MICROBLAZE_max) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 985834b8df..9b6264b61c 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -538,8 +538,8 @@ struct op_code_struct + {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst }, + {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst }, + {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst }, +- {"lli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ +- {"sli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ ++ {"lli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ ++ {"sli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ + {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */ + {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst }, + {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst }, +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 076dbcd0b3..5f2e190d23 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -40,8 +40,8 @@ enum microblaze_instr + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, + bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, +- sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, +- sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, ++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli, ++ sbi, shi, sli, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, + fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, + fint, fsqrt, + tget, tcget, tnget, tncget, tput, tcput, tnput, tncput, +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch new file mode 100644 index 000000000..a64285345 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch @@ -0,0 +1,36 @@ +From 7f6533a7c442b8966f30bbe7f0e872b1ef6a0d3f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 11 Sep 2018 13:48:33 +0530 +Subject: [PATCH 17/43] [Patch,Microblaze] : negl instruction is overriding + rsubl,fixed it by changing the instruction order... + +--- + opcodes/microblaze-opc.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 9b6264b61c..824afc0ab0 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -275,9 +275,7 @@ struct op_code_struct + {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */ + {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */ + {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */ +- {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ + {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */ +- {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, + {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, + {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, +@@ -555,6 +553,8 @@ struct op_code_struct + {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst }, + {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst }, + {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst }, ++ {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ ++ {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + + {"", 0, 0, 0, 0, 0, 0, 0, 0}, + }; +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0018-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0018-Added-relocations-for-MB-X.patch new file mode 100644 index 000000000..99c5f62ae --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0018-Added-relocations-for-MB-X.patch @@ -0,0 +1,346 @@ +From 6d241a6865abf8196ba0cfa2aed7e847df087b6e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 11 Sep 2018 17:30:17 +0530 +Subject: [PATCH 18/43] Added relocations for MB-X + +--- + bfd/bfd-in2.h | 11 +++-- + bfd/libbfd.h | 4 +- + bfd/reloc.c | 26 ++++++----- + gas/config/tc-microblaze.c | 90 ++++++++++++++++---------------------- + 4 files changed, 62 insertions(+), 69 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 4f777059d8..de46e78902 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5872,15 +5872,20 @@ done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_32_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative +- * +value in two words (with an imm instruction). No relocation is ++ * +value in two words (with an imml instruction). No relocation is + * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_NONE, ++ BFD_RELOC_MICROBLAZE_64_PCREL, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative ++/* This is a 64 bit reloc that stores the 32 bit relative + * +value in two words (with an imml instruction). No relocation is + * +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64, + ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imm instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_NONE, ++ + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset */ +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index 450653f2d8..d87a183d5e 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -2903,14 +2903,14 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", +- "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", +- "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", + "BFD_RELOC_MICROBLAZE_32_GOTOFF", + "BFD_RELOC_MICROBLAZE_COPY", ++ "BFD_RELOC_MICROBLAZE_64", ++ "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_64_TLS", + "BFD_RELOC_MICROBLAZE_64_TLSGD", + "BFD_RELOC_MICROBLAZE_64_TLSLD", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index ccf29f54cf..861f2d48c0 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6803,24 +6803,12 @@ ENUMDOC + done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_NONE +-ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64 + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64_GPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is +@@ -6906,6 +6894,20 @@ ENUMDOC + value in two words (with an imm instruction). The relocation is + relative offset from start of TEXT. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_AARCH64_RELOC_START + ENUMDOC +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 3f90b7c892..587a4d56ec 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -95,6 +95,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; + #define TEXT_OFFSET 17 + #define TEXT_PC_OFFSET 18 + #define DEFINED_64_OFFSET 19 ++#define DEFINED_64_PC_OFFSET 20 + + /* Initialize the relax table. */ + const relax_typeS md_relax_table[] = +@@ -119,7 +120,8 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ + // { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 16: TLSTPREL_OFFSET. */ +- { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 17: DEFINED_64_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 19: DEFINED_64_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 } /* 20: DEFINED_64_PC_OFFSET. */ + }; + + static struct hash_control * opcode_hash_control; /* Opcode mnemonics. */ +@@ -1180,33 +1182,6 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +-#if 0 //revisit +- else if (streq (name, "lli") || streq (name, "sli")) +- { +- temp = immed & 0xFFFFFFFFFFFF8000; +- if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000)) +- { +- /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- inst |= (reg1 << RD_LOW) & RD_MASK; +- inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM_MASK; +- } +-#endif + else + { + temp = immed & 0xFFFF8000; +@@ -1958,8 +1933,8 @@ md_assemble (char * str) + + if (exp.X_op != O_constant) + { +- char *opc = NULL; +- //char *opc = str_microblaze_64; ++ //char *opc = NULL; ++ char *opc = str_microblaze_64; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -2221,13 +2196,19 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; ++ case DEFINED_64_PC_OFFSET: ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PCREL); ++ fragP->fr_fix += INST_WORD_SIZE * 2; ++ fragP->fr_var = 0; ++ break; + case DEFINED_64_OFFSET: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, +- fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC); ++ fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, +- fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64); ++ fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2237,7 +2218,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, +- fragP->fr_offset, TRUE, BFD_RELOC_64); ++ fragP->fr_offset, FALSE, BFD_RELOC_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2457,14 +2438,17 @@ md_apply_fix (fixS * fixP, + } + } + break; ++ + case BFD_RELOC_64_PCREL: + case BFD_RELOC_64: + case BFD_RELOC_MICROBLAZE_64_TEXTREL: + case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_64_PCREL: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64 ++ || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + { + /* Generate the imm instruction. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); +@@ -2477,6 +2461,10 @@ md_apply_fix (fixS * fixP, + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_64; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; + } + else + { +@@ -2487,7 +2475,7 @@ md_apply_fix (fixS * fixP, + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } +- ++ + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; +@@ -2534,7 +2522,7 @@ md_apply_fix (fixS * fixP, + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) + as_bad (_("unknown opcode \"%s\""), "imml"); + else + as_bad (_("unknown opcode \"%s\""), "imm"); +@@ -2561,8 +2549,6 @@ md_apply_fix (fixS * fixP, + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) +- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; + else +@@ -2613,33 +2599,24 @@ md_estimate_size_before_relax (fragS * fragP, + if(streq (fragP->fr_opcode, str_microblaze_64)) + { + /* Used as an absolute value. */ +- fragP->fr_subtype = DEFINED_64_OFFSET; ++ fragP->fr_subtype = DEFINED_64_PC_OFFSET; + /* Variable part does not change. */ +- fragP->fr_var = INST_WORD_SIZE; ++ fragP->fr_var = INST_WORD_SIZE*2; + } + else + { + fragP->fr_subtype = DEFINED_PC_OFFSET; +- /* Don't know now whether we need an imm instruction. */ ++ /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } + } + else + { + fragP->fr_subtype = DEFINED_PC_OFFSET; +- /* Don't know now whether we need an imm instruction. */ ++ /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } + } +- #if 0 +- else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type && +- !S_IS_WEAK (fragP->fr_symbol)) +- { +- fragP->fr_subtype = DEFINED_PC_OFFSET; +- /* Don't know now whether we need an imm instruction. */ +- fragP->fr_var = INST_WORD_SIZE; +- } +-#endif + else if (S_IS_DEFINED (fragP->fr_symbol) + && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0)) + { +@@ -2669,6 +2646,13 @@ md_estimate_size_before_relax (fragS * fragP, + /* Variable part does not change. */ + fragP->fr_var = INST_WORD_SIZE*2; + } ++ else if (streq (fragP->fr_opcode, str_microblaze_64)) ++ { ++ /* Used as an absolute value. */ ++ fragP->fr_subtype = DEFINED_64_OFFSET; ++ /* Variable part does not change. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } + else if (streq (fragP->fr_opcode, str_microblaze_ro_anchor)) + { + /* It is accessed using the small data read only anchor. */ +@@ -2743,6 +2727,7 @@ md_estimate_size_before_relax (fragS * fragP, + case TLSTPREL_OFFSET: + case TLSDTPREL_OFFSET: + case DEFINED_64_OFFSET: ++ case DEFINED_64_PC_OFFSET: + fragP->fr_var = INST_WORD_SIZE*2; + break; + case DEFINED_RO_SEGMENT: +@@ -2796,7 +2781,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) + else + { + /* The case where we are going to resolve things... */ +- if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + return fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE; + else + return fixp->fx_where + fixp->fx_frag->fr_address; +@@ -2831,6 +2816,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GPC: + case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_64_PCREL: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0019-Fixed-MB-x-relocation-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0019-Fixed-MB-x-relocation-issues.patch new file mode 100644 index 000000000..edbfac0cb --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0019-Fixed-MB-x-relocation-issues.patch @@ -0,0 +1,373 @@ +From bb6c70cfa1402a685995103ac90e7ceeccdd0991 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 28 Sep 2018 12:04:55 +0530 +Subject: [PATCH 19/43] -Fixed MB-x relocation issues -Added imml for required + MB-x instructions + +--- + bfd/elf64-microblaze.c | 68 ++++++++++++++--- + gas/config/tc-microblaze.c | 152 +++++++++++++++++++++++++++---------- + gas/tc.h | 2 +- + 3 files changed, 167 insertions(+), 55 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 56a45f2a05..54a2461037 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -1476,8 +1476,17 @@ microblaze_elf_relocate_section (bfd *output_bfd, + relocation -= (input_section->output_section->vma + + input_section->output_offset + + offset + INST_WORD_SIZE); +- bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, + contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + endian + INST_WORD_SIZE); + } +@@ -1567,11 +1576,28 @@ microblaze_elf_relocate_section (bfd *output_bfd, + else + { + if (r_type == R_MICROBLAZE_64_PCREL) +- relocation -= (input_section->output_section->vma +- + input_section->output_offset +- + offset + INST_WORD_SIZE); +- bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ { ++ if (!input_section->output_section->vma && ++ !input_section->output_offset && !offset) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset); ++ else ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ } ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, + contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + endian + INST_WORD_SIZE); + } +@@ -1690,9 +1716,19 @@ static void + microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + { + unsigned long instr = bfd_get_32 (abfd, bfd_addr); +- instr &= ~0x0000ffff; +- instr |= (val & 0x0000ffff); +- bfd_put_32 (abfd, instr, bfd_addr); ++ ++ if (instr == 0xb2000000 || instr == 0xb2ffffff) ++ { ++ instr &= ~0x00ffffff; ++ instr |= (val & 0xffffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } ++ else ++ { ++ instr &= ~0x0000ffff; ++ instr |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } + } + + /* Read-modify-write into the bfd, an immediate value into appropriate fields of +@@ -1704,10 +1740,18 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + unsigned long instr_lo; + + instr_hi = bfd_get_32 (abfd, bfd_addr); +- instr_hi &= ~0x0000ffff; +- instr_hi |= ((val >> 16) & 0x0000ffff); +- bfd_put_32 (abfd, instr_hi, bfd_addr); +- ++ if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff) ++ { ++ instr_hi &= ~0x00ffffff; ++ instr_hi |= (val >> 16) & 0xffffff; ++ bfd_put_32 (abfd, instr_hi,bfd_addr); ++ } ++ else ++ { ++ instr_hi &= ~0x0000ffff; ++ instr_hi |= ((val >> 16) & 0x0000ffff); ++ bfd_put_32 (abfd, instr_hi, bfd_addr); ++ } + instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE); + instr_lo &= ~0x0000ffff; + instr_lo |= (val & 0x0000ffff); +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 587a4d56ec..fa437b6c98 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -392,7 +392,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED) + Integer arg to pass to the function. */ + /* If the pseudo-op is not found in this table, it searches in the obj-elf.c, + and then in the read.c table. */ +-const pseudo_typeS md_pseudo_table[] = ++pseudo_typeS md_pseudo_table[] = + { + {"lcomm", microblaze_s_lcomm, 1}, + {"data", microblaze_s_data, 0}, +@@ -401,7 +401,7 @@ const pseudo_typeS md_pseudo_table[] = + {"data32", cons, 4}, /* Same as word. */ + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ +- {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ ++ {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ + {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, +@@ -996,7 +996,7 @@ md_assemble (char * str) + unsigned reg2; + unsigned reg3; + unsigned isize; +- unsigned int immed, immed2, temp; ++ unsigned long immed, immed2, temp; + expressionS exp; + char name[20]; + long immedl; +@@ -1118,8 +1118,9 @@ md_assemble (char * str) + as_fatal (_("lmi pseudo instruction should not use a label in imm field")); + else if (streq (name, "smi")) + as_fatal (_("smi pseudo instruction should not use a label in imm field")); +- +- if (reg2 == REG_ROSDP) ++ if(streq (name, "lli") || streq (name, "sli")) ++ opc = str_microblaze_64; ++ else if (reg2 == REG_ROSDP) + opc = str_microblaze_ro_anchor; + else if (reg2 == REG_RWSDP) + opc = str_microblaze_rw_anchor; +@@ -1182,31 +1183,55 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +- else +- { +- temp = immed & 0xFFFF8000; +- if ((temp != 0) && (temp != 0xFFFF8000)) +- { ++ else if (streq (name, "lli") || streq (name, "sli")) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFF8000) ++ { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { +- as_bad (_("unknown opcode \"%s\""), "imm"); ++ as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } +- + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); +- } +- inst |= (reg1 << RD_LOW) & RD_MASK; +- inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM_MASK; +- } ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { ++ temp = immed & 0xFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_RD_R1_IMMS: +@@ -1832,12 +1857,20 @@ md_assemble (char * str) + case INST_TYPE_IMM: + if (streq (name, "imm")) + as_fatal (_("An IMM instruction should not be present in the .s file")); +- +- op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ if (microblaze_arch_size == 64) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + + if (exp.X_op != O_constant) + { +- char *opc = NULL; ++ char *opc; ++ if (microblaze_arch_size == 64 && (streq (name, "breai") || ++ streq (name, "breaid") || ++ streq (name, "brai") || streq (name, "braid"))) ++ opc = str_microblaze_64; ++ else ++ opc = NULL; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -1860,27 +1893,54 @@ md_assemble (char * str) + immed = exp.X_add_number; + } + ++ if (microblaze_arch_size == 64 && (streq (name, "breai") || ++ streq (name, "breaid") || ++ streq (name, "brai") || streq (name, "braid"))) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + +- temp = immed & 0xFFFF8000; +- if ((temp != 0) && (temp != 0xFFFF8000)) +- { +- /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imm"); +- return; ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); + } ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { ++ temp = immed & 0xFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } + +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- inst |= (immed << IMM_LOW) & IMM_MASK; ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_NONE: +@@ -2460,7 +2520,7 @@ md_apply_fix (fixS * fixP, + + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) + fixP->fx_r_type = BFD_RELOC_64; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) +@@ -2628,7 +2688,14 @@ md_estimate_size_before_relax (fragS * fragP, + } + else + { +- fragP->fr_subtype = UNDEFINED_PC_OFFSET; ++ if (fragP->fr_opcode != NULL) { ++ if (streq (fragP->fr_opcode, str_microblaze_64)) ++ fragP->fr_subtype = DEFINED_64_PC_OFFSET; ++ else ++ fragP->fr_subtype = UNDEFINED_PC_OFFSET; ++ } ++ else ++ fragP->fr_subtype = UNDEFINED_PC_OFFSET; + fragP->fr_var = INST_WORD_SIZE*2; + } + break; +@@ -2905,6 +2972,7 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + case OPTION_M64: + //if (arg != NULL && strcmp (arg, "64") == 0) + microblaze_arch_size = 64; ++ md_pseudo_table[7].poc_val = 8; + break; + default: + return 0; +diff --git a/gas/tc.h b/gas/tc.h +index 0a50a6985b..529a73b43b 100644 +--- a/gas/tc.h ++++ b/gas/tc.h +@@ -22,7 +22,7 @@ + /* In theory (mine, at least!) the machine dependent part of the assembler + should only have to include one file. This one. -- JF */ + +-extern const pseudo_typeS md_pseudo_table[]; ++extern pseudo_typeS md_pseudo_table[]; + + const char * md_atof (int, char *, int *); + int md_parse_option (int, const char *); +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0020-Fixing-the-branch-related-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0020-Fixing-the-branch-related-issues.patch new file mode 100644 index 000000000..528c92790 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0020-Fixing-the-branch-related-issues.patch @@ -0,0 +1,25 @@ +From 8375ef893eb327ae4a5dc9207041ffc0e9bc6e2b Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sun, 30 Sep 2018 17:06:58 +0530 +Subject: [PATCH 20/43] Fixing the branch related issues + +--- + bfd/elf64-microblaze.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 54a2461037..e9b3cf3a86 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -2532,7 +2532,7 @@ microblaze_elf_check_relocs (bfd * abfd, + + /* PR15323, ref flags aren't set for references in the same + object. */ +- h->root.non_ir_ref = 1; ++ h->root.non_ir_ref_regular = 1; + } + + switch (r_type) +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0021-Fixed-address-computation-issues-with-64bit-address.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0021-Fixed-address-computation-issues-with-64bit-address.patch new file mode 100644 index 000000000..d62f0ed2d --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0021-Fixed-address-computation-issues-with-64bit-address.patch @@ -0,0 +1,220 @@ +From 9f13e07180c09f814665676ac6c04cb7a2cd7c11 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 9 Oct 2018 10:14:22 +0530 +Subject: [PATCH 21/43] - Fixed address computation issues with 64bit address - + Fixed imml dissassamble issue + +--- + bfd/bfd-in2.h | 5 +++ + bfd/elf64-microblaze.c | 14 ++++---- + gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++----- + opcodes/microblaze-dis.c | 2 +- + 4 files changed, 79 insertions(+), 16 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index de46e78902..33c9cb62d9 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5881,6 +5881,11 @@ done here - only used for relaxing */ + * +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64, + ++/* This is a 64 bit reloc that stores the 32 bit relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_EA64, ++ + /* This is a 64 bit reloc that stores the 32 bit pc relative + * +value in two words (with an imm instruction). No relocation is + * +done here - only used for relaxing */ +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index e9b3cf3a86..40f10aac6d 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0, /* Rightshift. */ + 4, /* Size (0 = byte, 1 = short, 2 = long). */ + 64, /* Bitsize. */ +- TRUE, /* PC_relative. */ ++ FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_IMML_64", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ +- 0x0000ffff, /* Dest Mask. */ +- TRUE), /* PC relative offset? */ ++ 0xffffffffffffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ + + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ +@@ -585,9 +585,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_32: + microblaze_reloc = R_MICROBLAZE_32; + break; +- /* RVA is treated the same as 32 */ ++ /* RVA is treated the same as 64 */ + case BFD_RELOC_RVA: +- microblaze_reloc = R_MICROBLAZE_32; ++ microblaze_reloc = R_MICROBLAZE_IMML_64; + break; + case BFD_RELOC_32_PCREL: + microblaze_reloc = R_MICROBLAZE_32_PCREL; +@@ -619,7 +619,7 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; +- case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_EA64: + microblaze_reloc = R_MICROBLAZE_IMML_64; + break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: +@@ -1969,7 +1969,7 @@ microblaze_elf_relax_section (bfd *abfd, + efix = calc_fixup (target_address, 0, sec); + + /* Validate the in-band val. */ +- val = bfd_get_32 (abfd, contents + irel->r_offset); ++ val = bfd_get_64 (abfd, contents + irel->r_offset); + if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { + fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); + } +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index fa437b6c98..46df32e72f 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -402,7 +402,6 @@ pseudo_typeS md_pseudo_table[] = + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ + {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ +- {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, +@@ -2479,18 +2478,74 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_RVA: + case BFD_RELOC_32_PCREL: + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: ++ /* Don't do anything if the symbol is not defined. */ ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ { ++ if ((fixP->fx_r_type == BFD_RELOC_RVA) && (microblaze_arch_size == 64)) ++ { ++ if (target_big_endian) ++ { ++ buf[0] |= ((val >> 56) & 0xff); ++ buf[1] |= ((val >> 48) & 0xff); ++ buf[2] |= ((val >> 40) & 0xff); ++ buf[3] |= ((val >> 32) & 0xff); ++ buf[4] |= ((val >> 24) & 0xff); ++ buf[5] |= ((val >> 16) & 0xff); ++ buf[6] |= ((val >> 8) & 0xff); ++ buf[7] |= (val & 0xff); ++ } ++ else ++ { ++ buf[7] |= ((val >> 56) & 0xff); ++ buf[6] |= ((val >> 48) & 0xff); ++ buf[5] |= ((val >> 40) & 0xff); ++ buf[4] |= ((val >> 32) & 0xff); ++ buf[3] |= ((val >> 24) & 0xff); ++ buf[2] |= ((val >> 16) & 0xff); ++ buf[1] |= ((val >> 8) & 0xff); ++ buf[0] |= (val & 0xff); ++ } ++ } ++ else { ++ if (target_big_endian) ++ { ++ buf[0] |= ((val >> 24) & 0xff); ++ buf[1] |= ((val >> 16) & 0xff); ++ buf[2] |= ((val >> 8) & 0xff); ++ buf[3] |= (val & 0xff); ++ } ++ else ++ { ++ buf[3] |= ((val >> 24) & 0xff); ++ buf[2] |= ((val >> 16) & 0xff); ++ buf[1] |= ((val >> 8) & 0xff); ++ buf[0] |= (val & 0xff); ++ } ++ } ++ } ++ break; ++ ++ case BFD_RELOC_MICROBLAZE_EA64: + /* Don't do anything if the symbol is not defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { + if (target_big_endian) + { +- buf[0] |= ((val >> 24) & 0xff); +- buf[1] |= ((val >> 16) & 0xff); +- buf[2] |= ((val >> 8) & 0xff); +- buf[3] |= (val & 0xff); ++ buf[0] |= ((val >> 56) & 0xff); ++ buf[1] |= ((val >> 48) & 0xff); ++ buf[2] |= ((val >> 40) & 0xff); ++ buf[3] |= ((val >> 32) & 0xff); ++ buf[4] |= ((val >> 24) & 0xff); ++ buf[5] |= ((val >> 16) & 0xff); ++ buf[6] |= ((val >> 8) & 0xff); ++ buf[7] |= (val & 0xff); + } + else + { ++ buf[7] |= ((val >> 56) & 0xff); ++ buf[6] |= ((val >> 48) & 0xff); ++ buf[5] |= ((val >> 40) & 0xff); ++ buf[4] |= ((val >> 32) & 0xff); + buf[3] |= ((val >> 24) & 0xff); + buf[2] |= ((val >> 16) & 0xff); + buf[1] |= ((val >> 8) & 0xff); +@@ -2611,6 +2666,8 @@ md_apply_fix (fixS * fixP, + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; ++ else if(fixP->fx_r_type == BFD_RELOC_MICROBLAZE_EA64) ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_EA64; + else + fixP->fx_r_type = BFD_RELOC_NONE; + fixP->fx_addsy = section_symbol (absolute_section); +@@ -2882,6 +2939,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GPC: ++ case BFD_RELOC_MICROBLAZE_EA64: + case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_PCREL: + case BFD_RELOC_MICROBLAZE_64_GOT: +@@ -3027,10 +3085,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- if (microblaze_arch_size == 64) ++ /*if (microblaze_arch_size == 64) + r = BFD_RELOC_32; +- else +- r = BFD_RELOC_64; ++ else*/ ++ r = BFD_RELOC_MICROBLAZE_EA64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 20ea6a885a..f679a43606 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -61,7 +61,7 @@ get_field_imml (long instr) + { + char tmpstr[25]; + +- sprintf (tmpstr, "%d", (short)((instr & IMML_MASK) >> IMM_LOW)); ++ sprintf (tmpstr, "%d", (int)((instr & IMML_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); + } + +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0022-Adding-new-relocation-to-support-64bit-rodata.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0022-Adding-new-relocation-to-support-64bit-rodata.patch new file mode 100644 index 000000000..ec82926d6 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0022-Adding-new-relocation-to-support-64bit-rodata.patch @@ -0,0 +1,166 @@ +From beeceebb05a4eeaeca697f4ba7e214485b10369a Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sat, 13 Oct 2018 21:17:01 +0530 +Subject: [PATCH 22/43] Adding new relocation to support 64bit rodata + +--- + bfd/elf64-microblaze.c | 11 +++++++-- + gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++---- + 2 files changed, 54 insertions(+), 6 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 40f10aac6d..4d9b90647f 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -1461,6 +1461,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + case (int) R_MICROBLAZE_64_PCREL : + case (int) R_MICROBLAZE_64: + case (int) R_MICROBLAZE_32: ++ case (int) R_MICROBLAZE_IMML_64: + { + /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols + from removed linkonce sections, or sections discarded by +@@ -1470,6 +1471,8 @@ microblaze_elf_relocate_section (bfd *output_bfd, + relocation += addend; + if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset); + else + { + if (r_type == R_MICROBLAZE_64_PCREL) +@@ -1547,7 +1550,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + } + else + { +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64) + { + outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); + outrel.r_addend = relocation + addend; +@@ -1573,6 +1576,8 @@ microblaze_elf_relocate_section (bfd *output_bfd, + relocation += addend; + if (r_type == R_MICROBLAZE_32) + bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset + endian); + else + { + if (r_type == R_MICROBLAZE_64_PCREL) +@@ -2085,7 +2090,8 @@ microblaze_elf_relax_section (bfd *abfd, + microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, + irelscan->r_addend); + } +- if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32 ++ || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) + { + isym = isymbuf + ELF64_R_SYM (irelscan->r_info); + +@@ -2591,6 +2597,7 @@ microblaze_elf_check_relocs (bfd * abfd, + case R_MICROBLAZE_64: + case R_MICROBLAZE_64_PCREL: + case R_MICROBLAZE_32: ++ case R_MICROBLAZE_IMML_64: + { + if (h != NULL && !bfd_link_pic (info)) + { +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 46df32e72f..c6d2e4c82d 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -1119,6 +1119,13 @@ md_assemble (char * str) + as_fatal (_("smi pseudo instruction should not use a label in imm field")); + if(streq (name, "lli") || streq (name, "sli")) + opc = str_microblaze_64; ++ else if ((microblaze_arch_size == 64) && ((streq (name, "lbui") ++ || streq (name, "lhui") || streq (name, "lwi") || streq (name, "sbi") ++ || streq (name, "shi") || streq (name, "swi")))) ++ { ++ opc = str_microblaze_64; ++ subtype = opcode->inst_offset_type; ++ } + else if (reg2 == REG_ROSDP) + opc = str_microblaze_ro_anchor; + else if (reg2 == REG_RWSDP) +@@ -1182,7 +1189,10 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +- else if (streq (name, "lli") || streq (name, "sli")) ++ else if (streq (name, "lli") || streq (name, "sli") || ((microblaze_arch_size == 64) ++ && ((streq (name, "lbui")) || streq (name, "lhui") ++ || streq (name, "lwi") || streq (name, "sbi") ++ || streq (name, "shi") || streq (name, "swi")))) + { + temp = immed & 0xFFFFFF8000; + if (temp != 0 && temp != 0xFFFFFF8000) +@@ -1794,6 +1804,11 @@ md_assemble (char * str) + + if (exp.X_md != 0) + subtype = get_imm_otype(exp.X_md); ++ else if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) ++ { ++ opc = str_microblaze_64; ++ subtype = opcode->inst_offset_type; ++ } + else + subtype = opcode->inst_offset_type; + +@@ -1811,6 +1826,31 @@ md_assemble (char * str) + output = frag_more (isize); + immed = exp.X_add_number; + } ++ if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFF8000) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { + + temp = immed & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) +@@ -1834,6 +1874,7 @@ md_assemble (char * str) + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_R2: +@@ -3085,10 +3126,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- /*if (microblaze_arch_size == 64) +- r = BFD_RELOC_32; +- else*/ ++ if (microblaze_arch_size == 64) + r = BFD_RELOC_MICROBLAZE_EA64; ++ else ++ r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0023-fixing-the-.bss-relocation-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0023-fixing-the-.bss-relocation-issue.patch new file mode 100644 index 000000000..d1ec5dbfc --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0023-fixing-the-.bss-relocation-issue.patch @@ -0,0 +1,76 @@ +From 3f031961082caec9e172ff0224a51c08ab6e19c3 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 24 Oct 2018 12:34:37 +0530 +Subject: [PATCH 23/43] fixing the .bss relocation issue + +--- + bfd/elf64-microblaze.c | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 4d9b90647f..184b7d560d 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -1480,7 +1480,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + + input_section->output_offset + + offset + INST_WORD_SIZE); + unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); +- if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ if ((insn & 0xff000000) == 0xb2000000) + { + insn &= ~0x00ffffff; + insn |= (relocation >> 16) & 0xffffff; +@@ -1593,7 +1593,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + + offset + INST_WORD_SIZE); + } + unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); +- if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ if ((insn & 0xff000000) == 0xb2000000) + { + insn &= ~0x00ffffff; + insn |= (relocation >> 16) & 0xffffff; +@@ -1722,7 +1722,7 @@ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + { + unsigned long instr = bfd_get_32 (abfd, bfd_addr); + +- if (instr == 0xb2000000 || instr == 0xb2ffffff) ++ if ((instr & 0xff000000) == 0xb2000000) + { + instr &= ~0x00ffffff; + instr |= (val & 0xffffff); +@@ -1745,7 +1745,7 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + unsigned long instr_lo; + + instr_hi = bfd_get_32 (abfd, bfd_addr); +- if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff) ++ if ((instr_hi & 0xff000000) == 0xb2000000) + { + instr_hi &= ~0x00ffffff; + instr_hi |= (val >> 16) & 0xffffff; +@@ -2238,7 +2238,10 @@ microblaze_elf_relax_section (bfd *abfd, + unsigned long instr_lo = bfd_get_32 (abfd, ocontents + + irelscan->r_offset + + INST_WORD_SIZE); +- immediate = (instr_hi & 0x0000ffff) << 16; ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; + immediate |= (instr_lo & 0x0000ffff); + offset = calc_fixup (irelscan->r_addend, 0, sec); + immediate -= offset; +@@ -2282,7 +2285,10 @@ microblaze_elf_relax_section (bfd *abfd, + unsigned long instr_lo = bfd_get_32 (abfd, ocontents + + irelscan->r_offset + + INST_WORD_SIZE); +- immediate = (instr_hi & 0x0000ffff) << 16; ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; + immediate |= (instr_lo & 0x0000ffff); + target_address = immediate; + offset = calc_fixup (target_address, 0, sec); +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch new file mode 100644 index 000000000..207529397 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch @@ -0,0 +1,44 @@ +From 843b73643718b0776462bce6aba6b2c6fdb33d85 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 28 Nov 2018 14:00:29 +0530 +Subject: [PATCH 24/43] Fixed the bug in the R_MICROBLAZE_64_NONE relocation. + It was adjusting only lower 16bits. + +--- + bfd/elf32-microblaze.c | 4 ++-- + bfd/elf64-microblaze.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 035e71f311..2d8c062a42 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -2022,8 +2022,8 @@ microblaze_elf_relax_section (bfd *abfd, + sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); + efix = calc_fixup (target_address, 0, sec); + irel->r_addend -= (efix - sfix); +- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset +- + INST_WORD_SIZE, irel->r_addend); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); + } + break; + } +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 184b7d560d..ef6a87062b 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -2017,8 +2017,8 @@ microblaze_elf_relax_section (bfd *abfd, + sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); + efix = calc_fixup (target_address, 0, sec); + irel->r_addend -= (efix - sfix); +- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset +- + INST_WORD_SIZE, irel->r_addend); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); + } + break; + } +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch new file mode 100644 index 000000000..50179787d --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch @@ -0,0 +1,68 @@ +From 3a5e6a9c614c3f6abcf8bf853527ef07a5370f80 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Sun, 2 Dec 2018 14:49:14 +0530 +Subject: [PATCH 25/43] [Patch,MicroBlaze]: fixed Build issue which are due to + conflicts in patches. + +--- + bfd/elf32-microblaze.c | 1 + + bfd/elf64-microblaze.c | 12 ++++++------ + gas/config/tc-microblaze.c | 4 ++-- + 3 files changed, 9 insertions(+), 8 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 2d8c062a42..6a795c5069 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -1996,6 +1996,7 @@ microblaze_elf_relax_section (bfd *abfd, + /* This was a PC-relative instruction that was + completely resolved. */ + int sfix, efix; ++ unsigned int val; + bfd_vma target_address; + target_address = irel->r_addend + irel->r_offset; + sfix = calc_fixup (irel->r_offset, 0, sec); +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index ef6a87062b..bed534e7dd 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -2854,14 +2854,14 @@ microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ +- if (h->u.weakdef != NULL) ++ if (h->is_weakalias) + { +- BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined +- || h->u.weakdef->root.type == bfd_link_hash_defweak); +- h->root.u.def.section = h->u.weakdef->root.u.def.section; +- h->root.u.def.value = h->u.weakdef->root.u.def.value; ++ struct elf_link_hash_entry *def = weakdef (h); ++ BFD_ASSERT (def->root.type == bfd_link_hash_defined); ++ h->root.u.def.section = def->root.u.def.section; ++ h->root.u.def.value = def->root.u.def.value; + return TRUE; +- } ++ } + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index c6d2e4c82d..b3e49f0cf0 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -118,9 +118,9 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 15: TLSGOTTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 16: TLSTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ +- { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ ++ { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 18: TEXT_PC_OFFSET. */ + // { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 16: TLSTPREL_OFFSET. */ +- { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 19: DEFINED_64_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }, /* 19: DEFINED_64_OFFSET. */ + { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 } /* 20: DEFINED_64_PC_OFFSET. */ + }; + +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch new file mode 100644 index 000000000..aef46b3f9 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch @@ -0,0 +1,31 @@ +From e7f43c3afe90faa42c09f368671972c26c2b7b38 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 26 Feb 2019 17:31:41 +0530 +Subject: [PATCH 26/43] [Patch,Microblaze] : changes of "PR22458, failure to + choose a matching ELF target" is causing "Multiple Prevailing definition + errors",added check for best_match elf. + +--- + bfd/format.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/bfd/format.c b/bfd/format.c +index 97a92291a8..3a74cc49d2 100644 +--- a/bfd/format.c ++++ b/bfd/format.c +@@ -292,7 +292,12 @@ bfd_check_format_matches (bfd *abfd, bfd_format format, char ***matching) + + /* Don't check the default target twice. */ + if (*target == &binary_vec ++#if !BFD_SUPPORTS_PLUGINS + || (!abfd->target_defaulted && *target == save_targ)) ++#else ++ || (!abfd->target_defaulted && *target == save_targ) ++ || (*target)->match_priority > best_match) ++#endif + continue; + + /* If we already tried a match, the bfd is modified and may +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state.patch new file mode 100644 index 000000000..b0fe8231f --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state.patch @@ -0,0 +1,76 @@ +From 69b77a73f4e609883cd7a0946b407becd46bf918 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 27 Feb 2019 15:12:32 +0530 +Subject: [PATCH 27/43] Revert "ld: Remove unused expression state" + +This reverts commit 65f14869fd3fbee8ed4c4ca49de8aaa86dbc66cb. + +Conflicts: + ld/ChangeLog +--- + ld/ldexp.c | 8 +++++--- + ld/ldexp.h | 1 + + 2 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/ld/ldexp.c b/ld/ldexp.c +index 60b17ef576..dac4b52450 100644 +--- a/ld/ldexp.c ++++ b/ld/ldexp.c +@@ -1354,6 +1354,7 @@ static etree_type * + exp_assop (const char *dst, + etree_type *src, + enum node_tree_enum class, ++ bfd_boolean defsym, + bfd_boolean hidden) + { + etree_type *n; +@@ -1365,6 +1366,7 @@ exp_assop (const char *dst, + n->assign.type.node_class = class; + n->assign.src = src; + n->assign.dst = dst; ++ n->assign.defsym = defsym; + n->assign.hidden = hidden; + return n; + } +@@ -1374,7 +1376,7 @@ exp_assop (const char *dst, + etree_type * + exp_assign (const char *dst, etree_type *src, bfd_boolean hidden) + { +- return exp_assop (dst, src, etree_assign, hidden); ++ return exp_assop (dst, src, etree_assign, FALSE, hidden); + } + + /* Handle --defsym command-line option. */ +@@ -1382,7 +1384,7 @@ exp_assign (const char *dst, etree_type *src, bfd_boolean hidden) + etree_type * + exp_defsym (const char *dst, etree_type *src) + { +- return exp_assop (dst, src, etree_assign, FALSE); ++ return exp_assop (dst, src, etree_assign, TRUE, FALSE); + } + + /* Handle PROVIDE. */ +@@ -1390,7 +1392,7 @@ exp_defsym (const char *dst, etree_type *src) + etree_type * + exp_provide (const char *dst, etree_type *src, bfd_boolean hidden) + { +- return exp_assop (dst, src, etree_provide, hidden); ++ return exp_assop (dst, src, etree_provide, FALSE, hidden); + } + + /* Handle ASSERT. */ +diff --git a/ld/ldexp.h b/ld/ldexp.h +index 71395bc6c4..f94b00aedb 100644 +--- a/ld/ldexp.h ++++ b/ld/ldexp.h +@@ -66,6 +66,7 @@ typedef union etree_union { + node_type type; + const char *dst; + union etree_union *src; ++ bfd_boolean defsym; + bfd_boolean hidden; + } assign; + struct { +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0028-Patch-Microblaze-Binutils-security-check-is-causing-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0028-Patch-Microblaze-Binutils-security-check-is-causing-.patch new file mode 100644 index 000000000..0fd14f6d0 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0028-Patch-Microblaze-Binutils-security-check-is-causing-.patch @@ -0,0 +1,33 @@ +From 282a60ab92e6705853dac30fd38aaf298d7f02b0 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 11 Mar 2019 14:23:58 +0530 +Subject: [PATCH 28/43] [Patch,Microblaze] : Binutils security check is causing + build error for windows builds.commenting for now. + +--- + bfd/elf-attrs.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/bfd/elf-attrs.c b/bfd/elf-attrs.c +index bfe135e7fb..feb5cb37f5 100644 +--- a/bfd/elf-attrs.c ++++ b/bfd/elf-attrs.c +@@ -440,6 +440,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr) + /* PR 17512: file: 2844a11d. */ + if (hdr->sh_size == 0) + return; ++ #if 0 + if (hdr->sh_size > bfd_get_file_size (abfd)) + { + /* xgettext:c-format */ +@@ -448,6 +449,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr) + bfd_set_error (bfd_error_invalid_operation); + return; + } ++ #endif + + contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1); + if (!contents) +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0029-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0029-fixing-the-long-long-long-mingw-toolchain-issue.patch new file mode 100644 index 000000000..dbafc786f --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0029-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -0,0 +1,57 @@ +From 26662110955e26c62629f4263a999216dac326ef Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 29 Nov 2018 17:59:25 +0530 +Subject: [PATCH 29/43] fixing the long & long long mingw toolchain issue + +--- + gas/config/tc-microblaze.c | 10 +++++----- + opcodes/microblaze-opc.h | 4 ++-- + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index b3e49f0cf0..5b506d3348 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -783,7 +783,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) + } + + static char * +-parse_imml (char * s, expressionS * e, long min, long max) ++parse_imml (char * s, expressionS * e, long long min, long long max) + { + char *new_pointer; + char *atp; +@@ -834,11 +834,11 @@ parse_imml (char * s, expressionS * e, long min, long max) + ; /* An error message has already been emitted. */ + else if ((e->X_op != O_constant && e->X_op != O_symbol) ) + as_fatal (_("operand must be a constant or a label")); +- else if ((e->X_op == O_constant) && ((long) e->X_add_number < min +- || (long) e->X_add_number > max)) ++ else if ((e->X_op == O_constant) && ((long long) e->X_add_number < min ++ || (long long) e->X_add_number > max)) + { +- as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"), +- min, max, (long) e->X_add_number); ++ as_fatal (_("operand must be absolute in range %lld..%lld, not %lld"), ++ min, max, (long long) e->X_add_number); + } + + if (atp) +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 824afc0ab0..d59ee0a95f 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM6_WIDTH ((int) 0x00000001) + #define MAX_IMM6_WIDTH ((int) 0x00000040) + +-#define MIN_IMML ((long) 0xffffff8000000000L) +-#define MAX_IMML ((long) 0x0000007fffffffffL) ++#define MIN_IMML ((long long) 0xffffff8000000000L) ++#define MAX_IMML ((long long) 0x0000007fffffffffL) + + #endif /* MICROBLAZE_OPC */ + +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch new file mode 100644 index 000000000..8141095a2 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch @@ -0,0 +1,359 @@ +From 7b332d61cb3dbcae69021ce706f2c408c85af193 Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Fri, 23 Aug 2019 16:18:43 +0530 +Subject: [PATCH 30/43] Added support to new arithmetic single register + instructions + +--- + gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++- + opcodes/microblaze-dis.c | 12 +++ + opcodes/microblaze-opc.h | 43 ++++++++++- + opcodes/microblaze-opcm.h | 5 +- + 4 files changed, 201 insertions(+), 6 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 5b506d3348..12eef24a29 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -423,12 +423,33 @@ void + md_begin (void) + { + struct op_code_struct * opcode; ++ const char *prev_name = ""; + + opcode_hash_control = hash_new (); + + /* Insert unique names into hash table. */ +- for (opcode = opcodes; opcode->name; opcode ++) +- hash_insert (opcode_hash_control, opcode->name, (char *) opcode); ++ for (opcode = (struct opcodes *)opcodes; opcode->name; opcode ++) ++ { ++ if (strcmp (prev_name, opcode->name)) ++ { ++ prev_name = (char *) opcode->name; ++ hash_insert (opcode_hash_control, opcode->name, (char *) opcode); ++ } ++ } ++} ++ ++static int ++is_reg (char * s) ++{ ++ int is_reg = 0; ++ /* Strip leading whitespace. */ ++ while (ISSPACE (* s)) ++ ++ s; ++ if (TOLOWER (s[0]) == 'r') ++ { ++ is_reg =1; ++ } ++ return is_reg; + } + + /* Try to parse a reg name. */ +@@ -986,6 +1007,7 @@ md_assemble (char * str) + { + char * op_start; + char * op_end; ++ char * temp_op_end; + struct op_code_struct * opcode, *opcode1; + char * output = NULL; + int nlen = 0; +@@ -996,9 +1018,10 @@ md_assemble (char * str) + unsigned reg3; + unsigned isize; + unsigned long immed, immed2, temp; +- expressionS exp; ++ expressionS exp,exp1; + char name[20]; + long immedl; ++ int reg=0; + + /* Drop leading whitespace. */ + while (ISSPACE (* str)) +@@ -1029,7 +1052,78 @@ md_assemble (char * str) + as_bad (_("unknown opcode \"%s\""), name); + return; + } +- ++ ++ if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") || ++ streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli") ++ || streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc") ++ || streq (name, "andli") || streq (name, "andnli") || streq (name, "orli") ++ || streq (name, "xorli"))) ++ { ++ temp_op_end = op_end; ++ if (strcmp (temp_op_end, "")) ++ temp_op_end = parse_reg (temp_op_end + 1, ®1); /* Get rd. */ ++ if (strcmp (temp_op_end, "")) ++ reg = is_reg (temp_op_end + 1); ++ if (reg) ++ { ++ ++ opcode->inst_type=INST_TYPE_RD_R1_IMML; ++ opcode->inst_offset_type = OPCODE_MASK_H; ++ if (streq (name, "addli")) ++ opcode->bit_sequence = ADDLI_MASK; ++ else if (streq (name, "addlic")) ++ opcode->bit_sequence = ADDLIC_MASK; ++ else if (streq (name, "addlik")) ++ opcode->bit_sequence = ADDLIK_MASK; ++ else if (streq (name, "addlikc")) ++ opcode->bit_sequence = ADDLIKC_MASK; ++ else if (streq (name, "rsubli")) ++ opcode->bit_sequence = RSUBLI_MASK; ++ else if (streq (name, "rsublic")) ++ opcode->bit_sequence = RSUBLIC_MASK; ++ else if (streq (name, "rsublik")) ++ opcode->bit_sequence = RSUBLIK_MASK; ++ else if (streq (name, "rsublikc")) ++ opcode->bit_sequence = RSUBLIKC_MASK; ++ else if (streq (name, "andli")) ++ opcode->bit_sequence = ANDLI_MASK; ++ else if (streq (name, "andnli")) ++ opcode->bit_sequence = ANDLNI_MASK; ++ else if (streq (name, "orli")) ++ opcode->bit_sequence = ORLI_MASK; ++ else if (streq (name, "xorli")) ++ opcode->bit_sequence = XORLI_MASK; ++ } ++ else ++ { ++ opcode->inst_type=INST_TYPE_RD_IMML; ++ opcode->inst_offset_type = OPCODE_MASK_LIMM; ++ if (streq (name, "addli")) ++ opcode->bit_sequence = ADDLI_ONE_REG_MASK; ++ else if (streq (name, "addlic")) ++ opcode->bit_sequence = ADDLIC_ONE_REG_MASK; ++ else if (streq (name, "addlik")) ++ opcode->bit_sequence = ADDLIK_ONE_REG_MASK; ++ else if (streq (name, "addlikc")) ++ opcode->bit_sequence = ADDLIKC_ONE_REG_MASK; ++ else if (streq (name, "rsubli")) ++ opcode->bit_sequence = RSUBLI_ONE_REG_MASK; ++ else if (streq (name, "rsublic")) ++ opcode->bit_sequence = RSUBLIC_ONE_REG_MASK; ++ else if (streq (name, "rsublik")) ++ opcode->bit_sequence = RSUBLIK_ONE_REG_MASK; ++ else if (streq (name, "rsublikc")) ++ opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK; ++ else if (streq (name, "andli")) ++ opcode->bit_sequence = ANDLI_ONE_REG_MASK; ++ else if (streq (name, "andnli")) ++ opcode->bit_sequence = ANDLNI_ONE_REG_MASK; ++ else if (streq (name, "orli")) ++ opcode->bit_sequence = ORLI_ONE_REG_MASK; ++ else if (streq (name, "xorli")) ++ opcode->bit_sequence = XORLI_ONE_REG_MASK; ++ } ++ } + inst = opcode->bit_sequence; + isize = 4; + +@@ -1480,6 +1574,51 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM15_MASK; + break; + ++ case INST_TYPE_RD_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (®1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, ++ isize * 2, ++ subtype, ++ exp.X_add_symbol, ++ exp.X_add_number, ++ (char *) opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immed = exp.X_add_number; ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (immed << IMM_LOW) & IMM16_MASK; ++ break; ++ + case INST_TYPE_R1_RFSL: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index f679a43606..e5e880cb1c 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -114,6 +114,15 @@ get_field_imm15 (long instr) + return (strdup (tmpstr)); + } + ++static char * ++get_field_imm16 (long instr) ++{ ++ char tmpstr[25]; ++ ++ sprintf (tmpstr, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW)); ++ return (strdup (tmpstr)); ++} ++ + static char * + get_field_special (long instr, struct op_code_struct * op) + { +@@ -419,6 +428,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_RD_IMM15: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst)); + break; ++ case INST_TYPE_RD_IMML: ++ print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm16 (inst)); ++ break; + /* For mbar insn. */ + case INST_TYPE_IMM5: + print_func (stream, "\t%s", get_field_imm5_mbar (inst)); +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index d59ee0a95f..0774f70e08 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -69,6 +69,7 @@ + #define INST_TYPE_RD_R1_IMMW_IMMS 21 + + #define INST_TYPE_NONE 25 ++#define INST_TYPE_RD_IMML 26 + + + +@@ -84,6 +85,7 @@ + #define IMMVAL_MASK_MFS 0x0000 + + #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */ ++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */ + #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */ + #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ + #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ +@@ -106,6 +108,33 @@ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ + #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ + ++/*Defines to identify 64-bit single reg instructions */ ++#define ADDLI_ONE_REG_MASK 0x68000000 ++#define ADDLIC_ONE_REG_MASK 0x68020000 ++#define ADDLIK_ONE_REG_MASK 0x68040000 ++#define ADDLIKC_ONE_REG_MASK 0x68060000 ++#define RSUBLI_ONE_REG_MASK 0x68010000 ++#define RSUBLIC_ONE_REG_MASK 0x68030000 ++#define RSUBLIK_ONE_REG_MASK 0x68050000 ++#define RSUBLIKC_ONE_REG_MASK 0x68070000 ++#define ORLI_ONE_REG_MASK 0x68100000 ++#define ANDLI_ONE_REG_MASK 0x68110000 ++#define XORLI_ONE_REG_MASK 0x68120000 ++#define ANDLNI_ONE_REG_MASK 0x68130000 ++#define ADDLI_MASK 0x20000000 ++#define ADDLIC_MASK 0x28000000 ++#define ADDLIK_MASK 0x30000000 ++#define ADDLIKC_MASK 0x38000000 ++#define RSUBLI_MASK 0x24000000 ++#define RSUBLIC_MASK 0x2C000000 ++#define RSUBLIK_MASK 0x34000000 ++#define RSUBLIKC_MASK 0x3C000000 ++#define ANDLI_MASK 0xA4000000 ++#define ANDLNI_MASK 0xAC000000 ++#define ORLI_MASK 0xA0000000 ++#define XORLI_MASK 0xA8000000 ++ ++ + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ + /* Mask for mbar insn. */ +@@ -114,7 +143,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 412 ++#define MAX_OPCODES 424 + + struct op_code_struct + { +@@ -444,13 +473,21 @@ struct op_code_struct + {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, + {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, + {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst }, + {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst }, + {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst }, + {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst }, + {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst }, + {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst }, + {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst }, + {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst }, + {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, + {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, + {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, +@@ -501,9 +538,13 @@ struct op_code_struct + {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, + {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, + {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst }, + {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst }, + {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst }, + {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst }, + {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, + {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, + {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 5f2e190d23..4d2ee2dd0d 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -61,7 +61,9 @@ enum microblaze_instr + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, + + /* 64-bit instructions */ +- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc, ++ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ andli, andnli, orli, xorli, + bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, + andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, + brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, +@@ -166,5 +168,6 @@ enum microblaze_instr_type + + /* Imm mask for msrset, msrclr instructions. */ + #define IMM15_MASK 0x00007FFF ++#define IMM16_MASK 0x0000FFFF + + #endif /* MICROBLAZE-OPCM */ +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0031-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0031-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch new file mode 100644 index 000000000..f9f0fc554 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0031-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch @@ -0,0 +1,551 @@ +From 213df2cac38d404619614939de0c9d3dcbf7557d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 26 Aug 2019 15:29:42 +0530 +Subject: [PATCH 31/43] [Patch,MicroBlaze] : double imml generation for 64 bit + values. + +--- + gas/config/tc-microblaze.c | 322 ++++++++++++++++++++++++++++++------- + opcodes/microblaze-opc.h | 4 +- + 2 files changed, 263 insertions(+), 63 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 12eef24a29..3ff6a14baf 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -1008,7 +1008,7 @@ md_assemble (char * str) + char * op_start; + char * op_end; + char * temp_op_end; +- struct op_code_struct * opcode, *opcode1; ++ struct op_code_struct * opcode, *opcode1, *opcode2; + char * output = NULL; + int nlen = 0; + int i; +@@ -1192,7 +1192,12 @@ md_assemble (char * str) + reg2 = 0; + } + if (strcmp (op_end, "")) ++ { ++ if(microblaze_arch_size == 64) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ } + else + as_fatal (_("Error in statement syntax")); + +@@ -1288,24 +1293,51 @@ md_assemble (char * str) + || streq (name, "lwi") || streq (name, "sbi") + || streq (name, "shi") || streq (name, "swi")))) + { +- temp = immed & 0xFFFFFF8000; +- if (temp != 0 && temp != 0xFFFFFF8000) ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000) + { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else ++ { ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } ++ } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (immed << IMM_LOW) & IMM_MASK; +@@ -1316,14 +1348,13 @@ md_assemble (char * str) + if ((temp != 0) && (temp != 0xFFFF8000)) + { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } +- +- inst1 = opcode1->bit_sequence; ++ inst1 = opcode1->bit_sequence; + inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); +@@ -1564,7 +1595,7 @@ md_assemble (char * str) + as_fatal (_("Cannot use special register with this instruction")); + + if (exp.X_op != O_constant) +- as_fatal (_("Symbol used as immediate value for msrset/msrclr instructions")); ++ as_fatal (_("Symbol used as immediate value for arithmetic long instructions")); + else + { + output = frag_more (isize); +@@ -1898,8 +1929,9 @@ md_assemble (char * str) + temp = immed & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { ++ + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); +@@ -1928,7 +1960,12 @@ md_assemble (char * str) + reg1 = 0; + } + if (strcmp (op_end, "")) ++ { ++ if(microblaze_arch_size == 64) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ } + else + as_fatal (_("Error in statement syntax")); + +@@ -1967,30 +2004,55 @@ md_assemble (char * str) + } + if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) + { +- temp = immed & 0xFFFFFF8000; +- if (temp != 0 && temp != 0xFFFFFF8000) ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000) + { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } ++ else { ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (immed << IMM_LOW) & IMM_MASK; + } + else + { +- + temp = immed & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { +@@ -2076,25 +2138,50 @@ md_assemble (char * str) + streq (name, "breaid") || + streq (name, "brai") || streq (name, "braid"))) + { +- temp = immed & 0xFFFFFF8000; ++ temp = immed & 0xFFFFFFFFFFFF8000; + if (temp != 0) + { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } +- + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } ++ } + inst |= (immed << IMM_LOW) & IMM_MASK; + } + else +@@ -2194,21 +2281,45 @@ md_assemble (char * str) + { + output = frag_more (isize); + immedl = exp.X_add_number; +- +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); ++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode2 == NULL || opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } + } + + inst |= (reg1 << RD_LOW) & RD_MASK; +@@ -2257,21 +2368,46 @@ md_assemble (char * str) + { + output = frag_more (isize); + immedl = exp.X_add_number; +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- ++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode2 == NULL || opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); + inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } ++ } + + inst |= (reg1 << RA_LOW) & RA_MASK; + inst |= (immedl << IMM_LOW) & IMM_MASK; +@@ -2554,8 +2690,8 @@ md_apply_fix (fixS * fixP, + /* Note: use offsetT because it is signed, valueT is unsigned. */ + offsetT val = (offsetT) * valp; + int i; +- struct op_code_struct * opcode1; +- unsigned long inst1; ++ struct op_code_struct * opcode1, * opcode2; ++ unsigned long inst1,inst2; + + symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _("<unknown>"); + +@@ -2739,30 +2875,75 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_MICROBLAZE_64_TEXTREL: + case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_PCREL: +- /* Add an imm instruction. First save the current instruction. */ +- for (i = 0; i < INST_WORD_SIZE; i++) +- buf[i + INST_WORD_SIZE] = buf[i]; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64 + || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + { + /* Generate the imm instruction. */ ++ if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887) ++ { ++ /* Add an imm instruction. First save the current instruction. */ ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_64; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ buf[0] = INST_BYTE0 (inst1); ++ buf[1] = INST_BYTE1 (inst1); ++ buf[2] = INST_BYTE2 (inst1); ++ buf[3] = INST_BYTE3 (inst1); ++ } ++ else { ++ /* Add an imm instruction. First save the current instruction. */ ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE + 4] = buf[i]; ++ ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 ==NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 40) & IMML_MASK; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_64; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ inst2 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) +- fixP->fx_r_type = BFD_RELOC_64; ++ fixP->fx_r_type = BFD_RELOC_64; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) +- fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ buf[0] = INST_BYTE0 (inst1); ++ buf[1] = INST_BYTE1 (inst1); ++ buf[2] = INST_BYTE2 (inst1); ++ buf[3] = INST_BYTE3 (inst1); ++ buf[4] = INST_BYTE0 (inst2); ++ buf[5] = INST_BYTE1 (inst2); ++ buf[6] = INST_BYTE2 (inst2); ++ buf[7] = INST_BYTE3 (inst2); ++ } + } + else + { ++ /* Add an imm instruction. First save the current instruction. */ ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; + /* Generate the imm instruction. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) +@@ -2774,12 +2955,11 @@ md_apply_fix (fixS * fixP, + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; +- } + buf[0] = INST_BYTE0 (inst1); + buf[1] = INST_BYTE1 (inst1); + buf[2] = INST_BYTE2 (inst1); + buf[3] = INST_BYTE3 (inst1); +- ++ } + /* Add the value only if the symbol is defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { +@@ -2811,21 +2991,41 @@ md_apply_fix (fixS * fixP, + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) { ++ if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887) ++ { ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ } ++ else { ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE + 4] = buf[i]; ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ inst2 = opcode2->bit_sequence; ++ ++ /* We can fixup call to a defined non-global address ++ * within the same section only. */ ++ buf[4] = INST_BYTE0 (inst2); ++ buf[5] = INST_BYTE1 (inst2); ++ buf[6] = INST_BYTE2 (inst2); ++ buf[7] = INST_BYTE3 (inst2); ++ } ++ } + else + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) + as_bad (_("unknown opcode \"%s\""), "imml"); + else + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } +- + inst1 = opcode1->bit_sequence; +- + /* We can fixup call to a defined non-global address + within the same section only. */ + buf[0] = INST_BYTE0 (inst1); +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 0774f70e08..bd9d91cd57 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -626,8 +626,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM6_WIDTH ((int) 0x00000001) + #define MAX_IMM6_WIDTH ((int) 0x00000040) + +-#define MIN_IMML ((long long) 0xffffff8000000000L) +-#define MAX_IMML ((long long) 0x0000007fffffffffL) ++#define MIN_IMML ((long long) -9223372036854775808) ++#define MAX_IMML ((long long) 9223372036854775807) + + #endif /* MICROBLAZE_OPC */ + +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0032-Add-initial-port-of-linux-gdbserver.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0032-Add-initial-port-of-linux-gdbserver.patch new file mode 100644 index 000000000..7ac89d2de --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0032-Add-initial-port-of-linux-gdbserver.patch @@ -0,0 +1,435 @@ +From c347f9727cc86bb0174dc001446c0670e7306692 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 23 Jan 2017 19:07:44 +0530 +Subject: [PATCH 32/43] Add initial port of linux gdbserver add + gdb_proc_service_h to gdbserver microblaze-linux + +gdbserver needs to initialise the microblaze registers + +other archs use this step to run a *_arch_setup() to carry out all +architecture specific setup - may need to add in future + + * add linux-ptrace.o to gdbserver configure + * Update breakpoint opcode + * fix segfault on connecting gdbserver + * add microblaze_linux_memory_remove_breakpoint + * add set_solib_svr4_fetch_link_map_offsets + * add set_gdbarch_fetch_tls_load_module_address + * Force reading of r0 as 0, prevent stores + +Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com> +Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com> +--- + gdb/configure.host | 3 + + gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++ + gdb/microblaze-linux-tdep.c | 29 +++- + gdb/microblaze-tdep.c | 35 ++++- + gdb/microblaze-tdep.h | 4 +- + gdb/regformats/reg-microblaze.dat | 41 ++++++ + 6 files changed, 298 insertions(+), 3 deletions(-) + create mode 100644 gdb/gdbserver/linux-microblaze-low.c + create mode 100644 gdb/regformats/reg-microblaze.dat + +diff --git a/gdb/configure.host b/gdb/configure.host +index c87f997abc..de8d6b00f3 100644 +--- a/gdb/configure.host ++++ b/gdb/configure.host +@@ -65,6 +65,7 @@ hppa*) gdb_host_cpu=pa ;; + i[34567]86*) gdb_host_cpu=i386 ;; + m68*) gdb_host_cpu=m68k ;; + mips*) gdb_host_cpu=mips ;; ++microblaze*) gdb_host_cpu=microblaze ;; + powerpc* | rs6000) gdb_host_cpu=powerpc ;; + sparcv9 | sparc64) gdb_host_cpu=sparc ;; + s390*) gdb_host_cpu=s390 ;; +@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu) + mips*-*-freebsd*) gdb_host=fbsd ;; + mips64*-*-openbsd*) gdb_host=obsd64 ;; + ++microblaze*-*linux*) gdb_host=linux ;; ++ + powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*) + gdb_host=aix ;; + powerpc*-*-freebsd*) gdb_host=fbsd ;; +diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c +new file mode 100644 +index 0000000000..cba5d6fc58 +--- /dev/null ++++ b/gdb/gdbserver/linux-microblaze-low.c +@@ -0,0 +1,189 @@ ++/* GNU/Linux/Microblaze specific low level interface, for the remote server for ++ GDB. ++ Copyright (C) 1995-2013 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see <http://www.gnu.org/licenses/>. */ ++ ++#include "server.h" ++#include "linux-low.h" ++ ++#include <asm/ptrace.h> ++#include <sys/procfs.h> ++#include <sys/ptrace.h> ++ ++#include "gdb_proc_service.h" ++ ++static int microblaze_regmap[] = ++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3), ++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7), ++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11), ++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15), ++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19), ++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23), ++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27), ++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31), ++ PT_PC, PT_MSR, PT_EAR, PT_ESR, ++ PT_FSR ++ }; ++ ++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0]) ++ ++/* Defined in auto-generated file microblaze-linux.c. */ ++void init_registers_microblaze (void); ++ ++static int ++microblaze_cannot_store_register (int regno) ++{ ++ if (microblaze_regmap[regno] == -1 || regno == 0) ++ return 1; ++ ++ return 0; ++} ++ ++static int ++microblaze_cannot_fetch_register (int regno) ++{ ++ return 0; ++} ++ ++static CORE_ADDR ++microblaze_get_pc (struct regcache *regcache) ++{ ++ unsigned long pc; ++ ++ collect_register_by_name (regcache, "pc", &pc); ++ return (CORE_ADDR) pc; ++} ++ ++static void ++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc) ++{ ++ unsigned long newpc = pc; ++ ++ supply_register_by_name (regcache, "pc", &newpc); ++} ++ ++/* dbtrap insn */ ++/* brki r16, 0x18; */ ++static const unsigned long microblaze_breakpoint = 0xba0c0018; ++#define microblaze_breakpoint_len 4 ++ ++static int ++microblaze_breakpoint_at (CORE_ADDR where) ++{ ++ unsigned long insn; ++ ++ (*the_target->read_memory) (where, (unsigned char *) &insn, 4); ++ if (insn == microblaze_breakpoint) ++ return 1; ++ /* If necessary, recognize more trap instructions here. GDB only uses the ++ one. */ ++ return 0; ++} ++ ++static CORE_ADDR ++microblaze_reinsert_addr (struct regcache *regcache) ++{ ++ unsigned long pc; ++ collect_register_by_name (regcache, "r15", &pc); ++ return pc; ++} ++ ++#ifdef HAVE_PTRACE_GETREGS ++ ++static void ++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) ++{ ++ int size = register_size (regno); ++ ++ memset (buf, 0, sizeof (long)); ++ ++ if (size < sizeof (long)) ++ collect_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ collect_register (regcache, regno, buf); ++} ++ ++static void ++microblaze_supply_ptrace_register (struct regcache *regcache, ++ int regno, const char *buf) ++{ ++ int size = register_size (regno); ++ ++ if (regno == 0) { ++ unsigned long regbuf_0 = 0; ++ /* clobbering r0 so that it is always 0 as enforced by hardware */ ++ supply_register (regcache, regno, (const char*)®buf_0); ++ } else { ++ if (size < sizeof (long)) ++ supply_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ supply_register (regcache, regno, buf); ++ } ++} ++ ++/* Provide only a fill function for the general register set. ps_lgetregs ++ will use this for NPTL support. */ ++ ++static void microblaze_fill_gregset (struct regcache *regcache, void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++static void ++microblaze_store_gregset (struct regcache *regcache, const void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++#endif /* HAVE_PTRACE_GETREGS */ ++ ++struct regset_info target_regsets[] = { ++#ifdef HAVE_PTRACE_GETREGS ++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, ++ { 0, 0, 0, -1, -1, NULL, NULL }, ++#endif /* HAVE_PTRACE_GETREGS */ ++ { 0, 0, 0, -1, -1, NULL, NULL } ++}; ++ ++struct linux_target_ops the_low_target = { ++ init_registers_microblaze, ++ microblaze_num_regs, ++ microblaze_regmap, ++ NULL, ++ microblaze_cannot_fetch_register, ++ microblaze_cannot_store_register, ++ NULL, /* fetch_register */ ++ microblaze_get_pc, ++ microblaze_set_pc, ++ (const unsigned char *) µblaze_breakpoint, ++ microblaze_breakpoint_len, ++ microblaze_reinsert_addr, ++ 0, ++ microblaze_breakpoint_at, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ microblaze_collect_ptrace_register, ++ microblaze_supply_ptrace_register, ++}; +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 4e5f60cd4e..7ab650a1cc 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,6 +37,22 @@ + #include "tramp-frame.h" + #include "linux-tdep.h" + ++static int microblaze_debug_flag = 0; ++ ++static void ++microblaze_debug (const char *fmt, ...) ++{ ++ if (microblaze_debug_flag) ++ { ++ va_list args; ++ ++ va_start (args, fmt); ++ printf_unfiltered ("MICROBLAZE LINUX: "); ++ vprintf_unfiltered (fmt, args); ++ va_end (args); ++ } ++} ++ + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -46,18 +62,25 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + int val; + int bplen; + gdb_byte old_contents[BREAKPOINT_MAX]; ++ struct cleanup *cleanup; + + /* Determine appropriate breakpoint contents and size for this address. */ + bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); + ++ /* Make sure we see the memory breakpoints. */ ++ cleanup = make_show_memory_breakpoints_cleanup (1); + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the + program modified the code on us, so it is wrong to put back the + old value. */ + if (val == 0 && memcmp (bp, old_contents, bplen) == 0) +- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } + ++ do_cleanups (cleanup); + return val; + } + +@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info, + /* Trampolines. */ + tramp_frame_prepend_unwinder (gdbarch, + µblaze_linux_sighandler_tramp_frame); ++ ++ /* Enable TLS support. */ ++ set_gdbarch_fetch_tls_load_module_address (gdbarch, ++ svr4_fetch_objfile_link_map); + } + + void +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 1248acbdc9..730a2b281f 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc) + constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; + + typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; +- ++static int ++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, ++ struct bp_target_info *bp_tgt) ++{ ++ CORE_ADDR addr = bp_tgt->placed_address; ++ const unsigned char *bp; ++ int val; ++ int bplen; ++ gdb_byte old_contents[BREAKPOINT_MAX]; ++ struct cleanup *cleanup; ++ ++ /* Determine appropriate breakpoint contents and size for this address. */ ++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); ++ if (bp == NULL) ++ error (_("Software breakpoints not implemented for this target.")); ++ ++ /* Make sure we see the memory breakpoints. */ ++ cleanup = make_show_memory_breakpoints_cleanup (1); ++ val = target_read_memory (addr, old_contents, bplen); ++ ++ /* If our breakpoint is no longer at the address, this means that the ++ program modified the code on us, so it is wrong to put back the ++ old value. */ ++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0) ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } ++ ++ do_cleanups (cleanup); ++ return val; ++} + + /* Allocate and initialize a frame cache. */ + +@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + microblaze_breakpoint::bp_from_kind); ++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + + set_gdbarch_frame_args_skip (gdbarch, 8); + +@@ -770,4 +802,5 @@ When non-zero, microblaze specific debugging is enabled."), + NULL, + &setdebuglist, &showdebuglist); + ++ + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index a0048148e4..63aab84ef6 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -117,6 +117,8 @@ struct microblaze_frame_cache + + /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. + Only used for native debugging. */ +-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60} ++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} ++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} ++ + + #endif /* microblaze-tdep.h */ +diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat +new file mode 100644 +index 0000000000..bd8a438442 +--- /dev/null ++++ b/gdb/regformats/reg-microblaze.dat +@@ -0,0 +1,41 @@ ++name:microblaze ++expedite:r1,pc ++32:r0 ++32:r1 ++32:r2 ++32:r3 ++32:r4 ++32:r5 ++32:r6 ++32:r7 ++32:r8 ++32:r9 ++32:r10 ++32:r11 ++32:r12 ++32:r13 ++32:r14 ++32:r15 ++32:r16 ++32:r17 ++32:r18 ++32:r19 ++32:r20 ++32:r21 ++32:r22 ++32:r23 ++32:r24 ++32:r25 ++32:r26 ++32:r27 ++32:r28 ++32:r29 ++32:r30 ++32:r31 ++32:pc ++32:msr ++32:ear ++32:esr ++32:fsr ++32:slr ++32:shr +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0033-Initial-port-of-core-reading-support.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0033-Initial-port-of-core-reading-support.patch new file mode 100644 index 000000000..e6bbf2b71 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0033-Initial-port-of-core-reading-support.patch @@ -0,0 +1,388 @@ +From 0fd864ff792d7bcbbcbed5ee0ae9f429f1fd2353 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 24 Jan 2017 14:55:56 +0530 +Subject: [PATCH 33/43] Initial port of core reading support Added support for + reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO + information for rebuilding ".reg" sections of core dumps at run time. + +Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com> +Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com> +--- + bfd/elf32-microblaze.c | 84 ++++++++++++++++++++++++++++++++++ + gdb/configure.tgt | 2 +- + gdb/microblaze-linux-tdep.c | 57 +++++++++++++++++++++++ + gdb/microblaze-tdep.c | 90 +++++++++++++++++++++++++++++++++++++ + gdb/microblaze-tdep.h | 27 +++++++++++ + 5 files changed, 259 insertions(+), 1 deletion(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 6a795c5069..c280431df6 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -767,6 +767,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name) + return _bfd_elf_is_local_label_name (abfd, name); + } + ++/* Support for core dump NOTE sections. */ ++static bfd_boolean ++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) ++{ ++ int offset; ++ unsigned int size; ++ ++ switch (note->descsz) ++ { ++ default: ++ return FALSE; ++ ++ case 228: /* Linux/MicroBlaze */ ++ /* pr_cursig */ ++ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); ++ ++ /* pr_pid */ ++ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24); ++ ++ /* pr_reg */ ++ offset = 72; ++ size = 50 * 4; ++ ++ break; ++ } ++ ++ /* Make a ".reg/999" section. */ ++ return _bfd_elfcore_make_pseudosection (abfd, ".reg", ++ size, note->descpos + offset); ++} ++ ++static bfd_boolean ++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) ++{ ++ switch (note->descsz) ++ { ++ default: ++ return FALSE; ++ ++ case 128: /* Linux/MicroBlaze elf_prpsinfo */ ++ elf_tdata (abfd)->core->program ++ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16); ++ elf_tdata (abfd)->core->command ++ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80); ++ } ++ ++ /* Note that for some reason, a spurious space is tacked ++ onto the end of the args in some (at least one anyway) ++ implementations, so strip it off if it exists. */ ++ ++ { ++ char *command = elf_tdata (abfd)->core->command; ++ int n = strlen (command); ++ ++ if (0 < n && command[n - 1] == ' ') ++ command[n - 1] = '\0'; ++ } ++ ++ return TRUE; ++} ++ ++/* The microblaze linker (like many others) needs to keep track of ++ the number of relocs that it decides to copy as dynamic relocs in ++ check_relocs for each symbol. This is so that it can later discard ++ them if they are found to be unnecessary. We store the information ++ in a field extending the regular ELF linker hash table. */ ++ ++struct elf32_mb_dyn_relocs ++{ ++ struct elf32_mb_dyn_relocs *next; ++ ++ /* The input section of the reloc. */ ++ asection *sec; ++ ++ /* Total number of relocs copied for the input section. */ ++ bfd_size_type count; ++ ++ /* Number of pc-relative relocs copied for the input section. */ ++ bfd_size_type pc_count; ++}; ++ + /* ELF linker hash entry. */ + + struct elf32_mb_link_hash_entry +@@ -3672,4 +3753,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd, + #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections + #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook + ++#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus ++#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo ++ + #include "elf32-target.h" +diff --git a/gdb/configure.tgt b/gdb/configure.tgt +index 27f122ad04..622bd486b3 100644 +--- a/gdb/configure.tgt ++++ b/gdb/configure.tgt +@@ -397,7 +397,7 @@ mep-*-*) + + microblaze*-linux-*|microblaze*-*-linux*) + # Target: Xilinx MicroBlaze running Linux +- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \ ++ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \ + symfile-mem.o linux-tdep.o" + gdb_sim=../sim/microblaze/libsim.a + ;; +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 7ab650a1cc..e2225d778a 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -135,11 +135,54 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame = + microblaze_linux_sighandler_cache_init + }; + ++const struct microblaze_gregset microblaze_linux_core_gregset; ++ ++static void ++microblaze_linux_supply_core_gregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *gregs, size_t len) ++{ ++ microblaze_supply_gregset (µblaze_linux_core_gregset, regcache, ++ regnum, gregs); ++} ++ ++static void ++microblaze_linux_collect_core_gregset (const struct regset *regset, ++ const struct regcache *regcache, ++ int regnum, void *gregs, size_t len) ++{ ++ microblaze_collect_gregset (µblaze_linux_core_gregset, regcache, ++ regnum, gregs); ++} ++ ++static void ++microblaze_linux_supply_core_fpregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *fpregs, size_t len) ++{ ++ /* FIXME. */ ++ microblaze_supply_fpregset (regcache, regnum, fpregs); ++} ++ ++static void ++microblaze_linux_collect_core_fpregset (const struct regset *regset, ++ const struct regcache *regcache, ++ int regnum, void *fpregs, size_t len) ++{ ++ /* FIXME. */ ++ microblaze_collect_fpregset (regcache, regnum, fpregs); ++} + + static void + microblaze_linux_init_abi (struct gdbarch_info info, + struct gdbarch *gdbarch) + { ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ ++ tdep->gregset = regset_alloc (gdbarch, microblaze_linux_supply_core_gregset, ++ microblaze_linux_collect_core_gregset); ++ tdep->sizeof_gregset = 200; ++ + linux_init_abi (info, gdbarch); + + set_gdbarch_memory_remove_breakpoint (gdbarch, +@@ -153,6 +196,20 @@ microblaze_linux_init_abi (struct gdbarch_info info, + tramp_frame_prepend_unwinder (gdbarch, + µblaze_linux_sighandler_tramp_frame); + ++ /* BFD target for core files. */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ ++ ++ /* Shared library handling. */ ++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); ++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); ++ ++ set_gdbarch_regset_from_core_section (gdbarch, ++ microblaze_regset_from_core_section); ++ + /* Enable TLS support. */ + set_gdbarch_fetch_tls_load_module_address (gdbarch, + svr4_fetch_objfile_link_map); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 730a2b281f..49713ea9b1 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -137,6 +137,14 @@ microblaze_fetch_instruction (CORE_ADDR pc) + constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; + + typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; ++static CORE_ADDR ++microblaze_store_arguments (struct regcache *regcache, int nargs, ++ struct value **args, CORE_ADDR sp, ++ int struct_return, CORE_ADDR struct_addr) ++{ ++ error (_("store_arguments not implemented")); ++ return sp; ++} + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -541,6 +549,12 @@ microblaze_frame_base_address (struct frame_info *next_frame, + return cache->base; + } + ++static const struct frame_unwind * ++microblaze_frame_sniffer (struct frame_info *next_frame) ++{ ++ return µblaze_frame_unwind; ++} ++ + static const struct frame_base microblaze_frame_base = + { + µblaze_frame_unwind, +@@ -677,6 +691,71 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) + tdesc_microblaze_with_stack_protect); + } + ++void ++microblaze_supply_gregset (const struct microblaze_gregset *gregset, ++ struct regcache *regcache, ++ int regnum, const void *gregs) ++{ ++ unsigned int *regs = gregs; ++ if (regnum >= 0) ++ regcache_raw_supply (regcache, regnum, regs + regnum); ++ ++ if (regnum == -1) { ++ int i; ++ ++ for (i = 0; i < 50; i++) { ++ regcache_raw_supply (regcache, i, regs + i); ++ } ++ } ++} ++ ++ ++void ++microblaze_collect_gregset (const struct microblaze_gregset *gregset, ++ const struct regcache *regcache, ++ int regnum, void *gregs) ++{ ++ /* FIXME. */ ++} ++ ++void ++microblaze_supply_fpregset (struct regcache *regcache, ++ int regnum, const void *fpregs) ++{ ++ /* FIXME. */ ++} ++ ++void ++microblaze_collect_fpregset (const struct regcache *regcache, ++ int regnum, void *fpregs) ++{ ++ /* FIXME. */ ++} ++ ++ ++/* Return the appropriate register set for the core section identified ++ by SECT_NAME and SECT_SIZE. */ ++ ++const struct regset * ++microblaze_regset_from_core_section (struct gdbarch *gdbarch, ++ const char *sect_name, size_t sect_size) ++{ ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ ++ microblaze_debug ("microblaze_regset_from_core_section, sect_name = %s\n", sect_name); ++ ++ if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) ++ return tdep->gregset; ++ ++ if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) ++ return tdep->fpregset; ++ ++ microblaze_debug ("microblaze_regset_from_core_section returning null :-( \n"); ++ return NULL; ++} ++ ++ ++ + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { +@@ -733,6 +812,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + tdep = XCNEW (struct gdbarch_tdep); + gdbarch = gdbarch_alloc (&info, tdep); + ++ tdep->gregset = NULL; ++ tdep->sizeof_gregset = 0; ++ tdep->fpregset = NULL; ++ tdep->sizeof_fpregset = 0; + set_gdbarch_long_double_bit (gdbarch, 128); + + set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS); +@@ -781,6 +864,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); + if (tdesc_data != NULL) + tdesc_use_registers (gdbarch, tdesc, tdesc_data); ++ //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); ++ ++ /* If we have register sets, enable the generic core file support. */ ++ if (tdep->gregset) { ++ set_gdbarch_regset_from_core_section (gdbarch, ++ microblaze_regset_from_core_section); ++ } + + return gdbarch; + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 63aab84ef6..02650f61d9 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -22,8 +22,22 @@ + + + /* Microblaze architecture-specific information. */ ++struct microblaze_gregset ++{ ++ unsigned int gregs[32]; ++ unsigned int fpregs[32]; ++ unsigned int pregs[16]; ++}; ++ + struct gdbarch_tdep + { ++ int dummy; // declare something. ++ ++ /* Register sets. */ ++ struct regset *gregset; ++ size_t sizeof_gregset; ++ struct regset *fpregset; ++ size_t sizeof_fpregset; + }; + + /* Register numbers. */ +@@ -120,5 +134,18 @@ struct microblaze_frame_cache + #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} + #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} + ++extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset, ++ struct regcache *regcache, ++ int regnum, const void *gregs); ++extern void microblaze_collect_gregset (const struct microblaze_gregset *gregset, ++ const struct regcache *regcache, ++ int regnum, void *gregs); ++extern void microblaze_supply_fpregset (struct regcache *regcache, ++ int regnum, const void *fpregs); ++extern void microblaze_collect_fpregset (const struct regcache *regcache, ++ int regnum, void *fpregs); ++ ++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch, ++ const char *sect_name, size_t sect_size); + + #endif /* microblaze-tdep.h */ +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0034-Fix-debug-message-when-register-is-unavailable.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0034-Fix-debug-message-when-register-is-unavailable.patch new file mode 100644 index 000000000..df5b3db3a --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0034-Fix-debug-message-when-register-is-unavailable.patch @@ -0,0 +1,40 @@ +From e44a27432ce56bb48eb9785ffaae14bc3a12bd27 Mon Sep 17 00:00:00 2001 +From: Nathan Rossi <nathan.rossi@petalogix.com> +Date: Tue, 8 May 2012 18:11:17 +1000 +Subject: [PATCH 34/43] Fix debug message when register is unavailable + +Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com> +--- + gdb/frame.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +diff --git a/gdb/frame.c b/gdb/frame.c +index d8b5f819f1..49706dc97c 100644 +--- a/gdb/frame.c ++++ b/gdb/frame.c +@@ -1227,12 +1227,19 @@ frame_unwind_register_value (frame_info *next_frame, int regnum) + else + { + int i; +- const gdb_byte *buf = value_contents (value); ++ const gdb_byte *buf = NULL; ++ if (value_entirely_available(value)) { ++ buf = value_contents (value); ++ } + + fprintf_unfiltered (gdb_stdlog, " bytes="); + fprintf_unfiltered (gdb_stdlog, "["); +- for (i = 0; i < register_size (gdbarch, regnum); i++) +- fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]); ++ if (buf != NULL) { ++ for (i = 0; i < register_size (gdbarch, regnum); i++) ++ fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]); ++ } else { ++ fprintf_unfiltered (gdb_stdlog, "unavailable"); ++ } + fprintf_unfiltered (gdb_stdlog, "]"); + } + } +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0035-revert-master-rebase-changes-to-gdbserver.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0035-revert-master-rebase-changes-to-gdbserver.patch new file mode 100644 index 000000000..ddb53a075 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0035-revert-master-rebase-changes-to-gdbserver.patch @@ -0,0 +1,31 @@ +From 1c5dbbd272854e6e7912e2602bdfd78b64399319 Mon Sep 17 00:00:00 2001 +From: David Holsgrove <david.holsgrove@xilinx.com> +Date: Mon, 22 Jul 2013 11:16:05 +1000 +Subject: [PATCH 35/43] revert master-rebase changes to gdbserver + +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + gdb/gdbserver/configure.srv | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv +index d19d22b3a3..7a0be5b072 100644 +--- a/gdb/gdbserver/configure.srv ++++ b/gdb/gdbserver/configure.srv +@@ -210,6 +210,13 @@ case "${target}" in + srv_linux_usrregs=yes + srv_linux_thread_db=yes + ;; ++ microblaze*-*-linux*) srv_regobj=microblaze-linux.o ++ srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o " ++ srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o" ++ srv_linux_regsets=yes ++ srv_linux_usrregs=yes ++ srv_linux_thread_db=yes ++ ;; + powerpc*-*-linux*) srv_regobj="powerpc-32l.o" + srv_regobj="${srv_regobj} powerpc-altivec32l.o" + srv_regobj="${srv_regobj} powerpc-cell32l.o" +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver-previous-c.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver-previous-c.patch new file mode 100644 index 000000000..f2e5e9510 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver-previous-c.patch @@ -0,0 +1,33 @@ +From bd55e11af18006afb87a8b0fbd93bb0920354e0e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 30 Apr 2018 17:09:55 +0530 +Subject: [PATCH 36/43] revert master-rebase changes to gdbserver , previous + commit typo's + +--- + gdb/gdbserver/Makefile.in | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in +index 4ae13692a2..45d95e6cab 100644 +--- a/gdb/gdbserver/Makefile.in ++++ b/gdb/gdbserver/Makefile.in +@@ -169,6 +169,7 @@ SFILES = \ + $(srcdir)/linux-low.c \ + $(srcdir)/linux-m32r-low.c \ + $(srcdir)/linux-m68k-low.c \ ++ $(srcdir)/linux-microblaze-low.c \ + $(srcdir)/linux-mips-low.c \ + $(srcdir)/linux-nios2-low.c \ + $(srcdir)/linux-ppc-low.c \ +@@ -226,6 +227,7 @@ SFILES = \ + $(srcdir)/nat/linux-osdata.c \ + $(srcdir)/nat/linux-personality.c \ + $(srcdir)/nat/mips-linux-watch.c \ ++ $(srcdir)/nat/microblaze-linux.c \ + $(srcdir)/nat/ppc-linux.c \ + $(srcdir)/nat/fork-inferior.c \ + $(srcdir)/target/waitstatus.c +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch new file mode 100644 index 000000000..e2b601b66 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch @@ -0,0 +1,32 @@ +From 988a9a41ac91ce3293af8708c1c88c51c48a2a72 Mon Sep 17 00:00:00 2001 +From: David Holsgrove <david.holsgrove@xilinx.com> +Date: Mon, 16 Dec 2013 16:37:32 +1000 +Subject: [PATCH 37/43] microblaze: Add build_gdbserver=yes to top level + configure.tgt + +For Microblaze linux toolchains, set the build_gdbserver=yes +to allow driving gdbserver configuration from the upper level + +This patch has been absorbed into the original patch to add +linux gdbserver support for Microblaze. + +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + gdb/configure.tgt | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gdb/configure.tgt b/gdb/configure.tgt +index 622bd486b3..989523735b 100644 +--- a/gdb/configure.tgt ++++ b/gdb/configure.tgt +@@ -405,6 +405,7 @@ microblaze*-*-*) + # Target: Xilinx MicroBlaze running standalone + gdb_target_obs="microblaze-tdep.o" + gdb_sim=../sim/microblaze/libsim.a ++ build_gdbserver=yes + ;; + + mips*-*-linux*) +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0038-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0038-Initial-support-for-native-gdb.patch new file mode 100644 index 000000000..1a50f0a62 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0038-Initial-support-for-native-gdb.patch @@ -0,0 +1,511 @@ +From aa9cb6db79c663dc944cb67928d16e63f2a69f74 Mon Sep 17 00:00:00 2001 +From: David Holsgrove <david.holsgrove@petalogix.com> +Date: Fri, 20 Jul 2012 15:18:35 +1000 +Subject: [PATCH 38/43] Initial support for native gdb + +microblaze: Follow PPC method of getting setting registers +using PTRACE PEEK/POKE + +Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com> + +Conflicts: + gdb/Makefile.in +--- + gdb/Makefile.in | 4 +- + gdb/config/microblaze/linux.mh | 9 + + gdb/microblaze-linux-nat.c | 431 +++++++++++++++++++++++++++++++++ + 3 files changed, 443 insertions(+), 1 deletion(-) + create mode 100644 gdb/config/microblaze/linux.mh + create mode 100644 gdb/microblaze-linux-nat.c + +diff --git a/gdb/Makefile.in b/gdb/Makefile.in +index 215ef7933c..8c9a3c07c0 100644 +--- a/gdb/Makefile.in ++++ b/gdb/Makefile.in +@@ -1316,6 +1316,7 @@ HFILES_NO_SRCDIR = \ + memory-map.h \ + memrange.h \ + microblaze-tdep.h \ ++ microblaze-linux-tdep.h \ + mips-linux-tdep.h \ + mips-nbsd-tdep.h \ + mips-tdep.h \ +@@ -1349,6 +1350,7 @@ HFILES_NO_SRCDIR = \ + prologue-value.h \ + psympriv.h \ + psymtab.h \ ++ ia64-hpux-tdep.h \ + ravenscar-thread.h \ + record.h \ + record-full.h \ +@@ -2263,6 +2265,7 @@ ALLDEPFILES = \ + m68k-tdep.c \ + microblaze-linux-tdep.c \ + microblaze-tdep.c \ ++ microblaze-linux-nat.c \ + mingw-hdep.c \ + mips-fbsd-nat.c \ + mips-fbsd-tdep.c \ +@@ -2365,7 +2368,6 @@ ALLDEPFILES = \ + xtensa-linux-tdep.c \ + xtensa-tdep.c \ + xtensa-xtregs.c \ +- common/mingw-strerror.c \ + common/posix-strerror.c + + # Some files need explicit build rules (due to -Werror problems) or due +diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh +new file mode 100644 +index 0000000000..a4eaf540e1 +--- /dev/null ++++ b/gdb/config/microblaze/linux.mh +@@ -0,0 +1,9 @@ ++# Host: Microblaze, running Linux ++ ++NAT_FILE= config/nm-linux.h ++NATDEPFILES= inf-ptrace.o fork-child.o \ ++ microblaze-linux-nat.o proc-service.o linux-thread-db.o \ ++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o ++NAT_CDEPS = $(srcdir)/proc-service.list ++ ++LOADLIBES = -ldl $(RDYNAMIC) +diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c +new file mode 100644 +index 0000000000..e9b8c9c522 +--- /dev/null ++++ b/gdb/microblaze-linux-nat.c +@@ -0,0 +1,431 @@ ++/* Microblaze GNU/Linux native support. ++ ++ Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free ++ Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see <http://www.gnu.org/licenses/>. */ ++ ++#include "defs.h" ++#include "arch-utils.h" ++#include "dis-asm.h" ++#include "frame.h" ++#include "trad-frame.h" ++#include "symtab.h" ++#include "value.h" ++#include "gdbcmd.h" ++#include "breakpoint.h" ++#include "inferior.h" ++#include "regcache.h" ++#include "target.h" ++#include "frame.h" ++#include "frame-base.h" ++#include "frame-unwind.h" ++#include "dwarf2-frame.h" ++#include "osabi.h" ++ ++#include "gdb_assert.h" ++#include "gdb_string.h" ++#include "target-descriptions.h" ++#include "opcodes/microblaze-opcm.h" ++#include "opcodes/microblaze-dis.h" ++ ++#include "linux-nat.h" ++#include "target-descriptions.h" ++ ++#include <sys/user.h> ++#include <sys/utsname.h> ++#include <sys/procfs.h> ++#include <sys/ptrace.h> ++ ++/* Prototypes for supply_gregset etc. */ ++#include "gregset.h" ++ ++#include "microblaze-tdep.h" ++ ++#include <elf/common.h> ++#include "auxv.h" ++ ++/* Defines ps_err_e, struct ps_prochandle. */ ++#include "gdb_proc_service.h" ++ ++/* On GNU/Linux, threads are implemented as pseudo-processes, in which ++ case we may be tracing more than one process at a time. In that ++ case, inferior_ptid will contain the main process ID and the ++ individual thread (process) ID. get_thread_id () is used to get ++ the thread id if it's available, and the process id otherwise. */ ++ ++int ++get_thread_id (ptid_t ptid) ++{ ++ int tid = TIDGET (ptid); ++ if (0 == tid) ++ tid = PIDGET (ptid); ++ return tid; ++} ++ ++#define GET_THREAD_ID(PTID) get_thread_id (PTID) ++ ++/* Non-zero if our kernel may support the PTRACE_GETREGS and ++ PTRACE_SETREGS requests, for reading and writing the ++ general-purpose registers. Zero if we've tried one of ++ them and gotten an error. */ ++int have_ptrace_getsetregs = 1; ++ ++static int ++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) ++{ ++ int u_addr = -1; ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace ++ interface, and not the wordsize of the program's ABI. */ ++ int wordsize = sizeof (long); ++ ++ /* General purpose registers occupy 1 slot each in the buffer. */ ++ if (regno >= MICROBLAZE_R0_REGNUM ++ && regno <= MICROBLAZE_FSR_REGNUM) ++ u_addr = (regno * wordsize); ++ ++ return u_addr; ++} ++ ++ ++static void ++fetch_register (struct regcache *regcache, int tid, int regno) ++{ ++ struct gdbarch *gdbarch = get_regcache_arch (regcache); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int bytes_transferred; ++ unsigned int offset; /* Offset of registers within the u area. */ ++ char buf[MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ { ++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ ++ regcache_raw_supply (regcache, regno, buf); ++ return; ++ } ++ ++ /* Read the raw register using sizeof(long) sized chunks. On a ++ 32-bit platform, 64-bit floating-point registers will require two ++ transfers. */ ++ for (bytes_transferred = 0; ++ bytes_transferred < register_size (gdbarch, regno); ++ bytes_transferred += sizeof (long)) ++ { ++ long l; ++ ++ errno = 0; ++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); ++ regaddr += sizeof (long); ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "reading register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ memcpy (&buf[bytes_transferred], &l, sizeof (l)); ++ } ++ ++ /* Now supply the register. Keep in mind that the regcache's idea ++ of the register's size may not be a multiple of sizeof ++ (long). */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values are always found at the left end of the ++ bytes transferred. */ ++ regcache_raw_supply (regcache, regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values are found at the right end of the bytes ++ transferred. */ ++ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); ++ regcache_raw_supply (regcache, regno, buf + padding); ++ } ++ else ++ internal_error (__FILE__, __LINE__, ++ _("fetch_register: unexpected byte order: %d"), ++ gdbarch_byte_order (gdbarch)); ++} ++ ++/* This function actually issues the request to ptrace, telling ++ it to get all general-purpose registers and put them into the ++ specified regset. ++ ++ If the ptrace request does not exist, this function returns 0 ++ and properly sets the have_ptrace_* flag. If the request fails, ++ this function calls perror_with_name. Otherwise, if the request ++ succeeds, then the regcache gets filled and 1 is returned. */ ++static int ++fetch_all_gp_regs (struct regcache *regcache, int tid) ++{ ++ struct gdbarch *gdbarch = get_regcache_arch (regcache); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ gdb_gregset_t gregset; ++ ++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) ++ { ++ if (errno == EIO) ++ { ++ have_ptrace_getsetregs = 0; ++ return 0; ++ } ++ perror_with_name (_("Couldn't get general-purpose registers.")); ++ } ++ ++ supply_gregset (regcache, (const gdb_gregset_t *) &gregset); ++ ++ return 1; ++} ++ ++ ++/* This is a wrapper for the fetch_all_gp_regs function. It is ++ responsible for verifying if this target has the ptrace request ++ that can be used to fetch all general-purpose registers at one ++ shot. If it doesn't, then we should fetch them using the ++ old-fashioned way, which is to iterate over the registers and ++ request them one by one. */ ++static void ++fetch_gp_regs (struct regcache *regcache, int tid) ++{ ++ struct gdbarch *gdbarch = get_regcache_arch (regcache); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ int i; ++ ++ if (have_ptrace_getsetregs) ++ if (fetch_all_gp_regs (regcache, tid)) ++ return; ++ ++ /* If we've hit this point, it doesn't really matter which ++ architecture we are using. We just need to read the ++ registers in the "old-fashioned way". */ ++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) ++ fetch_register (regcache, tid, i); ++} ++ ++ ++static void ++store_register (const struct regcache *regcache, int tid, int regno) ++{ ++ struct gdbarch *gdbarch = get_regcache_arch (regcache); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int i; ++ size_t bytes_to_transfer; ++ char buf[MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ return; ++ ++ /* First collect the register. Keep in mind that the regcache's ++ idea of the register's size may not be a multiple of sizeof ++ (long). */ ++ memset (buf, 0, sizeof buf); ++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values always sit at the left end of the buffer. */ ++ regcache_raw_collect (regcache, regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values sit at the right end of the buffer. */ ++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); ++ regcache_raw_collect (regcache, regno, buf + padding); ++ } ++ ++ for (i = 0; i < bytes_to_transfer; i += sizeof (long)) ++ { ++ long l; ++ ++ memcpy (&l, &buf[i], sizeof (l)); ++ errno = 0; ++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); ++ regaddr += sizeof (long); ++ ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "writing register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ } ++} ++ ++/* This function actually issues the request to ptrace, telling ++ it to store all general-purpose registers present in the specified ++ regset. ++ ++ If the ptrace request does not exist, this function returns 0 ++ and properly sets the have_ptrace_* flag. If the request fails, ++ this function calls perror_with_name. Otherwise, if the request ++ succeeds, then the regcache is stored and 1 is returned. */ ++static int ++store_all_gp_regs (const struct regcache *regcache, int tid, int regno) ++{ ++ struct gdbarch *gdbarch = get_regcache_arch (regcache); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ gdb_gregset_t gregset; ++ ++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) ++ { ++ if (errno == EIO) ++ { ++ have_ptrace_getsetregs = 0; ++ return 0; ++ } ++ perror_with_name (_("Couldn't get general-purpose registers.")); ++ } ++ ++ fill_gregset (regcache, &gregset, regno); ++ ++ if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) ++ { ++ if (errno == EIO) ++ { ++ have_ptrace_getsetregs = 0; ++ return 0; ++ } ++ perror_with_name (_("Couldn't set general-purpose registers.")); ++ } ++ ++ return 1; ++} ++ ++/* This is a wrapper for the store_all_gp_regs function. It is ++ responsible for verifying if this target has the ptrace request ++ that can be used to store all general-purpose registers at one ++ shot. If it doesn't, then we should store them using the ++ old-fashioned way, which is to iterate over the registers and ++ store them one by one. */ ++static void ++store_gp_regs (const struct regcache *regcache, int tid, int regno) ++{ ++ struct gdbarch *gdbarch = get_regcache_arch (regcache); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ int i; ++ ++ if (have_ptrace_getsetregs) ++ if (store_all_gp_regs (regcache, tid, regno)) ++ return; ++ ++ /* If we hit this point, it doesn't really matter which ++ architecture we are using. We just need to store the ++ registers in the "old-fashioned way". */ ++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) ++ store_register (regcache, tid, i); ++} ++ ++ ++/* Fetch registers from the child process. Fetch all registers if ++ regno == -1, otherwise fetch all general registers or all floating ++ point registers depending upon the value of regno. */ ++ ++static void ++microblaze_linux_fetch_inferior_registers (struct target_ops *ops, ++ struct regcache *regcache, int regno) ++{ ++ /* Get the thread id for the ptrace call. */ ++ int tid = GET_THREAD_ID (inferior_ptid); ++ ++ if (regno == -1) ++ fetch_gp_regs (regcache, tid); ++ else ++ fetch_register (regcache, tid, regno); ++} ++ ++/* Store registers back into the inferior. Store all registers if ++ regno == -1, otherwise store all general registers or all floating ++ point registers depending upon the value of regno. */ ++ ++static void ++microblaze_linux_store_inferior_registers (struct target_ops *ops, ++ struct regcache *regcache, int regno) ++{ ++ /* Get the thread id for the ptrace call. */ ++ int tid = GET_THREAD_ID (inferior_ptid); ++ ++ if (regno >= 0) ++ store_register (regcache, tid, regno); ++ else ++ store_gp_regs (regcache, tid, -1); ++} ++ ++/* Wrapper functions for the standard regset handling, used by ++ thread debugging. */ ++ ++void ++fill_gregset (const struct regcache *regcache, ++ gdb_gregset_t *gregsetp, int regno) ++{ ++ microblaze_collect_gregset (NULL, regcache, regno, gregsetp); ++} ++ ++void ++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) ++{ ++ microblaze_supply_gregset (NULL, regcache, -1, gregsetp); ++} ++ ++void ++fill_fpregset (const struct regcache *regcache, ++ gdb_fpregset_t *fpregsetp, int regno) ++{ ++ /* FIXME. */ ++} ++ ++void ++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) ++{ ++ /* FIXME. */ ++} ++ ++static const struct target_desc * ++microblaze_linux_read_description (struct target_ops *ops) ++{ ++ CORE_ADDR microblaze_hwcap = 0; ++ ++ if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1) ++ return NULL; ++ ++ return NULL; ++} ++ ++ ++void _initialize_microblaze_linux_nat (void); ++ ++void ++_initialize_microblaze_linux_nat (void) ++{ ++ struct target_ops *t; ++ ++ /* Fill in the generic GNU/Linux methods. */ ++ t = linux_target (); ++ ++ /* Add our register access methods. */ ++ t->to_fetch_registers = microblaze_linux_fetch_inferior_registers; ++ t->to_store_registers = microblaze_linux_store_inferior_registers; ++ ++ t->to_read_description = microblaze_linux_read_description; ++ ++ /* Register the target. */ ++ linux_nat_add_target (t); ++} +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch new file mode 100644 index 000000000..0b1475a79 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch @@ -0,0 +1,309 @@ +From 0b5b76d6c9757ebb1c9677772c24272957190345 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 17 Feb 2017 14:09:40 +0530 +Subject: [PATCH 39/43] Fixing the issues related to GDB-7.12 added all the + required function which are new in 7.12 and removed few deprecated functions + from 7.6 + +--- + gdb/config/microblaze/linux.mh | 4 +- + gdb/gdbserver/configure.srv | 3 +- + gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++---- + gdb/microblaze-linux-tdep.c | 68 +++++++++++++++++-- + gdb/microblaze-tdep.h | 1 + + 5 files changed, 153 insertions(+), 20 deletions(-) + +diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh +index a4eaf540e1..74a53b854a 100644 +--- a/gdb/config/microblaze/linux.mh ++++ b/gdb/config/microblaze/linux.mh +@@ -1,9 +1,11 @@ + # Host: Microblaze, running Linux + ++#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o + NAT_FILE= config/nm-linux.h + NATDEPFILES= inf-ptrace.o fork-child.o \ + microblaze-linux-nat.o proc-service.o linux-thread-db.o \ +- linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o ++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \ ++ linux-waitpid.o linux-personality.o linux-namespaces.o + NAT_CDEPS = $(srcdir)/proc-service.list + + LOADLIBES = -ldl $(RDYNAMIC) +diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv +index 7a0be5b072..c421790bd0 100644 +--- a/gdb/gdbserver/configure.srv ++++ b/gdb/gdbserver/configure.srv +@@ -211,8 +211,7 @@ case "${target}" in + srv_linux_thread_db=yes + ;; + microblaze*-*-linux*) srv_regobj=microblaze-linux.o +- srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o " +- srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o" ++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o " + srv_linux_regsets=yes + srv_linux_usrregs=yes + srv_linux_thread_db=yes +diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c +index cba5d6fc58..a2733f3c21 100644 +--- a/gdb/gdbserver/linux-microblaze-low.c ++++ b/gdb/gdbserver/linux-microblaze-low.c +@@ -39,10 +39,11 @@ static int microblaze_regmap[] = + PT_FSR + }; + +-#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0]) ++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0])) + + /* Defined in auto-generated file microblaze-linux.c. */ + void init_registers_microblaze (void); ++extern const struct target_desc *tdesc_microblaze; + + static int + microblaze_cannot_store_register (int regno) +@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc) + static const unsigned long microblaze_breakpoint = 0xba0c0018; + #define microblaze_breakpoint_len 4 + ++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ ++ ++static const gdb_byte * ++microblaze_sw_breakpoint_from_kind (int kind, int *size) ++{ ++ *size = microblaze_breakpoint_len; ++ return (const gdb_byte *) µblaze_breakpoint; ++} ++ + static int + microblaze_breakpoint_at (CORE_ADDR where) + { +@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache) + static void + microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) + { +- int size = register_size (regno); ++ int size = register_size (regcache->tdesc, regno); + + memset (buf, 0, sizeof (long)); + +@@ -121,7 +131,7 @@ static void + microblaze_supply_ptrace_register (struct regcache *regcache, + int regno, const char *buf) + { +- int size = register_size (regno); ++ int size = register_size (regcache->tdesc, regno); + + if (regno == 0) { + unsigned long regbuf_0 = 0; +@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf) + + #endif /* HAVE_PTRACE_GETREGS */ + +-struct regset_info target_regsets[] = { ++static struct regset_info microblaze_regsets[] = { + #ifdef HAVE_PTRACE_GETREGS + { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, +- { 0, 0, 0, -1, -1, NULL, NULL }, ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, + #endif /* HAVE_PTRACE_GETREGS */ +- { 0, 0, 0, -1, -1, NULL, NULL } ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, ++ NULL_REGSET + }; + ++static struct usrregs_info microblaze_usrregs_info = ++ { ++ microblaze_num_regs, ++ microblaze_regmap, ++ }; ++ ++static struct regsets_info microblaze_regsets_info = ++ { ++ microblaze_regsets, /* regsets */ ++ 0, /* num_regsets */ ++ NULL, /* disabled_regsets */ ++ }; ++ ++static struct regs_info regs_info = ++ { ++ NULL, /* regset_bitmap */ ++ µblaze_usrregs_info, ++ µblaze_regsets_info ++ }; ++ ++static const struct regs_info * ++microblaze_regs_info (void) ++{ ++ return ®s_info; ++} ++ ++/* Support for hardware single step. */ ++ ++static int ++microblaze_supports_hardware_single_step (void) ++{ ++ return 1; ++} ++ ++ ++static void ++microblaze_arch_setup (void) ++{ ++ current_process ()->tdesc = tdesc_microblaze; ++} ++ + struct linux_target_ops the_low_target = { +- init_registers_microblaze, +- microblaze_num_regs, +- microblaze_regmap, +- NULL, ++ microblaze_arch_setup, ++ microblaze_regs_info, + microblaze_cannot_fetch_register, + microblaze_cannot_store_register, + NULL, /* fetch_register */ + microblaze_get_pc, + microblaze_set_pc, +- (const unsigned char *) µblaze_breakpoint, +- microblaze_breakpoint_len, +- microblaze_reinsert_addr, ++ NULL, ++ microblaze_sw_breakpoint_from_kind, ++ NULL, + 0, + microblaze_breakpoint_at, + NULL, + NULL, + NULL, + NULL, ++ NULL, + microblaze_collect_ptrace_register, + microblaze_supply_ptrace_register, ++ NULL, /* siginfo_fixup */ ++ NULL, /* new_process */ ++ NULL, /* new_thread */ ++ NULL, /* new_fork */ ++ NULL, /* prepare_to_resume */ ++ NULL, /* process_qsupported */ ++ NULL, /* supports_tracepoints */ ++ NULL, /* get_thread_area */ ++ NULL, /* install_fast_tracepoint_jump_pad */ ++ NULL, /* emit_ops */ ++ NULL, /* get_min_fast_tracepoint_insn_len */ ++ NULL, /* supports_range_stepping */ ++ NULL, /* breakpoint_kind_from_current_state */ ++ microblaze_supports_hardware_single_step, + }; ++ ++void ++initialize_low_arch (void) ++{ ++ init_registers_microblaze (); ++} +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index e2225d778a..011e513941 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -29,13 +29,76 @@ + #include "regcache.h" + #include "value.h" + #include "osabi.h" +-#include "regset.h" + #include "solib-svr4.h" + #include "microblaze-tdep.h" + #include "trad-frame.h" + #include "frame-unwind.h" + #include "tramp-frame.h" + #include "linux-tdep.h" ++#include "glibc-tdep.h" ++ ++#include "gdb_assert.h" ++ ++#ifndef REGSET_H ++#define REGSET_H 1 ++ ++struct gdbarch; ++struct regcache; ++ ++/* Data structure for the supported register notes in a core file. */ ++struct core_regset_section ++{ ++ const char *sect_name; ++ int size; ++ const char *human_name; ++}; ++ ++/* Data structure describing a register set. */ ++ ++typedef void (supply_regset_ftype) (const struct regset *, struct regcache *, ++ int, const void *, size_t); ++typedef void (collect_regset_ftype) (const struct regset *, ++ const struct regcache *, ++ int, void *, size_t); ++ ++struct regset ++{ ++ /* Data pointer for private use by the methods below, presumably ++ providing some sort of description of the register set. */ ++ const void *descr; ++ ++ /* Function supplying values in a register set to a register cache. */ ++ supply_regset_ftype *supply_regset; ++ ++ /* Function collecting values in a register set from a register cache. */ ++ collect_regset_ftype *collect_regset; ++ ++ /* Architecture associated with the register set. */ ++ struct gdbarch *arch; ++}; ++ ++#endif ++ ++/* Allocate a fresh 'struct regset' whose supply_regset function is ++ SUPPLY_REGSET, and whose collect_regset function is COLLECT_REGSET. ++ If the regset has no collect_regset function, pass NULL for ++ COLLECT_REGSET. ++ ++ The object returned is allocated on ARCH's obstack. */ ++ ++struct regset * ++regset_alloc (struct gdbarch *arch, ++ supply_regset_ftype *supply_regset, ++ collect_regset_ftype *collect_regset) ++{ ++ struct regset *regset = GDBARCH_OBSTACK_ZALLOC (arch, struct regset); ++ ++ regset->arch = arch; ++ regset->supply_regset = supply_regset; ++ regset->collect_regset = collect_regset; ++ ++ return regset; ++} + + static int microblaze_debug_flag = 0; + +@@ -207,9 +270,6 @@ microblaze_linux_init_abi (struct gdbarch_info info, + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); + set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); + +- set_gdbarch_regset_from_core_section (gdbarch, +- microblaze_regset_from_core_section); +- + /* Enable TLS support. */ + set_gdbarch_fetch_tls_load_module_address (gdbarch, + svr4_fetch_objfile_link_map); +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 02650f61d9..3777cbb6a8 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -24,6 +24,7 @@ + /* Microblaze architecture-specific information. */ + struct microblaze_gregset + { ++ microblaze_gregset() {} + unsigned int gregs[32]; + unsigned int fpregs[32]; + unsigned int pregs[16]; +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch new file mode 100644 index 000000000..6582af01a --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch @@ -0,0 +1,1168 @@ +From 34e572e123b166122cc54a8d8e66676c36515711 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 31 Jan 2019 14:36:00 +0530 +Subject: [PATCH 40/43] [Patch, microblaze]: Adding 64 bit MB support Added new + architecture to Microblaze 64-bit support to GDB Signed-off-by :Nagaraju + Mekala <nmekala@xilix.com> + +Merged on top of binutils work. + +Signed-off-by: Mark Hatle <mark.hatle@xilinx.com> +--- + bfd/archures.c | 2 + + bfd/bfd-in2.h | 2 + + bfd/cpu-microblaze.c | 12 +- + bfd/elf32-microblaze.c | 93 +------- + gas/config/tc-microblaze.c | 16 +- + gas/config/tc-microblaze.h | 4 + + gdb/Makefile.in | 2 +- + gdb/features/Makefile | 3 + + gdb/features/microblaze-core.xml | 6 +- + gdb/features/microblaze-stack-protect.xml | 4 +- + gdb/features/microblaze-with-stack-protect.c | 8 +- + gdb/features/microblaze.c | 6 +- + gdb/features/microblaze64-core.xml | 69 ++++++ + gdb/features/microblaze64-stack-protect.xml | 12 + + .../microblaze64-with-stack-protect.c | 79 +++++++ + .../microblaze64-with-stack-protect.xml | 12 + + gdb/features/microblaze64.c | 77 +++++++ + gdb/features/microblaze64.xml | 11 + + gdb/microblaze-tdep.c | 207 ++++++++++++++++-- + gdb/microblaze-tdep.h | 8 +- + .../microblaze-with-stack-protect.dat | 4 +- + opcodes/microblaze-opc.h | 1 - + 22 files changed, 504 insertions(+), 134 deletions(-) + create mode 100644 gdb/features/microblaze64-core.xml + create mode 100644 gdb/features/microblaze64-stack-protect.xml + create mode 100644 gdb/features/microblaze64-with-stack-protect.c + create mode 100644 gdb/features/microblaze64-with-stack-protect.xml + create mode 100644 gdb/features/microblaze64.c + create mode 100644 gdb/features/microblaze64.xml + +diff --git a/bfd/archures.c b/bfd/archures.c +index 647cf0d8d4..3fdf7c3c0e 100644 +--- a/bfd/archures.c ++++ b/bfd/archures.c +@@ -512,6 +512,8 @@ DESCRIPTION + . bfd_arch_lm32, {* Lattice Mico32. *} + .#define bfd_mach_lm32 1 + . bfd_arch_microblaze,{* Xilinx MicroBlaze. *} ++.#define bfd_mach_microblaze 1 ++.#define bfd_mach_microblaze64 2 + . bfd_arch_tilepro, {* Tilera TILEPro. *} + . bfd_arch_tilegx, {* Tilera TILE-Gx. *} + .#define bfd_mach_tilepro 1 +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 33c9cb62d9..db624c62b9 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -2411,6 +2411,8 @@ enum bfd_architecture + bfd_arch_lm32, /* Lattice Mico32. */ + #define bfd_mach_lm32 1 + bfd_arch_microblaze,/* Xilinx MicroBlaze. */ ++#define bfd_mach_microblaze 1 ++#define bfd_mach_microblaze64 2 + bfd_arch_tilepro, /* Tilera TILEPro. */ + bfd_arch_tilegx, /* Tilera TILE-Gx. */ + #define bfd_mach_tilepro 1 +diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c +index c91ba46f75..8e7bcead28 100644 +--- a/bfd/cpu-microblaze.c ++++ b/bfd/cpu-microblaze.c +@@ -30,8 +30,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] = + 64, /* 32 bits in a word. */ + 64, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ +- bfd_arch_microblaze, /* Architecture. */ +- 0, /* Machine number - 0 for now. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze64, /* 64 bit Machine */ + "microblaze", /* Architecture name. */ + "MicroBlaze", /* Printable name. */ + 3, /* Section align power. */ +@@ -46,7 +46,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] = + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_microblaze, /* Architecture. */ +- 0, /* Machine number - 0 for now. */ ++ bfd_mach_microblaze, /* 32 bit Machine */ + "microblaze", /* Architecture name. */ + "MicroBlaze", /* Printable name. */ + 3, /* Section align power. */ +@@ -62,7 +62,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] = + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_microblaze, /* Architecture. */ +- 0, /* Machine number - 0 for now. */ ++ bfd_mach_microblaze, /* 32 bit Machine */ + "microblaze", /* Architecture name. */ + "MicroBlaze", /* Printable name. */ + 3, /* Section align power. */ +@@ -76,8 +76,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] = + 64, /* 32 bits in a word. */ + 64, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ +- bfd_arch_microblaze, /* Architecture. */ +- 0, /* Machine number - 0 for now. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze64, /* 64 bit Machine */ + "microblaze", /* Architecture name. */ + "MicroBlaze", /* Printable name. */ + 3, /* Section align power. */ +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index c280431df6..f9996eae12 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -767,87 +767,6 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name) + return _bfd_elf_is_local_label_name (abfd, name); + } + +-/* Support for core dump NOTE sections. */ +-static bfd_boolean +-microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) +-{ +- int offset; +- unsigned int size; +- +- switch (note->descsz) +- { +- default: +- return FALSE; +- +- case 228: /* Linux/MicroBlaze */ +- /* pr_cursig */ +- elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); +- +- /* pr_pid */ +- elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24); +- +- /* pr_reg */ +- offset = 72; +- size = 50 * 4; +- +- break; +- } +- +- /* Make a ".reg/999" section. */ +- return _bfd_elfcore_make_pseudosection (abfd, ".reg", +- size, note->descpos + offset); +-} +- +-static bfd_boolean +-microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) +-{ +- switch (note->descsz) +- { +- default: +- return FALSE; +- +- case 128: /* Linux/MicroBlaze elf_prpsinfo */ +- elf_tdata (abfd)->core->program +- = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16); +- elf_tdata (abfd)->core->command +- = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80); +- } +- +- /* Note that for some reason, a spurious space is tacked +- onto the end of the args in some (at least one anyway) +- implementations, so strip it off if it exists. */ +- +- { +- char *command = elf_tdata (abfd)->core->command; +- int n = strlen (command); +- +- if (0 < n && command[n - 1] == ' ') +- command[n - 1] = '\0'; +- } +- +- return TRUE; +-} +- +-/* The microblaze linker (like many others) needs to keep track of +- the number of relocs that it decides to copy as dynamic relocs in +- check_relocs for each symbol. This is so that it can later discard +- them if they are found to be unnecessary. We store the information +- in a field extending the regular ELF linker hash table. */ +- +-struct elf32_mb_dyn_relocs +-{ +- struct elf32_mb_dyn_relocs *next; +- +- /* The input section of the reloc. */ +- asection *sec; +- +- /* Total number of relocs copied for the input section. */ +- bfd_size_type count; +- +- /* Number of pc-relative relocs copied for the input section. */ +- bfd_size_type pc_count; +-}; +- + /* ELF linker hash entry. */ + + struct elf32_mb_link_hash_entry +@@ -3683,6 +3602,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd, + return TRUE; + } + ++ ++static bfd_boolean ++elf_microblaze_object_p (bfd *abfd) ++{ ++ /* Set the right machine number for an s390 elf32 file. */ ++ return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze); ++} ++ + /* Hook called by the linker routine which adds symbols from an object + file. We use it to put .comm items in .sbss, and not .bss. */ + +@@ -3752,8 +3679,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd, + #define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol + #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections + #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook +- +-#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus +-#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo ++#define elf_backend_object_p elf_microblaze_object_p + + #include "elf32-target.h" +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 3ff6a14baf..95a1e69729 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -426,7 +426,10 @@ md_begin (void) + const char *prev_name = ""; + + opcode_hash_control = hash_new (); +- ++ if (microblaze_arch_size == 64) ++ bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze64); ++ else ++ bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze); + /* Insert unique names into hash table. */ + for (opcode = (struct opcodes *)opcodes; opcode->name; opcode ++) + { +@@ -1348,7 +1351,7 @@ md_assemble (char * str) + if ((temp != 0) && (temp != 0xFFFF8000)) + { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imm"); +@@ -3431,6 +3434,15 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED) + } + + ++unsigned long ++microblaze_mach (void) ++{ ++ if (microblaze_arch_size == 64) ++ return bfd_mach_microblaze64; ++ else ++ return bfd_mach_microblaze; ++} ++ + /* Create a fixup for a cons expression. If parse_cons_expression_microblaze + found a machine specific op in an expression, + then we create relocs accordingly. */ +diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h +index 9d38d2ced5..13f58917e7 100644 +--- a/gas/config/tc-microblaze.h ++++ b/gas/config/tc-microblaze.h +@@ -23,6 +23,10 @@ + #define TC_MICROBLAZE 1 + + #define TARGET_ARCH bfd_arch_microblaze ++#define TARGET_MACH (microblaze_mach ()) ++#define DEFAULT_MACHINE bfd_mach_microblaze64 ++extern unsigned long microblaze_mach (void); ++ + #ifndef TARGET_BYTES_BIG_ENDIAN + /* Used to initialise target_big_endian. */ + #define TARGET_BYTES_BIG_ENDIAN 1 +diff --git a/gdb/Makefile.in b/gdb/Makefile.in +index 8c9a3c07c0..15387197c7 100644 +--- a/gdb/Makefile.in ++++ b/gdb/Makefile.in +@@ -2265,7 +2265,7 @@ ALLDEPFILES = \ + m68k-tdep.c \ + microblaze-linux-tdep.c \ + microblaze-tdep.c \ +- microblaze-linux-nat.c \ ++ microblaze-linux-nat.c \ + mingw-hdep.c \ + mips-fbsd-nat.c \ + mips-fbsd-tdep.c \ +diff --git a/gdb/features/Makefile b/gdb/features/Makefile +index 3d84ca09a1..fdeec19753 100644 +--- a/gdb/features/Makefile ++++ b/gdb/features/Makefile +@@ -64,6 +64,7 @@ WHICH = aarch64 \ + i386/x32-avx-avx512-linux \ + mips-linux mips-dsp-linux \ + microblaze-with-stack-protect \ ++ microblaze64-with-stack-protect \ + mips64-linux mips64-dsp-linux \ + nios2-linux \ + rs6000/powerpc-32 \ +@@ -135,7 +136,9 @@ XMLTOC = \ + arm/arm-with-vfpv2.xml \ + arm/arm-with-vfpv3.xml \ + microblaze-with-stack-protect.xml \ ++ microblaze64-with-stack-protect.xml \ + microblaze.xml \ ++ microblaze64.xml \ + mips-dsp-linux.xml \ + mips-linux.xml \ + mips64-dsp-linux.xml \ +diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml +index 88c93e5d66..5bc3e49f84 100644 +--- a/gdb/features/microblaze-core.xml ++++ b/gdb/features/microblaze-core.xml +@@ -8,7 +8,7 @@ + <!DOCTYPE feature SYSTEM "gdb-target.dtd"> + <feature name="org.gnu.gdb.microblaze.core"> + <reg name="r0" bitsize="32" regnum="0"/> +- <reg name="r1" bitsize="32" type="data_ptr"/> ++ <reg name="r1" bitsize="32"/> + <reg name="r2" bitsize="32"/> + <reg name="r3" bitsize="32"/> + <reg name="r4" bitsize="32"/> +@@ -39,7 +39,7 @@ + <reg name="r29" bitsize="32"/> + <reg name="r30" bitsize="32"/> + <reg name="r31" bitsize="32"/> +- <reg name="rpc" bitsize="32" type="code_ptr"/> ++ <reg name="rpc" bitsize="32"/> + <reg name="rmsr" bitsize="32"/> + <reg name="rear" bitsize="32"/> + <reg name="resr" bitsize="32"/> +@@ -64,4 +64,6 @@ + <reg name="rtlbsx" bitsize="32"/> + <reg name="rtlblo" bitsize="32"/> + <reg name="rtlbhi" bitsize="32"/> ++ <reg name="slr" bitsize="32"/> ++ <reg name="shr" bitsize="32"/> + </feature> +diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml +index 870c148bb0..a7f27b903c 100644 +--- a/gdb/features/microblaze-stack-protect.xml ++++ b/gdb/features/microblaze-stack-protect.xml +@@ -7,6 +7,6 @@ + + <!DOCTYPE feature SYSTEM "gdb-target.dtd"> + <feature name="org.gnu.gdb.microblaze.stack-protect"> +- <reg name="rslr" bitsize="32"/> +- <reg name="rshr" bitsize="32"/> ++ <reg name="slr" bitsize="32"/> ++ <reg name="shr" bitsize="32"/> + </feature> +diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c +index b39aa19887..609934e2b4 100644 +--- a/gdb/features/microblaze-with-stack-protect.c ++++ b/gdb/features/microblaze-with-stack-protect.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + + feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect"); +- tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); + + tdesc_microblaze_with_stack_protect = result; + } +diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c +index 6c86fc0770..ceb98ca8b8 100644 +--- a/gdb/features/microblaze.c ++++ b/gdb/features/microblaze.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void) + + feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); + + tdesc_microblaze = result; + } +diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml +new file mode 100644 +index 0000000000..96e99e2fb2 +--- /dev/null ++++ b/gdb/features/microblaze64-core.xml +@@ -0,0 +1,69 @@ ++<?xml version="1.0"?> ++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc. ++ ++ Copying and distribution of this file, with or without modification, ++ are permitted in any medium without royalty provided the copyright ++ notice and this notice are preserved. --> ++ ++<!DOCTYPE feature SYSTEM "gdb-target.dtd"> ++<feature name="org.gnu.gdb.microblaze64.core"> ++ <reg name="r0" bitsize="64" regnum="0"/> ++ <reg name="r1" bitsize="64"/> ++ <reg name="r2" bitsize="64"/> ++ <reg name="r3" bitsize="64"/> ++ <reg name="r4" bitsize="64"/> ++ <reg name="r5" bitsize="64"/> ++ <reg name="r6" bitsize="64"/> ++ <reg name="r7" bitsize="64"/> ++ <reg name="r8" bitsize="64"/> ++ <reg name="r9" bitsize="64"/> ++ <reg name="r10" bitsize="64"/> ++ <reg name="r11" bitsize="64"/> ++ <reg name="r12" bitsize="64"/> ++ <reg name="r13" bitsize="64"/> ++ <reg name="r14" bitsize="64"/> ++ <reg name="r15" bitsize="64"/> ++ <reg name="r16" bitsize="64"/> ++ <reg name="r17" bitsize="64"/> ++ <reg name="r18" bitsize="64"/> ++ <reg name="r19" bitsize="64"/> ++ <reg name="r20" bitsize="64"/> ++ <reg name="r21" bitsize="64"/> ++ <reg name="r22" bitsize="64"/> ++ <reg name="r23" bitsize="64"/> ++ <reg name="r24" bitsize="64"/> ++ <reg name="r25" bitsize="64"/> ++ <reg name="r26" bitsize="64"/> ++ <reg name="r27" bitsize="64"/> ++ <reg name="r28" bitsize="64"/> ++ <reg name="r29" bitsize="64"/> ++ <reg name="r30" bitsize="64"/> ++ <reg name="r31" bitsize="64"/> ++ <reg name="rpc" bitsize="64"/> ++ <reg name="rmsr" bitsize="32"/> ++ <reg name="rear" bitsize="64"/> ++ <reg name="resr" bitsize="32"/> ++ <reg name="rfsr" bitsize="32"/> ++ <reg name="rbtr" bitsize="64"/> ++ <reg name="rpvr0" bitsize="32"/> ++ <reg name="rpvr1" bitsize="32"/> ++ <reg name="rpvr2" bitsize="32"/> ++ <reg name="rpvr3" bitsize="32"/> ++ <reg name="rpvr4" bitsize="32"/> ++ <reg name="rpvr5" bitsize="32"/> ++ <reg name="rpvr6" bitsize="32"/> ++ <reg name="rpvr7" bitsize="32"/> ++ <reg name="rpvr8" bitsize="64"/> ++ <reg name="rpvr9" bitsize="64"/> ++ <reg name="rpvr10" bitsize="32"/> ++ <reg name="rpvr11" bitsize="32"/> ++ <reg name="redr" bitsize="32"/> ++ <reg name="rpid" bitsize="32"/> ++ <reg name="rzpr" bitsize="32"/> ++ <reg name="rtlbx" bitsize="32"/> ++ <reg name="rtlbsx" bitsize="32"/> ++ <reg name="rtlblo" bitsize="32"/> ++ <reg name="rtlbhi" bitsize="32"/> ++ <reg name="slr" bitsize="64"/> ++ <reg name="shr" bitsize="64"/> ++</feature> +diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml +new file mode 100644 +index 0000000000..1bbf5fc3ce +--- /dev/null ++++ b/gdb/features/microblaze64-stack-protect.xml +@@ -0,0 +1,12 @@ ++<?xml version="1.0"?> ++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc. ++ ++ Copying and distribution of this file, with or without modification, ++ are permitted in any medium without royalty provided the copyright ++ notice and this notice are preserved. --> ++ ++<!DOCTYPE feature SYSTEM "gdb-target.dtd"> ++<feature name="org.gnu.gdb.microblaze64.stack-protect"> ++ <reg name="slr" bitsize="64"/> ++ <reg name="shr" bitsize="64"/> ++</feature> +diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c +new file mode 100644 +index 0000000000..f448c9a749 +--- /dev/null ++++ b/gdb/features/microblaze64-with-stack-protect.c +@@ -0,0 +1,79 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze-with-stack-protect.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze64_with_stack_protect; ++static void ++initialize_tdesc_microblaze64_with_stack_protect (void) ++{ ++ struct target_desc *result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ ++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ ++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze64_with_stack_protect = result; ++} +diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml +new file mode 100644 +index 0000000000..0e9f01611f +--- /dev/null ++++ b/gdb/features/microblaze64-with-stack-protect.xml +@@ -0,0 +1,12 @@ ++<?xml version="1.0"?> ++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc. ++ ++ Copying and distribution of this file, with or without modification, ++ are permitted in any medium without royalty provided the copyright ++ notice and this notice are preserved. --> ++ ++<!DOCTYPE target SYSTEM "gdb-target.dtd"> ++<target> ++ <xi:include href="microblaze64-core.xml"/> ++ <xi:include href="microblaze64-stack-protect.xml"/> ++</target> +diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c +new file mode 100644 +index 0000000000..1aa37c4512 +--- /dev/null ++++ b/gdb/features/microblaze64.c +@@ -0,0 +1,77 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze64; ++static void ++initialize_tdesc_microblaze64 (void) ++{ ++ struct target_desc *result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ ++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze64 = result; ++} +diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml +new file mode 100644 +index 0000000000..515d18e65c +--- /dev/null ++++ b/gdb/features/microblaze64.xml +@@ -0,0 +1,11 @@ ++<?xml version="1.0"?> ++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc. ++ ++ Copying and distribution of this file, with or without modification, ++ are permitted in any medium without royalty provided the copyright ++ notice and this notice are preserved. --> ++ ++<!DOCTYPE target SYSTEM "gdb-target.dtd"> ++<target> ++ <xi:include href="microblaze64-core.xml"/> ++</target> +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 49713ea9b1..0605283c9e 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -40,7 +40,9 @@ + #include "remote.h" + + #include "features/microblaze-with-stack-protect.c" ++#include "features/microblaze64-with-stack-protect.c" + #include "features/microblaze.c" ++#include "features/microblaze64.c" + + /* Instruction macros used for analyzing the prologue. */ + /* This set of instruction macros need to be changed whenever the +@@ -75,12 +77,13 @@ static const char *microblaze_register_names[] = + "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6", + "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11", + "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi", +- "rslr", "rshr" ++ "slr", "shr" + }; + + #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names) + + static unsigned int microblaze_debug_flag = 0; ++int reg_size = 4; + + static void ATTRIBUTE_PRINTF (1, 2) + microblaze_debug (const char *fmt, ...) +@@ -145,6 +148,7 @@ microblaze_store_arguments (struct regcache *regcache, int nargs, + error (_("store_arguments not implemented")); + return sp; + } ++#if 0 + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -154,7 +158,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + int val; + int bplen; + gdb_byte old_contents[BREAKPOINT_MAX]; +- struct cleanup *cleanup; ++ //struct cleanup *cleanup; + + /* Determine appropriate breakpoint contents and size for this address. */ + bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); +@@ -162,7 +166,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + error (_("Software breakpoints not implemented for this target.")); + + /* Make sure we see the memory breakpoints. */ +- cleanup = make_show_memory_breakpoints_cleanup (1); ++ scoped_restore ++ cleanup = make_scoped_restore_show_memory_breakpoints (1); + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the +@@ -178,6 +183,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + return val; + } + ++#endif + /* Allocate and initialize a frame cache. */ + + static struct microblaze_frame_cache * +@@ -570,17 +576,16 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache, + gdb_byte *valbuf) + { + gdb_byte buf[8]; +- + /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF. */ + switch (TYPE_LENGTH (type)) + { + case 1: /* return last byte in the register. */ + regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); +- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1); ++ memcpy(valbuf, buf + reg_size - 1, 1); + return; + case 2: /* return last 2 bytes in register. */ + regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); +- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2); ++ memcpy(valbuf, buf + reg_size - 2, 2); + return; + case 4: /* for sizes 4 or 8, copy the required length. */ + case 8: +@@ -647,7 +652,119 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) + return (TYPE_LENGTH (type) == 16); + } + +- ++#if 0 ++static std::vector<CORE_ADDR> ++microblaze_software_single_step (struct regcache *regcache) ++{ ++// struct gdbarch *arch = get_frame_arch(frame); ++ struct gdbarch *arch = get_regcache_arch (regcache); ++ struct address_space *aspace = get_regcache_aspace (regcache); ++// struct address_space *aspace = get_frame_address_space (frame); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch); ++ static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE; ++ static char be_breakp[] = MICROBLAZE_BREAKPOINT; ++ enum bfd_endian byte_order = gdbarch_byte_order (arch); ++ char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp; ++ std::vector<CORE_ADDR> ret = 0; ++ ++ /* Save the address and the values of the next_pc and the target */ ++ static struct sstep_breaks ++ { ++ CORE_ADDR address; ++ bfd_boolean valid; ++ /* Shadow contents. */ ++ char data[INST_WORD_SIZE]; ++ } stepbreaks[2]; ++ int ii; ++ ++ if (1) ++ { ++ CORE_ADDR pc; ++ std::vector<CORE_ADDR> *next_pcs = NULL; ++ long insn; ++ enum microblaze_instr minstr; ++ bfd_boolean isunsignednum; ++ enum microblaze_instr_type insn_type; ++ short delay_slots; ++ int imm; ++ bfd_boolean immfound = FALSE; ++ ++ /* Set a breakpoint at the next instruction */ ++ /* If the current instruction is an imm, set it at the inst after */ ++ /* If the instruction has a delay slot, skip the delay slot */ ++ pc = regcache_read_pc (regcache); ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ if (insn_type == immediate_inst) ++ { ++ int rd, ra, rb; ++ immfound = TRUE; ++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); ++ pc = pc + INST_WORD_SIZE; ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ } ++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE; ++ if (insn_type != return_inst) { ++ stepbreaks[0].valid = TRUE; ++ } else { ++ stepbreaks[0].valid = FALSE; ++ } ++ ++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn); ++ /* Now check for branch or return instructions */ ++ if (insn_type == branch_inst || insn_type == return_inst) { ++ int limm; ++ int lrd, lra, lrb; ++ int ra, rb; ++ bfd_boolean targetvalid; ++ bfd_boolean unconditionalbranch; ++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm); ++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS) ++ ra = regcache_raw_get_unsigned(regcache, lra); ++ else ++ ra = 0; ++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS) ++ rb = regcache_raw_get_unsigned(regcache, lrb); ++ else ++ rb = 0; ++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch); ++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address); ++ if (unconditionalbranch) ++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */ ++ if (targetvalid && (stepbreaks[0].valid == FALSE || ++ (stepbreaks[0].address != stepbreaks[1].address)) ++ && (stepbreaks[1].address != pc)) { ++ stepbreaks[1].valid = TRUE; ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ ++ /* Insert the breakpoints */ ++ for (ii = 0; ii < 2; ++ii) ++ { ++ ++ /* ignore invalid breakpoint. */ ++ if (stepbreaks[ii].valid) { ++ VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);; ++// insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address); ++ ret = next_pcs; ++ } ++ } ++ } ++ return ret; ++} ++#endif ++ ++static void ++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) ++{ ++ regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc); ++} ++ + static int dwarf2_to_reg_map[78] = + { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ + 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ +@@ -682,13 +799,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) + static void + microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) + { ++ + register_remote_g_packet_guess (gdbarch, +- 4 * MICROBLAZE_NUM_CORE_REGS, +- tdesc_microblaze); ++ 4 * MICROBLAZE_NUM_REGS, ++ tdesc_microblaze64); + + register_remote_g_packet_guess (gdbarch, + 4 * MICROBLAZE_NUM_REGS, +- tdesc_microblaze_with_stack_protect); ++ tdesc_microblaze64_with_stack_protect); + } + + void +@@ -696,15 +814,15 @@ microblaze_supply_gregset (const struct microblaze_gregset *gregset, + struct regcache *regcache, + int regnum, const void *gregs) + { +- unsigned int *regs = gregs; ++ const gdb_byte *regs = (const gdb_byte *) gregs; + if (regnum >= 0) +- regcache_raw_supply (regcache, regnum, regs + regnum); ++ regcache->raw_supply (regnum, regs + regnum); + + if (regnum == -1) { + int i; + + for (i = 0; i < 50; i++) { +- regcache_raw_supply (regcache, i, regs + i); ++ regcache->raw_supply (regnum, regs + i); + } + } + } +@@ -755,6 +873,17 @@ microblaze_regset_from_core_section (struct gdbarch *gdbarch, + } + + ++static void ++make_regs (struct gdbarch *arch) ++{ ++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch); ++ int mach = gdbarch_bfd_arch_info (arch)->mach; ++ ++ if (mach == bfd_mach_microblaze64) ++ { ++ set_gdbarch_ptr_bit (arch, 64); ++ } ++} + + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -769,8 +898,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + if (arches != NULL) + return arches->gdbarch; + if (tdesc == NULL) +- tdesc = tdesc_microblaze; +- ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } ++ else ++ tdesc = tdesc_microblaze; ++ } + /* Check any target description for validity. */ + if (tdesc_has_registers (tdesc)) + { +@@ -778,27 +914,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- feature = tdesc_find_feature (tdesc, ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze64.core"); ++ else ++ feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze.core"); + if (feature == NULL) + return NULL; + tdesc_data = tdesc_data_alloc (); + + valid_p = 1; +- for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++) ++ for (i = 0; i < MICROBLAZE_NUM_REGS; i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data, i, + microblaze_register_names[i]); +- feature = tdesc_find_feature (tdesc, ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze64.stack-protect"); ++ else ++ feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze.stack-protect"); + if (feature != NULL) + { + valid_p = 1; + valid_p &= tdesc_numbered_register (feature, tdesc_data, + MICROBLAZE_SLR_REGNUM, +- "rslr"); ++ "slr"); + valid_p &= tdesc_numbered_register (feature, tdesc_data, + MICROBLAZE_SHR_REGNUM, +- "rshr"); ++ "shr"); + } + + if (!valid_p) +@@ -806,6 +950,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + tdesc_data_cleanup (tdesc_data); + return NULL; + } ++ + } + + /* Allocate space for the new architecture. */ +@@ -825,7 +970,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + /* Register numbers of various important registers. */ + set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); + set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); ++ ++ /* Register set. ++ make_regs (gdbarch); */ ++ switch (info.bfd_arch_info->mach) ++ { ++ case bfd_mach_microblaze64: ++ set_gdbarch_ptr_bit (gdbarch, 64); ++ break; ++ } + ++ + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); + +@@ -845,13 +1000,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + microblaze_breakpoint::bp_from_kind); +- set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); ++// set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); ++ ++// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + + set_gdbarch_frame_args_skip (gdbarch, 8); + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); + +- microblaze_register_g_packet_guesses (gdbarch); ++ //microblaze_register_g_packet_guesses (gdbarch); + + frame_base_set_default (gdbarch, µblaze_frame_base); + +@@ -866,11 +1023,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + tdesc_use_registers (gdbarch, tdesc, tdesc_data); + //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); + +- /* If we have register sets, enable the generic core file support. */ ++ /* If we have register sets, enable the generic core file support. + if (tdep->gregset) { + set_gdbarch_regset_from_core_section (gdbarch, + microblaze_regset_from_core_section); +- } ++ }*/ + + return gdbarch; + } +@@ -882,6 +1039,8 @@ _initialize_microblaze_tdep (void) + + initialize_tdesc_microblaze_with_stack_protect (); + initialize_tdesc_microblaze (); ++ initialize_tdesc_microblaze64_with_stack_protect (); ++ initialize_tdesc_microblaze64 (); + /* Debug this files internals. */ + add_setshow_zuinteger_cmd ("microblaze", class_maintenance, + µblaze_debug_flag, _("\ +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 3777cbb6a8..55f5dd1962 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -27,7 +27,7 @@ struct microblaze_gregset + microblaze_gregset() {} + unsigned int gregs[32]; + unsigned int fpregs[32]; +- unsigned int pregs[16]; ++ unsigned int pregs[18]; + }; + + struct gdbarch_tdep +@@ -101,9 +101,9 @@ enum microblaze_regnum + MICROBLAZE_RTLBSX_REGNUM, + MICROBLAZE_RTLBLO_REGNUM, + MICROBLAZE_RTLBHI_REGNUM, +- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM, ++ MICROBLAZE_SLR_REGNUM, + MICROBLAZE_SHR_REGNUM, +- MICROBLAZE_NUM_REGS ++ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS + }; + + struct microblaze_frame_cache +@@ -128,7 +128,7 @@ struct microblaze_frame_cache + struct trad_frame_saved_reg *saved_regs; + }; + /* All registers are 32 bits. */ +-#define MICROBLAZE_REGISTER_SIZE 4 ++//#define MICROBLAZE_REGISTER_SIZE 8 + + /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. + Only used for native debugging. */ +diff --git a/gdb/regformats/microblaze-with-stack-protect.dat b/gdb/regformats/microblaze-with-stack-protect.dat +index 8040a7b3fd..450e321d49 100644 +--- a/gdb/regformats/microblaze-with-stack-protect.dat ++++ b/gdb/regformats/microblaze-with-stack-protect.dat +@@ -60,5 +60,5 @@ expedite:r1,rpc + 32:rtlbsx + 32:rtlblo + 32:rtlbhi +-32:rslr +-32:rshr ++32:slr ++32:shr +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index bd9d91cd57..12d4456bc2 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -134,7 +134,6 @@ + #define ORLI_MASK 0xA0000000 + #define XORLI_MASK 0xA8000000 + +- + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ + /* Mask for mbar insn. */ +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0041-patch-MicroBlaze-porting-GDB-for-linux.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0041-patch-MicroBlaze-porting-GDB-for-linux.patch new file mode 100644 index 000000000..1a0153b8a --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0041-patch-MicroBlaze-porting-GDB-for-linux.patch @@ -0,0 +1,155 @@ +From 07757f455d343beb50ac04815c77b04075bf9534 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 12 Dec 2019 14:56:17 +0530 +Subject: [PATCH 41/43] [patch,MicroBlaze] : porting GDB for linux + +--- + gdb/features/microblaze-linux.xml | 12 ++++++++++ + gdb/gdbserver/Makefile.in | 2 ++ + gdb/gdbserver/configure.srv | 3 ++- + gdb/microblaze-linux-tdep.c | 39 ++++++++++++++++++++++++------- + 4 files changed, 47 insertions(+), 9 deletions(-) + create mode 100644 gdb/features/microblaze-linux.xml + +diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml +new file mode 100644 +index 0000000000..8983e66eb3 +--- /dev/null ++++ b/gdb/features/microblaze-linux.xml +@@ -0,0 +1,12 @@ ++<?xml version="1.0"?> ++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc. ++ ++ Copying and distribution of this file, with or without modification, ++ are permitted in any medium without royalty provided the copyright ++ notice and this notice are preserved. --> ++ ++<!DOCTYPE target SYSTEM "gdb-target.dtd"> ++<target> ++ <osabi>GNU/Linux</osabi> ++ <xi:include href="microblaze-core.xml"/> ++</target> +diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in +index 45d95e6cab..7c8fa3c246 100644 +--- a/gdb/gdbserver/Makefile.in ++++ b/gdb/gdbserver/Makefile.in +@@ -633,6 +633,8 @@ common/%.o: ../common/%.c + + %-generated.c: ../regformats/rs6000/%.dat | $(regdat_sh) + $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@ ++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh) ++ $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c + + # + # Dependency tracking. +diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv +index c421790bd0..6ad0ac9fa6 100644 +--- a/gdb/gdbserver/configure.srv ++++ b/gdb/gdbserver/configure.srv +@@ -210,8 +210,9 @@ case "${target}" in + srv_linux_usrregs=yes + srv_linux_thread_db=yes + ;; +- microblaze*-*-linux*) srv_regobj=microblaze-linux.o ++ microblaze*-*-linux*) srv_regobj="microblaze-linux.o" + srv_tgtobj="$srv_linux_obj linux-microblaze-low.o " ++ srv_xmlfiles="microblaze-linux.xml" + srv_linux_regsets=yes + srv_linux_usrregs=yes + srv_linux_thread_db=yes +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 011e513941..e3d2a7508d 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -41,7 +41,7 @@ + + #ifndef REGSET_H + #define REGSET_H 1 +- ++int MICROBLAZE_REGISTER_SIZE=4; + struct gdbarch; + struct regcache; + +@@ -115,7 +115,7 @@ microblaze_debug (const char *fmt, ...) + va_end (args); + } + } +- ++#if 0 + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -131,7 +131,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); + + /* Make sure we see the memory breakpoints. */ +- cleanup = make_show_memory_breakpoints_cleanup (1); ++ cleanup = make_scoped_restore_show_memory_breakpoints (1); + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the +@@ -146,6 +146,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + do_cleanups (cleanup); + return val; + } ++#endif + + static void + microblaze_linux_sigtramp_cache (struct frame_info *next_frame, +@@ -248,8 +249,8 @@ microblaze_linux_init_abi (struct gdbarch_info info, + + linux_init_abi (info, gdbarch); + +- set_gdbarch_memory_remove_breakpoint (gdbarch, +- microblaze_linux_memory_remove_breakpoint); ++// set_gdbarch_memory_remove_breakpoint (gdbarch, ++// microblaze_linux_memory_remove_breakpoint); + + /* Shared library handling. */ + set_solib_svr4_fetch_link_map_offsets (gdbarch, +@@ -261,10 +262,30 @@ microblaze_linux_init_abi (struct gdbarch_info info, + + /* BFD target for core files. */ + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) +- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze"); ++ MICROBLAZE_REGISTER_SIZE=8; ++ } ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ } + else +- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel"); ++ MICROBLAZE_REGISTER_SIZE=8; ++ } ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ } + ++ switch (info.bfd_arch_info->mach) ++ { ++ case bfd_mach_microblaze64: ++ set_gdbarch_ptr_bit (gdbarch, 64); ++ break; ++ } + + /* Shared library handling. */ + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); +@@ -278,6 +299,8 @@ microblaze_linux_init_abi (struct gdbarch_info info, + void + _initialize_microblaze_linux_tdep (void) + { +- gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, ++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, ++ microblaze_linux_init_abi); ++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, + microblaze_linux_init_abi); + } +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0042-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0042-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch new file mode 100644 index 000000000..ad8dcb53d --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0042-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch @@ -0,0 +1,146 @@ +From c2a4667e87bd610a48a6690fcc9fdc6761398bcf Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Thu, 19 Dec 2019 12:22:04 +0530 +Subject: [PATCH 42/43] Correcting the register names from slr & shr to rslr & + rshr + +--- + gdb/features/microblaze-core.xml | 4 ++-- + gdb/features/microblaze-stack-protect.xml | 4 ++-- + gdb/features/microblaze-with-stack-protect.c | 4 ++-- + gdb/features/microblaze.c | 4 ++-- + gdb/features/microblaze64-core.xml | 4 ++-- + gdb/features/microblaze64-stack-protect.xml | 4 ++-- + gdb/features/microblaze64-with-stack-protect.c | 4 ++-- + gdb/features/microblaze64.c | 4 ++-- + gdb/microblaze-tdep.c | 2 +- + 9 files changed, 17 insertions(+), 17 deletions(-) + +diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml +index 5bc3e49f84..6f73f4eb84 100644 +--- a/gdb/features/microblaze-core.xml ++++ b/gdb/features/microblaze-core.xml +@@ -64,6 +64,6 @@ + <reg name="rtlbsx" bitsize="32"/> + <reg name="rtlblo" bitsize="32"/> + <reg name="rtlbhi" bitsize="32"/> +- <reg name="slr" bitsize="32"/> +- <reg name="shr" bitsize="32"/> ++ <reg name="rslr" bitsize="32"/> ++ <reg name="rshr" bitsize="32"/> + </feature> +diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml +index a7f27b903c..870c148bb0 100644 +--- a/gdb/features/microblaze-stack-protect.xml ++++ b/gdb/features/microblaze-stack-protect.xml +@@ -7,6 +7,6 @@ + + <!DOCTYPE feature SYSTEM "gdb-target.dtd"> + <feature name="org.gnu.gdb.microblaze.stack-protect"> +- <reg name="slr" bitsize="32"/> +- <reg name="shr" bitsize="32"/> ++ <reg name="rslr" bitsize="32"/> ++ <reg name="rshr" bitsize="32"/> + </feature> +diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c +index 609934e2b4..ab162fd258 100644 +--- a/gdb/features/microblaze-with-stack-protect.c ++++ b/gdb/features/microblaze-with-stack-protect.c +@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect"); +- tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int"); + + tdesc_microblaze_with_stack_protect = result; + } +diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c +index ceb98ca8b8..7919ac96e6 100644 +--- a/gdb/features/microblaze.c ++++ b/gdb/features/microblaze.c +@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); +- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64"); + + tdesc_microblaze = result; + } +diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml +index 96e99e2fb2..b9adadfade 100644 +--- a/gdb/features/microblaze64-core.xml ++++ b/gdb/features/microblaze64-core.xml +@@ -64,6 +64,6 @@ + <reg name="rtlbsx" bitsize="32"/> + <reg name="rtlblo" bitsize="32"/> + <reg name="rtlbhi" bitsize="32"/> +- <reg name="slr" bitsize="64"/> +- <reg name="shr" bitsize="64"/> ++ <reg name="rslr" bitsize="64"/> ++ <reg name="rshr" bitsize="64"/> + </feature> +diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml +index 1bbf5fc3ce..9d7ea8b9fd 100644 +--- a/gdb/features/microblaze64-stack-protect.xml ++++ b/gdb/features/microblaze64-stack-protect.xml +@@ -7,6 +7,6 @@ + + <!DOCTYPE feature SYSTEM "gdb-target.dtd"> + <feature name="org.gnu.gdb.microblaze64.stack-protect"> +- <reg name="slr" bitsize="64"/> +- <reg name="shr" bitsize="64"/> ++ <reg name="rslr" bitsize="64"/> ++ <reg name="rshr" bitsize="64"/> + </feature> +diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c +index f448c9a749..249cb534da 100644 +--- a/gdb/features/microblaze64-with-stack-protect.c ++++ b/gdb/features/microblaze64-with-stack-protect.c +@@ -72,8 +72,8 @@ initialize_tdesc_microblaze64_with_stack_protect (void) + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect"); +- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); +- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64"); + + tdesc_microblaze64_with_stack_protect = result; + } +diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c +index 1aa37c4512..5d3e2c8cd9 100644 +--- a/gdb/features/microblaze64.c ++++ b/gdb/features/microblaze64.c +@@ -70,8 +70,8 @@ initialize_tdesc_microblaze64 (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); +- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64"); + + tdesc_microblaze64 = result; + } +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 0605283c9e..7a0c2527f4 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -77,7 +77,7 @@ static const char *microblaze_register_names[] = + "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6", + "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11", + "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi", +- "slr", "shr" ++ "rslr", "rshr" + }; + + #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names) +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0043-Removing-the-header-gdb_assert.h-from-MB-target-file.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0043-Removing-the-header-gdb_assert.h-from-MB-target-file.patch new file mode 100644 index 000000000..930e161c5 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0043-Removing-the-header-gdb_assert.h-from-MB-target-file.patch @@ -0,0 +1,24 @@ +From 9562530bc48c76d8f824b8f4901ad90dd2969086 Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Fri, 17 Jan 2020 15:45:48 +0530 +Subject: [PATCH 43/43] Removing the header "gdb_assert.h" from MB target file + +--- + gdb/microblaze-linux-tdep.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index e3d2a7508d..5ef937219c 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,7 +37,6 @@ + #include "linux-tdep.h" + #include "glibc-tdep.h" + +-#include "gdb_assert.h" + + #ifndef REGSET_H + #define REGSET_H 1 +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0044-gdb-microblaze-linux-nat.c-Fix-target-compilation-of.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0044-gdb-microblaze-linux-nat.c-Fix-target-compilation-of.patch new file mode 100644 index 000000000..29e198cd9 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0044-gdb-microblaze-linux-nat.c-Fix-target-compilation-of.patch @@ -0,0 +1,364 @@ +From 4f0e06249d23629e1d56b296e7a040b6968484e9 Mon Sep 17 00:00:00 2001 +From: Mark Hatle <mark.hatle@xilinx.com> +Date: Mon, 20 Jan 2020 12:48:13 -0800 +Subject: [PATCH 44/45] gdb/microblaze-linux-nat.c: Fix target compilation of + gdb + +Add the nat to the configure file + +Remove gdb_assert.h and gdb_string.h. + +Adjust include for opcodes as well. + +Update to match latest style of components, similar to ppc-linux-nat.c + +Update: + get_regcache_arch(regcache) to regcache->arch() + regcache_raw_supply(regcache, ...) to regcache->raw_supply(...) + regcache_raw_collect(regcache, ...) to regcache->raw_collect(...) + +Signed-off-by: Mark Hatle <mark.hatle@xilinx.com> +--- + gdb/configure.nat | 4 + + gdb/microblaze-linux-nat.c | 149 +++++++++++++------------------------ + gdb/microblaze-tdep.c | 3 +- + 3 files changed, 57 insertions(+), 99 deletions(-) + +diff --git a/gdb/configure.nat b/gdb/configure.nat +index 3118263ac6..b8dc7398a5 100644 +--- a/gdb/configure.nat ++++ b/gdb/configure.nat +@@ -260,6 +260,10 @@ case ${gdb_host} in + # Host: Motorola m68k running GNU/Linux. + NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o" + ;; ++ microblaze*) ++ # Host: Microblaze, running Linux ++ NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o" ++ ;; + mips) + # Host: Linux/MIPS + NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \ +diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c +index e9b8c9c522..e09a86bb3f 100644 +--- a/gdb/microblaze-linux-nat.c ++++ b/gdb/microblaze-linux-nat.c +@@ -36,11 +36,9 @@ + #include "dwarf2-frame.h" + #include "osabi.h" + +-#include "gdb_assert.h" +-#include "gdb_string.h" + #include "target-descriptions.h" +-#include "opcodes/microblaze-opcm.h" +-#include "opcodes/microblaze-dis.h" ++#include "../opcodes/microblaze-opcm.h" ++#include "../opcodes/microblaze-dis.h" + + #include "linux-nat.h" + #include "target-descriptions.h" +@@ -61,34 +59,27 @@ + /* Defines ps_err_e, struct ps_prochandle. */ + #include "gdb_proc_service.h" + +-/* On GNU/Linux, threads are implemented as pseudo-processes, in which +- case we may be tracing more than one process at a time. In that +- case, inferior_ptid will contain the main process ID and the +- individual thread (process) ID. get_thread_id () is used to get +- the thread id if it's available, and the process id otherwise. */ +- +-int +-get_thread_id (ptid_t ptid) +-{ +- int tid = TIDGET (ptid); +- if (0 == tid) +- tid = PIDGET (ptid); +- return tid; +-} +- +-#define GET_THREAD_ID(PTID) get_thread_id (PTID) +- + /* Non-zero if our kernel may support the PTRACE_GETREGS and + PTRACE_SETREGS requests, for reading and writing the + general-purpose registers. Zero if we've tried one of + them and gotten an error. */ + int have_ptrace_getsetregs = 1; + ++struct microblaze_linux_nat_target final : public linux_nat_target ++{ ++ /* Add our register access methods. */ ++ void fetch_registers (struct regcache *, int) override; ++ void store_registers (struct regcache *, int) override; ++ ++ const struct target_desc *read_description () override; ++}; ++ ++static microblaze_linux_nat_target the_microblaze_linux_nat_target; ++ + static int + microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) + { + int u_addr = -1; +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace + interface, and not the wordsize of the program's ABI. */ + int wordsize = sizeof (long); +@@ -105,18 +96,16 @@ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) + static void + fetch_register (struct regcache *regcache, int tid, int regno) + { +- struct gdbarch *gdbarch = get_regcache_arch (regcache); +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ struct gdbarch *gdbarch = regcache->arch(); + /* This isn't really an address. But ptrace thinks of it as one. */ + CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); + int bytes_transferred; +- unsigned int offset; /* Offset of registers within the u area. */ +- char buf[MAX_REGISTER_SIZE]; ++ char buf[sizeof(long)]; + + if (regaddr == -1) + { + memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ +- regcache_raw_supply (regcache, regno, buf); ++ regcache->raw_supply (regno, buf); + return; + } + +@@ -149,14 +138,14 @@ fetch_register (struct regcache *regcache, int tid, int regno) + { + /* Little-endian values are always found at the left end of the + bytes transferred. */ +- regcache_raw_supply (regcache, regno, buf); ++ regcache->raw_supply (regno, buf); + } + else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) + { + /* Big-endian values are found at the right end of the bytes + transferred. */ + size_t padding = (bytes_transferred - register_size (gdbarch, regno)); +- regcache_raw_supply (regcache, regno, buf + padding); ++ regcache->raw_supply (regno, buf + padding); + } + else + internal_error (__FILE__, __LINE__, +@@ -175,8 +164,6 @@ fetch_register (struct regcache *regcache, int tid, int regno) + static int + fetch_all_gp_regs (struct regcache *regcache, int tid) + { +- struct gdbarch *gdbarch = get_regcache_arch (regcache); +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + gdb_gregset_t gregset; + + if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) +@@ -204,8 +191,6 @@ fetch_all_gp_regs (struct regcache *regcache, int tid) + static void + fetch_gp_regs (struct regcache *regcache, int tid) + { +- struct gdbarch *gdbarch = get_regcache_arch (regcache); +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int i; + + if (have_ptrace_getsetregs) +@@ -219,17 +204,29 @@ fetch_gp_regs (struct regcache *regcache, int tid) + fetch_register (regcache, tid, i); + } + ++/* Fetch registers from the child process. Fetch all registers if ++ regno == -1, otherwise fetch all general registers or all floating ++ point registers depending upon the value of regno. */ ++void ++microblaze_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) ++{ ++ pid_t tid = get_ptrace_pid (regcache->ptid ()); ++ ++ if (regno == -1) ++ fetch_gp_regs (regcache, tid); ++ else ++ fetch_register (regcache, tid, regno); ++} + + static void + store_register (const struct regcache *regcache, int tid, int regno) + { +- struct gdbarch *gdbarch = get_regcache_arch (regcache); +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ struct gdbarch *gdbarch = regcache->arch(); + /* This isn't really an address. But ptrace thinks of it as one. */ + CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); + int i; + size_t bytes_to_transfer; +- char buf[MAX_REGISTER_SIZE]; ++ char buf[sizeof(long)]; + + if (regaddr == -1) + return; +@@ -242,13 +239,13 @@ store_register (const struct regcache *regcache, int tid, int regno) + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) + { + /* Little-endian values always sit at the left end of the buffer. */ +- regcache_raw_collect (regcache, regno, buf); ++ regcache->raw_collect (regno, buf); + } + else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) + { + /* Big-endian values sit at the right end of the buffer. */ + size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); +- regcache_raw_collect (regcache, regno, buf + padding); ++ regcache->raw_collect (regno, buf + padding); + } + + for (i = 0; i < bytes_to_transfer; i += sizeof (long)) +@@ -281,8 +278,6 @@ store_register (const struct regcache *regcache, int tid, int regno) + static int + store_all_gp_regs (const struct regcache *regcache, int tid, int regno) + { +- struct gdbarch *gdbarch = get_regcache_arch (regcache); +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + gdb_gregset_t gregset; + + if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) +@@ -319,8 +314,6 @@ store_all_gp_regs (const struct regcache *regcache, int tid, int regno) + static void + store_gp_regs (const struct regcache *regcache, int tid, int regno) + { +- struct gdbarch *gdbarch = get_regcache_arch (regcache); +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int i; + + if (have_ptrace_getsetregs) +@@ -335,33 +328,10 @@ store_gp_regs (const struct regcache *regcache, int tid, int regno) + } + + +-/* Fetch registers from the child process. Fetch all registers if +- regno == -1, otherwise fetch all general registers or all floating +- point registers depending upon the value of regno. */ +- +-static void +-microblaze_linux_fetch_inferior_registers (struct target_ops *ops, +- struct regcache *regcache, int regno) +-{ +- /* Get the thread id for the ptrace call. */ +- int tid = GET_THREAD_ID (inferior_ptid); +- +- if (regno == -1) +- fetch_gp_regs (regcache, tid); +- else +- fetch_register (regcache, tid, regno); +-} +- +-/* Store registers back into the inferior. Store all registers if +- regno == -1, otherwise store all general registers or all floating +- point registers depending upon the value of regno. */ +- +-static void +-microblaze_linux_store_inferior_registers (struct target_ops *ops, +- struct regcache *regcache, int regno) ++void ++microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno) + { +- /* Get the thread id for the ptrace call. */ +- int tid = GET_THREAD_ID (inferior_ptid); ++ pid_t tid = get_ptrace_pid (regcache->ptid ()); + + if (regno >= 0) + store_register (regcache, tid, regno); +@@ -373,59 +343,44 @@ microblaze_linux_store_inferior_registers (struct target_ops *ops, + thread debugging. */ + + void +-fill_gregset (const struct regcache *regcache, +- gdb_gregset_t *gregsetp, int regno) ++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) + { +- microblaze_collect_gregset (NULL, regcache, regno, gregsetp); ++ microblaze_supply_gregset (NULL, regcache, -1, gregsetp); + } + + void +-supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) ++fill_gregset (const struct regcache *regcache, ++ gdb_gregset_t *gregsetp, int regno) + { +- microblaze_supply_gregset (NULL, regcache, -1, gregsetp); ++ microblaze_collect_gregset (NULL, regcache, regno, gregsetp); + } + + void +-fill_fpregset (const struct regcache *regcache, +- gdb_fpregset_t *fpregsetp, int regno) ++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) + { + /* FIXME. */ ++ return; + } + + void +-supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) ++fill_fpregset (const struct regcache *regcache, ++ gdb_fpregset_t *fpregsetp, int regno) + { + /* FIXME. */ ++ return; + } + +-static const struct target_desc * +-microblaze_linux_read_description (struct target_ops *ops) ++const struct target_desc * ++microblaze_linux_nat_target::read_description () + { +- CORE_ADDR microblaze_hwcap = 0; +- +- if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1) +- return NULL; +- + return NULL; + } + +- +-void _initialize_microblaze_linux_nat (void); +- + void + _initialize_microblaze_linux_nat (void) + { +- struct target_ops *t; +- +- /* Fill in the generic GNU/Linux methods. */ +- t = linux_target (); +- +- /* Add our register access methods. */ +- t->to_fetch_registers = microblaze_linux_fetch_inferior_registers; +- t->to_store_registers = microblaze_linux_store_inferior_registers; +- +- t->to_read_description = microblaze_linux_read_description; ++ linux_target = &the_microblaze_linux_nat_target; + + /* Register the target. */ +- linux_nat_add_target (t); ++ add_inf_child_target (linux_target); + } +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 7a0c2527f4..23deb24d26 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -657,7 +657,7 @@ static std::vector<CORE_ADDR> + microblaze_software_single_step (struct regcache *regcache) + { + // struct gdbarch *arch = get_frame_arch(frame); +- struct gdbarch *arch = get_regcache_arch (regcache); ++ struct gdbarch *arch = regcache->arch(); + struct address_space *aspace = get_regcache_aspace (regcache); + // struct address_space *aspace = get_frame_address_space (frame); + struct gdbarch_tdep *tdep = gdbarch_tdep (arch); +@@ -876,7 +876,6 @@ microblaze_regset_from_core_section (struct gdbarch *gdbarch, + static void + make_regs (struct gdbarch *arch) + { +- struct gdbarch_tdep *tdep = gdbarch_tdep (arch); + int mach = gdbarch_bfd_arch_info (arch)->mach; + + if (mach == bfd_mach_microblaze64) +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0045-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0045-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch new file mode 100644 index 000000000..118c5629f --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0045-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch @@ -0,0 +1,86 @@ +From d64ce07a2b9206ce1e53d8958b28de02cc7cca2b Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Wed, 22 Jan 2020 16:31:12 +0530 +Subject: [PATCH 45/45] Fixed bug in generation of IMML instruction for the new + MB-64 instructions with single register. + +--- + gas/config/tc-microblaze.c | 50 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 47 insertions(+), 3 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 95a1e69729..dc79328df6 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -1642,12 +1642,56 @@ md_assemble (char * str) + exp.X_add_symbol, + exp.X_add_number, + (char *) opc); +- immedl = 0L; ++ immed = 0L; + } + else + { + output = frag_more (isize); + immed = exp.X_add_number; ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000) ++ { ++ /* Needs an immediate inst. */ ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } + } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (immed << IMM_LOW) & IMM16_MASK; +@@ -2141,8 +2185,8 @@ md_assemble (char * str) + streq (name, "breaid") || + streq (name, "brai") || streq (name, "braid"))) + { +- temp = immed & 0xFFFFFFFFFFFF8000; +- if (temp != 0) ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000) + { + /* Needs an immediate inst. */ + if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) +-- +2.17.1 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0046-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0046-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch new file mode 100644 index 000000000..7677ab355 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0046-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch @@ -0,0 +1,38 @@ +From 9c8f4f1c11d324f0788da3a077b06c6bc9e6f2b8 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 16 Apr 2020 18:08:58 +0530 +Subject: [PATCH] [Patch,MicroBlaze m64] : This patch will remove imml 0 and + imml -1 instructions when the offset is less than 16 bit for Type A branch EA + instructions. + +--- + gas/config/tc-microblaze.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 088eae73a9..12fd145a03 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -2150,9 +2150,7 @@ md_assemble (char * str) + if (exp.X_op != O_constant) + { + char *opc; +- if (microblaze_arch_size == 64 && (streq (name, "breai") || +- streq (name, "breaid") || +- streq (name, "brai") || streq (name, "braid"))) ++ if (microblaze_arch_size == 64 && (streq (name, "brai") || streq (name, "braid"))) + opc = str_microblaze_64; + else + opc = NULL; +@@ -2920,7 +2918,7 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_PCREL: + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64 +- || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL || (fixP->fx_r_type == BFD_RELOC_64_PCREL && microblaze_arch_size == 64)) + { + /* Generate the imm instruction. */ + if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887) +-- +2.17.1 + |