summaryrefslogtreecommitdiff
path: root/poky/meta/recipes-core/musl
diff options
context:
space:
mode:
Diffstat (limited to 'poky/meta/recipes-core/musl')
-rw-r--r--poky/meta/recipes-core/musl/musl-obstack.bb22
-rw-r--r--poky/meta/recipes-core/musl/musl.inc2
-rw-r--r--poky/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch67
-rw-r--r--poky/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch55
-rw-r--r--poky/meta/recipes-core/musl/musl_git.bb8
5 files changed, 150 insertions, 4 deletions
diff --git a/poky/meta/recipes-core/musl/musl-obstack.bb b/poky/meta/recipes-core/musl/musl-obstack.bb
new file mode 100644
index 000000000..3003935fe
--- /dev/null
+++ b/poky/meta/recipes-core/musl/musl-obstack.bb
@@ -0,0 +1,22 @@
+# Copyright (C) 2019 Khem Raj <raj.khem@gmail.com>
+# Released under the MIT license (see COPYING.MIT for the terms)
+
+SUMMARY = "A standalone library to implement GNU libc's obstack"
+DESCRIPTION = "copy + paste of the obstack functions and macros found in GNU gcc libiberty library for use with musl libc"
+HOMEPAGE = "https://github.com/pullmoll/musl-obstack"
+LICENSE = "GPL-2.0+"
+LIC_FILES_CHKSUM = "file://COPYING;md5=3d23e4eef8243efcaab6f0a438078932"
+SECTION = "libs"
+
+PV = "1.1"
+SRCREV = "d2ad66b0df44a4b784956f7f7f2717131ddc05f4"
+SRC_URI = "git://github.com/pullmoll/musl-obstack"
+
+UPSTREAM_CHECK_COMMITS = "1"
+
+inherit autotools pkgconfig
+
+S = "${WORKDIR}/git"
+
+COMPATIBLE_HOST = ".*-musl.*"
+
diff --git a/poky/meta/recipes-core/musl/musl.inc b/poky/meta/recipes-core/musl/musl.inc
index 8408c5da6..0683bf85e 100644
--- a/poky/meta/recipes-core/musl/musl.inc
+++ b/poky/meta/recipes-core/musl/musl.inc
@@ -9,7 +9,7 @@ standards-conformance and safety."
HOMEPAGE = "http://www.musl-libc.org/"
LICENSE = "MIT"
SECTION = "libs"
-LIC_FILES_CHKSUM = "file://COPYRIGHT;md5=8a4bb28f771c817fe57d3a7c4240e3aa"
+LIC_FILES_CHKSUM = "file://COPYRIGHT;md5=d0fe2be17bc45ff4a42ade1c13ed6340"
INHIBIT_DEFAULT_DEPS = "1"
diff --git a/poky/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch b/poky/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch
new file mode 100644
index 000000000..a9abb1872
--- /dev/null
+++ b/poky/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch
@@ -0,0 +1,67 @@
+From 52a37610650e7366a398dd07393d3902d2f3faa3 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Sat, 28 Sep 2019 12:19:57 -0700
+Subject: [PATCH] Change container for riscv floating-point state to __riscv_mc_fp_state
+
+Match the struct elements with glibc
+glibc also uses __riscv_mc prefix, some packages like gdb uses that
+
+Upstream-Status: Submitted [https://www.openwall.com/lists/musl/2019/09/28/1]
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ arch/riscv64/bits/signal.h | 18 +++++++++---------
+ arch/riscv64/bits/user.h | 2 +-
+ 2 files changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/arch/riscv64/bits/signal.h b/arch/riscv64/bits/signal.h
+index 76d7ad80..aba7ab00 100644
+--- a/arch/riscv64/bits/signal.h
++++ b/arch/riscv64/bits/signal.h
+@@ -13,25 +13,25 @@ typedef unsigned long greg_t;
+ typedef unsigned long gregset_t[32];
+
+ struct __riscv_mc_f_ext_state {
+- unsigned int f[32];
+- unsigned int fcsr;
++ unsigned int __f[32];
++ unsigned int __fcsr;
+ };
+
+ struct __riscv_mc_d_ext_state {
+- unsigned long long f[32];
+- unsigned int fcsr;
++ unsigned long long __f[32];
++ unsigned int __fcsr;
+ };
+
+ struct __riscv_mc_q_ext_state {
+- unsigned long long f[64] __attribute__((aligned(16)));
+- unsigned int fcsr;
++ unsigned long long __f[64] __attribute__((aligned(16)));
++ unsigned int __fcsr;
+ unsigned int reserved[3];
+ };
+
+ union __riscv_mc_fp_state {
+- struct __riscv_mc_f_ext_state f;
+- struct __riscv_mc_d_ext_state d;
+- struct __riscv_mc_q_ext_state q;
++ struct __riscv_mc_f_ext_state __f;
++ struct __riscv_mc_d_ext_state __d;
++ struct __riscv_mc_q_ext_state __q;
+ };
+
+ typedef union __riscv_mc_fp_state fpregset_t;
+diff --git a/arch/riscv64/bits/user.h b/arch/riscv64/bits/user.h
+index d2e383b2..9918a2fe 100644
+--- a/arch/riscv64/bits/user.h
++++ b/arch/riscv64/bits/user.h
+@@ -5,4 +5,4 @@ struct user_fpregs_struct {
+
+ #define ELF_NGREG 32
+ typedef unsigned long elf_greg_t, elf_gregset_t[ELF_NGREG];
+-typedef struct user_fpregs_struct elf_fpregset_t;
++typedef union __riscv_mc_fp_state elf_fpregset_t;
+--
+2.23.0
+
diff --git a/poky/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch b/poky/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch
new file mode 100644
index 000000000..09b71cb29
--- /dev/null
+++ b/poky/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch
@@ -0,0 +1,55 @@
+From 59f2954fcaacd9426827c69a729e2647cb9977e5 Mon Sep 17 00:00:00 2001
+From: Palmer Dabbelt <palmer@sifive.com>
+Date: Tue, 24 Sep 2019 20:30:15 -0700
+Subject: [PATCH] correct the operand specifiers in the riscv64 CAS routines
+
+The operand sepcifiers in a_cas and a_casp for riscv64 were incorrect:
+there's a backwards branch in the routine, so despite tmp being written
+at the end of the assembly fragment it cannot be allocated in one of the
+input registers because the input values may be needed for another trip
+around the loop.
+
+For code that follows the guarnteed forward progress requirements, he
+backwards branch is rarely taken: SiFive's hardware only fails a store
+conditional on execptional cases (ie, instruction cache misses inside
+the loop), and until recently a bug in QEMU allowed back-to-back
+store conditionals to succeed. The bug has been fixed in the latest
+QEMU release, but it turns out that the fix caused this latent bug in
+musl to manifest.
+
+Full disclosure: I haven't actually even compiled musl. I just guessed
+this would fix a bug introducted by the new QEMU behavior, Alistair
+(CC'd) actually checked it fixes the problem. The rest is just
+conjecture.
+
+Upstream-Status: Submitted
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ arch/riscv64/atomic_arch.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
+index c9765342..41ad4d04 100644
+--- a/arch/riscv64/atomic_arch.h
++++ b/arch/riscv64/atomic_arch.h
+@@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int s)
+ " sc.w.aqrl %1, %4, (%2)\n"
+ " bnez %1, 1b\n"
+ "1:"
+- : "=&r"(old), "=r"(tmp)
++ : "=&r"(old), "=&r"(tmp)
+ : "r"(p), "r"(t), "r"(s)
+ : "memory");
+ return old;
+@@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
+ " sc.d.aqrl %1, %4, (%2)\n"
+ " bnez %1, 1b\n"
+ "1:"
+- : "=&r"(old), "=r"(tmp)
++ : "=&r"(old), "=&r"(tmp)
+ : "r"(p), "r"(t), "r"(s)
+ : "memory");
+ return old;
+--
+2.23.0
+
diff --git a/poky/meta/recipes-core/musl/musl_git.bb b/poky/meta/recipes-core/musl/musl_git.bb
index a7fae4a65..13fd17353 100644
--- a/poky/meta/recipes-core/musl/musl_git.bb
+++ b/poky/meta/recipes-core/musl/musl_git.bb
@@ -4,9 +4,9 @@
require musl.inc
inherit linuxloader
-SRCREV = "ac304227bb3ea1787d581f17d76a5f5f3abff51f"
+SRCREV = "1f0e9f9cc2e3fa354f94e18b3b362de5f1ec7272"
-BASEVER = "1.1.22"
+BASEVER = "1.1.23"
PV = "${BASEVER}+git${SRCPV}"
@@ -15,6 +15,8 @@ PV = "${BASEVER}+git${SRCPV}"
SRC_URI = "git://git.musl-libc.org/musl \
file://0001-Make-dynamic-linker-a-relative-symlink-to-libc.patch \
file://0002-ldso-Use-syslibdir-and-libdir-as-default-pathes-to-l.patch \
+ file://0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch \
+ file://0001-Change-container-for-riscv-floating-point-state-to-_.patch \
"
S = "${WORKDIR}/git"
@@ -63,7 +65,7 @@ do_install() {
oe_runmake install DESTDIR='${D}'
install -d ${D}${bindir}
- rm -f ${D}${bindir}/ldd
+ rm -f ${D}${bindir}/ldd ${D}${GLIBC_LDSO}
lnr ${D}${libdir}/libc.so ${D}${bindir}/ldd
lnr ${D}${libdir}/libc.so ${D}${GLIBC_LDSO}
for l in crypt dl m pthread resolv rt util xnet