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Add a development (insecure, also known as 'imprint') key to
linux-aspeed that can be used for signing the Kernel fitImage
for U-Boot FIT Signature Verification.
The key was generated according to U-Boot documentation, using:
$ openssl genpkey -algorithm RSA -out rsa_oem_fitimage_key.key \
-pkeyopt rsa_keygen_bits:4096 -pkeyopt rsa_keygen_pubexp:65537
The certificate was created according to U-Boot documentation, using:
$ openssl req -batch -new -x509 -key rsa_oem_fitimage_key.key \
-out rsa_oem_fitimage_key.crt
Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Change-Id: Ic67024ab389c8a4a3fc6709e1d7d92dc72783ca5
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This updates the OpenBMC kernel tree to a 5.7 base. It has been three
releases since the kernel was updated, making it over 9 months of
development time. The stable releses up to v5.7.9 are integrated in this
bump.
There are 106 out of tree kernel patches carried in the OpenBMC tree.
The defconfigs are regenerated with one change made to enable debugfs,
as it will default to off with the new kernel without explicitly
enabling it, and some platforms (eg Witherspoon) reply on it being
enabled.
Alexander Amelkin (1):
mtd: spi-nor: fix options for mx66l51235f
Andrew Geissler (1):
ARM: dts: tacoma: Add KCS node for LPC MCTP
Andrew Jeffery (14):
dt-bindings: hwmon: pmbus: Add Maxim MAX31785 documentation
pmbus (max31785): Add support for devicetree configuration
pmbus (core): Use driver callbacks in pmbus_get_fan_rate()
pmbus (core): One-shot retries for failure to set page
pmbus (max31785): Wrap all I2C accessors in one-shot failure handlers
soc: aspeed: Miscellaneous control interfaces
ARM: dts: aspeed: witherspoon: Update max31785 node
ARM: dts: aspeed-g5: Expose VGA and SuperIO scratch registers
pinctrl: aspeed: Improve debug output
soc: aspeed: Fail probe of lpc-ctrl if reserved memory is not aligned
misc: Add ASPEED KCS driver for MCTP purposes
ARM: dts: witherspoon: Add KCS node for LPC MCTP
pinctrl: aspeed: Describe the heartbeat function on ball Y23
ARM: dts: rainier: Configure ball Y23 as GPIOP7 for MCLR_VPP
Ben Tyner (2):
ARM: dts: aspeed: rainier: Add line-name checkstop
ARM: dts: aspeed: tacoma: Remove checkstop gpio-key
Brad Bishop (4):
ARM: dts: aspeed-g6: Expose SuperIO scratch registers
soc: aspeed: lpc: Add G6 compatible strings
ipmi: aspeed-g6: Add compatible strings
reset: simple: Add AST2600 compatibility string
Cédric Le Goater (22):
mtd: spi-nor: aspeed: use command mode for reads
mtd: spi-nor: aspeed: add support for SPI dual IO read mode
mtd: spi-nor: aspeed: link controller with the ahb clock
mtd: spi-nor: aspeed: optimize read mode
mtd: spi-nor: aspeed: limit the maximum SPI frequency
mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helper
mtd: spi-nor: aspeed: clarify 4BYTE address mode mask
mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization buffer
mtd: spi-nor: aspeed: add support for the 4B opcodes
mtd: spi-nor: Add support for w25q512jv
mtd: spi-nor: aspeed: Introduce a field for the AHB physical address
mtd: spi-nor: aspeed: Introduce segment operations
mtd: spi-nor: aspeed: add initial support for ast2600
mtd: spi-nor: aspeed: Check for disabled segments on the AST2600
mtd: spi-nor: aspeed: Introduce training operations per platform
mtd: spi-nor: aspeed: Introduce a HCLK mask for training
mtd: spi-nor: aspeed: check upper freq limit when doing training
mtd: spi-nor: aspeed: add support for AST2600 training
mtd: spi-nor: aspeed: fix training of multiple CS on the AST2600
mtd: spi-nor: aspeed: Disable zero size segments on the AST2600
spi-nor: aspeed-smc: Detect 4b opcodes differently
/dev/mem: add a devmem kernel parameter to activate the device
Eddie James (21):
ARM: dts: rainier: Add KCS node for LPC MCTP
ARM: dts: aspeed: Add witherspoon-128 machine
fsi: aspeed: Enable 23-bit addressing
clk: ast2600: Fix AHB clock divider for A1
dt-bindings: fsi: Add P10 OCC device documentation
fsi: occ: Add support for P10
hwmon: (occ) Add new temperature sensor type
i2c: fsi: Fix the port number field in status register
i2c: fsi: Prevent adding adapters for ports without dts nodes
ARM: dts: aspeed: rainier: Add second cfam on the hub
dt-bindings: soc: Add Aspeed XDMA Engine
soc: aspeed: Add XDMA Engine Driver
soc: aspeed: xdma: Add user interface
soc: aspeed: xdma: Add reset ioctl
ARM: dts: aspeed: ast2600: Update XDMA engine node
ARM: dts: aspeed: ast2500: Update XDMA engine node
ARM: dts: aspeed: witherspoon: Enable XDMA engine
ARM: dts: aspeed: tacoma: Enable XDMA engine
clk: AST2600: Add mux for EMMC clock
mmc: sdhci-of-aspeed: Prevent clock divider of zero
leds: pca955x: Add an IBM software implementation of the PCA9552 chip
Fran Hsu (3):
ARM: dts: nuvoton: Add NPCM730 common device tree
ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrl
ARM: dts: nuvoton: Add Quanta GSJ BMC
George Hung (2):
dt-binding: edac: add NPCM ECC documentation
edac: npcm: Add Nuvoton NPCM7xx EDAC driver
Jae Hyun Yoo (12):
clk: ast2600: enable BCLK for PCI/PCIe bus always
dt-bindings: Add PECI subsystem document
Documentation: ioctl: Add ioctl numbers for PECI subsystem
peci: Add support for PECI bus driver core
dt-bindings: Add bindings document of Aspeed PECI adapter
ARM: dts: aspeed: Add PECI node
peci: Add Aspeed PECI adapter driver
dt-bindings: mfd: Add Intel PECI client bindings document
mfd: intel-peci-client: Add Intel PECI client driver
Documentation: hwmon: Add documents for PECI hwmon drivers
hwmon: Add PECI cputemp driver
hwmon: Add PECI dimmtemp driver
Joel Stanley (13):
ARM: dts: aspeed-g4: Expose SuperIO scratch registers
ARM: dts: nuvoton: Fix warnings in NPCM7xx common device tree
ARM: dts: nuvoton: Update EVB for new PECI layout
ARM: dts: nuvoton: evb: Rework enabling of nodes
soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600
fsi: aspeed: Support cabled FSI
fsi: aspeed: Run the bus at maximum speed
fsi: aspeed: Add module param for bus divisor
ARM: dts: aspeed: ast2600evb: Add MAC0
ARM: configs: aspeed: Update defconfigs
hwmon (peci-dmmtemp): Fix 'sizeof' warning
soc: aspeed-lpc-ctrl: Fix printf warning
Revert "ARM: dts: aspeed: tacoma: Add gpio-key definitions"
Tomer Maimon (11):
dt-binding: bmc: Add NPCM7xx LPC BPC documentation
misc: npcm7xx-lpc-bpc: add NPCM7xx BIOS post code driver
dt-binding: bmc: add npcm7xx pci mailbox document
misc: mbox: add npcm7xx pci mailbox driver
dt-binding: net: document NPCM7xx EMC DT bindings
net: npcm: add NPCM7xx Ethernet MAC controller
ARM: configs: add defconfig for Nuvoton NPCM7xx BMC
ARM: dts: npcm7xx: Update device tree
arm: dts: Add NPCM7xx RunBMC Olympus Quanta machine.
dt-bindings: peci: add NPCM PECI documentation
peci: npcm: add NPCM PECI driver
(From meta-aspeed rev: a1d8d7791b8257b85eb85d73f08c2961c8c94f16)
Change-Id: I84ae1a28349144db398b7a43e0a2951c1eee434d
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
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OE-Core adds the value of SOC_FAMILY to MACHINEOVERRIDES, so explicitly
setting a MACHINEOVERRIDES is redundant. Drop the explicit
ast2400/ast2500 MACHINEOVERRIDES and use the OE-Core provided aspeed-g4
and aspeed-g5 instead.
After the redundant ast2400/ast2500 overrides are dropped, the ordering
of the values in MACHINEOVERRIDES is wrong:
MACHINEOVERRIDES="aspeed-g5:aspeed"
This means that:
FOO_aspeed = "bar"
will override:
FOO_aspeed-g5 = "baz"
which is the opposite of expectation. The ordering is a function of
config file include order and choice of the predot vs postdot operator.
Use the same include ordering and dot operators as meta-fsl-arm to get
the overrides to appear in MACHINEOVERRIDES in the correct order such
that the expected semantics are provided and:
FOO_aspeed-g5 = "bar"
will override:
FOO_aspeed = "baz"
Drop explicit setting for FILESPATH as OE-Core adds OVERRIDES to
FILESPATH and bitbake will find the appropriate defconfig without them.
Move defconfigs to aspeed-g4 and aspeed-g5 since the ast2400 and ast2500
are being removed.
(From meta-aspeed rev: 85d614a69c1e752fb4d5917499500c37c4f745ac)
Change-Id: I63c0f71f14bf9145e7e769902be87bb267a78a30
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
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The new subtree paradigm has moved the meta-bsp layers to the top level
Change-Id: Ic4f64c39465be699bed3649e125e027d17daf938
Signed-off-by: Dave Cobbley <david.j.cobbley@linux.intel.com>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
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