From b4d1cba25c7a6564ea7789007c2675f738d571a6 Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Tue, 21 Sep 2021 18:31:17 +0000 Subject: x86-power-control: srcrev bump 1aa08b2364..61b4a5bf7e Jason M. Bills (1): Start the watchdog each time waitForSIOPowerGood is set Jean-Marie Verdun (2): Fix gpio logic following parity code insertion SioPowerGoodAssert check at boot for HPE Proliant Change-Id: Ie9dcb53cd9249bc5657adc4b4a73da0bf29ed5af Signed-off-by: Andrew Geissler --- meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb b/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb index e9bad0698..102b3fcb8 100755 --- a/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb +++ b/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb @@ -2,7 +2,7 @@ SUMMARY = "Chassis Power Control service for Intel based platforms" DESCRIPTION = "Chassis Power Control service for Intel based platforms" SRC_URI = "git://github.com/openbmc/x86-power-control.git;protocol=ssh" -SRCREV = "1aa08b23645a85c655fe4712fe7bbb81c7f46dfc" +SRCREV = "61b4a5bf7e8e7be92807fcb85a9780075e8893b4" PV = "1.0+git${SRCPV}" -- cgit v1.2.3