From e4175bb9c38b112600abe7f61cbc56e4fa6d827f Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Thu, 9 Apr 2020 20:30:30 +0000 Subject: x86-power-control: srcrev bump e7520ba18a..fc1ecc5910 Vijay Khemka (1): Add phosphor log (From meta-intel rev: fe94c9a65b4b8f113ab41dc14e85f6c66ecbb513) Change-Id: I5b4186f14fd7be726f5949d69aa03fc5423a63c0 Signed-off-by: Andrew Geissler Signed-off-by: Andrew Geissler --- meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'meta-intel/meta-common/recipes-intel') diff --git a/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb b/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb index 2922b6a36..7dd149e81 100755 --- a/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb +++ b/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb @@ -2,7 +2,7 @@ SUMMARY = "Chassis Power Control service for Intel based platforms" DESCRIPTION = "Chassis Power Control service for Intel based platforms" SRC_URI = "git://github.com/openbmc/x86-power-control.git;protocol=ssh" -SRCREV = "e7520ba18a5b5ba6c8eb7a9d543704f9699295a1" +SRCREV = "fc1ecc59100d21c953501703bc5db9e02e25b333" PV = "1.0+git${SRCPV}" -- cgit v1.2.3