From 82dbc15a05125a812c140a3c8cff81c366482229 Mon Sep 17 00:00:00 2001 From: "Jason M. Bills" Date: Mon, 7 Dec 2020 13:45:20 -0800 Subject: Update to internal 0.26 Signed-off-by: Jason M. Bills --- ...d-WDT-to-u-boot-to-cover-booting-failures.patch | 272 +++++++++++++++++++++ ...n-host-console-is-broken-due-to-BMC-reset.patch | 124 ++++++++++ 2 files changed, 396 insertions(+) create mode 100644 meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch create mode 100644 meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch (limited to 'meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files') diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch new file mode 100644 index 000000000..2d2b906b5 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0048-Add-WDT-to-u-boot-to-cover-booting-failures.patch @@ -0,0 +1,272 @@ +From 367c6c2734e54ff37eac2ace4691f55b0e3d6096 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo +Date: Mon, 14 Sep 2020 17:38:28 -0700 +Subject: [PATCH] Add WDT to u-boot to cover booting failures + +This commit enables WDT1 in early booting phase in u-boot to make BMC +reset to cover booting failures. If BMC meet any failure or if +systemd can't initiate watchdog timer service properly, BMC will +be reset by this watchdog. This watchdog will get feeding by +WATCHDOG_RESET macro calls from several points in u-boot loop +code. The early u-boot WD timeout is 5 seconds and kernel booting WD +timeout is 100 seconds. + +Signed-off-by: Jae Hyun Yoo +--- + arch/arm/mach-aspeed/flash.c | 7 +++ + arch/arm/mach-aspeed/platform_g5.S | 78 ++++++++++++++++++++++++++++++ + board/aspeed/ast-g5/ast-g5-intel.c | 3 ++ + board/aspeed/ast-g5/ast-g5.c | 30 +++++++++++- + common/bootm_os.c | 5 ++ + 5 files changed, 121 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c +index d33fb9e0fe78..31bbf77e9e67 100644 +--- a/arch/arm/mach-aspeed/flash.c ++++ b/arch/arm/mach-aspeed/flash.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -610,6 +611,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) + } + + putc ('.'); ++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) ++ WATCHDOG_RESET(); ++#endif + } + } + puts (" done\n"); +@@ -679,6 +683,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) + src += count; + cnt -= count; + printf("%c\b", pat[(patcnt++) & 0x03]); ++#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) ++ WATCHDOG_RESET(); ++#endif + } + + reset_flash(info); +diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S +index f221c97b19dc..e468ed68d687 100644 +--- a/arch/arm/mach-aspeed/platform_g5.S ++++ b/arch/arm/mach-aspeed/platform_g5.S +@@ -582,6 +582,31 @@ espi_early_init_done: + mov r1, #0xAE + str r1, [r0] + ++#ifdef CONFIG_HW_WATCHDOG ++ /* Enable WDT1 to recover u-boot hang */ ++ ldr r0, =0x1e785004 ++ ldr r1, =0x00500000 @ ~5 seconds ++ str r1, [r0] ++ ldr r0, =0x1e785008 ++ ldr r1, =0x00004755 ++ str r1, [r0] ++ ldr r0, =0x1e78500c ++ ldr r1, =0x00000033 ++ str r1, [r0] ++ ++ /* Clear Scratch register Bit 6 to do DDR training again on WDT1 reset */ ++ ldr r0, =0x1e6e203c ++ ldr r1, [r0] ++ tst r1, #(1<<2) ++ beq bypass_scratch_reg_clear ++ ldr r0, =0x1e6e2040 ++ ldr r1, [r0] ++ and r1, r1, #0xFFFFFFBF ++ str r1, [r0] ++ ++bypass_scratch_reg_clear: ++#endif ++ + /* Test - DRAM initial time */ + ldr r0, =0x1e78203c + ldr r1, =0x0000F000 +@@ -2335,6 +2360,13 @@ spi_checksum_wait_0: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_0 ++ ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x31 @ '1' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + ldr r0, =0x1e620090 + ldr r5, [r0] @ record golden checksum + ldr r0, =0x1e620080 +@@ -2363,6 +2395,13 @@ spi_checksum_wait_1: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_1 ++ ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 +@@ -2377,6 +2416,13 @@ spi_checksum_wait_2: + ldr r1, [r0] + tst r1, r2 + beq spi_checksum_wait_2 ++ ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + ldr r0, =0x1e620090 + ldr r2, [r0] @ read checksum + ldr r0, =0x1e620080 +@@ -2394,6 +2440,12 @@ spi_cbr_next_delay_e: + blt spi_cbr_next_delay_s + b spi_cbr_next_clkrate + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + spi_cbr_end: + ldr r0, =0x1e620094 + str r8, [r0] +@@ -2401,6 +2453,16 @@ spi_cbr_end: + mov r1, #0x0 + str r1, [r0] + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x32 @ '2' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + /****************************************************************************** + Miscellaneous Setting + ******************************************************************************/ +@@ -2447,6 +2509,16 @@ spi_cbr_end: + mov r1, #0 + str r1, [r0] + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x33 @ '3' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++ mov r1, #0x2E @ '.' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + /****************************************************************************** + Configure MAC timing + ******************************************************************************/ +@@ -2535,6 +2607,12 @@ set_D2PLL: + ldr r1, =0xEA + str r1, [r0] + ++/* Debug - UART console message */ ++ ldr r0, =0x1e784000 ++ mov r1, #0x34 @ '4' ++ str r1, [r0] ++/* Debug - UART console message */ ++ + /* restore lr */ + mov lr, r4 + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index c46bd70b71b2..92518a66fa67 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -701,6 +701,9 @@ void ast_g5_intel(void) + timer8_init(); + enable_onboard_tpm(); + if (intel_force_firmware_jumper_enabled()) { ++#ifdef CONFIG_HW_WATCHDOG ++ hw_watchdog_disable(); ++#endif + /* FFUJ mode:- ChassisID: Solid Blue, StatusLED: Solid Amber */ + id_led_control(GPIO_ID_LED, EIDLED_On); + id_led_control(GPIO_GREEN_LED, EIDLED_Off); +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index 00bd92ae5f94..3f27503bce62 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -125,9 +125,35 @@ int board_eth_init(bd_t *bd) + + /* Called by macro WATCHDOG_RESET */ + #if defined(CONFIG_HW_WATCHDOG) ++#define AST_WDT_COUNTER_STATUS 0x00 ++#define AST_WDT_COUNTER_RELOAD_VALUE 0x04 ++#define AST_WDT_COUNTER_RESTART_CTRL 0x08 ++#define AST_WDT_RESTART_VALUE 0x4755 ++#define AST_WDT_CTRL 0x0c ++#define AST_WDT_EN_1MHZ_CLK BIT(4) ++#define AST_WDT_SYS_RESET BIT(1) ++#define AST_WDT_ENABLE BIT(0) ++#define AST_WDT_TIMEOUT_DEFAULT 0x6000000 /* ~100 seconds */ + void hw_watchdog_reset(void) + { +- /* Restart WD2 timer */ +- writel(0x4755, AST_WDT2_BASE + 0x08); ++ /* Restart WDT1 */ ++ writel(AST_WDT_RESTART_VALUE, ++ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++} ++ ++void hw_watchdog_init(void) ++{ ++ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); ++ writel(AST_WDT_TIMEOUT_DEFAULT, ++ AST_WDT1_BASE + AST_WDT_COUNTER_RELOAD_VALUE); ++ writel(AST_WDT_RESTART_VALUE, ++ AST_WDT1_BASE + AST_WDT_COUNTER_RESTART_CTRL); ++ writel(AST_WDT_EN_1MHZ_CLK | AST_WDT_SYS_RESET | AST_WDT_ENABLE, ++ AST_WDT1_BASE + AST_WDT_CTRL); ++} ++ ++void hw_watchdog_disable(void) ++{ ++ writel(0, AST_WDT1_BASE + AST_WDT_CTRL); + } + #endif /* CONFIG_WATCHDOG */ +diff --git a/common/bootm_os.c b/common/bootm_os.c +index b56eb39780e8..ec0e12ac84b9 100644 +--- a/common/bootm_os.c ++++ b/common/bootm_os.c +@@ -473,11 +473,16 @@ __weak void arch_preboot_os(void) + /* please define platform specific arch_preboot_os() */ + } + ++extern void hw_watchdog_init(void); ++ + int boot_selected_os(int argc, char * const argv[], int state, + bootm_headers_t *images, boot_os_fn *boot_fn) + { + disable_interrupts(); + arch_preboot_os(); ++#ifdef CONFIG_HW_WATCHDOG ++ hw_watchdog_init(); /* Re-init WDT with 100 seconds timeout */ ++#endif + boot_fn(state, argc, argv, images); + + /* Stand-alone may return when 'autostart' is 'no' */ +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch new file mode 100644 index 000000000..3c1705c05 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2500/recipes-bsp/u-boot/files/0049-Fix-issue-on-host-console-is-broken-due-to-BMC-reset.patch @@ -0,0 +1,124 @@ +From b6f1f040f515a43d1903f4c4020032dfe436670d Mon Sep 17 00:00:00 2001 +From: Kuiying Wang +Date: Sun, 27 Sep 2020 17:45:56 +0800 +Subject: [PATCH] Fix issue on host console is broken due to BMC reset by + watchdog. + +obmc-console service changed uart routing to support SOL. +UART routing must be changed to normal, when BMC reset happens, +as BMC reset must be treated as SOL connection closure. +User needs to establish a new SOL connection after BMC reset, +and routing will be initialized for SOL at that time. +Which need several seconds (depends on BMC cycle time), +or even never been recoverred if stopped at u-boot shell. + +error situaton as below: +root@intel-obmc:~# devmem 0x1e78909c +0x03450003 +root@intel-obmc:~# /sbin/watchdog -T 0 -F /dev/watchdog1 + +U-Boot 2016.07 (Aug 25 2020 - 05:24:44 +0000) + +SOC : AST2500-A2 +RST : 0x08 (WDT2) +PLL : 24 MHz +CPU : 792 MHz +MEM : 792 MHz, EEC: Disable, Cache: Disable +VGA : 16 MiB +DRAM : init by SOC + Watchdog enabled +DRAM: 496 MiB +Flash: 64 MiB +In: serial +Out: serial +Err: serial +Un-Protected 1 sectors +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +Protected 1 sectors +Net: MAC0 : RMII/NCSI +MAC1 : RGMII +FTGMAC100#0, FTGMAC100#1 +ast# +ast# +ast# md 0x1e78909c +1e78909c: 03450003 ffceff00 19000000 00000000 + +Tested: +u-boot could reset HICRA 0x1e78909c + +correct situation as below: +root@intel-obmc:~# devmem 0x1e78909c +0x03450003 +root@intel-obmc:~# /sbin/watchdog -T 0 -F /dev/watchdog1 + +U-Boot 2016.07 (Sep 27 2020 - 09:34:20 +0000) + +SOC : AST2500-A2 +RST : 0x08 (WDT2) +PLL : 24 MHz +CPU : 792 MHz +MEM : 792 MHz, EEC: Disable, Cache: Disable +VGA : 16 MiB +DRAM : init by SOC + Watchdog enabled +DRAM: 496 MiB +Flash: 64 MiB +In: serial +Out: serial +Err: serial +Un-Protected 1 sectors +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +Protected 1 sectors +Net: MAC0 : RMII/NCSI +MAC1 : RGMII +FTGMAC100#0, FTGMAC100#1 +ast# +ast# +ast# md 0x1e78909c +1e78909c: 00000000 ffceff00 19000000 00000000 + +Signed-off-by: Kuiying Wang +--- + arch/arm/include/asm/arch-aspeed/regs-lpc.h | 1 + + board/aspeed/ast-g5/ast-g5.c | 3 +++ + 2 files changed, 4 insertions(+) + +diff --git a/arch/arm/include/asm/arch-aspeed/regs-lpc.h b/arch/arm/include/asm/arch-aspeed/regs-lpc.h +index b0162ae4f3..b4d3da2906 100644 +--- a/arch/arm/include/asm/arch-aspeed/regs-lpc.h ++++ b/arch/arm/include/asm/arch-aspeed/regs-lpc.h +@@ -18,6 +18,7 @@ + */ + + #define AST_LPC_HICR5 0x80 ++#define AST_LPC_HICRA 0x9C + #define AST_LPC_HICRB 0x100 + + /* AST_LPC_HICR5 : 0x80 Host Interface Control Register 5 */ +diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c +index 00bd92ae5f..4c5997ab8a 100644 +--- a/board/aspeed/ast-g5/ast-g5.c ++++ b/board/aspeed/ast-g5/ast-g5.c +@@ -45,6 +45,9 @@ int board_init(void) + val |= LPC_HICRB_ILPC2AHB; + writel(val, AST_LPC_BASE + AST_LPC_HICRB); + ++ /* Reset UART routing */ ++ writel(0x0, AST_LPC_BASE + AST_LPC_HICRA); ++ + /* P2A, PCIe BMC */ + val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET); + val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA +-- +2.17.1 + -- cgit v1.2.3