From 4aeb24cf629a60980d4ad270fc1750754826613d Mon Sep 17 00:00:00 2001 From: "Jason M. Bills" Date: Mon, 16 Dec 2019 12:21:26 -0800 Subject: Update to internal 2019-12-16 Signed-off-by: Jason M. Bills --- .../0001-Add-ast2600-intel-as-a-new-board.patch | 196 +++++++++++++-------- ...003-ast2600-intel-layout-environment-addr.patch | 51 ++++++ ...ble-host-searial-port-clock-configuration.patch | 72 ++++++++ .../files/0039-AST2500-increase-boot-speed.patch | 40 +++++ .../u-boot/files/0102-Add-espi-polling-check.patch | 141 --------------- .../u-boot/u-boot-aspeed-sdk_%.bbappend | 3 +- .../recipes-bsp/u-boot/u-boot-aspeed_%.bbappend | 1 + 7 files changed, 289 insertions(+), 215 deletions(-) create mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch create mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch create mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0039-AST2500-increase-boot-speed.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0102-Add-espi-polling-check.patch (limited to 'meta-openbmc-mods/meta-common/recipes-bsp') diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch index e76c61a15..a084c4a8c 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch @@ -1,4 +1,4 @@ -From e02a837d388a45e4fb12c7d44eb0a1dc62140d29 Mon Sep 17 00:00:00 2001 +From 069a20560bf9efbd358503c76f043fcdd3a68a94 Mon Sep 17 00:00:00 2001 From: Vernon Mauery Date: Thu, 24 Oct 2019 14:06:33 -0700 Subject: [PATCH] Add ast2600-intel as a new board @@ -13,7 +13,7 @@ Signed-off-by: Jae Hyun Yoo arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c | 1 + board/aspeed/ast2600_intel/Kconfig | 13 + board/aspeed/ast2600_intel/Makefile | 4 + - board/aspeed/ast2600_intel/ast-espi.c | 232 ++++++++++++++ + board/aspeed/ast2600_intel/ast-espi.c | 282 +++++++++++++++++ board/aspeed/ast2600_intel/ast-irq.c | 399 +++++++++++++++++++++++++ board/aspeed/ast2600_intel/ast-irq.h | 8 + board/aspeed/ast2600_intel/ast-timer.c | 59 ++++ @@ -22,7 +22,7 @@ Signed-off-by: Jae Hyun Yoo common/autoboot.c | 10 + common/board_r.c | 8 +- include/configs/evb_ast2600.h | 2 +- - 16 files changed, 1090 insertions(+), 6 deletions(-) + 16 files changed, 1140 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/ast2600-intel.dts create mode 100644 board/aspeed/ast2600_intel/Kconfig create mode 100644 board/aspeed/ast2600_intel/Makefile @@ -322,10 +322,10 @@ index 000000000000..37d2f0064f38 +obj-y += ast-timer.o diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c new file mode 100644 -index 000000000000..2778d7b67d54 +index 000000000000..8dc12d7c9fe8 --- /dev/null +++ b/board/aspeed/ast2600_intel/ast-espi.c -@@ -0,0 +1,232 @@ +@@ -0,0 +1,282 @@ +/* + * Copyright 2018 Intel Corporation + * @@ -338,18 +338,20 @@ index 000000000000..2778d7b67d54 +#include +#include + -+#define AST_LPC_BASE 0x1e6e9000 -+#define AST_ESPI_BASE 0x1e6ee000 -+#define AST_SCU_BASE 0x1e6e2000 -+#define AST_SCU_HW_STRAP1 0x510 -+#define SCU_HW_STRAP_ESPI_ENABLED 0x40 ++#define AST_LPC_BASE 0x1e6e9000 ++#define AST_ESPI_BASE 0x1e6ee000 ++#define AST_SCU_BASE 0x1e6e2000 ++#define AST_SCU_HW_STRAP1 0x510 ++#define SCU_HW_STRAP_ESPI_ENABLED 0x40 + -+#define DEBUG_ESPI_ENABLED 1 -+#ifdef DEBUG_ESPI_ENABLED -+#define DBG_ESPI debug ++#define USE_HW_HANDSHAKE 1 ++#define DEBUG_ESPI_ENABLED 1 ++#if DEBUG_ESPI_ENABLED ++#define DBG_ESPI printf +#else +#define DBG_ESPI(...) +#endif ++ +/* eSPI controller registers */ +#define ESPI000 0x000 /* Engine Control. */ +#define ESPI004 0x004 /* Engine Status. */ @@ -376,6 +378,7 @@ index 000000000000..2778d7b67d54 +#define ESPI070 0x070 /* DMA Addr of Flash Channel Tx pkt. */ +#define ESPI074 0x074 /* Control of Flash Channel Tx pkt. */ +#define ESPI078 0x078 /* Data port of Flash Channel Tx pkt. */ ++#define ESPI080 0x080 /* Engine Control 2. */ +#define ESPI084 0x084 /* Mapping Src Addr of Peripheral Channel Rx pkt. */ +#define ESPI088 0x088 /* Mapping Tgt Addr of Peripheral Channel Rx pkt. */ +#define ESPI08C 0x08C /* Mapping Addr Mask of Peripheral Channel Rx pkt. */ @@ -416,35 +419,63 @@ index 000000000000..2778d7b67d54 +#define ESPICFG818 0x818 /* Mapping Addr Mask of Peripheral Channel Rx pkt */ + +/* ESPI000 bits */ -+#define AST_ESPI_OOB_CHRDY (1 << 4) -+#define AST_ESPI_FLASH_SW_CHRDY (0x1 << 7) -+#define AST_ESPI_FLASH_SW_READ (0x1 << 10) ++#define AST_ESPI_OOB_CHRDY BIT(4) ++#define AST_ESPI_FLASH_SW_CHRDY BIT(7) ++#define AST_ESPI_FLASH_SW_READ BIT(10) + +/* ESPI00C bits (Interrupt Enable) */ -+#define AST_ESPI_IEN_SYS_EV (1 << 8) -+#define AST_ESPI_IEN_GPIO_EV (1 << 9) ++#define AST_ESPI_IEN_HW_RST BIT(31) ++#define AST_ESPI_IEN_SYS1_EV BIT(22) ++#define AST_ESPI_IEN_SYS_EV BIT(8) ++#define AST_ESPI_IEN_GPIO_EV BIT(9) + +/* ESPI008 bits ISR */ -+#define AST_ESPI_VW_SYS_EVT (1 << 8) -+#define AST_ESPI_VW_SYS_EV1 (1 << 22) ++#define AST_ESPI_VW_SYS_EVT BIT(8) ++#define AST_ESPI_VW_SYS_EV1 BIT(9) ++#define AST_ESPI_HW_RST BIT(31) ++ ++/* ESPI080 bits */ ++#define AST_ESPI_AUTO_ACK_HOST_RST_WARN BIT(2) ++#define AST_ESPI_AUTO_ACK_OOB_RST_WARN BIT(1) ++#define AST_ESPI_AUTO_ACK_SUS_WARN BIT(0) + +/* ESPI098 and ESPI11C bits */ -+#define AST_ESPI_OOB_RST_WARN (1 << 6) -+#define AST_ESPI_HOST_RST_WARN (1 << 8) -+#define AST_ESPI_OOB_RST_ACK (1 << 16) -+#define AST_ESPI_SL_BT_DONE (1 << 20) -+#define AST_ESPI_SL_BT_STATUS (1 << 23) -+#define AST_ESPI_HOST_RST_ACK (1 << 27) ++#define AST_ESPI_OOB_RST_WARN BIT(6) ++#define AST_ESPI_HOST_RST_WARN BIT(8) ++#define AST_ESPI_PLTRSTN BIT(5) ++#define AST_ESPI_OOB_RST_ACK BIT(16) ++#define AST_ESPI_SL_BT_DONE BIT(20) ++#define AST_ESPI_SL_BT_STATUS BIT(23) ++#define AST_ESPI_HOST_RST_ACK BIT(27) + +/* ESPI104 bits */ -+#define AST_ESPI_SUS_WARN (1 << 0) -+#define AST_ESPI_SUS_ACK (1 << 20) ++#define AST_ESPI_SUS_WARN BIT(0) ++#define AST_ESPI_SUS_ACK BIT(20) + +/* LPC chip ID */ -+#define SCR0SIO 0x170 -+#define IRQ_SRC_ESPI 74 /* IRQ 74 */ ++#define SCR0SIO 0x170 ++#define IRQ_SRC_ESPI 74 /* IRQ 74 */ + -+static int espi_irq_handler(struct pt_regs *regs) ++static void espi_handshake_ack(void) ++{ ++ /* IRQ only serviced if strapped, so no strap check */ ++ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { ++ DBG_ESPI("Setting espi slave boot done\n"); ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ } ++ ++ uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104); ++ if (sys1_event & AST_ESPI_SUS_WARN && ++ !(sys1_event & AST_ESPI_SUS_ACK)) { ++ DBG_ESPI("Boot SUS_WARN, evt: 0x%08x\n", sys1_event); ++ writel(sys1_event | AST_ESPI_SUS_ACK, AST_ESPI_BASE + ESPI104); ++ DBG_ESPI("SUS_WARN sent ack\n"); ++ } ++} ++ ++int espi_irq_handler(struct pt_regs *regs) +{ + uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008); + @@ -456,22 +487,29 @@ index 000000000000..2778d7b67d54 + + DBG_ESPI("sys_status : 0x%08X\n", sys_status); + if (sys_status & AST_ESPI_HOST_RST_WARN) { -+ DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event); ++ DBG_ESPI("HOST_RST_WARN evt: 0x%08X\n", sys_event); + if (sys_event & AST_ESPI_HOST_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_HOST_RST_ACK; ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_HOST_RST_ACK; + writel(v, AST_ESPI_BASE + ESPI098); ++ DBG_ESPI("HOST_RST_WARN sent ack\n"); + } + } + if (sys_status & AST_ESPI_OOB_RST_WARN) { -+ DBG_ESPI("OOB_RST_WARN ev: %08X\n", sys_event); ++ DBG_ESPI("OOB_RST_WARN evt: 0x%08X\n", sys_event); + if (sys_event & AST_ESPI_OOB_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_OOB_RST_ACK; ++ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_OOB_RST_ACK; + writel(v, AST_ESPI_BASE + ESPI098); ++ DBG_ESPI("OOB_RST_WARN sent ack\n"); + } + } -+ writel(sys_status, AST_ESPI_BASE + ESPI11C); // clear status ++ if (sys_status & AST_ESPI_PLTRSTN) { ++ DBG_ESPI("PLTRSTN: %c, evt: 0x%08X\n", ++ (sys_event & AST_ESPI_PLTRSTN) ? '1' : '0', ++ sys_event); ++ } ++ writel(sys_status, AST_ESPI_BASE + ESPI11C); /* clear status */ + } + + if (irq_status & AST_ESPI_VW_SYS_EV1) { @@ -480,35 +518,31 @@ index 000000000000..2778d7b67d54 + + DBG_ESPI("sys1_status : 0x%08X\n", sys1_status); + if (sys1_status & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("SUS WARN ev: %08X\n", sys1_event); ++ DBG_ESPI("SUS WARN evt: 0x%08X\n", sys1_event); + if (sys1_event & AST_ESPI_SUS_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) -+ | AST_ESPI_SUS_ACK; ++ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | ++ AST_ESPI_SUS_ACK; + writel(v, AST_ESPI_BASE + ESPI104); ++ DBG_ESPI("SUS_WARN sent ack\n"); + } + } -+ writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status ++ writel(sys1_status, AST_ESPI_BASE + ESPI12C); /* clear status */ + } -+ writel(irq_status, AST_ESPI_BASE + ESPI008); // clear irq_status -+ return 0; -+} + -+static void espi_handshake_ack(void) -+{ -+ // IRQ only serviced if strapped, so no strap check -+ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { -+ DBG_ESPI("Setting espi slave boot done\n"); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } ++ if (irq_status & AST_ESPI_HW_RST) { ++ uint32_t v = readl(AST_ESPI_BASE + ESPI000) & 0x00ffffffff; ++ writel(v, AST_ESPI_BASE + ESPI000); ++ v |= 0xff000000; ++ writel(v, AST_ESPI_BASE + ESPI000); ++ ++ DBG_ESPI("HW_RESET\n"); + -+ if (readl(AST_ESPI_BASE + ESPI104) & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("Boot SUS WARN set %08x\n", -+ readl(AST_ESPI_BASE + ESPI104)); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; -+ writel(v, AST_ESPI_BASE + ESPI104); ++ espi_handshake_ack(); + } ++ ++ writel(irq_status, AST_ESPI_BASE + ESPI008); /* clear irq_status */ ++ ++ return 0; +} + +void espi_init(void) @@ -517,43 +551,59 @@ index 000000000000..2778d7b67d54 + & SCU_HW_STRAP_ESPI_ENABLED) { + uint32_t v; + ++ DBG_ESPI("espi init\n"); ++ ++ writel(0xff000000, AST_SCU_BASE + 0x454); /* driving strength */ ++ + /* Block flash access from Host */ + v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_FLASH_SW_CHRDY; + v |= AST_ESPI_FLASH_SW_READ | AST_ESPI_OOB_CHRDY; + writel(v, AST_ESPI_BASE + ESPI000); + -+ /* Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for -+ * BIOS using in eSPI mode */ ++ /* ++ * Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for ++ * BIOS using in eSPI mode. ++ */ + v = readl(AST_LPC_BASE + SCR0SIO) & ~0x000000ff; + writel(v, AST_LPC_BASE + SCR0SIO); + v = readl(AST_LPC_BASE + SCR0SIO) | 0xa8; + writel(v, AST_LPC_BASE + SCR0SIO); + -+ v = readl(AST_ESPI_BASE + ESPI000) | AST_ESPI_OOB_CHRDY; -+ writel(v, AST_ESPI_BASE + ESPI000); ++#if USE_HW_HANDSHAKE ++ v = readl(AST_ESPI_BASE + ESPI098) | ++ AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; ++ writel(v, AST_ESPI_BASE + ESPI098); ++ ++ return; ++#endif ++ ++ v = readl(AST_ESPI_BASE + ESPI080); ++ v &= ~(AST_ESPI_AUTO_ACK_HOST_RST_WARN | ++ AST_ESPI_AUTO_ACK_OOB_RST_WARN | ++ AST_ESPI_AUTO_ACK_SUS_WARN); ++ writel(v, AST_ESPI_BASE + ESPI080); /* Disable auto H/W ack */ + + writel(0, AST_ESPI_BASE + ESPI110); + writel(0, AST_ESPI_BASE + ESPI114); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN, -+ AST_ESPI_BASE + ESPI118); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN, -+ AST_ESPI_BASE + ESPI094); ++ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN | ++ AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI118); ++ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN | ++ AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI094); + + writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE + ESPI120); // int type 0 susp warn ++ AST_ESPI_BASE + ESPI120); /* int type 0 susp warn */ + writel(0, AST_ESPI_BASE + ESPI124); + writel(0, AST_ESPI_BASE + ESPI128); + writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE -+ + ESPI100); // Enable sysev1 ints for susp warn ++ AST_ESPI_BASE + ++ ESPI100); /* Enable sysev1 ints for susp warn */ + -+ writel(AST_ESPI_IEN_SYS_EV, -+ AST_ESPI_BASE + ESPI00C); // Enable only sys events ++ writel(AST_ESPI_IEN_HW_RST | AST_ESPI_IEN_SYS1_EV | ++ AST_ESPI_IEN_SYS_EV, AST_ESPI_BASE + ESPI00C); + + espi_handshake_ack(); + + irq_install_handler(IRQ_SRC_ESPI, espi_irq_handler, NULL); -+ + } else { + DBG_ESPI("No espi strap\n"); + } diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch new file mode 100644 index 000000000..a1a8acf81 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch @@ -0,0 +1,51 @@ +From e074cf61bd6a726c8cb513336507047ece5423d0 Mon Sep 17 00:00:00 2001 +From: Kuiying Wang +Date: Thu, 12 Dec 2019 12:54:18 +0800 +Subject: [PATCH] ast2600: intel-layout-environment-addr + +Tested: +Both kernel and u-boot work at the area /dev/mtd/u-boot-env + +Signed-off-by: Kuiying Wang +--- + include/configs/aspeed-common.h | 5 ++++- + include/configs/evb_ast2600_spl.h | 2 +- + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h +index d1eb468..8ad9deb 100644 +--- a/include/configs/aspeed-common.h ++++ b/include/configs/aspeed-common.h +@@ -56,12 +56,15 @@ + #define CONFIG_BOOTCOMMAND "bootm 20080000" + #endif + #define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET 0x2400000 ++#define CONFIG_ENV_SIZE 0x10000 ++#define CONFIG_ENV_SECT_SIZE (4 << 10) + + #define CONFIG_SYS_BOOTM_LEN (0x800000 * 2) + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=yes\0" \ +- "spi_dma=no\0" \ ++ "spi_dma=yes\0" \ + "" + + /* +diff --git a/include/configs/evb_ast2600_spl.h b/include/configs/evb_ast2600_spl.h +index 8bbd6e1..8529f46 100644 +--- a/include/configs/evb_ast2600_spl.h ++++ b/include/configs/evb_ast2600_spl.h +@@ -19,7 +19,7 @@ + + /* Environment */ + #define CONFIG_ENV_SIZE 0x10000 +-#define CONFIG_ENV_OFFSET 0x90000 ++#define CONFIG_ENV_OFFSET 0x2400000 + #define CONFIG_ENV_SECT_SIZE (4 << 10) + + #ifdef CONFIG_SPL_TINY +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch new file mode 100644 index 000000000..5522d5f6c --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch @@ -0,0 +1,72 @@ +From ccfc20ceb2931e84ffb02b01099ccb7610b44d9c Mon Sep 17 00:00:00 2001 +From: Kuiying Wang +Date: Tue, 10 Dec 2019 14:58:10 +0800 +Subject: [PATCH] AST2600: Enable host searial port clock configuration in + u-boot + +In u-boot could read env variable "hostsearialcfg" and set the corresponding +clock for host searail port. + +Tested: +setenv hostsearialcfg 1, speed is set to 192Mhz (baud rate 921600) +other value, speed is set to 24Mhz(baud rate 115200) +by default is 24Mhz. + +Signed-off-by: Kuiying Wang +--- + board/aspeed/ast2600_intel/intel.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c +index 100eb1e..eb6fbaf 100644 +--- a/board/aspeed/ast2600_intel/intel.c ++++ b/board/aspeed/ast2600_intel/intel.c +@@ -35,9 +35,45 @@ int gpio_abort(void) + return value <= 0 ? 0 : 1; + } + ++#define SCU_BASE 0x1E6E2000 ++#define SCU_338 0x338 //Generate UART 24 MHz Reference from UXCLK ++#define SCU_33C 0x33c //Generate UART 24 MHz Reference from HUXCLK ++#define SCU_338_R_VALUE_192MHZ 0x8e ++#define SCU_338_N_VALUE_192MHZ 0x3c3 ++#define SCU_338_R_VALUE_24MHZ 0x06 ++#define SCU_338_N_VALUE_24MHZ 0x145 ++#define HOST_SERIAL_HIGH_SPEED_192MHZ 1 ++#define R_VALUE_BITS 8 ++#define V_VALUE_BITS 10 ++#define R_V_VALUE_MASK (1 << (R_VALUE_BITS + V_VALUE_BITS)) ++ + int misc_init_r(void) + { + /* This is called near the end of the _r init sequence */ ++ /* By default host serail is set 24Mhz */ ++ uint32_t host_serial_cfg = 0; ++ char *host_serial_cfg_txt = NULL; ++ ++ /* Config the uart clock source based on environment configuration */ ++ host_serial_cfg_txt = env_get("hostserialcfg"); ++ ++ if (host_serial_cfg_txt != NULL) ++ host_serial_cfg = simple_strtoul(host_serial_cfg_txt, NULL, 16); ++ ++ if (host_serial_cfg > HOST_SERIAL_HIGH_SPEED_192MHZ || host_serial_cfg < 0) { ++ printf("Invalid hostserialcfg %x, 24Mhz is set by default!\n", host_serial_cfg); ++ host_serial_cfg = 0; ++ } ++ ++ if (host_serial_cfg & HOST_SERIAL_HIGH_SPEED_192MHZ) { ++ writel((readl(SCU_BASE | SCU_338) & R_V_VALUE_MASK) | ++ (SCU_338_N_VALUE_192MHZ << R_VALUE_BITS) | SCU_338_R_VALUE_192MHZ, ++ SCU_BASE | SCU_338); ++ } else { ++ writel((readl(SCU_BASE | SCU_338) & R_V_VALUE_MASK) | ++ (SCU_338_N_VALUE_24MHZ << R_VALUE_BITS) | SCU_338_R_VALUE_24MHZ, ++ SCU_BASE | SCU_338); ++ } + + return 0; + } +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0039-AST2500-increase-boot-speed.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0039-AST2500-increase-boot-speed.patch new file mode 100644 index 000000000..ce36b580e --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0039-AST2500-increase-boot-speed.patch @@ -0,0 +1,40 @@ +From 1e9a4afdfa995e924f74139f620e8b2f985a705f Mon Sep 17 00:00:00 2001 +From: James Feist +Date: Tue, 10 Dec 2019 16:21:24 -0800 +Subject: [PATCH 1/1] AST2500 increase boot speed + +This hardcodes the IOMODE to x2 as that is the fastest +we support. + +Signed-off-by: James Feist +--- + arch/arm/mach-aspeed/flash.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c +index d33fb9e0fe..31d2ef6001 100644 +--- a/arch/arm/mach-aspeed/flash.c ++++ b/arch/arm/mach-aspeed/flash.c +@@ -730,7 +730,7 @@ static ulong flash_get_size (ulong base, flash_info_t *info) + ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ; + info->flash_id = ulID; + +-// printf("SPI Flash ID: %x \n", ulID); ++ printf("SPI Flash ID: %x \n", ulID); + + /* init default */ + info->iomode = IOMODEx1; +@@ -1258,6 +1258,10 @@ static ulong flash_get_size (ulong base, flash_info_t *info) + } /* JDEC */ + } + ++ info->readcmd = 0xbb; ++ info->dualport = 1; ++ info->iomode = IOMODEx2_dummy; ++ + sector = base; + for (j = 0; j < info->sector_count; j++) { + +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0102-Add-espi-polling-check.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0102-Add-espi-polling-check.patch deleted file mode 100644 index 683178054..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0102-Add-espi-polling-check.patch +++ /dev/null @@ -1,141 +0,0 @@ -From ea6dad13d4d4b8c7a39829f75425290447e0f148 Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo -Date: Tue, 12 Nov 2019 16:46:01 -0800 -Subject: [PATCH] Add espi polling check - -Since interrupt in u-boot isn't working so this commit adds espi -polling check into cli as a WA to handle host espi events. - -This is a temporary WA. - -Signed-off-by: Jae Hyun Yoo ---- - board/aspeed/ast2600_intel/ast-espi.c | 24 ++++++++++++++++++------ - common/console.c | 3 +++ - 2 files changed, 21 insertions(+), 6 deletions(-) - -diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c -index 2778d7b67d54..c88098efcdb5 100644 ---- a/board/aspeed/ast2600_intel/ast-espi.c -+++ b/board/aspeed/ast2600_intel/ast-espi.c -@@ -18,7 +18,7 @@ - - #define DEBUG_ESPI_ENABLED 1 - #ifdef DEBUG_ESPI_ENABLED --#define DBG_ESPI debug -+#define DBG_ESPI printf - #else - #define DBG_ESPI(...) - #endif -@@ -116,11 +116,13 @@ - #define SCR0SIO 0x170 - #define IRQ_SRC_ESPI 74 /* IRQ 74 */ - --static int espi_irq_handler(struct pt_regs *regs) -+int espi_irq_handler(struct pt_regs *regs) - { - uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008); - -+#if 0 - DBG_ESPI("ISR irq_status : 0x%08X\n", irq_status); -+#endif - - if (irq_status & AST_ESPI_VW_SYS_EVT) { - uint32_t sys_status = readl(AST_ESPI_BASE + ESPI11C); -@@ -128,19 +130,21 @@ static int espi_irq_handler(struct pt_regs *regs) - - DBG_ESPI("sys_status : 0x%08X\n", sys_status); - if (sys_status & AST_ESPI_HOST_RST_WARN) { -- DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event); -+ DBG_ESPI("HOST_RST_WARN evt: 0x%08X\n", sys_event); - if (sys_event & AST_ESPI_HOST_RST_WARN) { - uint32_t v = readl(AST_ESPI_BASE + ESPI098) - | AST_ESPI_HOST_RST_ACK; - writel(v, AST_ESPI_BASE + ESPI098); -+ DBG_ESPI("HOST_RST_WARN sent ack\n"); - } - } - if (sys_status & AST_ESPI_OOB_RST_WARN) { -- DBG_ESPI("OOB_RST_WARN ev: %08X\n", sys_event); -+ DBG_ESPI("OOB_RST_WARN evt: 0x%08X\n", sys_event); - if (sys_event & AST_ESPI_OOB_RST_WARN) { - uint32_t v = readl(AST_ESPI_BASE + ESPI098) - | AST_ESPI_OOB_RST_ACK; - writel(v, AST_ESPI_BASE + ESPI098); -+ DBG_ESPI("OOB_RST_WARN sent ack\n"); - } - } - writel(sys_status, AST_ESPI_BASE + ESPI11C); // clear status -@@ -152,16 +156,19 @@ static int espi_irq_handler(struct pt_regs *regs) - - DBG_ESPI("sys1_status : 0x%08X\n", sys1_status); - if (sys1_status & AST_ESPI_SUS_WARN) { -- DBG_ESPI("SUS WARN ev: %08X\n", sys1_event); -+ DBG_ESPI("SUS WARN evt: 0x%08X\n", sys1_event); - if (sys1_event & AST_ESPI_SUS_WARN) { - uint32_t v = readl(AST_ESPI_BASE + ESPI104) - | AST_ESPI_SUS_ACK; - writel(v, AST_ESPI_BASE + ESPI104); -+ DBG_ESPI("SUS_WARN sent ack\n"); - } - } - writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status - } -+ - writel(irq_status, AST_ESPI_BASE + ESPI008); // clear irq_status -+ - return 0; - } - -@@ -176,7 +183,7 @@ static void espi_handshake_ack(void) - } - - if (readl(AST_ESPI_BASE + ESPI104) & AST_ESPI_SUS_WARN) { -- DBG_ESPI("Boot SUS WARN set %08x\n", -+ DBG_ESPI("Boot SUS WARN set 0x%08x\n", - readl(AST_ESPI_BASE + ESPI104)); - uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; - writel(v, AST_ESPI_BASE + ESPI104); -@@ -189,6 +196,8 @@ void espi_init(void) - & SCU_HW_STRAP_ESPI_ENABLED) { - uint32_t v; - -+ DBG_ESPI("espi init\n"); -+ - /* Block flash access from Host */ - v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_FLASH_SW_CHRDY; - v |= AST_ESPI_FLASH_SW_READ | AST_ESPI_OOB_CHRDY; -@@ -226,6 +235,9 @@ void espi_init(void) - - irq_install_handler(IRQ_SRC_ESPI, espi_irq_handler, NULL); - -+#if 1 -+ espi_irq_handler(NULL); -+#endif - } else { - DBG_ESPI("No espi strap\n"); - } -diff --git a/common/console.c b/common/console.c -index 0b0dd76256c7..90cdf7701c9d 100644 ---- a/common/console.c -+++ b/common/console.c -@@ -308,6 +308,8 @@ int serial_printf(const char *fmt, ...) - return i; - } - -+extern int espi_irq_handler(struct pt_regs *regs); -+ - int fgetc(int file) - { - if (file < MAX_FILES) { -@@ -315,6 +317,7 @@ int fgetc(int file) - * Effectively poll for input wherever it may be available. - */ - for (;;) { -+ espi_irq_handler(NULL); - WATCHDOG_RESET(); - #if CONFIG_IS_ENABLED(CONSOLE_MUX) - /* --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend index 13b7d45e5..376b785c1 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend @@ -6,5 +6,6 @@ FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:" SRC_URI_append_intel-ast2600 = " \ file://intel.cfg \ file://0001-Add-ast2600-intel-as-a-new-board.patch \ - file://0102-Add-espi-polling-check.patch \ + file://0021-AST2600-Enable-host-searial-port-clock-configuration.patch \ + file://0003-ast2600-intel-layout-environment-addr.patch \ " diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend index 675c9493b..a536dce34 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend @@ -38,6 +38,7 @@ SRC_URI_append_intel-ast2500 = " \ file://0036-Re-Enable-KCS.patch \ file://0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch \ file://0038-Increase-default-fan-speed-for-cooper-city.patch \ + file://0039-AST2500-increase-boot-speed.patch \ " PFR_SRC_URI = " \ file://0022-u-boot-env-change-for-PFR-image.patch \ -- cgit v1.2.3