From eda2c7c523d858d25fe25052254a7f393767310b Mon Sep 17 00:00:00 2001 From: "Jason M. Bills" Date: Tue, 5 May 2020 15:31:17 -0700 Subject: Update to internal 0.53 Signed-off-by: Jason M. Bills --- .../0001-Add-ast2600-intel-as-a-new-board.patch | 1350 ----------------- .../0001-flash-use-readX-writeX-not-udelay.patch | 424 ------ .../files/0002-intel-layout-environment-addr.patch | 51 - ...003-ast2600-intel-layout-environment-addr.patch | 67 - ...0004-AST2600-Adjust-default-GPIO-settings.patch | 86 -- ...re-debug-uart-is-using-24MHz-clock-source.patch | 73 - .../0005-Ast2600-Enable-interrupt-in-u-boot.patch | 435 ------ .../files/0005-enable-passthrough-in-uboot.patch | 53 - .../0006-Add-Aspeed-g5-interrupt-support.patch | 387 ----- .../u-boot/files/0006-SPI-Quad-IO-Mode.patch | 105 -- .../u-boot/files/0007-Add-espi-support.patch | 347 ----- .../0007-ast2600-Override-OTP-strap-settings.patch | 78 - .../files/0008-AST2600-Add-TPM-pulse-trigger.patch | 60 - ...d-sgio-support-for-port80-snoop-post-LEDs.patch | 158 -- .../u-boot/files/0009-Add-basic-GPIO-support.patch | 427 ------ ...ce-Firmware-Update-Jumper-to-use-new-gpio.patch | 96 -- ...sic-timer-support-for-Aspeed-g5-in-U-Boot.patch | 158 -- .../files/0012-Add-status-and-ID-LED-support.patch | 149 -- .../u-boot/files/0013-aspeed-Add-Pwm-Driver.patch | 141 -- ...Keep-interrupts-enabled-until-last-second.patch | 89 -- ...ite-memmove-to-optimize-on-word-transfers.patch | 112 -- ...u-boot-full-platform-reset-espi-oob-ready.patch | 46 - .../0020-Add-system-reset-status-support.patch | 164 --- .../u-boot/files/0020-Enable-PCIe-L1-support.patch | 36 - ...ble-host-searial-port-clock-configuration.patch | 71 - ...-uart-clock-source-using-environment-vari.patch | 106 -- .../files/0022-KCS-driver-support-in-uBoot.patch | 613 -------- .../0022-u-boot-env-change-for-PFR-image.patch | 37 - .../0023-Add-TPM-enable-pulse-triggering.patch | 50 - ...I-command-handler-implementation-in-uboot.patch | 330 ----- ...acturing-mode-physical-presence-detection.patch | 114 -- .../files/0026-Aspeed-I2C-support-in-U-Boot.patch | 1524 -------------------- ...0027-CPLD-u-boot-commands-support-for-PFR.patch | 302 ---- ...g-uart1-uart2-in-u-boot-for-BIOS-messages.patch | 59 - ...IPMI-commands-and-flash-support-in-u-boot.patch | 1273 ---------------- ...030-Support-Get-Set-Security-mode-command.patch | 124 -- ...0031-Make-it-so-TFTP-port-can-be-modified.patch | 40 - ...W-update-and-checkpoint-support-in-u-boot.patch | 530 ------- ...33-Reboot-into-UBOOT-on-Watchdog-Failures.patch | 110 -- .../files/0034-Disable-uart-debug-interface.patch | 54 - ...-PFR-platform-EXTRST-reset-mask-selection.patch | 124 -- .../u-boot/files/0036-Re-Enable-KCS.patch | 35 - ...scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch | 80 - ...ncrease-default-fan-speed-for-cooper-city.patch | 131 -- ...ialize-the-BMC-host-mailbox-at-reset-time.patch | 65 - .../u-boot/files/0041-Disabling-boot-delay.patch | 27 - ...R-u-boot-env-changes-as-per-PFR-BMC-image.patch | 36 - ...ip-counting-WDT2-event-when-EXTRST-is-set.patch | 45 - .../meta-common/recipes-bsp/u-boot/files/intel.cfg | 27 - .../recipes-bsp/u-boot/u-boot-%.bbappend | 5 + .../u-boot/u-boot-aspeed-sdk_%.bbappend | 26 - .../recipes-bsp/u-boot/u-boot-aspeed_%.bbappend | 72 - .../u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend | 18 - .../u-boot/u-boot-fw-utils-aspeed_%.bbappend | 1 - 54 files changed, 5 insertions(+), 11116 deletions(-) delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-flash-use-readX-writeX-not-udelay.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch delete mode 100755 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0030-Support-Get-Set-Security-mode-command.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0031-Make-it-so-TFTP-port-can-be-modified.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0033-Reboot-into-UBOOT-on-Watchdog-Failures.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0034-Disable-uart-debug-interface.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0036-Re-Enable-KCS.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0038-Increase-default-fan-speed-for-cooper-city.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0041-Disabling-boot-delay.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg create mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-%.bbappend delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend delete mode 100644 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend delete mode 120000 meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend (limited to 'meta-openbmc-mods/meta-common/recipes-bsp') diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch deleted file mode 100644 index 373893a44..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch +++ /dev/null @@ -1,1350 +0,0 @@ -From 145ffdf95955562eddf96d0342bcdebd98f8dc95 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Thu, 24 Oct 2019 14:06:33 -0700 -Subject: [PATCH] Add ast2600-intel as a new board - -Signed-off-by: Vernon Mauery -Signed-off-by: Jae Hyun Yoo -Signed-off-by: Kuiying Wang ---- - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/ast2600-intel.dts | 197 ++++++++++++++++ - arch/arm/lib/interrupts.c | 5 + - arch/arm/mach-aspeed/ast2600/Kconfig | 8 + - board/aspeed/ast2600_intel/Kconfig | 13 ++ - board/aspeed/ast2600_intel/Makefile | 4 + - board/aspeed/ast2600_intel/ast-espi.c | 298 ++++++++++++++++++++++++ - board/aspeed/ast2600_intel/ast-irq.c | 399 +++++++++++++++++++++++++++++++++ - board/aspeed/ast2600_intel/ast-irq.h | 8 + - board/aspeed/ast2600_intel/ast-timer.c | 59 +++++ - board/aspeed/ast2600_intel/intel.c | 177 +++++++++++++++ - cmd/Kconfig | 2 +- - common/autoboot.c | 10 + - 13 files changed, 1181 insertions(+), 2 deletions(-) - create mode 100644 arch/arm/dts/ast2600-intel.dts - create mode 100644 board/aspeed/ast2600_intel/Kconfig - create mode 100644 board/aspeed/ast2600_intel/Makefile - create mode 100644 board/aspeed/ast2600_intel/ast-espi.c - create mode 100644 board/aspeed/ast2600_intel/ast-irq.c - create mode 100644 board/aspeed/ast2600_intel/ast-irq.h - create mode 100644 board/aspeed/ast2600_intel/ast-timer.c - create mode 100644 board/aspeed/ast2600_intel/intel.c - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index e4dae2937968..da8903123999 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -683,7 +683,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ - ast2600-fpga.dtb \ - ast2600-rainier.dtb \ - ast2600-slt.dtb \ -- ast2600-tacoma.dtb -+ ast2600-tacoma.dtb \ -+ ast2600-intel.dtb - - dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb - -diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts -new file mode 100644 -index 000000000000..9a15e204f83b ---- /dev/null -+++ b/arch/arm/dts/ast2600-intel.dts -@@ -0,0 +1,197 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright (c) 2019-2020 Intel Corporation -+/dts-v1/; -+ -+#include "ast2600-u-boot.dtsi" -+ -+/ { -+ memory { -+ device_type = "memory"; -+ reg = <0x80000000 0x40000000>; -+ }; -+ -+ chosen { -+ stdout-path = &uart5; -+ }; -+ -+ aliases { -+ spi0 = &fmc; -+ ethernet1 = &mac1; -+ }; -+ -+ cpus { -+ cpu@0 { -+ clock-frequency = <800000000>; -+ }; -+ cpu@1 { -+ clock-frequency = <800000000>; -+ }; -+ }; -+ -+ system-leds { -+ compatible = "gpio-leds"; -+ green-led { -+ label = "green"; -+ gpios = <&gpio0 50 GPIO_ACTIVE_LOW>; -+ default-state = "blink"; -+ }; -+ amber-led { -+ label = "amber"; -+ gpios = <&gpio0 51 GPIO_ACTIVE_LOW>; -+ default-state = "off"; -+ }; -+ id-led { -+ label = "id"; -+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -+ default-state = "blink"; -+ }; -+ hb-led { -+ label = "hb"; -+ gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+}; -+ -+&gpio0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&uart5 { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&sdrammc { -+ clock-frequency = <400000000>; -+}; -+ -+&wdt1 { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&wdt2 { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&wdt3 { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&mdio { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ ethphy1: ethernet-phy@1 { -+ reg = <0>; -+ }; -+ -+ ethphy2: ethernet-phy@2 { -+ reg = <0>; -+ }; -+ -+ ethphy3: ethernet-phy@3 { -+ reg = <0>; -+ }; -+ -+ ethphy4: ethernet-phy@4 { -+ reg = <0>; -+ }; -+}; -+ -+&mac1 { -+ status = "okay"; -+ phy-mode = "rgmii"; -+ phy-handle = <ðphy2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mac2link_default &pinctrl_mdio2_default>; -+}; -+ -+&fmc { -+ status = "okay"; -+#if 0 -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fmcquad_default>; -+#endif -+ flash@0 { -+ compatible = "spi-flash", "sst,w25q256"; -+ status = "okay"; -+ spi-max-frequency = <40000000>; -+ spi-tx-bus-width = <2>; -+ spi-rx-bus-width = <2>; -+ }; -+}; -+ -+&emmc_slot0 { -+ status = "okay"; -+ bus-width = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_emmc_default>; -+}; -+ -+&i2c4 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c5_default>; -+}; -+ -+&i2c5 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c6_default>; -+}; -+ -+&i2c6 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c7_default>; -+}; -+ -+&i2c7 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c8_default>; -+}; -+ -+&i2c8 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c9_default>; -+}; -+ -+&i2c9 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c10_default>; -+}; -+ -+&i2c12 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c13_default>; -+}; -+ -+&i2c13 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c14_default>; -+}; -\ No newline at end of file -diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c -index ee775ce5d264..8c985532afb4 100644 ---- a/arch/arm/lib/interrupts.c -+++ b/arch/arm/lib/interrupts.c -@@ -25,6 +25,7 @@ - - DECLARE_GLOBAL_DATA_PTR; - -+int interrupt_init (void) __attribute__((weak)); - int interrupt_init (void) - { - /* -@@ -35,10 +36,13 @@ int interrupt_init (void) - return 0; - } - -+void enable_interrupts (void) __attribute__((weak)); - void enable_interrupts (void) - { - return; - } -+ -+int disable_interrupts (void) __attribute__((weak)); - int disable_interrupts (void) - { - return 0; -@@ -189,6 +193,7 @@ void do_fiq (struct pt_regs *pt_regs) - bad_mode (); - } - -+void do_irq (struct pt_regs *pt_regs) __attribute__((weak)); - void do_irq (struct pt_regs *pt_regs) - { - efi_restore_gd(); -diff --git a/arch/arm/mach-aspeed/ast2600/Kconfig b/arch/arm/mach-aspeed/ast2600/Kconfig -index dd991e87c795..7ccbb0b5e0ea 100644 ---- a/arch/arm/mach-aspeed/ast2600/Kconfig -+++ b/arch/arm/mach-aspeed/ast2600/Kconfig -@@ -51,6 +51,13 @@ config TARGET_SLT_AST2600 - help - SLT-AST2600 is Aspeed SLT board for AST2600 chip. - -+config TARGET_AST2600_INTEL -+ bool "AST2600-INTEL" -+ depends on ASPEED_AST2600 -+ help -+ AST2600-INTEL is an Intel server board with the AST2600 -+ as the BMC. -+ - endchoice - - source "board/aspeed/evb_ast2600a0/Kconfig" -@@ -59,5 +66,6 @@ source "board/aspeed/ncsi_ast2600a0/Kconfig" - source "board/aspeed/ncsi_ast2600a1/Kconfig" - source "board/aspeed/fpga_ast2600/Kconfig" - source "board/aspeed/slt_ast2600/Kconfig" -+source "board/aspeed/ast2600_intel/Kconfig" - - endif -diff --git a/board/aspeed/ast2600_intel/Kconfig b/board/aspeed/ast2600_intel/Kconfig -new file mode 100644 -index 000000000000..b841dab60c76 ---- /dev/null -+++ b/board/aspeed/ast2600_intel/Kconfig -@@ -0,0 +1,13 @@ -+if TARGET_AST2600_INTEL -+ -+config SYS_BOARD -+ default "ast2600_intel" -+ -+config SYS_VENDOR -+ default "aspeed" -+ -+config SYS_CONFIG_NAME -+ string "board configuration name" -+ default "ast2600_intel" -+ -+endif -diff --git a/board/aspeed/ast2600_intel/Makefile b/board/aspeed/ast2600_intel/Makefile -new file mode 100644 -index 000000000000..37d2f0064f38 ---- /dev/null -+++ b/board/aspeed/ast2600_intel/Makefile -@@ -0,0 +1,4 @@ -+obj-y += intel.o -+obj-y += ast-espi.o -+obj-y += ast-irq.o -+obj-y += ast-timer.o -diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c -new file mode 100644 -index 000000000000..1852dd3d86e2 ---- /dev/null -+++ b/board/aspeed/ast2600_intel/ast-espi.c -@@ -0,0 +1,298 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+ -+#define AST_LPC_BASE 0x1e6e9000 -+#define AST_ESPI_BASE 0x1e6ee000 -+#define AST_SCU_BASE 0x1e6e2000 -+#define AST_SCU_HW_STRAP2 0x510 -+#define SCU_HW_STRAP_ESPI_ENABLED 0x40 -+ -+#define USE_HW_HANDSHAKE 0 -+#define DEBUG_ESPI_ENABLED 0 -+#if DEBUG_ESPI_ENABLED -+#define DBG_ESPI printf -+#else -+#define DBG_ESPI(...) -+#endif -+ -+/* eSPI controller registers */ -+#define ESPI000 0x000 /* Engine Control. */ -+#define ESPI004 0x004 /* Engine Status. */ -+#define ESPI008 0x008 /* Interrupt Status. */ -+#define ESPI00C 0x00C /* Interrupt Enable. */ -+#define ESPI010 0x010 /* DMA Addr of Peripheral Channel Posted Rx pkt */ -+#define ESPI014 0x014 /* Control of Peripheral Channel Posted Rx pkt. */ -+#define ESPI018 0x018 /* Data port of Peripheral Channel Posted Rx pkt. */ -+#define ESPI020 0x020 /* DMA Addr of Peripheral Channel Posted Tx pkt. */ -+#define ESPI024 0x024 /* Control of Peripheral Channel Posted Tx pkt. */ -+#define ESPI028 0x028 /* Data port of Peripheral Channel Posted Tx pkt. */ -+#define ESPI030 0x030 /* DMA Addr of Peripheral Channel Non-Posted Tx pkt. */ -+#define ESPI034 0x034 /* Control of Peripheral Channel Non-Posted Tx pkt. */ -+#define ESPI038 0x038 /* Data port of Peripheral Channel Non-Posted Tx pkt. */ -+#define ESPI040 0x040 /* DMA Addr of OOB Channel Rx pkt. */ -+#define ESPI044 0x044 /* Control of OOB Channel Rx pkt. */ -+#define ESPI048 0x048 /* Data port of OOB Channel Rx pkt. */ -+#define ESPI050 0x050 /* DMA Addr of OOB Channel Tx pkt. */ -+#define ESPI054 0x054 /* Control of OOB Channel Tx pkt. */ -+#define ESPI058 0x058 /* Data port of OOB Channel Tx pkt. */ -+#define ESPI060 0x060 /* DMA Addr of Flash Channel Rx pkt. */ -+#define ESPI064 0x064 /* Control of Flash Channel Rx pkt. */ -+#define ESPI068 0x068 /* Data port of Flash Channel Rx pkt. */ -+#define ESPI070 0x070 /* DMA Addr of Flash Channel Tx pkt. */ -+#define ESPI074 0x074 /* Control of Flash Channel Tx pkt. */ -+#define ESPI078 0x078 /* Data port of Flash Channel Tx pkt. */ -+#define ESPI080 0x080 /* Engine Control 2. */ -+#define ESPI084 0x084 /* Mapping Src Addr of Peripheral Channel Rx pkt. */ -+#define ESPI088 0x088 /* Mapping Tgt Addr of Peripheral Channel Rx pkt. */ -+#define ESPI08C 0x08C /* Mapping Addr Mask of Peripheral Channel Rx pkt. */ -+#define ESPI090 0x090 /* Mapping Target Addr and Mask of Flash Channel. */ -+#define ESPI094 0x094 /* Interrupt enable of System Event from Master. */ -+#define ESPI098 0x098 /* System Event from and to Master. */ -+#define ESPI09C 0x09C /* GPIO through Virtual Wire Channel. */ -+#define ESPI0A0 0x0A0 /* General Capabilities and Configurations. */ -+#define ESPI0A4 0x0A4 /* Channel 0 Capabilities and Configurations. */ -+#define ESPI0A8 0x0A8 /* Channel 1 Capabilities and Configurations. */ -+#define ESPI0AC 0x0AC /* Channel 2 Capabilities and Configurations. */ -+#define ESPI0B0 0x0B0 /* Channel 3 Capabilities and Configurations. */ -+#define ESPI0B4 0x0B4 /* GPIO Direction of Virtual Wire Channel. */ -+#define ESPI0B8 0x0B8 /* GPIO Selection of Virtual Wire Channel. */ -+#define ESPI0BC 0x0BC /* GPIO Reset Selection of Virtual Wire Channel. */ -+#define ESPI100 0x100 /* Interrupt enable of System Event 1 from Master. */ -+#define ESPI104 0x104 /* System Event 1 from and to Master. */ -+#define ESPI110 0x110 /* Interrupt type 0 of System Event from Master. */ -+#define ESPI114 0x114 /* Interrupt type 1 of System Event from Master. */ -+#define ESPI118 0x118 /* Interrupt type 2 of System Event from Master. */ -+#define ESPI11C 0x11C /* Interrupt status of System Event from Master. */ -+#define ESPI120 0x120 /* Interrupt type 0 of System Event 1 from Master. */ -+#define ESPI124 0x124 /* Interrupt type 1 of System Event 1 from Master. */ -+#define ESPI128 0x128 /* Interrupt type 2 of System Event 1 from Master. */ -+#define ESPI12C 0x12C /* Interrupt status of System Event 1 from Master. */ -+#define ESPICFG004 0x004 /* Device Identification. */ -+#define ESPICFG008 0x008 /* General Capabilities and Configurations. */ -+#define ESPICFG010 0x010 /* Channel 0 Capabilities and Configurations. */ -+#define ESPICFG020 0x020 /* Channel 1 Capabilities and Configurations. */ -+#define ESPICFG030 0x030 /* Channel 2 Capabilities and Configurations. */ -+#define ESPICFG040 0x040 /* Channel 3 Capabilities and Configurations. */ -+#define ESPICFG044 0x044 /* Channel 3 Capabilities and Configurations 2. */ -+#define ESPICFG800 0x800 /* GPIO Direction of Virtual Wire Channel. */ -+#define ESPICFG804 0x804 /* GPIO Selection of Virtual Wire Channel. */ -+#define ESPICFG808 0x808 /* GPIO Reset Selection of Virtual Wire Channel. */ -+#define ESPICFG810 0x810 /* Mapping Src Addr of Peripheral Channel Rx pkt */ -+#define ESPICFG814 0x814 /* Mapping Tgt Addr of Peripheral Channel Rx pkt */ -+#define ESPICFG818 0x818 /* Mapping Addr Mask of Peripheral Channel Rx pkt */ -+ -+/* ESPI000 bits */ -+#define AST_ESPI_OOB_CHRDY BIT(4) -+#define AST_ESPI_FLASH_SW_CHRDY BIT(7) -+#define AST_ESPI_FLASH_SW_READ BIT(10) -+ -+/* ESPI00C bits (Interrupt Enable) */ -+#define AST_ESPI_IEN_HW_RST BIT(31) -+#define AST_ESPI_IEN_SYS1_EV BIT(22) -+#define AST_ESPI_IEN_SYS_EV BIT(8) -+#define AST_ESPI_IEN_GPIO_EV BIT(9) -+ -+/* ESPI008 bits ISR */ -+#define AST_ESPI_VW_SYS_EVT BIT(8) -+#define AST_ESPI_VW_GPIO_EVT BIT(9) -+#define AST_ESPI_VW_SYS_EV1 BIT(22) -+#define AST_ESPI_HW_RST BIT(31) -+ -+/* ESPI080 bits */ -+#define AST_ESPI_AUTO_ACK_HOST_RST_WARN BIT(2) -+#define AST_ESPI_AUTO_ACK_OOB_RST_WARN BIT(1) -+#define AST_ESPI_AUTO_ACK_SUS_WARN BIT(0) -+ -+/* ESPI098 and ESPI11C bits */ -+#define AST_ESPI_OOB_RST_WARN BIT(6) -+#define AST_ESPI_HOST_RST_WARN BIT(8) -+#define AST_ESPI_PLTRSTN BIT(5) -+#define AST_ESPI_OOB_RST_ACK BIT(16) -+#define AST_ESPI_SL_BT_DONE BIT(20) -+#define AST_ESPI_SL_BT_STATUS BIT(23) -+#define AST_ESPI_HOST_RST_ACK BIT(27) -+ -+/* ESPI104 bits */ -+#define AST_ESPI_SUS_WARN BIT(0) -+#define AST_ESPI_SUS_ACK BIT(20) -+ -+/* LPC chip ID */ -+#define SCR0SIO 0x170 -+#define IRQ_SRC_ESPI 74 /* IRQ 74 */ -+ -+static void espi_handshake_ack(void) -+{ -+ /* IRQ only serviced if strapped, so no strap check */ -+ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { -+ DBG_ESPI("Setting espi slave boot done\n"); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | -+ AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } -+ -+ uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104); -+ if (sys1_event & AST_ESPI_SUS_WARN && -+ !(sys1_event & AST_ESPI_SUS_ACK)) { -+ DBG_ESPI("Boot SUS_WARN, evt: 0x%08x\n", sys1_event); -+ writel(sys1_event | AST_ESPI_SUS_ACK, AST_ESPI_BASE + ESPI104); -+ DBG_ESPI("SUS_WARN sent ack\n"); -+ } -+} -+ -+int espi_irq_handler(struct pt_regs *regs) -+{ -+ uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008); -+ -+ DBG_ESPI("espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x,\ -+ ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x,\ -+ ESPI12c=0X%x, irq_status=0x%x\n", -+ readl(AST_ESPI_BASE + ESPI008), -+ readl(AST_ESPI_BASE + ESPI00C), -+ readl(AST_ESPI_BASE + ESPI100), -+ readl(AST_ESPI_BASE + ESPI11C), -+ readl(AST_ESPI_BASE + ESPI094), -+ readl(AST_ESPI_BASE + ESPI12C), irq_status); -+ -+ if (irq_status & AST_ESPI_VW_SYS_EVT) { -+ uint32_t sys_status = readl(AST_ESPI_BASE + ESPI11C); -+ uint32_t sys_event = readl(AST_ESPI_BASE + ESPI098); -+ -+ DBG_ESPI("sys_status : 0x%08X\n", sys_status); -+ if (sys_status & AST_ESPI_HOST_RST_WARN) { -+ DBG_ESPI("HOST_RST_WARN evt: 0x%08X\n", sys_event); -+ if (sys_event & AST_ESPI_HOST_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | -+ AST_ESPI_HOST_RST_ACK; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ DBG_ESPI("HOST_RST_WARN sent ack\n"); -+ } -+ } -+ if (sys_status & AST_ESPI_OOB_RST_WARN) { -+ DBG_ESPI("OOB_RST_WARN evt: 0x%08X\n", sys_event); -+ if (sys_event & AST_ESPI_OOB_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) | -+ AST_ESPI_OOB_RST_ACK; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ DBG_ESPI("OOB_RST_WARN sent ack\n"); -+ } -+ } -+ if (sys_status & AST_ESPI_PLTRSTN) { -+ DBG_ESPI("PLTRSTN: %c, evt: 0x%08X\n", -+ (sys_event & AST_ESPI_PLTRSTN) ? '1' : '0', -+ sys_event); -+ } -+ writel(sys_status, AST_ESPI_BASE + ESPI11C); /* clear status */ -+ } -+ -+ if (irq_status & AST_ESPI_VW_SYS_EV1) { -+ uint32_t sys1_status = readl(AST_ESPI_BASE + ESPI12C); -+ uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104); -+ -+ DBG_ESPI("sys1_status : 0x%08X\n", sys1_status); -+ if (sys1_status & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("SUS WARN evt: 0x%08X\n", sys1_event); -+ if (sys1_event & AST_ESPI_SUS_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | -+ AST_ESPI_SUS_ACK; -+ writel(v, AST_ESPI_BASE + ESPI104); -+ DBG_ESPI("SUS_WARN sent ack\n"); -+ } -+ } -+ writel(sys1_status, AST_ESPI_BASE + ESPI12C); /* clear status */ -+ } -+ -+ if (irq_status & AST_ESPI_HW_RST) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI000) & 0x00ffffffff; -+ writel(v, AST_ESPI_BASE + ESPI000); -+ v |= 0xff000000; -+ writel(v, AST_ESPI_BASE + ESPI000); -+ -+ DBG_ESPI("HW_RESET\n"); -+ -+ espi_handshake_ack(); -+ } -+ -+ writel(irq_status, AST_ESPI_BASE + ESPI008); /* clear irq_status */ -+ -+ DBG_ESPI("end espi_irq_handler, ESPI008=0X%x, ESPI00c=0X%x,\ -+ ESPI100=0X%x, ESPI11c=0X%x, ESPI094=0X%x,\ -+ ESPI12c=0X%x, irq_status=0X%x\n", -+ readl(AST_ESPI_BASE + ESPI008), -+ readl(AST_ESPI_BASE + ESPI00C), -+ readl(AST_ESPI_BASE + ESPI100), -+ readl(AST_ESPI_BASE + ESPI11C), -+ readl(AST_ESPI_BASE + ESPI094), -+ readl(AST_ESPI_BASE + ESPI12C), irq_status); -+ return 0; -+} -+ -+void espi_init(void) -+{ -+ if (!readl(AST_SCU_BASE + AST_SCU_HW_STRAP2) & -+ SCU_HW_STRAP_ESPI_ENABLED) { -+ uint32_t v; -+ -+ DBG_ESPI("espi init\n"); -+ -+ writel(0xff000000, AST_SCU_BASE + 0x454); /* driving strength */ -+ -+ /* Block flash access from Host */ -+ v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_FLASH_SW_CHRDY; -+ v |= AST_ESPI_FLASH_SW_READ | AST_ESPI_OOB_CHRDY; -+ writel(v, AST_ESPI_BASE + ESPI000); -+ -+ /* -+ * Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for -+ * BIOS using in eSPI mode. -+ */ -+ v = readl(AST_LPC_BASE + SCR0SIO) & ~0x000000ff; -+ writel(v, AST_LPC_BASE + SCR0SIO); -+ v = readl(AST_LPC_BASE + SCR0SIO) | 0xa8; -+ writel(v, AST_LPC_BASE + SCR0SIO); -+ -+#if USE_HW_HANDSHAKE -+ v = readl(AST_ESPI_BASE + ESPI098) | -+ AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ -+ return; -+#endif -+ -+ v = readl(AST_ESPI_BASE + ESPI080); -+ v &= ~(AST_ESPI_AUTO_ACK_HOST_RST_WARN | -+ AST_ESPI_AUTO_ACK_OOB_RST_WARN | -+ AST_ESPI_AUTO_ACK_SUS_WARN); -+ writel(v, AST_ESPI_BASE + ESPI080); /* Disable auto H/W ack */ -+ -+ writel(0, AST_ESPI_BASE + ESPI110); -+ writel(0, AST_ESPI_BASE + ESPI114); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN | -+ AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI118); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN | -+ AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI094); -+ -+ writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE + ESPI120); /* int type 0 susp warn */ -+ writel(0, AST_ESPI_BASE + ESPI124); -+ writel(0, AST_ESPI_BASE + ESPI128); -+ writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE + -+ ESPI100); /* Enable sysev1 ints for susp warn */ -+ -+ writel(AST_ESPI_IEN_HW_RST | AST_ESPI_IEN_SYS1_EV | -+ AST_ESPI_IEN_SYS_EV, AST_ESPI_BASE + ESPI00C); -+ -+ irq_install_handler(IRQ_SRC_ESPI, espi_irq_handler, NULL); -+ } else { -+ DBG_ESPI("No espi strap\n"); -+ } -+} -diff --git a/board/aspeed/ast2600_intel/ast-irq.c b/board/aspeed/ast2600_intel/ast-irq.c -new file mode 100644 -index 000000000000..f817f8cd7c81 ---- /dev/null -+++ b/board/aspeed/ast2600_intel/ast-irq.c -@@ -0,0 +1,399 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#define GIC_DISTRIBUTOR_OFFSET 0x1000 -+#define GIC_CPU_OFFSET 0x2000 -+#define GIC_INTERFACE_OFFSET 0x4000 -+#define GIC_VIRT_OFFSET 0x6000 -+ -+#define VIC_STATUS_L 0x80 -+#define VIC_STATUS_H 0x84 -+#define VIC_IRQ_SELECTION_L 0x98 -+#define VIC_IRQ_SELECTION_H 0x9C -+#define VIC_ENABLE_L 0xA0 -+#define VIC_ENABLE_H 0xA4 -+#define VIC_ENABLE_CLEAR_L 0xA8 -+#define VIC_ENABLE_CLEAR_H 0xAC -+#define VIC_INTERRUPT_CLEAR_L 0xD8 -+#define VIC_INTERRUPT_CLEAR_H 0xDC -+ -+#define VIC_CLEAR_ALL (~0) -+ -+/* GIC_DISTRIBUTOR_OFFSET register offsets */ -+#define GICD_CTLR 0x000 -+#define GICD_TYPER 0x004 -+#define GICD_IIDR 0x008 -+#define GICD_IGROUPRn 0x080 -+#define GICD_ISENABLERn 0x100 -+#define GICD_ICENABLERn 0x180 -+#define GICD_ISPENDRn 0x200 -+#define GICD_ICPENDRn 0x280 -+#define GICD_ISACTIVERn 0x300 -+#define GICD_ICACTIVERn 0x380 -+#define GICD_IPRIORITYRn 0x400 -+#define GICD_ITARGETSRn 0x800 -+#define GICD_ICFGRn 0xc00 -+#define GICD_PPISR 0xd00 -+#define GICD_SPISRn 0xd04 -+#define GICD_SGIR 0xf00 -+#define GICD_CPENDINGIRn 0xf10 -+#define GICD_SPENDINGIRn 0xf10 -+#define GICD_PIDR4 0xfd0 -+#define GICD_PIDR5 0xfd4 -+#define GICD_PIDR6 0xfd8 -+#define GICD_PIDR7 0xfdc -+#define GICD_PIDR0 0xfe0 -+#define GICD_PIDR1 0xfe4 -+#define GICD_PIDR2 0xfe8 -+#define GICD_PIDR3 0xfec -+#define GICD_CIDR0 0xff0 -+#define GICD_CIDR1 0xff4 -+#define GICD_CIDR2 0xff8 -+#define GICD_CIDR3 0xffc -+ -+#define GIC_DISTRIBUTOR_IMPLEMENTER_MAGIC 0x0100143b -+ -+/* GIC_CPU_OFFSET register offsets */ -+#define GICC_CTLR 0x0000 -+#define GICC_PMRn 0x0004 -+#define GICC_BPR 0x0008 -+#define GICC_IAR 0x000c -+#define GICC_EOIR 0x0010 -+#define GICC_RPR 0x0014 -+#define GICC_HPPIR 0x0018 -+#define GICC_ABPR 0x001c -+#define GICC_AIAR 0x0020 -+#define GICC_AEOIR 0x0024 -+#define GICC_AHPPIR 0x0028 -+#define GICC_APR0 0x00d0 -+#define GICC_NSAPR0 0x00e0 -+#define GICC_IIDR 0x00fc -+#define GICC_DIR 0x1000 -+ -+#define GIC_CPU_IMPLEMENTER_MAGIC 0x0102143b -+ -+/* GIC_INTERFACE_OFFSET register offsets */ -+#define GICH_HCR 0x000 -+#define GICH_VTR 0x004 -+#define GICH_VMCR 0x008 -+#define GICH_MISR 0x010 -+#define GICH_EISR0 0x020 -+#define GICH_ELSR0 0x020 -+#define GICH_APR0 0x0f0 -+#define GICH_LR0 0x100 -+#define GICH_LR1 0x104 -+#define GICH_LR2 0x108 -+#define GICH_LR3 0x10c -+ -+/* GIC_VIRT_OFFSET register offsets */ -+#define GICV_CTLR 0x0000 -+#define GICV_PMR 0x0004 -+#define GICV_BPR 0x0008 -+#define GICV_IAR 0x000c -+#define GICV_EOIR 0x0010 -+#define GICV_RPR 0x0014 -+#define GICV_HPPIR 0x0018 -+#define GICV_ABPR 0x001c -+#define GICV_AIAR 0x0020 -+#define GICV_AEOIR 0x0024 -+#define GICV_AHPPIR 0x0028 -+#define GICV_APR0 0x00d0 -+#define GICV_NSAPR0 0x00e0 -+#define GICV_IIDR 0x00fc -+#define GICV_DIR 0x1000 -+ -+#define GIC_VIRT_CPU_IMPLEMENTER_MAGIC 0x0102143b -+ -+#define GICD_CTLR_ENABLE 0x03 -+ -+#define GICD_INT_DEF_PRI 0xa0 -+#define GICD_INT_DEF_PRI_X4 (\ -+ (GICD_INT_DEF_PRI << 24) |\ -+ (GICD_INT_DEF_PRI << 16) |\ -+ (GICD_INT_DEF_PRI << 8) |\ -+ GICD_INT_DEF_PRI) -+ -+#define GICD_INT_ACTLOW_LVLTRIG 0 -+#define GICD_INT_EN_CLR_X32 0xffffffff -+#define GICD_INT_EN_CLR_PPI 0xffff0000 -+#define GICD_INT_EN_SET_SGI 0x0000ffff -+ -+#define gicd_readl(OFFSET) readl(gbase + GIC_DISTRIBUTOR_OFFSET + (OFFSET)) -+#define gicd_writel(VALUE, OFFSET) \ -+ writel((VALUE), gbase + GIC_DISTRIBUTOR_OFFSET + (OFFSET)) -+#define gicc_readl(OFFSET) readl(gbase + GIC_CPU_OFFSET + (OFFSET)) -+#define gich_readl(OFFSET) readl(gbase + GIC_INTERFACE_OFFSET + (OFFSET)) -+#define gicv_readl(OFFSET) readl(gbase + GIC_VIRT_OFFSET + (OFFSET)) -+ -+static size_t max_irq = 0; -+ -+#define ITLINES_MASK 0x1f -+#define ITLINES_SHIFT 5 -+ -+#define GIC_MAX_IRQ 1020 -+static interrupt_handler_t *handlers[GIC_MAX_IRQ] = {NULL}; -+static unsigned long irq_total = 0; -+static unsigned long irq_counts[GIC_MAX_IRQ] = {0}; -+static uint32_t gbase = 0; -+ -+/* TODO: This, hard-coded, or from dts? */ -+static inline uint32_t gic_base(void) -+{ -+ uint32_t base; -+ /* read the base address of the private peripheral space */ -+ __asm__ __volatile__("mrc p15, 4, %r0, c15, c0, 0\n\t" : "=r"(base) : ); -+ return base; -+} -+ -+static void enable_gic(void) -+{ -+ uint32_t gicd_ctlr; -+ -+ /* add GIC offset ref table 1-3 for interrupt distributor address */ -+ gicd_ctlr = gicd_readl(GICD_CTLR); -+ gicd_writel(gicd_ctlr | GICD_CTLR_ENABLE, GICD_CTLR); -+} -+ -+static void disable_gic(void) -+{ -+ uint32_t gicd_ctlr; -+ -+ /* add GIC offset ref table 1-3 for interrupt distributor address */ -+ gicd_ctlr = gicd_readl(GICD_CTLR); -+ gicd_writel(gicd_ctlr & ~GICD_CTLR_ENABLE, GICD_CTLR); -+} -+ -+static void enable_irq_id(unsigned int id) -+{ -+ uint32_t grp = id >> ITLINES_SHIFT; -+ uint32_t grp_bit = 1 << (id & ITLINES_MASK); -+ gicd_writel(grp_bit, GICD_ISENABLERn + grp * sizeof(uint32_t)); -+} -+ -+static void disable_irq_id(unsigned int id) -+{ -+ uint32_t grp = id >> ITLINES_SHIFT; -+ uint32_t grp_bit = 1 << (id & ITLINES_MASK); -+ gicd_writel(grp_bit, GICD_ICENABLERn + grp * sizeof(uint32_t)); -+} -+ -+static int gic_probe(void) -+{ -+ int i; -+ gbase = gic_base(); -+ enable_gic(); -+ -+ if (gicd_readl(GICD_IIDR) != GIC_DISTRIBUTOR_IMPLEMENTER_MAGIC && -+ gicc_readl(GICC_IIDR) != GIC_CPU_IMPLEMENTER_MAGIC && -+ gicv_readl(GICV_IIDR) != GIC_VIRT_CPU_IMPLEMENTER_MAGIC) -+ { -+ return 0; -+ } -+ /* GIC supports up to 1020 lines */ -+ max_irq = ((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) << ITLINES_SHIFT; -+ if (max_irq > GIC_MAX_IRQ) -+ max_irq = GIC_MAX_IRQ; -+ /* set all lines to be level triggered N-N */ -+ for (i = 32; i < max_irq; i += 16) -+ gicd_writel(0, GICD_ICFGRn + i / 4); -+ -+ /* Set priority on all interrupts. */ -+ for (i = 0; i < max_irq; i += 4) -+ gicd_writel(GICD_INT_DEF_PRI_X4, GICD_IPRIORITYRn + i); -+ -+ /* Deactivate and disable all SPIs. */ -+ for (i = 32; i < max_irq; i += 32) { -+ gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn + i / 8); -+ gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICENABLERn + i / 8); -+ } -+ gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn); -+ gicd_writel(GICD_INT_EN_CLR_PPI, GICD_ICENABLERn); -+ gicd_writel(GICD_INT_EN_SET_SGI, GICD_ISENABLERn); -+ -+ return 0; -+} -+ -+void irq_free_handler (int irq); -+static void gic_shutdown(void) -+{ -+ int i; -+ for (i = 0; i < max_irq; i++) -+ { -+ irq_free_handler(i); -+ } -+ disable_gic(); -+} -+ -+int arch_interrupt_init_early(void) -+{ -+ return 0; -+} -+ -+int arch_interrupt_init(void) -+{ -+ int i; -+ for (i = 0; i < GIC_MAX_IRQ; i++) -+ { -+ handlers[i] = NULL; -+ irq_counts[i] = 0; -+ } -+ return gic_probe(); -+} -+ -+int arch_interrupt_fini(void) -+{ -+ gic_shutdown(); -+ return 0; -+} -+ -+int interrupt_init (void) -+{ -+ /* -+ * setup up stacks if necessary -+ */ -+ IRQ_STACK_START_IN = gd->irq_sp + 8; -+ -+ printf("%s()\n", __FUNCTION__); -+ return arch_interrupt_init(); -+ -+ return 0; -+} -+ -+int global_interrupts_enabled (void) -+{ -+ unsigned long cpsr; -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ : "=r" (cpsr) -+ : -+ : "memory"); -+ -+ return (cpsr & 0x80) == 0; -+} -+ -+void enable_interrupts (void) -+{ -+ unsigned long cpsr; -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "bic %0, %0, #0x80\n" -+ "msr cpsr_c, %0" -+ : "=r" (cpsr) -+ : -+ : "memory"); -+ -+ return; -+} -+ -+int disable_interrupts (void) -+{ -+ unsigned long cpsr, temp; -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (cpsr), "=r" (temp) -+ : -+ : "memory"); -+ return (cpsr & 0x80) == 0; -+} -+ -+void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx) -+{ -+ if (irq > max_irq) { -+ printf("irq %d out of range\n", irq); -+ return; -+ } -+ if (handlers[irq]) { -+ printf("irq %d already in use (%p)\n", irq, handlers[irq]); -+ return; -+ } -+ printf("registering handler for irq %d\n", irq); -+ handlers[irq] = handler; -+ enable_irq_id(irq); -+} -+ -+void irq_free_handler (int irq) -+{ -+ if (irq >= max_irq) { -+ printf("irq %d out of range\n", irq); -+ return; -+ } -+ if (handlers[irq]) { -+ handlers[irq] = NULL; -+ disable_irq_id(irq); -+ } -+} -+ -+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -+{ -+ int i; -+ int enabled = global_interrupts_enabled(); -+ printf("GIC base = 0x%x\n", gbase); -+ printf("interrupts %sabled\n", (enabled ? "en" : "dis")); -+ uint32_t grp_en = 0; -+ for (i = 0; i < max_irq; i++) { -+ if ((i & ITLINES_MASK) == 0) -+ grp_en = gicd_readl(GICD_ISENABLERn + -+ (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -+ int irq_enabled = grp_en & (1 << (i & ITLINES_MASK)); -+ if (!irq_enabled) -+ continue; -+ printf("% 2i (% 3s): %lu\n", i, -+ (irq_enabled ? "on" : "off"), irq_counts[i]); -+ } -+ printf("total: %lu\n", irq_total); -+ return 0; -+} -+ -+void do_irq(struct pt_regs *pt_regs) -+{ -+ int i; -+ if (!gbase) { -+ static int printed_msg = 0; -+ if (!printed_msg) -+ { -+ printed_msg = 1; -+ printf("interrupt before configured!\n"); -+ } -+ return; -+ } -+ irq_total++; -+ uint32_t grp_pend = 0; -+ for (i = 0; i < max_irq; i++) { -+ /* limit reads of the pending register to once in 32 */ -+ if ((i & ITLINES_MASK) == 0) -+ grp_pend = gicd_readl(GICD_ISPENDRn + -+ (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -+ uint32_t pending = grp_pend & (1 << (i & ITLINES_MASK)); -+ if (pending) { -+ irq_counts[i]++; -+ /* mask via GICD_ICENABLERn */ -+ gicd_writel(pending, GICD_ICENABLERn + -+ (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -+ if (handlers[i]) { -+ handlers[i](pt_regs); -+ /* unmask via GICD_ISENABLERn */ -+ gicd_writel(pending, GICD_ISENABLERn + -+ (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -+ /* clear pending via GICD_ICPENDRn */ -+ gicd_writel(pending, GICD_ICPENDRn + -+ (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -+ } else { -+ printf("unexpected interrupt %i; masking\n", i); -+ /* clear pending via GICD_ICPENDRn */ -+ gicd_writel(pending, GICD_ISPENDRn + -+ (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -+ } -+ } -+ } -+} -diff --git a/board/aspeed/ast2600_intel/ast-irq.h b/board/aspeed/ast2600_intel/ast-irq.h -new file mode 100644 -index 000000000000..9957f2baa7ff ---- /dev/null -+++ b/board/aspeed/ast2600_intel/ast-irq.h -@@ -0,0 +1,8 @@ -+#ifndef _AST_IRQ_H_ -+#define _AST_IRQ_H_ -+ -+int request_irq(int irq, interrupt_handler_t *handler); -+int release_irq(int irq); -+int arch_interrupt_init_early(void); -+ -+#endif -diff --git a/board/aspeed/ast2600_intel/ast-timer.c b/board/aspeed/ast2600_intel/ast-timer.c -new file mode 100644 -index 000000000000..cf8c69aba5d3 ---- /dev/null -+++ b/board/aspeed/ast2600_intel/ast-timer.c -@@ -0,0 +1,59 @@ -+/* -+ * Copyright 2019 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+ -+static const int timer_irqs[] = {48, 49, 50, 51, 52, 53, 54, 55}; -+#define AST_TIMER_BASE 0x1e782000 -+/* offsets from AST_TIMER_BASE for each timer */ -+static const uint32_t timer_bases[] = {0, 0x10, 0x20, 0x40, -+ 0x50, 0x60, 0x70, 0x80}; -+#define TIMER_1MHZ_CLK_COUNT 1000000u -+#define TIMER_ENABLE 1 -+#define TIMER_1MHZ_CLK_SEL 2 -+#define TIMER_ENABLE_IRQ 4 -+#define TIMER_RESET_BY_WDT 8 -+#define TIMER_CONTROL 0x30 -+#define TIMER_RELOAD 0x04 -+#define TIMER_CONTROL_CLEAR 0x3c -+ -+void timer_disable(int n) -+{ -+ if (n < 0 || n > 7) { -+ return; -+ } -+ uint32_t tctrl = 0xf << (n * 4); -+ writel(tctrl, AST_TIMER_BASE + TIMER_CONTROL_CLEAR); -+} -+ -+void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler) -+{ -+ if (n < 0 || n > 7) { -+ return; -+ } -+ if (!freq) -+ return; -+ -+ timer_disable(n); -+ -+ uint32_t v = TIMER_1MHZ_CLK_COUNT / freq; -+ writel(v, AST_TIMER_BASE + timer_bases[n] + TIMER_RELOAD); -+ -+ uint32_t tctrl = ( -+ TIMER_ENABLE | -+ TIMER_1MHZ_CLK_SEL | -+ TIMER_RESET_BY_WDT) << (n * 4); -+ -+ if (handler) { -+ irq_install_handler(timer_irqs[n], handler, NULL); -+ tctrl |= (TIMER_ENABLE_IRQ << (n * 4)); -+ } -+ writel(tctrl, AST_TIMER_BASE + TIMER_CONTROL); -+} -diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -new file mode 100644 -index 000000000000..a02e246d0d81 ---- /dev/null -+++ b/board/aspeed/ast2600_intel/intel.c -@@ -0,0 +1,177 @@ -+/* Intel customizations of Das U-Boot */ -+#include -+#include -+#include -+ -+/* use GPIOC0 on intel boards */ -+#define FFUJ_GPIO "gpio@1e78000016" -+ -+int read_ffuj(void) -+{ -+ struct gpio_desc desc; -+ int ret; -+ -+ ret = dm_gpio_lookup_name(FFUJ_GPIO, &desc); -+ if (ret) -+ return ret; -+ ret = dm_gpio_request(&desc, "ffuj"); -+ if (ret) -+ return ret; -+ ret = dm_gpio_set_dir_flags(&desc, GPIOD_ACTIVE_LOW); -+ if (ret) -+ return ret; -+ ret = dm_gpio_get_value(&desc); -+ dm_gpio_free(desc.dev, &desc); -+ return ret; -+} -+ -+/* gpio_abort is a weak symbol in common/autoboot.c */ -+int gpio_abort(void) -+{ -+ int value; -+ /* check ffuj to abort the autoboot */ -+ value = read_ffuj(); -+ printf("FFUJ: %d\n", value); -+ return value <= 0 ? 0 : 1; -+} -+ -+#define SCU_BASE 0x1E6E2000 -+int misc_init_r(void) -+{ -+ /* This is called near the end of the _r init sequence */ -+ -+ return 0; -+} -+ -+static void gpio_passthru_init(void) -+{ -+ /* FIXME: do this without the hard-coded SCU values */ -+ /* enable passthru gpio (for now) */ -+ writel(0x0f000000, 0x1e6e24bc); -+ writel(0xc0000060, 0x1e6e2418); -+} -+ -+#define AST_LPC_BASE 0x1e789000 -+#define LPC_SNOOP_ADDR 0x80 -+#define HICR5 0x080 /* Host Interface Control Register 5 */ -+#define HICR6 0x084 /* Host Interface Control Register 6 */ -+#define SNPWADR 0x090 /* LPC Snoop Address Register */ -+#define HICRB 0x100 /* Host Interface Control Register B */ -+ -+/* HICR5 Bits */ -+#define HICR5_EN_SIOGIO (1 << 31) /* Enable SIOGIO */ -+#define HICR5_EN80HGIO (1 << 30) /* Enable 80hGIO */ -+#define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */ -+#define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */ -+#define HICR5_UNKVAL_MASK 0x1FFF0000 /* Bits with unknown values on reset */ -+#define HICR5_ENINT_SNP0W (1 << 1) /* Enable Snooping address 0 */ -+#define HICR5_EN_SNP0W (1 << 0) /* Enable Snooping address 0 */ -+ -+/* HRCR6 Bits */ -+#define HICR6_STR_SNP0W (1 << 0) /* Interrupt Status Snoop address 0 */ -+#define HICR6_STR_SNP1W (1 << 1) /* Interrupt Status Snoop address 1 */ -+ -+/* HICRB Bits */ -+#define HICRB_EN80HSGIO (1 << 13) /* Enable 80hSGIO */ -+ -+static void port80h_snoop_init(void) -+{ -+ uint32_t value; -+ /* enable port80h snoop and sgpio */ -+ /* set lpc snoop #0 to port 0x80 */ -+ value = readl(AST_LPC_BASE + SNPWADR) & 0xffff0000; -+ writel(value | LPC_SNOOP_ADDR, AST_LPC_BASE + SNPWADR); -+ -+ /* clear interrupt status */ -+ value = readl(AST_LPC_BASE + HICR6); -+ value |= HICR6_STR_SNP0W | HICR6_STR_SNP1W; -+ writel(value, AST_LPC_BASE + HICR6); -+ -+ /* enable lpc snoop #0 and SIOGIO */ -+ value = readl(AST_LPC_BASE + HICR5) & ~(HICR5_UNKVAL_MASK); -+ value |= HICR5_EN_SIOGIO | HICR5_EN_SNP0W; -+ writel(value, AST_LPC_BASE + HICR5); -+ -+ /* enable port80h snoop on SGPIO */ -+ value = readl(AST_LPC_BASE + HICRB) | HICRB_EN80HSGIO; -+ writel(value, AST_LPC_BASE + HICRB); -+} -+ -+#define AST_GPIO_BASE 0x1e780000 -+ -+static void sgpio_init(void) -+{ -+#define SGPIO_CLK_DIV(N) ((N) << 16) -+#define SGPIO_BYTES(N) ((N) << 6) -+#define SGPIO_ENABLE 1 -+#define GPIO554 0x554 -+#define SCU_414 0x414 /* Multi-function Pin Control #5 */ -+#define SCU_414_SGPM_MASK GENMASK(27, 24) -+ -+ uint32_t value; -+ /* set the sgpio clock to pclk/(2*(5+1)) or ~2 MHz */ -+ value = SGPIO_CLK_DIV(256) | SGPIO_BYTES(10) | SGPIO_ENABLE; -+ writel(value, AST_GPIO_BASE + GPIO554); -+ writel(readl(SCU_BASE | SCU_414) | SCU_414_SGPM_MASK, -+ SCU_BASE | SCU_414); -+} -+ -+void espi_init(void); -+int arch_interrupt_init_early(void); -+ -+static void timer_handler(void *regs) -+{ -+ printf("+"); -+} -+ -+void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler); -+int board_early_init_f(void) -+{ -+ /* This is called before relocation; beware! */ -+ /* initialize running timer? timer_init is next in the list but -+ * I am not sure if it actually does anything... */ -+ arch_interrupt_init_early(); -+ -+ gpio_passthru_init(); -+ -+ port80h_snoop_init(); -+ -+ sgpio_init(); -+ -+ /* TODO: is it too late to enforce HW security registers? */ -+ return 0; -+} -+ -+int board_early_init_r(void) -+{ -+ debug("board_early_init_r\n"); -+ /* timer_enable(0, 1, timer_handler); */ -+ -+ espi_init(); -+ -+ return 0; -+} -+ -+/* aspeed/board.c defines these functions -+int arch_early_init_r(void) -+{ -+ return 0; -+} -+*/ -+ -+/* -+void board_init(void) -+{ -+} -+*/ -+ -+#ifdef CONFIG_WATCHDOG -+/* watchdog stuff */ -+void watchdog_init(void) -+{ -+} -+ -+void watchdog_reset(void) -+{ -+} -+#endif -diff --git a/cmd/Kconfig b/cmd/Kconfig -index d5aa204290bd..89f6668b788e 100644 ---- a/cmd/Kconfig -+++ b/cmd/Kconfig -@@ -1876,7 +1876,7 @@ config CMD_DIAG - - config CMD_IRQ - bool "irq - Show information about interrupts" -- depends on !ARM && !MIPS && !SH -+ depends on !MIPS && !SH - help - This enables two commands: - -diff --git a/common/autoboot.c b/common/autoboot.c -index 94133eaeda78..5e69000b848b 100644 ---- a/common/autoboot.c -+++ b/common/autoboot.c -@@ -255,10 +255,20 @@ static int __abortboot(int bootdelay) - } - # endif /* CONFIG_AUTOBOOT_KEYED */ - -+int gpio_abort(void) __attribute__((weak)); -+int gpio_abort(void) -+{ -+ return 0; -+} -+ - static int abortboot(int bootdelay) - { - int abort = 0; - -+ abort = gpio_abort(); -+ if (abort) -+ return abort; -+ - if (bootdelay >= 0) - abort = __abortboot(bootdelay); - --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-flash-use-readX-writeX-not-udelay.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-flash-use-readX-writeX-not-udelay.patch deleted file mode 100644 index 73ab78a65..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-flash-use-readX-writeX-not-udelay.patch +++ /dev/null @@ -1,424 +0,0 @@ -Index: u-boot/arch/arm/mach-aspeed/flash.c -=================================================================== ---- u-boot.orig/arch/arm/mach-aspeed/flash.c -+++ u-boot/arch/arm/mach-aspeed/flash.c -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -199,7 +200,7 @@ static void reset_flash (flash_info_t * - if (info->dualport) - ulCtrlData |= 0x08; - #endif -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - } - -@@ -228,28 +229,22 @@ static void enable_write (flash_info_t * - - ulCtrlData = (info->tCK_Write << 8); - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x06); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x06, base); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x05); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x05, base); - do { -- jReg = *(volatile uchar *) (base); -+ jReg = readb(base); - } while (!(jReg & 0x02)); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - } - -@@ -280,30 +275,23 @@ static void write_status_register (flash - - ulCtrlData = (info->tCK_Write << 8); - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x01); -- udelay(10); -- *(uchar *) (base) = (uchar) (data); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x01, base); -+ writeb(data, base); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x05); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x05, base); - do { -- jReg = *(volatile uchar *) (base); -+ jReg = readb(base); - } while (jReg & 0x01); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - } - - static void enable4b (flash_info_t * info) -@@ -330,13 +318,11 @@ static void enable4b (flash_info_t * inf - - ulCtrlData = (info->tCK_Write << 8); - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0xb7); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0xb7, base); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - } /* enable4b */ - -@@ -366,29 +352,23 @@ static void enable4b_spansion (flash_inf - /* Enable 4B: BAR0 D[7] = 1 */ - ulCtrlData = (info->tCK_Write << 8); - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x17); -- udelay(10); -- *(uchar *) (base) = (uchar) (0x80); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x17, base); -+ writeb(0x80, base); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x16); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x16, base); - do { -- jReg = *(volatile uchar *) (base); -+ jReg = readb(base); - } while (!(jReg & 0x80)); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - } /* enable4b_spansion */ - -@@ -420,14 +400,11 @@ static void enable4b_numonyx (flash_info - /* Enable 4B: CMD:0xB7 */ - ulCtrlData = (info->tCK_Write << 8); - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0xB7); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0xB7, base); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - } /* enable4b_numonyx */ - -@@ -463,63 +440,49 @@ static void flash_write_buffer (flash_in - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x02); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x02, base); - if (info->address32) - { -- *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24); -- udelay(10); -+ writeb((uchar) ((offset & 0xff000000) >> 24), base); - } -- *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16); -- udelay(10); -- *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8); -- udelay(10); -- *(uchar *) (base) = (uchar) ((offset & 0x0000ff)); -- udelay(10); -+ writeb((uchar) ((offset & 0xff0000) >> 16), base); -+ writeb((uchar) ((offset & 0x00ff00) >> 8), base); -+ writeb((uchar) ((offset & 0x0000ff)), base); - - for (j=0; jreg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x05); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x05, base); - do { -- jReg = *(volatile uchar *) (base); -+ jReg = readb(base); - } while ((jReg & 0x01)); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - /* RFSR */ - if (info->specificspi == SpecificSPI_N25Q512) - { - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x70); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x70, base); - do { -- jReg = *(volatile uchar *) (base); -+ jReg = readb(base); - } while (!(jReg & 0x80)); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - } - } - -@@ -603,57 +566,44 @@ int flash_erase (flash_info_t * info, in - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0xd8); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0xd8, base); - if (info->address32) - { -- *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24); -- udelay(10); -+ writeb((uchar) ((offset & 0xff000000) >> 24), base); - } -- *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16); -- udelay(10); -- *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8); -- udelay(10); -- *(uchar *) (base) = (uchar) ((offset & 0x0000ff)); -- udelay(10); -+ writeb((uchar) ((offset & 0xff0000) >> 16), base); -+ writeb((uchar) ((offset & 0x00ff00) >> 8), base); -+ writeb((uchar) ((offset & 0x0000ff)), base); - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x05); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x05, base); - do { -- jReg = *(volatile uchar *) (base); -+ jReg = readb(base); - } while ((jReg & 0x01)); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - - /* RFSR */ - if (info->specificspi == SpecificSPI_N25Q512) - { - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (base) = (uchar) (0x70); -- udelay(10); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x70, base); - do { -- jReg = *(volatile uchar *) (base); -+ jReg = readb(base); - } while (!(jReg & 0x80)); - ulCtrlData &= CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - } - - putc ('.'); -@@ -764,22 +714,16 @@ static ulong flash_get_size (ulong base, - } - - /* Get Flash ID */ -- ulCtrlData = *(ulong *) (info->reg_base + CtrlOffset) & CMD_MASK; -+ ulCtrlData = readl(info->reg_base + CtrlOffset) & CMD_MASK; - ulCtrlData |= CE_LOW | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -- *(uchar *) (vbase) = (uchar) (0x9F); -- udelay(10); -- ch[0] = *(volatile uchar *)(vbase); -- udelay(10); -- ch[1] = *(volatile uchar *)(vbase); -- udelay(10); -- ch[2] = *(volatile uchar *)(vbase); -- udelay(10); -- ulCtrlData = *(ulong *) (info->reg_base + CtrlOffset) & CMD_MASK; -+ writel(ulCtrlData, info->reg_base + CtrlOffset); -+ writeb(0x9F, vbase); -+ ch[0] = readb(vbase); -+ ch[1] = readb(vbase); -+ ch[2] = readb(vbase); -+ ulCtrlData = readl(info->reg_base + CtrlOffset) & CMD_MASK; - ulCtrlData |= CE_HIGH | USERMODE; -- *(ulong *) (info->reg_base + CtrlOffset) = ulCtrlData; -- udelay(200); -+ writel(ulCtrlData, info->reg_base + CtrlOffset); - ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ; - info->flash_id = ulID; - -@@ -1294,13 +1238,13 @@ static ulong flash_get_size (ulong base, - - if (info->address32) { - #ifndef AST_SOC_G5 -- reg = *((volatile ulong*) 0x1e6e2070); /* set H/W Trappings */ -+ reg = readl(0x1e6e2070); /* set H/W Trappings */ - reg |= 0x10; -- *((volatile ulong*) 0x1e6e2070) = reg; -+ writel(reg, 0x1e6e2070); - #endif -- reg = *((volatile ulong*) (info->reg_base + 0x4)); /* enable 32b control bit*/ -+ reg = readl(info->reg_base + 0x4); /* enable 32b control bit*/ - reg |= (0x01 << info->CE); -- *((volatile ulong*) (info->reg_base + 0x4)) = reg; -+ writel(reg, info->reg_base + 0x4); - - /* set flash chips to 32bits addressing mode */ - if ((info->flash_id & 0xFF) == 0x01) /* Spansion */ -@@ -1322,7 +1266,7 @@ unsigned long flash_init (void) - unsigned long size = 0; - int i; - -- *((volatile ulong*) AST_FMC_BASE) |= 0x800f0000; /* enable Flash Write */ -+ writel(readl(AST_FMC_BASE) | 0x800f0000, AST_FMC_BASE); /* enable Flash Write */ - - /* Init: FMC */ - /* BANK 0 : FMC CS0 , 1: FMC CS1, */ -@@ -1352,7 +1296,7 @@ unsigned long flash_init (void) - #ifdef CONFIG_SPI0_CS - //pin switch by trap[13:12] -- [0:1] Enable SPI Master - ast_scu_spi_master(1); /* enable SPI master */ -- *((volatile ulong*) AST_FMC_SPI0_BASE) |= 0x10000; /* enable Flash Write */ -+ writel(readl(AST_FMC_SPI0_BASE) | 0x10000, AST_FMC_SPI0_BASE); /* enable Flash Write */ - flash_info[CONFIG_FMC_CS].sysspi = 1; - flash_info[CONFIG_FMC_CS].reg_base = AST_FMC_SPI0_BASE; - flash_info[CONFIG_FMC_CS].flash_id = FLASH_UNKNOWN; -@@ -1403,21 +1347,24 @@ void memmove_dma(void * dest,const void - poll_time = 100; /* set 100 us as default */ - - /* force end of burst read */ -- *(volatile ulong *) (AST_FMC_BASE + CS0_CTRL) |= CE_HIGH; -- *(volatile ulong *) (AST_FMC_BASE + CS0_CTRL) &= ~CE_HIGH; -- -- *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE); -- *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_FLASH_BASE) = (ulong) (src); -- *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_DRAM_BASE) = (ulong) (dest); -- *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_LENGTH) = (ulong) (count_align); -- *(ulong *) (AST_FMC_BASE + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE); -+ data = readl(AST_FMC_BASE + CS0_CTRL); -+ writel(data | CE_HIGH, AST_FMC_BASE + CS0_CTRL); -+ writel(data & ~CE_HIGH, AST_FMC_BASE + CS0_CTRL); -+ -+ writel(~FLASH_DMA_ENABLE, AST_FMC_BASE + REG_FLASH_DMA_CONTROL); -+ writel((ulong)src, AST_FMC_BASE + REG_FLASH_DMA_FLASH_BASE); -+ writel((ulong)dest, AST_FMC_BASE + REG_FLASH_DMA_DRAM_BASE); -+ writel(count_align, AST_FMC_BASE + REG_FLASH_DMA_LENGTH); -+ writel(FLASH_DMA_ENABLE, AST_FMC_BASE + REG_FLASH_DMA_CONTROL); - - /* wait poll */ - do { - udelay(poll_time); -- data = *(ulong *) (AST_FMC_BASE + REG_FLASH_INTERRUPT_STATUS); -+ data = readl(AST_FMC_BASE + REG_FLASH_INTERRUPT_STATUS); - } while (!(data & FLASH_STATUS_DMA_READY)); - - /* clear status */ -- *(ulong *) (AST_FMC_BASE + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR; -+ data = readl(AST_FMC_BASE + REG_FLASH_INTERRUPT_STATUS); -+ writel(data | FLASH_STATUS_DMA_CLEAR, -+ AST_FMC_BASE + REG_FLASH_INTERRUPT_STATUS); - } diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch deleted file mode 100644 index 8937047c5..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0002-intel-layout-environment-addr.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 7979a73fba832747ed3c037c0b47c9e67dcf283e Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Mon, 30 Apr 2018 10:52:37 -0700 - ---- - common/board_r.c | 8 ++++++-- - include/configs/ast-common.h | 9 ++++++--- - 2 files changed, 12 insertions(+), 5 deletions(-) - -diff --git a/common/board_r.c b/common/board_r.c -index d959ad3..74797ed 100644 ---- a/common/board_r.c -+++ b/common/board_r.c -@@ -494,10 +494,14 @@ static int should_load_env(void) - static int initr_env(void) - { - /* initialize environment */ -- if (should_load_env()) -+ if (should_load_env()) { -+ /* try again, in case the environment failed to load the first time */ -+ if (!gd->env_valid) -+ env_init(); - env_relocate(); -- else -+ } else { - set_default_env(NULL); -+ } - #ifdef CONFIG_OF_CONTROL - setenv_addr("fdtcontroladdr", gd->fdt_blob); - #endif -diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h -index eff6d2b..b7d7192 100644 ---- a/include/configs/ast-common.h -+++ b/include/configs/ast-common.h -@@ -103,10 +103,13 @@ - #define CONFIG_SYS_MAX_FLASH_BANKS (CONFIG_FMC_CS) - #define CONFIG_SYS_MAX_FLASH_SECT (8192) /* max number of sectors on one chip */ - #define CONFIG_ENV_IS_IN_FLASH 1 --#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + 0x60000) -+#define CONFIG_ENV_OFFSET 0x2400000 /* environment starts here */ -+#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) -+#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - --#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */ --#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -+#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET_REDUND) -+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - - #define CONFIG_BOOTCOMMAND "bootm 20080000" - #define CONFIG_ENV_OVERWRITE diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch deleted file mode 100644 index 326f36df1..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 3195e1ec2d772d5e4c16ae5b60c294086cfc17be Mon Sep 17 00:00:00 2001 -From: Kuiying Wang -Date: Thu, 12 Dec 2019 12:54:18 +0800 -Subject: [PATCH] ast2600: intel-layout-environment-addr - -Tested: -Both kernel and u-boot work at the area /dev/mtd/u-boot-env - -Signed-off-by: Kuiying Wang -Signed-off-by: Jae Hyun Yoo ---- - common/board_r.c | 13 ++++++++++--- - include/configs/aspeed-common.h | 11 ++++++++++- - 2 files changed, 20 insertions(+), 4 deletions(-) - -diff --git a/common/board_r.c b/common/board_r.c -index 472987d5d52f..b665d0e30262 100644 ---- a/common/board_r.c -+++ b/common/board_r.c -@@ -433,10 +433,17 @@ static int should_load_env(void) - static int initr_env(void) - { - /* initialize environment */ -- if (should_load_env()) -- env_relocate(); -- else -+ if (should_load_env()) { -+ /* -+ * try again, in case the environment failed to load the first -+ * time -+ */ -+ if (!gd->env_valid) -+ env_init(); -+ env_relocate(); -+ } else { - set_default_env(NULL, 0); -+ } - #ifdef CONFIG_OF_CONTROL - env_set_hex("fdtcontroladdr", - (unsigned long)map_to_sysmem(gd->fdt_blob)); -diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h -index cdbffc97a223..6065ec58db0a 100644 ---- a/include/configs/aspeed-common.h -+++ b/include/configs/aspeed-common.h -@@ -65,9 +65,18 @@ - #endif - - #ifndef CONFIG_ENV_OFFSET --#define CONFIG_ENV_OFFSET 0xF0000 -+#define CONFIG_ENV_OFFSET 0x2400000 - #endif - -+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -+#define CONFIG_ENV_OVERWRITE -+ -+#define AST_FMC_CS0_BASE 0x20000000 /* CS0 */ -+#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) -+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -+#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET_REDUND) -+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -+ - #define CONFIG_ENV_SECT_SIZE (4 << 10) - - /* --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch deleted file mode 100644 index 950382544..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 8dfc080bafc688ccdb3253eff79b72ad72f93761 Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo -Date: Fri, 3 Jan 2020 15:14:09 -0800 -Subject: [PATCH] AST2600: Adjust default GPIO settings - -- Disable GPIOC3 to prevent unexpected host failures. -- Fixed GPIOC5, GPIOG6, GPIOI0~7 and GPIOL6~7 directions and - default values. -- Disabled internal pull-down of GPIOB6. - -Signed-off-by: Jae Hyun Yoo ---- - board/aspeed/ast2600_intel/intel.c | 50 ++++++++++++++++++++++++++++++++++++++ - 1 file changed, 50 insertions(+) - -diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index eb9b3959625e..b4a3dd222f3f 100644 ---- a/board/aspeed/ast2600_intel/intel.c -+++ b/board/aspeed/ast2600_intel/intel.c -@@ -151,6 +151,54 @@ static void sgpio_init(void) - SCU_BASE | SCU_414); - } - -+static void set_gpio_default_state(void) -+{ -+#define SCU_410 0x410 /* Multi-function Pin Control #4 */ -+#define SCU_410_RGMII3TXD1 BIT(19) -+#define GPIO_004 0x004 /* GPIO A/B/C/D Direction */ -+#define GPIO_000 0x000 /* GPIO A/B/C/D Value */ -+#define GPIO_C3 BIT(19) -+ -+ /* -+ * Set GPIOC3 as an output with value high explicitly since it doesn't -+ * have an external pull up. It uses direct register access because -+ * it's called from board_early_init_f(). -+ */ -+ writel(readl(SCU_BASE | SCU_410) & ~SCU_410_RGMII3TXD1, -+ SCU_BASE | SCU_410); -+ writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C3, -+ AST_GPIO_BASE | GPIO_004); -+ writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C3, -+ AST_GPIO_BASE | GPIO_000); -+ -+#define SCU_610 0x610 /* Disable internal pull-down #0 */ -+#define SCU_610_GPIOB6 BIT(14) -+ writel(readl(SCU_BASE | SCU_610) | SCU_610_GPIOB6, SCU_BASE | SCU_610); -+ -+#define GPIO_C5 BIT(21) -+ writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C5, -+ AST_GPIO_BASE | GPIO_004); -+ writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C5, -+ AST_GPIO_BASE | GPIO_000); -+ -+#define GPIO_024 0x024 /* GPIO E/F/G/H Direction */ -+#define GPIO_020 0x020 /* GPIO E/F/G/H Value */ -+#define GPIO_G6 BIT(22) -+ writel(readl(AST_GPIO_BASE | GPIO_024) | GPIO_G6, -+ AST_GPIO_BASE | GPIO_024); -+ writel(readl(AST_GPIO_BASE | GPIO_020) | GPIO_G6, -+ AST_GPIO_BASE | GPIO_020); -+ -+#define GPIO_074 0x074 /* GPIO I/J/K/L Direction */ -+#define GPIO_070 0x070 /* GPIO I/J/K/L Value */ -+#define GPIO_I_MASK GENMASK(7, 0) -+#define GPIO_L_MASK GENMASK(29, 28) -+ writel(readl(AST_GPIO_BASE | GPIO_074) | GPIO_I_MASK | GPIO_L_MASK, -+ AST_GPIO_BASE | GPIO_074); -+ writel(readl(AST_GPIO_BASE | GPIO_070) | GPIO_I_MASK | GPIO_L_MASK, -+ AST_GPIO_BASE | GPIO_070); -+} -+ - void espi_init(void); - int arch_interrupt_init_early(void); - -@@ -167,6 +215,8 @@ int board_early_init_f(void) - * I am not sure if it actually does anything... */ - arch_interrupt_init_early(); - -+ set_gpio_default_state(); -+ - gpio_passthru_init(); - - port80h_snoop_init(); --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch deleted file mode 100644 index e7e6c56d7..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 954e7dd9ff9c5d1159f0896afa34c673061b82ea Mon Sep 17 00:00:00 2001 -From: Yong Li -Date: Tue, 11 Sep 2018 16:24:06 +0800 -Subject: [PATCH] Make sure debug uart is using 24MHz clock source - -u-boot defines the uart5(debug console) as 24MHz, -set the SCU14[28] to 0, to make sure the clock source is 24M - -Signed-off-by: Yong Li - ---- - arch/arm/include/asm/arch-aspeed/ast_scu.h | 2 ++ - arch/arm/include/asm/arch-aspeed/platform.h | 1 + - arch/arm/mach-aspeed/ast-scu.c | 6 ++++++ - board/aspeed/ast-g5/ast-g5.c | 8 ++++++++ - 4 files changed, 17 insertions(+) - -diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h -index dcbc673..06825ce 100644 ---- a/arch/arm/include/asm/arch-aspeed/ast_scu.h -+++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h -@@ -46,4 +46,6 @@ extern void ast_scu_init_eth(u8 num); - extern void ast_scu_multi_func_eth(u8 num); - extern void ast_scu_multi_func_romcs(u8 num); - -+void ast_config_uart5_clk(void); -+ - #endif -diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h -index 1c02914..92ea33b 100644 ---- a/arch/arm/include/asm/arch-aspeed/platform.h -+++ b/arch/arm/include/asm/arch-aspeed/platform.h -@@ -27,6 +27,7 @@ - #include - #elif defined(AST_SOC_G5) - #include -+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - #else - #err "No define for platform.h" - #endif -diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index 12de9b8..fff02dc 100644 ---- a/arch/arm/mach-aspeed/ast-scu.c -+++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -538,3 +538,9 @@ void ast_scu_get_who_init_dram(void) - break; - } - } -+ -+void ast_config_uart5_clk(void) -+{ -+ ast_scu_write(ast_scu_read(AST_SCU_MISC2_CTRL) & -+ ~(1 << 28), AST_SCU_MISC2_CTRL); -+} -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index e67a4bf..5a1fade 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -16,6 +16,14 @@ - - DECLARE_GLOBAL_DATA_PTR; - -+int board_early_init_f(void) -+{ -+ /* make sure uart5 is using 24MHz clock */ -+ ast_config_uart5_clk(); -+ -+ return 0; -+} -+ - int board_init(void) - { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch deleted file mode 100644 index 66f3d3b12..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch +++ /dev/null @@ -1,435 +0,0 @@ -From 143fb89b03af61bd807b0d6f9f11d6801cf8fe69 Mon Sep 17 00:00:00 2001 -From: Kuiying Wang -Date: Fri, 3 Jan 2020 12:52:29 +0800 -Subject: [PATCH] Enable interrupt in u-boot. - -Ast2600 is Cortex-A7 -GIC V2 is used as the interrupt controller -GIC includes GICD and GICC - -Testedby: -1. Enable interrupt based SW handshake for ESPI -2. Both ArcherCity and Ast2600 EVB are working well. - -Signed-off-by: Kuiying Wang ---- - arch/arm/lib/vectors.S | 31 ++++++- - board/aspeed/ast2600_intel/ast-irq.c | 154 +++++++++++++++++------------------ - 2 files changed, 105 insertions(+), 80 deletions(-) - -diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S -index 2ca6e2494a7a..e2ed04a204de 100644 ---- a/arch/arm/lib/vectors.S -+++ b/arch/arm/lib/vectors.S -@@ -13,7 +13,7 @@ - */ - - #include -- -+#define CONFIG_USE_IRQ - /* - * A macro to allow insertion of an ARM exception vector either - * for the non-boot0 case or by a boot0-header. -@@ -145,6 +145,17 @@ fiq: - - #else /* !CONFIG_SPL_BUILD */ - -+#ifdef CONFIG_USE_IRQ -+/* IRQ stack memory (calculated at run-time) */ -+.globl IRQ_STACK_START -+IRQ_STACK_START: -+ .word 0x0badc0de -+/* IRQ stack memory (calculated at run-time) */ -+.globl FIQ_STACK_START -+FIQ_STACK_START: -+ .word 0x0badc0de -+#endif -+ - /* IRQ stack memory (calculated at run-time) + 8 bytes */ - .globl IRQ_STACK_START_IN - IRQ_STACK_START_IN: -@@ -277,17 +288,31 @@ not_used: - bad_save_user_regs - bl do_not_used - -+ .align 5 -+#ifdef CONFIG_USE_IRQ -+irq: -+ get_irq_stack -+ irq_save_user_regs -+ bl do_irq -+ irq_restore_user_regs -+ .align 5 -+fiq: -+ get_fiq_stack -+ /* someone ought to write a more effective fiq_save_user_regs */ -+ irq_save_user_regs -+ bl do_fiq -+ irq_restore_user_regs - - .align 5 -+#else - irq: - get_bad_stack - bad_save_user_regs - bl do_irq -- - .align 5 - fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq -- -+#endif /* CONFIG_USE_IRQ */ - #endif /* CONFIG_SPL_BUILD */ -diff --git a/board/aspeed/ast2600_intel/ast-irq.c b/board/aspeed/ast2600_intel/ast-irq.c -index f817f8cd7c81..6e91b17ab186 100644 ---- a/board/aspeed/ast2600_intel/ast-irq.c -+++ b/board/aspeed/ast2600_intel/ast-irq.c -@@ -18,19 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; - #define GIC_INTERFACE_OFFSET 0x4000 - #define GIC_VIRT_OFFSET 0x6000 - --#define VIC_STATUS_L 0x80 --#define VIC_STATUS_H 0x84 --#define VIC_IRQ_SELECTION_L 0x98 --#define VIC_IRQ_SELECTION_H 0x9C --#define VIC_ENABLE_L 0xA0 --#define VIC_ENABLE_H 0xA4 --#define VIC_ENABLE_CLEAR_L 0xA8 --#define VIC_ENABLE_CLEAR_H 0xAC --#define VIC_INTERRUPT_CLEAR_L 0xD8 --#define VIC_INTERRUPT_CLEAR_H 0xDC -- --#define VIC_CLEAR_ALL (~0) -- - /* GIC_DISTRIBUTOR_OFFSET register offsets */ - #define GICD_CTLR 0x000 - #define GICD_TYPER 0x004 -@@ -82,7 +69,9 @@ DECLARE_GLOBAL_DATA_PTR; - #define GICC_IIDR 0x00fc - #define GICC_DIR 0x1000 - --#define GIC_CPU_IMPLEMENTER_MAGIC 0x0102143b -+#define GIC_CPU_IMPLEMENTER_MAGIC 0x0102143b -+#define GICC_IAR_INT_ID_MASK 0x3ff -+#define GIC_CPU_DEACTIVATE 0x1000 - - /* GIC_INTERFACE_OFFSET register offsets */ - #define GICH_HCR 0x000 -@@ -116,9 +105,10 @@ DECLARE_GLOBAL_DATA_PTR; - - #define GIC_VIRT_CPU_IMPLEMENTER_MAGIC 0x0102143b - --#define GICD_CTLR_ENABLE 0x03 -- --#define GICD_INT_DEF_PRI 0xa0 -+#define GICD_CTLR_ENABLE 0x03 /*enable group 0 and 1*/ -+#define GICC_CTLR_ENABLE 0x03 -+#define GICD_ITARGET_ALL 0xffffffff -+#define GICD_INT_DEF_PRI 0xa0 - #define GICD_INT_DEF_PRI_X4 (\ - (GICD_INT_DEF_PRI << 24) |\ - (GICD_INT_DEF_PRI << 16) |\ -@@ -129,20 +119,30 @@ DECLARE_GLOBAL_DATA_PTR; - #define GICD_INT_EN_CLR_X32 0xffffffff - #define GICD_INT_EN_CLR_PPI 0xffff0000 - #define GICD_INT_EN_SET_SGI 0x0000ffff -+#define GICD_ICFG_LEVEL_TRIGGER 0x55555555 -+#define GICC_UNMASK_ALL_PRIORITY 0xff - - #define gicd_readl(OFFSET) readl(gbase + GIC_DISTRIBUTOR_OFFSET + (OFFSET)) - #define gicd_writel(VALUE, OFFSET) \ - writel((VALUE), gbase + GIC_DISTRIBUTOR_OFFSET + (OFFSET)) - #define gicc_readl(OFFSET) readl(gbase + GIC_CPU_OFFSET + (OFFSET)) -+#define gicc_writel(VALUE, OFFSET) \ -+ writel((VALUE), gbase + GIC_CPU_OFFSET + (OFFSET)) - #define gich_readl(OFFSET) readl(gbase + GIC_INTERFACE_OFFSET + (OFFSET)) - #define gicv_readl(OFFSET) readl(gbase + GIC_VIRT_OFFSET + (OFFSET)) -- --static size_t max_irq = 0; -- - #define ITLINES_MASK 0x1f - #define ITLINES_SHIFT 5 -- - #define GIC_MAX_IRQ 1020 -+#define SPI_INT_NUM_MIN 32 -+#define MAX_IRQ 0xfffffffe -+#define DEBUG_IRQ_ENABLED 0 -+#if DEBUG_IRQ_ENABLED -+#define DBG_IRQ printf -+#else -+#define DBG_IRQ(...) -+#endif -+ -+static size_t max_irq = 0; - static interrupt_handler_t *handlers[GIC_MAX_IRQ] = {NULL}; - static unsigned long irq_total = 0; - static unsigned long irq_counts[GIC_MAX_IRQ] = {0}; -@@ -159,31 +159,40 @@ static inline uint32_t gic_base(void) - - static void enable_gic(void) - { -- uint32_t gicd_ctlr; -+ uint32_t gicd_ctlr, gicc_ctlr; - -+ DBG_IRQ(" %s()\n", __FUNCTION__); - /* add GIC offset ref table 1-3 for interrupt distributor address */ - gicd_ctlr = gicd_readl(GICD_CTLR); -+ gicc_ctlr = gicc_readl(GICC_CTLR); - gicd_writel(gicd_ctlr | GICD_CTLR_ENABLE, GICD_CTLR); -+ gicc_writel(gicc_ctlr | GICC_CTLR_ENABLE, GICC_CTLR); - } - - static void disable_gic(void) - { -- uint32_t gicd_ctlr; -- -+ uint32_t gicd_ctlr, gicc_ctlr; -+ DBG_IRQ(" %s()\n", __FUNCTION__); - /* add GIC offset ref table 1-3 for interrupt distributor address */ - gicd_ctlr = gicd_readl(GICD_CTLR); - gicd_writel(gicd_ctlr & ~GICD_CTLR_ENABLE, GICD_CTLR); -+ gicc_ctlr = gicc_readl(GICC_CTLR); -+ gicc_writel(gicc_ctlr & ~GICC_CTLR_ENABLE, GICC_CTLR); - } - - static void enable_irq_id(unsigned int id) - { -+ DBG_IRQ(" %s()\n", __FUNCTION__); -+ - uint32_t grp = id >> ITLINES_SHIFT; - uint32_t grp_bit = 1 << (id & ITLINES_MASK); - gicd_writel(grp_bit, GICD_ISENABLERn + grp * sizeof(uint32_t)); -+ gicd_writel(GICD_ITARGET_ALL, GICD_ITARGETSRn + id / 4 * 4); - } - - static void disable_irq_id(unsigned int id) - { -+ DBG_IRQ(" %s()\n", __FUNCTION__); - uint32_t grp = id >> ITLINES_SHIFT; - uint32_t grp_bit = 1 << (id & ITLINES_MASK); - gicd_writel(grp_bit, GICD_ICENABLERn + grp * sizeof(uint32_t)); -@@ -193,22 +202,29 @@ static int gic_probe(void) - { - int i; - gbase = gic_base(); -+ DBG_IRQ("gic_probe GIC base = 0x%x, magicd=0x%x\n", -+ gbase, gicd_readl(GICD_IIDR)); - enable_gic(); - - if (gicd_readl(GICD_IIDR) != GIC_DISTRIBUTOR_IMPLEMENTER_MAGIC && - gicc_readl(GICC_IIDR) != GIC_CPU_IMPLEMENTER_MAGIC && - gicv_readl(GICV_IIDR) != GIC_VIRT_CPU_IMPLEMENTER_MAGIC) - { -+ printf("error: magic check \n"); - return 0; - } - /* GIC supports up to 1020 lines */ -- max_irq = ((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) << ITLINES_SHIFT; -+ max_irq = (((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) * 32) - 1; - if (max_irq > GIC_MAX_IRQ) - max_irq = GIC_MAX_IRQ; - /* set all lines to be level triggered N-N */ - for (i = 32; i < max_irq; i += 16) -- gicd_writel(0, GICD_ICFGRn + i / 4); -+ gicd_writel(GICD_ICFG_LEVEL_TRIGGER, GICD_ICFGRn + i / 4); - -+ DBG_IRQ("max_irq = 0x%x, typer=0x%x, config=0x%x, maxirq=0x%x\n", max_irq, -+ (gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1, -+ gicd_readl(GICD_ICFGRn + 0x8), -+ ((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) * 0x20); - /* Set priority on all interrupts. */ - for (i = 0; i < max_irq; i += 4) - gicd_writel(GICD_INT_DEF_PRI_X4, GICD_IPRIORITYRn + i); -@@ -218,9 +234,11 @@ static int gic_probe(void) - gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn + i / 8); - gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICENABLERn + i / 8); - } -- gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn); -- gicd_writel(GICD_INT_EN_CLR_PPI, GICD_ICENABLERn); -+ gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn); -+ gicd_writel(GICD_INT_EN_CLR_PPI, GICD_ICENABLERn); - gicd_writel(GICD_INT_EN_SET_SGI, GICD_ISENABLERn); -+ /* unmask all priority */ -+ gicc_writel(GICC_UNMASK_ALL_PRIORITY, GICC_PMRn); - - return 0; - } -@@ -228,6 +246,7 @@ static int gic_probe(void) - void irq_free_handler (int irq); - static void gic_shutdown(void) - { -+ DBG_IRQ(" %s()\n", __FUNCTION__); - int i; - for (i = 0; i < max_irq; i++) - { -@@ -238,6 +257,7 @@ static void gic_shutdown(void) - - int arch_interrupt_init_early(void) - { -+ DBG_IRQ(" %s()\n", __FUNCTION__); - return 0; - } - -@@ -249,11 +269,13 @@ int arch_interrupt_init(void) - handlers[i] = NULL; - irq_counts[i] = 0; - } -+ DBG_IRQ("arch_interrupt_init\n"); - return gic_probe(); - } - - int arch_interrupt_fini(void) - { -+ DBG_IRQ(" %s()\n", __FUNCTION__); - gic_shutdown(); - return 0; - } -@@ -261,14 +283,12 @@ int arch_interrupt_fini(void) - int interrupt_init (void) - { - /* -- * setup up stacks if necessary -- */ -+ * setup up stacks if necessary*/ -+ IRQ_STACK_START = gd->irq_sp + 8; - IRQ_STACK_START_IN = gd->irq_sp + 8; - -- printf("%s()\n", __FUNCTION__); -+ DBG_IRQ(" %s()\n", __FUNCTION__); - return arch_interrupt_init(); -- -- return 0; - } - - int global_interrupts_enabled (void) -@@ -286,12 +306,12 @@ void enable_interrupts (void) - { - unsigned long cpsr; - __asm__ __volatile__("mrs %0, cpsr\n" -- "bic %0, %0, #0x80\n" -+ "bic %0, %0, #0x1c0\n" - "msr cpsr_c, %0" - : "=r" (cpsr) - : - : "memory"); -- -+ DBG_IRQ(" %s()\n", __FUNCTION__); - return; - } - -@@ -304,11 +324,13 @@ int disable_interrupts (void) - : "=r" (cpsr), "=r" (temp) - : - : "memory"); -+ DBG_IRQ(" %s()\n", __FUNCTION__); - return (cpsr & 0x80) == 0; - } - - void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx) - { -+ DBG_IRQ(" %s()\n", __FUNCTION__); - if (irq > max_irq) { - printf("irq %d out of range\n", irq); - return; -@@ -317,13 +339,14 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx) - printf("irq %d already in use (%p)\n", irq, handlers[irq]); - return; - } -- printf("registering handler for irq %d\n", irq); -+ DBG_IRQ("registering handler for irq %d\n", irq); - handlers[irq] = handler; - enable_irq_id(irq); - } - - void irq_free_handler (int irq) - { -+ DBG_IRQ(" %s()\n", __FUNCTION__); - if (irq >= max_irq) { - printf("irq %d out of range\n", irq); - return; -@@ -338,9 +361,10 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) - { - int i; - int enabled = global_interrupts_enabled(); -- printf("GIC base = 0x%x\n", gbase); -- printf("interrupts %sabled\n", (enabled ? "en" : "dis")); -+ DBG_IRQ("GIC base = 0x%x\n", gbase); -+ DBG_IRQ("interrupts %sabled\n", (enabled ? "en" : "dis")); - uint32_t grp_en = 0; -+ - for (i = 0; i < max_irq; i++) { - if ((i & ITLINES_MASK) == 0) - grp_en = gicd_readl(GICD_ISENABLERn + -@@ -348,52 +372,28 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) - int irq_enabled = grp_en & (1 << (i & ITLINES_MASK)); - if (!irq_enabled) - continue; -- printf("% 2i (% 3s): %lu\n", i, -+ DBG_IRQ("%2d (%3s): %lu\n", i, - (irq_enabled ? "on" : "off"), irq_counts[i]); - } -- printf("total: %lu\n", irq_total); -+ DBG_IRQ("total: %lu\n", irq_total); - return 0; - } - - void do_irq(struct pt_regs *pt_regs) - { -- int i; -- if (!gbase) { -- static int printed_msg = 0; -- if (!printed_msg) -- { -- printed_msg = 1; -- printf("interrupt before configured!\n"); -- } -- return; -- } -- irq_total++; -- uint32_t grp_pend = 0; -- for (i = 0; i < max_irq; i++) { -- /* limit reads of the pending register to once in 32 */ -- if ((i & ITLINES_MASK) == 0) -- grp_pend = gicd_readl(GICD_ISPENDRn + -- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -- uint32_t pending = grp_pend & (1 << (i & ITLINES_MASK)); -- if (pending) { -- irq_counts[i]++; -- /* mask via GICD_ICENABLERn */ -- gicd_writel(pending, GICD_ICENABLERn + -- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -- if (handlers[i]) { -- handlers[i](pt_regs); -- /* unmask via GICD_ISENABLERn */ -- gicd_writel(pending, GICD_ISENABLERn + -- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -- /* clear pending via GICD_ICPENDRn */ -- gicd_writel(pending, GICD_ICPENDRn + -- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -- } else { -- printf("unexpected interrupt %i; masking\n", i); -- /* clear pending via GICD_ICPENDRn */ -- gicd_writel(pending, GICD_ISPENDRn + -- (i >> ITLINES_SHIFT) * sizeof(uint32_t)); -- } -+ uint32_t irqstat = 0, irqnr = 0; -+ -+ if (irq_total < MAX_IRQ) -+ irq_total++; -+ irqstat = gicc_readl(GICC_IAR); -+ irqnr = irqstat & GICC_IAR_INT_ID_MASK; -+ -+ if (irqnr > SPI_INT_NUM_MIN && irqnr < GIC_MAX_IRQ) { -+ gicc_writel(irqnr, GICC_EOIR); -+ if (irq_counts[irqnr] < MAX_IRQ) -+ irq_counts[irqnr]++; -+ if (handlers[irqnr]) { -+ handlers[irqnr](NULL); - } - } - } --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch deleted file mode 100644 index 6bd063e39..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 7e11461d6b65969005605f13677269eb91d39643 Mon Sep 17 00:00:00 2001 -From: Kuiying Wang -Date: Wed, 7 Nov 2018 13:57:57 +0800 -Subject: [PATCH] enable passthrough in uboot - ---- - arch/arm/mach-aspeed/ast-scu.c | 22 ++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5.c | 2 ++ - 2 files changed, 24 insertions(+) - -diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index fff02dc..d27f3d3 100644 ---- a/arch/arm/mach-aspeed/ast-scu.c -+++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -544,3 +544,25 @@ void ast_config_uart5_clk(void) - ast_scu_write(ast_scu_read(AST_SCU_MISC2_CTRL) & - ~(1 << 28), AST_SCU_MISC2_CTRL); - } -+ -+ -+void ast_enable_pass_through(void) -+{ -+ //Enable GPIOE pin mode, SCU80[16:23] = 00 */ -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & (~0x00FF0000), -+ AST_SCU_FUN_PIN_CTRL1); -+ -+ //Enable all pass through pins by setting SCU8C[15:12] = 0x3. -+ //Pass-through pins set: -+ //GPIOE0 -> GPIOE1 -+ //GPIOE2 -> GPIOE3 -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL4) | (0x3000), -+ AST_SCU_FUN_PIN_CTRL4); -+ -+ //Disable HWStrap for GPIOE pass-through mode -+ //The write operation to SCU70(0x1e6e2070) only can set to '1'. -+ //To clear to '0', it must write '1' to 0x1e6e207c -+ if (ast_scu_read(AST_SCU_HW_STRAP1) & (0x1 << 22)){ -+ ast_scu_write((0x1 << 22), AST_SCU_REVISION_ID); -+ } -+} -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index 5a1fade..b492003 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -20,6 +20,8 @@ int board_early_init_f(void) - { - /* make sure uart5 is using 24MHz clock */ - ast_config_uart5_clk(); -+ /*enable pass through*/ -+ ast_enable_pass_through(); - - return 0; - } diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch deleted file mode 100644 index 4f90d6dfe..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-Add-Aspeed-g5-interrupt-support.patch +++ /dev/null @@ -1,387 +0,0 @@ -From e782f6a90468fee35877b78e248a17f39f67c94c Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Wed, 14 Nov 2018 10:21:40 -0800 -Subject: [PATCH] Add Aspeed g5 interrupt support - -This adds a few new files to the board g5 directory. Several Intel -features require interrupts running in U-Boot, so this adds basic -interrupt registration and handling support. - -Signed-off-by: Vernon Mauery -Change-Id: Id7072f1408dcf364968b1b74f2192e50a22a82f0 - ---- - Kconfig | 13 +++ - arch/arm/lib/interrupts.c | 11 +++ - board/aspeed/ast-g5/Makefile | 3 +- - board/aspeed/ast-g5/ast-g5-irq.c | 176 ++++++++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-irq.h | 39 ++++++++ - board/aspeed/ast-g5/ast-g5.c | 3 + - board/aspeed/ast-g5/ast-g5.h | 7 ++ - cmd/Kconfig | 5 + - configs/ast_g5_ncsi_2boot_defconfig | 1 + - configs/ast_g5_ncsi_defconfig | 1 + - configs/ast_g5_phy_defconfig | 1 + - 11 files changed, 259 insertions(+), 1 deletion(-) - create mode 100644 board/aspeed/ast-g5/ast-g5-irq.c - create mode 100644 board/aspeed/ast-g5/ast-g5-irq.h - create mode 100644 board/aspeed/ast-g5/ast-g5.h - -diff --git a/Kconfig b/Kconfig -index 3ceff25..d6439d0 100644 ---- a/Kconfig -+++ b/Kconfig -@@ -115,6 +115,19 @@ if EXPERT - When disabling this, please check if malloc calls, maybe - should be replaced by calloc - if one expects zeroed memory. - endif -+ -+config USE_IRQ -+ bool "Use interrupts" -+ default n -+ -+config STACKSIZE_IRQ -+ int "Size for IRQ stack (only if USE_IRQ enabled)" -+ default 16384 -+ -+config STACKSIZE_FIQ -+ int "Size for FIQ stack (only if USE_IRQ enabled)" -+ default 16384 -+ - endmenu # General setup - - menu "Boot images" -diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c -index ed83043..a96b3aa 100644 ---- a/arch/arm/lib/interrupts.c -+++ b/arch/arm/lib/interrupts.c -@@ -94,6 +94,17 @@ int disable_interrupts (void) - : "memory"); - return (old & 0x80) == 0; - } -+ -+int global_interrupts_enabled(void) -+{ -+ unsigned long old; -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ : "=r" (old) -+ : -+ : "memory"); -+ return (old & 0x80) == 0; -+} -+ - #else - int interrupt_init (void) - { -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index d1d7f85..df4e639 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -1 +1,2 @@ --obj-y = ast-g5.o -+obj-y += ast-g5.o -+obj-y += ast-g5-irq.o -diff --git a/board/aspeed/ast-g5/ast-g5-irq.c b/board/aspeed/ast-g5/ast-g5-irq.c -new file mode 100644 -index 0000000..860f16c ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-irq.c -@@ -0,0 +1,176 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "ast-g5.h" -+#include "ast-g5-irq.h" -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#ifdef CONFIG_USE_IRQ -+ -+#define VIC_STATUS_L 0x80 -+#define VIC_STATUS_H 0x84 -+#define VIC_IRQ_SELECTION_L 0x98 -+#define VIC_IRQ_SELECTION_H 0x9C -+#define VIC_ENABLE_L 0xA0 -+#define VIC_ENABLE_H 0xA4 -+#define VIC_ENABLE_CLEAR_L 0xA8 -+#define VIC_ENABLE_CLEAR_H 0xAC -+#define VIC_INTERRUPT_CLEAR_L 0xD8 -+#define VIC_INTERRUPT_CLEAR_H 0xDC -+ -+#define VIC_CLEAR_ALL (~0) -+ -+int arch_interrupt_init_early(void) -+{ -+ writel(VIC_CLEAR_ALL, AST_VIC_BASE + VIC_ENABLE_CLEAR_L); -+ writel(VIC_CLEAR_ALL, AST_VIC_BASE + VIC_ENABLE_CLEAR_H); -+ return 0; -+} -+int arch_interrupt_init(void) -+{ -+ return 0; -+} -+ -+#define AST_IRQ_START_L 0 -+#define AST_IRQ_END_L 31 -+#define AST_IRQ_START_H 32 -+#define AST_IRQ_END_H 63 -+#define AST_IRQ_COUNT 64 -+static interrupt_handler_t *handlers[AST_IRQ_COUNT] = {NULL}; -+static unsigned long irq_total = 0; -+static unsigned long irq_counts[AST_IRQ_COUNT] = {0}; -+ -+int request_irq(int irq, interrupt_handler_t *handler) -+{ -+ if (irq < AST_IRQ_START_L || irq > AST_IRQ_END_H) { -+ printf("irq %d out of range\n", irq); -+ return -1; -+ } -+ if (handlers[irq]) { -+ printf("irq %d already in use (%p)\n", irq, handlers[irq]); -+ return -1; -+ } -+ handlers[irq] = handler; -+ if (irq < AST_IRQ_START_H) { -+ writel((1 << irq), AST_VIC_BASE + VIC_ENABLE_L); -+ } else { -+ writel((1 << (irq - AST_IRQ_START_H)), -+ AST_VIC_BASE + VIC_ENABLE_H); -+ } -+ return 0; -+} -+ -+int release_irq(int irq) -+{ -+ if (irq < AST_IRQ_START_L || irq > AST_IRQ_END_H) { -+ return -1; -+ } -+ if (handlers[irq]) { -+ handlers[irq] = NULL; -+ if (irq < AST_IRQ_START_H) { -+ writel((1 << irq), AST_VIC_BASE + VIC_ENABLE_CLEAR_L); -+ } else { -+ writel((1 << (irq - AST_IRQ_START_H)), -+ AST_VIC_BASE + VIC_ENABLE_CLEAR_H); -+ } -+ } -+ return 0; -+} -+ -+extern int global_interrupts_enabled(void); -+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -+{ -+ int i; -+ int enabled = global_interrupts_enabled(); -+ unsigned long long irqs_enabled = -+ ((unsigned long long)readl(AST_VIC_BASE + VIC_ENABLE_H)) -+ << AST_IRQ_START_H -+ | readl(AST_VIC_BASE + VIC_ENABLE_L); -+ printf("interrupts %sabled\n", (enabled ? "en" : "dis")); -+ for (i = AST_IRQ_START_L; i < AST_IRQ_COUNT; i++) { -+ printf("% 2i (% 3s): %lu\n", i, -+ ((irqs_enabled & 1) ? "on" : "off"), irq_counts[i]); -+ irqs_enabled >>= 1; -+ } -+ printf("total: %lu\n", irq_total); -+ return 0; -+} -+ -+void do_irq(struct pt_regs *pt_regs) -+{ -+ uint32_t irq = readl(AST_VIC_BASE + VIC_STATUS_L); -+ int i; -+ irq_total++; -+ if (irq) { -+ // handler irq0-31 -+ for (i = AST_IRQ_START_L; i <= AST_IRQ_END_L; i++) { -+ if (irq & (1 << i)) { -+ irq_counts[i]++; -+ /* mask */ -+ writel((1 << i), -+ AST_VIC_BASE + VIC_ENABLE_CLEAR_L); -+ if (handlers[i]) { -+ handlers[i](pt_regs); -+ /* clear */ -+ writel((1 << i), -+ AST_VIC_BASE -+ + VIC_INTERRUPT_CLEAR_L); -+ /* unmask */ -+ writel((1 << i), -+ AST_VIC_BASE + VIC_ENABLE_L); -+ } else { -+ printf("unexpected interrupt %i; masking\n", -+ i); -+ /* clear; do not unmask */ -+ writel((1 << i), -+ AST_VIC_BASE -+ + VIC_INTERRUPT_CLEAR_L); -+ } -+ } -+ } -+ } -+ irq = readl(AST_VIC_BASE + VIC_STATUS_H); -+ if (irq) { -+ // handler irq32-63 -+ for (i = AST_IRQ_START_H; i <= AST_IRQ_END_H; i++) { -+ if (irq & (1 << (i - AST_IRQ_START_H))) { -+ irq_counts[i]++; -+ /* mask */ -+ writel((1 << (i - AST_IRQ_START_H)), -+ AST_VIC_BASE + VIC_ENABLE_CLEAR_H); -+ if (handlers[i]) { -+ handlers[i](pt_regs); -+ /* clear */ -+ writel((1 << (i - AST_IRQ_START_H)), -+ AST_VIC_BASE -+ + VIC_INTERRUPT_CLEAR_H); -+ /* unmask */ -+ writel((1 << (i - AST_IRQ_START_H)), -+ AST_VIC_BASE + VIC_ENABLE_H); -+ } else { -+ printf("unexpected interrupt %i; masking\n", -+ i); -+ /* clear; do not unmask */ -+ writel((1 << (i - AST_IRQ_START_H)), -+ AST_VIC_BASE -+ + VIC_INTERRUPT_CLEAR_H); -+ } -+ } -+ } -+ } -+} -+#endif -diff --git a/board/aspeed/ast-g5/ast-g5-irq.h b/board/aspeed/ast-g5/ast-g5-irq.h -new file mode 100644 -index 0000000..703eeab ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-irq.h -@@ -0,0 +1,39 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#ifndef __AST_G5_IRQ_H__ -+#define __AST_G5_IRQ_H__ -+ -+#include -+ -+#ifdef CONFIG_USE_IRQ -+ -+int arch_interrupt_init_early(void); -+ -+int request_irq(int irq, interrupt_handler_t *handler); -+ -+int release_irq(int irq); -+ -+#else /* CONFIG_USE_IRQ */ -+ -+int arch_interrupt_init_early(void) { -+ return 0; -+} -+ -+int request_irq(int irq, interrupt_handler_t *handler) { -+ return -1; -+} -+ -+int release_irq(int irq) { -+ return -1; -+} -+ -+#endif /* CONFIG_USE_IRQ */ -+ -+#endif /* __AST_G5_IRQ_H__ */ -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index b492003..2472aa3 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -14,6 +14,8 @@ - #include - #include - -+#include "ast-g5.h" -+ - DECLARE_GLOBAL_DATA_PTR; - - int board_early_init_f(void) -@@ -22,6 +24,7 @@ int board_early_init_f(void) - ast_config_uart5_clk(); - /*enable pass through*/ - ast_enable_pass_through(); -+ arch_interrupt_init_early(); - - return 0; - } -diff --git a/board/aspeed/ast-g5/ast-g5.h b/board/aspeed/ast-g5/ast-g5.h -new file mode 100644 -index 0000000..9fd10ec ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5.h -@@ -0,0 +1,7 @@ -+#ifndef _AST_G5_H_ -+#define _AST_G5_H_ -+ -+#include -+#include "ast-g5-irq.h" -+ -+#endif /* _AST_G5_H_ */ -diff --git a/cmd/Kconfig b/cmd/Kconfig -index d69b817..33be240 100644 ---- a/cmd/Kconfig -+++ b/cmd/Kconfig -@@ -313,6 +313,11 @@ endmenu - - menu "Device access commands" - -+config CMD_IRQ -+ bool "interrupts - enable/disable interrupts" -+ depends on USE_IRQ -+ default y -+ - config CMD_DM - bool "dm - Access to driver model information" - depends on DM -diff --git a/configs/ast_g5_ncsi_2boot_defconfig b/configs/ast_g5_ncsi_2boot_defconfig -index 2d28c86..d5b7894 100644 ---- a/configs/ast_g5_ncsi_2boot_defconfig -+++ b/configs/ast_g5_ncsi_2boot_defconfig -@@ -33,3 +33,4 @@ CONFIG_CMD_CRC32=y - CONFIG_LOOPW=y - CONFIG_CMD_MEMTEST=y - CONFIG_CMD_MX_CYCLIC=y -+CONFIG_USE_IRQ=y -diff --git a/configs/ast_g5_ncsi_defconfig b/configs/ast_g5_ncsi_defconfig -index 74029ed..9481e5f 100644 ---- a/configs/ast_g5_ncsi_defconfig -+++ b/configs/ast_g5_ncsi_defconfig -@@ -11,3 +11,4 @@ CONFIG_HUSH_PARSER=y - CONFIG_OF_LIBFDT=y - CONFIG_SPI_FLASH=y - CONFIG_SYS_NS16550=y -+CONFIG_USE_IRQ=y -diff --git a/configs/ast_g5_phy_defconfig b/configs/ast_g5_phy_defconfig -index 767f3af..4aefcf4 100644 ---- a/configs/ast_g5_phy_defconfig -+++ b/configs/ast_g5_phy_defconfig -@@ -12,3 +12,4 @@ CONFIG_HUSH_PARSER=y - CONFIG_OF_LIBFDT=y - CONFIG_SPI_FLASH=y - CONFIG_SYS_NS16550=y -+CONFIG_USE_IRQ=y diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch deleted file mode 100644 index 34d8b1abb..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch +++ /dev/null @@ -1,105 +0,0 @@ -From c438edace30a3408c827faaae2d5004fe5ae010d Mon Sep 17 00:00:00 2001 -From: arun-pm -Date: Fri, 29 Nov 2019 00:19:09 +0530 -Subject: [PATCH] SPI Quad IO Mode - -This commit adds quad IO mode in SPI driver for AST2600. - -Note:- Removed n25q00 Quad I/O support for the time being due to clock issue - with chip 'Micron 8UA15 - rw182 (128MB)' while enabling Quad I/O mode. ---- - arch/arm/dts/ast2600-intel.dts | 6 ++---- - drivers/mtd/spi/spi-nor-ids.c | 7 ++++++- - drivers/spi/aspeed_spi.c | 18 +++++++++++++++++- - 3 files changed, 25 insertions(+), 6 deletions(-) - mode change 100755 => 100644 drivers/spi/aspeed_spi.c - -diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts -index d16581c5811d..ab78b516b6a3 100644 ---- a/arch/arm/dts/ast2600-intel.dts -+++ b/arch/arm/dts/ast2600-intel.dts -@@ -101,16 +101,14 @@ - - &fmc { - status = "okay"; --#if 0 - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fmcquad_default>; --#endif - flash@0 { - compatible = "spi-flash", "sst,w25q256"; - status = "okay"; - spi-max-frequency = <40000000>; -- spi-tx-bus-width = <2>; -- spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; - }; - }; - -diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c -index ad733e71988b..257ab472305c 100644 ---- a/drivers/mtd/spi/spi-nor-ids.c -+++ b/drivers/mtd/spi/spi-nor-ids.c -@@ -164,7 +164,12 @@ const struct flash_info spi_nor_ids[] = { - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, -- { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -+ /* Removed n25q00 Quad I/O support for the time being due to clock issue with chip 'Micron 8UA15 - rw182 (128MB)' -+ * while enabling Quad I/O mode. As this chip is default shipped in platforms, marking it -+ * as Not supported for the time being. Once all chips are replaced with the new model, this can be enabled -+ * back(Note:- Certain other chips having same name(n25q00) but different part number has no issues). -+ */ -+ { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | NO_CHIP_ERASE) }, - { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, - { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, - #endif -diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c -old mode 100755 -new mode 100644 -index c7b998fadfde..930b18443a48 ---- a/drivers/spi/aspeed_spi.c -+++ b/drivers/spi/aspeed_spi.c -@@ -16,6 +16,9 @@ - #include - - #define ASPEED_SPI_MAX_CS 3 -+#define AST2600A0 0x05000303 -+#define AST2600A0_MAX_FREQ 40000000 -+#define AST_MAX_FREQ 100000000 - - struct aspeed_spi_regs { - u32 conf; /* 0x00 CE Type Setting */ -@@ -1011,6 +1014,19 @@ static int aspeed_spi_bind(struct udevice *bus) - return 0; - } - -+static int aspeed_get_max_freq(void) -+{ -+ u32 rev_id = readl(ASPEED_REVISION_ID); -+ -+ /*Limit max spi frequency less than 50MHz on AST2600-A0 due -+ * to FWSPICLK signal quality issue. -+ */ -+ if(rev_id == AST2600A0) -+ return AST2600A0_MAX_FREQ; -+ else -+ return AST_MAX_FREQ; -+} -+ - static int aspeed_spi_probe(struct udevice *bus) - { - struct resource res_regs, res_ahb; -@@ -1041,7 +1057,7 @@ static int aspeed_spi_probe(struct udevice *bus) - clk_free(&hclk); - - priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", -- 100000000); -+ aspeed_get_max_freq()); - - priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); - --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch deleted file mode 100644 index 40336d3dd..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-Add-espi-support.patch +++ /dev/null @@ -1,347 +0,0 @@ -From dff3a123b0318f83ecd753eea8945ebdc15fd2f9 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Wed, 14 Nov 2018 10:21:40 -0800 -Subject: [PATCH 1/1] Add espi support - -This adds basic eSPI support for U-Boot. The eSPI driver works best with -interrupts because the timing of the initialization with the PCH is not -trivial. - -The espi driver is currently just a bare-minimum driver allowing the -host to boot. In the future it may be expanded to have further -functions. - -Signed-off-by: Vernon Mauery -Signed-off-by: James Feist ---- - arch/arm/include/asm/arch-aspeed/regs-scu.h | 2 + - board/aspeed/ast-g5/Makefile | 2 + - board/aspeed/ast-g5/ast-g5-espi.c | 248 ++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-intel.c | 16 ++ - board/aspeed/ast-g5/ast-g5.c | 3 + - 5 files changed, 271 insertions(+) - create mode 100644 board/aspeed/ast-g5/ast-g5-espi.c - create mode 100644 board/aspeed/ast-g5/ast-g5-intel.c - -diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h -index c9b91795d1..019c00036a 100644 ---- a/arch/arm/include/asm/arch-aspeed/regs-scu.h -+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h -@@ -554,6 +554,8 @@ - - #define CLK_25M_IN (0x1 << 23) - -+#define SCU_HW_STRAP_FAST_RESET (1 << 27) -+#define SCU_HW_STRAP_ESPI_ENABLED (1 << 25) - #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) - #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) - #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index df4e63966e..58e0c648f4 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -1,2 +1,4 @@ - obj-y += ast-g5.o -+obj-y += ast-g5-intel.o -+obj-y += ast-g5-espi.o - obj-y += ast-g5-irq.o -diff --git a/board/aspeed/ast-g5/ast-g5-espi.c b/board/aspeed/ast-g5/ast-g5-espi.c -new file mode 100644 -index 0000000000..5a3ffe7bef ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-espi.c -@@ -0,0 +1,248 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "ast-g5.h" -+ -+#define DEBUG_ESPI_ENABLED 1 -+#ifdef DEBUG_ESPI_ENABLED -+#define DBG_ESPI debug -+#else -+#define DBG_ESPI(...) -+#endif -+/* eSPI controller registers */ -+#define ESPI000 0x000 /* Engine Control. */ -+#define ESPI004 0x004 /* Engine Status. */ -+#define ESPI008 0x008 /* Interrupt Status. */ -+#define ESPI00C 0x00C /* Interrupt Enable. */ -+#define ESPI010 0x010 /* DMA Addr of Peripheral Channel Posted Rx pkt */ -+#define ESPI014 0x014 /* Control of Peripheral Channel Posted Rx pkt. */ -+#define ESPI018 0x018 /* Data port of Peripheral Channel Posted Rx pkt. */ -+#define ESPI020 0x020 /* DMA Addr of Peripheral Channel Posted Tx pkt. */ -+#define ESPI024 0x024 /* Control of Peripheral Channel Posted Tx pkt. */ -+#define ESPI028 0x028 /* Data port of Peripheral Channel Posted Tx pkt. */ -+#define ESPI030 0x030 /* DMA Addr of Peripheral Channel Non-Posted Tx pkt. */ -+#define ESPI034 0x034 /* Control of Peripheral Channel Non-Posted Tx pkt. */ -+#define ESPI038 0x038 /* Data port of Peripheral Channel Non-Posted Tx pkt. */ -+#define ESPI040 0x040 /* DMA Addr of OOB Channel Rx pkt. */ -+#define ESPI044 0x044 /* Control of OOB Channel Rx pkt. */ -+#define ESPI048 0x048 /* Data port of OOB Channel Rx pkt. */ -+#define ESPI050 0x050 /* DMA Addr of OOB Channel Tx pkt. */ -+#define ESPI054 0x054 /* Control of OOB Channel Tx pkt. */ -+#define ESPI058 0x058 /* Data port of OOB Channel Tx pkt. */ -+#define ESPI060 0x060 /* DMA Addr of Flash Channel Rx pkt. */ -+#define ESPI064 0x064 /* Control of Flash Channel Rx pkt. */ -+#define ESPI068 0x068 /* Data port of Flash Channel Rx pkt. */ -+#define ESPI070 0x070 /* DMA Addr of Flash Channel Tx pkt. */ -+#define ESPI074 0x074 /* Control of Flash Channel Tx pkt. */ -+#define ESPI078 0x078 /* Data port of Flash Channel Tx pkt. */ -+#define ESPI084 0x084 /* Mapping Src Addr of Peripheral Channel Rx pkt. */ -+#define ESPI088 0x088 /* Mapping Tgt Addr of Peripheral Channel Rx pkt. */ -+#define ESPI08C 0x08C /* Mapping Addr Mask of Peripheral Channel Rx pkt. */ -+#define ESPI090 0x090 /* Mapping Target Addr and Mask of Flash Channel. */ -+#define ESPI094 0x094 /* Interrupt enable of System Event from Master. */ -+#define ESPI098 0x098 /* System Event from and to Master. */ -+#define ESPI09C 0x09C /* GPIO through Virtual Wire Channel. */ -+#define ESPI0A0 0x0A0 /* General Capabilities and Configurations. */ -+#define ESPI0A4 0x0A4 /* Channel 0 Capabilities and Configurations. */ -+#define ESPI0A8 0x0A8 /* Channel 1 Capabilities and Configurations. */ -+#define ESPI0AC 0x0AC /* Channel 2 Capabilities and Configurations. */ -+#define ESPI0B0 0x0B0 /* Channel 3 Capabilities and Configurations. */ -+#define ESPI0B4 0x0B4 /* GPIO Direction of Virtual Wire Channel. */ -+#define ESPI0B8 0x0B8 /* GPIO Selection of Virtual Wire Channel. */ -+#define ESPI0BC 0x0BC /* GPIO Reset Selection of Virtual Wire Channel. */ -+#define ESPI100 0x100 /* Interrupt enable of System Event 1 from Master. */ -+#define ESPI104 0x104 /* System Event 1 from and to Master. */ -+#define ESPI110 0x110 /* Interrupt type 0 of System Event from Master. */ -+#define ESPI114 0x114 /* Interrupt type 1 of System Event from Master. */ -+#define ESPI118 0x118 /* Interrupt type 2 of System Event from Master. */ -+#define ESPI11C 0x11C /* Interrupt status of System Event from Master. */ -+#define ESPI120 0x120 /* Interrupt type 0 of System Event 1 from Master. */ -+#define ESPI124 0x124 /* Interrupt type 1 of System Event 1 from Master. */ -+#define ESPI128 0x128 /* Interrupt type 2 of System Event 1 from Master. */ -+#define ESPI12C 0x12C /* Interrupt status of System Event 1 from Master. */ -+#define ESPICFG004 0x004 /* Device Identification. */ -+#define ESPICFG008 0x008 /* General Capabilities and Configurations. */ -+#define ESPICFG010 0x010 /* Channel 0 Capabilities and Configurations. */ -+#define ESPICFG020 0x020 /* Channel 1 Capabilities and Configurations. */ -+#define ESPICFG030 0x030 /* Channel 2 Capabilities and Configurations. */ -+#define ESPICFG040 0x040 /* Channel 3 Capabilities and Configurations. */ -+#define ESPICFG044 0x044 /* Channel 3 Capabilities and Configurations 2. */ -+#define ESPICFG800 0x800 /* GPIO Direction of Virtual Wire Channel. */ -+#define ESPICFG804 0x804 /* GPIO Selection of Virtual Wire Channel. */ -+#define ESPICFG808 0x808 /* GPIO Reset Selection of Virtual Wire Channel. */ -+#define ESPICFG810 0x810 /* Mapping Src Addr of Peripheral Channel Rx pkt */ -+#define ESPICFG814 0x814 /* Mapping Tgt Addr of Peripheral Channel Rx pkt */ -+#define ESPICFG818 0x818 /* Mapping Addr Mask of Peripheral Channel Rx pkt */ -+ -+/* ESPI000 bits */ -+#define AST_ESPI_OOB_CHRDY (1 << 4) -+#define AST_ESPI_FLASH_SW_CHRDY (0x1 << 7) -+#define AST_ESPI_FLASH_SW_READ (0x1 << 10) -+#define ASPEED_ESPI_CTRL_SW_RESET GENMASK(31, 24) -+ -+/* ESPI00C bits (Interrupt Enable) */ -+#define AST_ESPI_IEN_SYS_EV (1 << 8) -+#define AST_ESPI_IEN_GPIO_EV (1 << 9) -+#define AST_ESPI_IEN_HW_RST (1 << 31) -+ -+/* ESPI008 bits ISR */ -+#define AST_ESPI_VW_SYS_EVT (1 << 8) -+#define AST_ESPI_VW_SYS_EV1 (1 << 22) -+ -+/* ESPI098 and ESPI11C bits */ -+#define AST_ESPI_OOB_RST_WARN (1 << 6) -+#define AST_ESPI_HOST_RST_WARN (1 << 8) -+#define AST_ESPI_OOB_RST_ACK (1 << 16) -+#define AST_ESPI_SL_BT_DONE (1 << 20) -+#define AST_ESPI_SL_BT_STATUS (1 << 23) -+#define AST_ESPI_HOST_RST_ACK (1 << 27) -+ -+/* ESPI104 bits */ -+#define AST_ESPI_SUS_WARN (1 << 0) -+#define AST_ESPI_SUS_ACK (1 << 20) -+ -+/* LPC chip ID */ -+#define SCR0SIO 0x170 -+#define IRQ_SRC_ESPI 23 /* IRQ 23 */ -+ -+static void espi_handshake_ack(void) -+{ -+ // IRQ only serviced if strapped, so no strap check -+ if (!(readl(AST_ESPI_BASE + ESPI098) & AST_ESPI_SL_BT_STATUS)) { -+ DBG_ESPI("Setting espi slave boot done\n"); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } -+ -+ if (readl(AST_ESPI_BASE + ESPI104) & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("Boot SUS WARN set %08x\n", -+ readl(AST_ESPI_BASE + ESPI104)); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) | AST_ESPI_SUS_ACK; -+ writel(v, AST_ESPI_BASE + ESPI104); -+ } -+} -+ -+static int espi_irq_handler(struct pt_regs *regs) -+{ -+ uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008); -+ DBG_ESPI("ISR irq_status : 0x%08X\n", irq_status); -+ -+ if (irq_status & AST_ESPI_VW_SYS_EV1) { -+ uint32_t sys1_status = readl(AST_ESPI_BASE + ESPI12C); -+ uint32_t sys1_event = readl(AST_ESPI_BASE + ESPI104); -+ -+ DBG_ESPI("sys1_status : 0x%08X\n", sys1_status); -+ if (sys1_status & AST_ESPI_SUS_WARN) { -+ DBG_ESPI("SUS WARN ev: %08X\n", sys1_event); -+ if (sys1_event & AST_ESPI_SUS_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI104) -+ | AST_ESPI_SUS_ACK; -+ writel(v, AST_ESPI_BASE + ESPI104); -+ } -+ } -+ writel(sys1_status, AST_ESPI_BASE + ESPI12C); // clear status -+ } -+ -+ if (irq_status & AST_ESPI_VW_SYS_EVT) { -+ uint32_t sys_status = readl(AST_ESPI_BASE + ESPI11C); -+ uint32_t sys_event = readl(AST_ESPI_BASE + ESPI098); -+ -+ if (!(sys_event & AST_ESPI_SL_BT_STATUS)) { -+ DBG_ESPI("Setting espi slave boot done\n"); -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_SL_BT_STATUS | AST_ESPI_SL_BT_DONE; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } -+ -+ DBG_ESPI("sys_status : 0x%08X\n", sys_status); -+ if (sys_status & AST_ESPI_HOST_RST_WARN) { -+ DBG_ESPI("HOST_RST_WARN ev: %08X\n", sys_event); -+ if (sys_event & AST_ESPI_HOST_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_HOST_RST_ACK; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } -+ } -+ if (sys_status & AST_ESPI_OOB_RST_WARN) { -+ DBG_ESPI("OOB_RST_WARN ev: %08X\n", sys_event); -+ if (sys_event & AST_ESPI_OOB_RST_WARN) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI098) -+ | AST_ESPI_OOB_RST_ACK; -+ writel(v, AST_ESPI_BASE + ESPI098); -+ } -+ } -+ writel(sys_status, AST_ESPI_BASE + ESPI11C); // clear status -+ } -+ -+ if (irq_status & AST_ESPI_IEN_HW_RST) { -+ uint32_t v = readl(AST_ESPI_BASE + ESPI000); -+ writel(v & ~ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000); -+ writel(v | ASPEED_ESPI_CTRL_SW_RESET, AST_ESPI_BASE + ESPI000); -+ espi_handshake_ack(); -+ } -+ -+ writel(irq_status, AST_ESPI_BASE + ESPI008); // clear irq_status -+ return 0; -+} -+ -+void espi_init(void) -+{ -+ if (readl(AST_SCU_BASE + AST_SCU_HW_STRAP1) -+ & SCU_HW_STRAP_ESPI_ENABLED) { -+ uint32_t v; -+ DBG_ESPI("espi_init\n"); -+ -+ /* Block flash access from Host */ -+ v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_FLASH_SW_CHRDY; -+ v |= AST_ESPI_FLASH_SW_READ; -+ writel(v, AST_ESPI_BASE + ESPI000); -+ -+ /* Set SIO register 0x28 to 0xa8 as a faked ASPEED ChipID for -+ * BIOS using in eSPI mode */ -+ v = readl(AST_LPC_BASE + SCR0SIO) & ~0x000000ff; -+ writel(v, AST_LPC_BASE + SCR0SIO); -+ v = readl(AST_LPC_BASE + SCR0SIO) | 0xa8; -+ writel(v, AST_LPC_BASE + SCR0SIO); -+ -+ v = readl(AST_ESPI_BASE + ESPI000) | AST_ESPI_OOB_CHRDY; -+ writel(v, AST_ESPI_BASE + ESPI000); -+ -+ writel(0, AST_ESPI_BASE + ESPI110); -+ writel(0, AST_ESPI_BASE + ESPI114); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN, -+ AST_ESPI_BASE + ESPI118); -+ writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN, -+ AST_ESPI_BASE + ESPI094); -+ -+ writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE + ESPI120); // int type 0 susp warn -+ writel(0, AST_ESPI_BASE + ESPI124); -+ writel(0, AST_ESPI_BASE + ESPI128); -+ writel(AST_ESPI_SUS_WARN, -+ AST_ESPI_BASE -+ + ESPI100); // Enable sysev1 ints for susp warn -+ -+ writel(AST_ESPI_IEN_SYS_EV | AST_ESPI_IEN_HW_RST -+ | AST_ESPI_VW_SYS_EV1, -+ AST_ESPI_BASE + ESPI00C); // Enable events -+ -+ espi_handshake_ack(); -+ -+ request_irq(IRQ_SRC_ESPI, espi_irq_handler); -+ } else { -+ DBG_ESPI("No espi strap\n"); -+ } -+} -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -new file mode 100644 -index 0000000000..e79235c8d0 ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -0,0 +1,16 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+ -+extern void espi_init(void); -+void ast_g5_intel(void) -+{ -+ espi_init(); -+} -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index ca25348178..cab5fabcef 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -21,6 +21,8 @@ - - DECLARE_GLOBAL_DATA_PTR; - -+extern void ast_g5_intel(void); -+ - int board_early_init_f(void) - { - /* make sure uart5 is using 24MHz clock */ -@@ -84,6 +86,7 @@ int board_init(void) - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - gd->flags = 0; - -+ ast_g5_intel(); - return 0; - } - --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch deleted file mode 100644 index e8ffb4e72..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch +++ /dev/null @@ -1,78 +0,0 @@ -From ddf356e738ab147775bf49a3a4fae179c0dde9ef Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo -Date: Wed, 29 Jan 2020 14:55:44 -0800 -Subject: [PATCH] ast2600: Override OTP strap settings - -This commit adds settings to override OTP strap. -Also, this commit disables SoC debug interface. - -Signed-off-by: Jae Hyun Yoo ---- - arch/arm/mach-aspeed/ast2600/platform.S | 26 +++++++++++++++++++++++--- - 1 file changed, 23 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index d107ed80a835..eb3cb2f38cb6 100644 ---- a/arch/arm/mach-aspeed/ast2600/platform.S -+++ b/arch/arm/mach-aspeed/ast2600/platform.S -@@ -45,7 +45,9 @@ - #define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) - #define AST_SCU_MFP_CTRL15 (AST_SCU_BASE + 0x454) - #define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) -+#define AST_SCU_HW_STRAP1_CLR (AST_SCU_BASE + 0x504) - #define AST_SCU_HW_STRAP2 (AST_SCU_BASE + 0x510) -+#define AST_SCU_HW_STRAP2_CLR (AST_SCU_BASE + 0x514) - #define AST_SCU_CA7_CTRL (AST_SCU_BASE + 0x800) - #define AST_SCU_CA7_AXI_PREFETCH_START (AST_SCU_BASE + 0x808) - #define AST_SCU_CA7_AXI_PREFETCH_END (AST_SCU_BASE + 0x80C) -@@ -146,6 +148,26 @@ do_primary_core_setup: - /* unlock system control unit */ - scu_unlock - -+ /* disable CA7 CPU boot */ -+ ldr r0, =AST_SCU_HW_STRAP1_CLR -+ movw r1, #0x0001 @; Disable ARM CA7 CPU boot -+ movt r1, #0x0000 -+ str r1, [r0] -+ -+ /* enable eSPI, debug interface and disable UART5 boot*/ -+ ldr r0, =AST_SCU_HW_STRAP2_CLR -+ movw r1, #0x0040 @; Select eSPI -+ movt r1, #0x0000 -+ orr r1, #0x0010 @; Enable debug interface -+ orr r1, #0x0100 @; Disable UART5 boot -+ str r1, [r0] -+ -+ /* enable ACPI */ -+ ldr r0, =AST_SCU_HW_STRAP2 -+ ldr r1, [r0] -+ orr r1, #0x20 @; Enable ACPI -+ str r1, [r0] -+ - /* identify AST2600 A0/A1 */ - ldr r0, =AST_SCU_REV_ID - ldr r0, [r0] -@@ -241,19 +263,17 @@ wait_lock: - ldr r1, =AST_FMC_CE0_CTRL - str r0, [r1] - --#if 0 - /* disable UART-based SoC Debug Interface UART5 and P2A bridge*/ - ldr r0, =AST_SCU_DEBUG_CTRL - ldr r1, [r0] - orr r1, #0x03 - str r1, [r0] -- -+ - /* disable UART-based SoC Debug Interface UART1 and LPC2AHB bridge */ - ldr r0, =AST_SCU_DEBUG_CTRL2 - ldr r1, [r0] - orr r1, #0x0A - str r1, [r0] --#endif - - /* Strongest LADESPID Driving Strngth */ - ldr r0, =AST_SCU_MFP_CTRL15 --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch deleted file mode 100644 index 9af713c99..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 9d2d9b9db7796a49d03ac8b19dfbdefbe840c506 Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo -Date: Wed, 25 Mar 2020 15:04:26 -0700 -Subject: [PATCH] AST2600: Add TPM pulse trigger - -This commit adds TPM pulse trigger into u-boot booting. - -Signed-off-by: Jae Hyun Yoo ---- - board/aspeed/ast2600_intel/intel.c | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index 04fd450d14fc..34b37cc24f91 100644 ---- a/board/aspeed/ast2600_intel/intel.c -+++ b/board/aspeed/ast2600_intel/intel.c -@@ -35,6 +35,31 @@ int gpio_abort(void) - return value <= 0 ? 0 : 1; - } - -+/* use GPIOC2 on intel boards */ -+#define TPM_EN_GPIO "gpio@1e78000018" -+ -+int enable_onboard_tpm(void) -+{ -+ struct gpio_desc desc; -+ int ret; -+ -+ ret = dm_gpio_lookup_name(TPM_EN_GPIO, &desc); -+ if (ret) -+ return ret; -+ ret = dm_gpio_request(&desc, "tpm_en_pulse"); -+ if (ret) -+ return ret; -+ if (dm_gpio_is_valid(&desc)) { -+ dm_gpio_set_value(&desc, 1); -+ mdelay(50); -+ dm_gpio_set_value(&desc, 0); -+ printf("TPM: Pulse triggered\n"); -+ } -+ dm_gpio_free(desc.dev, &desc); -+ -+ return ret; -+} -+ - #define SCU_BASE 0x1E6E2000 - #define SCU_338 0x338 //Generate UART 24 MHz Reference from UXCLK - #define SCU_33C 0x33c //Generate UART 24 MHz Reference from HUXCLK -@@ -234,6 +259,8 @@ int board_early_init_r(void) - - espi_init(); - -+ (void) enable_onboard_tpm(); -+ - return 0; - } - --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch deleted file mode 100644 index 5fa4bffa1..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-add-sgio-support-for-port80-snoop-post-LEDs.patch +++ /dev/null @@ -1,158 +0,0 @@ -From 40e02e4ffa13c0128db555a3a3982a7cdc0ebf60 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Wed, 14 Nov 2018 12:09:52 -0800 -Subject: [PATCH] add sgio support for port80 snoop post LEDs - -This ties together the port 80 snooping to the SGPIO output that -ultimately drives the POST code LEDs. - -Signed-off-by: Vernon Mauery -Change-Id: Iaa1b91cd40f4b6323dba0598da373cb631459e66 - ---- - arch/arm/include/asm/arch-aspeed/ast_scu.h | 1 + - arch/arm/mach-aspeed/ast-scu.c | 8 +++ - board/aspeed/ast-g5/ast-g5-intel.c | 96 ++++++++++++++++++++++++++++++ - 3 files changed, 105 insertions(+) - -diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h -index 06825ce..369c4e3 100644 ---- a/arch/arm/include/asm/arch-aspeed/ast_scu.h -+++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h -@@ -45,6 +45,7 @@ extern u32 ast_scu_get_vga_memsize(void); - extern void ast_scu_init_eth(u8 num); - extern void ast_scu_multi_func_eth(u8 num); - extern void ast_scu_multi_func_romcs(u8 num); -+extern void ast_scu_multi_func_sgpio(void); - - void ast_config_uart5_clk(void); - -diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index d27f3d3..3a9ba05 100644 ---- a/arch/arm/mach-aspeed/ast-scu.c -+++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -449,6 +449,14 @@ void ast_scu_multi_func_romcs(u8 num) - SCU_FUN_PIN_ROMCS(num), AST_SCU_FUN_PIN_CTRL3); - } - -+void ast_scu_multi_func_sgpio(void) -+{ -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL2) | -+ SCU_FUN_PIN_SGPMI | SCU_FUN_PIN_SGPMO | -+ SCU_FUN_PIN_SGPMLD | SCU_FUN_PIN_SGPMCK, -+ AST_SCU_FUN_PIN_CTRL2); -+} -+ - u32 ast_scu_revision_id(void) - { - int i; -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e79235c..c2a8b33 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -8,9 +8,105 @@ - */ - - #include -+#include -+#include -+#include -+#include -+ -+#include "ast-g5.h" -+ -+#define LPC_SNOOP_ADDR 0x80 -+#define HICR5 0x080 /* Host Interface Control Register 5 */ -+#define HICR6 0x084 /* Host Interface Control Register 6 */ -+#define HICR7 0x088 /* Host Interface Control Register 7 */ -+#define HICR8 0x08c /* Host Interface Control Register 8 */ -+#define SNPWADR 0x090 /* LPC Snoop Address Register */ -+#define SNPWDR 0x094 /* LPC Snoop Data Register */ -+#define HICR9 0x098 /* Host Interface Control Register 9 */ -+#define HICRA 0x09c /* Host Interface Control Register A */ -+#define LHCR0 0x0a0 /* LPC Host Control Register 0 */ -+#define LHCR1 0x0a4 /* LPC Host Control Register 1 */ -+#define LHCR2 0x0a8 /* LPC Host Control Register 2 */ -+#define LHCR3 0x0ac /* LPC Host Control Register 3 */ -+#define LHCR4 0x0b0 /* LPC Host Control Register 4 */ -+#define LHCR5 0x0b4 /* LPC Host Control Register 5 */ -+#define LHCR6 0x0b8 /* LPC Host Control Register 6 */ -+#define LHCR7 0x0bc /* LPC Host Control Register 7 */ -+#define LHCR8 0x0c0 /* LPC Host Control Register 8 */ -+#define PCCR6 0x0c4 /* Post Code Control Register 6 */ -+#define LHCRA 0x0c8 /* LPC Host Control Register A */ -+#define LHCRB 0x0cc /* LPC Host Control Register B */ -+#define PCCR4 0x0d0 /* Post Code Control Register 4 */ -+#define PCCR5 0x0d4 /* Post Code Control Register 5 */ -+#define HICRB 0x100 /* Host Interface Control Register B */ -+#define HICRC 0x104 /* Host Interface Control Register C */ -+/* HICR5 Bits */ -+#define HICR5_EN_SIOGIO (1 << 31) /* Enable SIOGIO */ -+#define HICR5_EN80HGIO (1 << 30) /* Enable 80hGIO */ -+#define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */ -+#define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */ -+#define HICR5_UNKVAL_MASK 0x1FFF0000 /* Bits with unknown values on reset */ -+#define HICR5_ENINT_SNP0W (1 << 1) /* Enable Snooping address 0 */ -+#define HICR5_EN_SNP0W (1 << 0) /* Enable Snooping address 0 */ -+ -+/* HRCR6 Bits */ -+#define HICR6_STR_SNP0W (1 << 0) /* Interrupt Status Snoop address 0 */ -+#define HICR6_STR_SNP1W (1 << 1) /* Interrupt Status Snoop address 1 */ -+ -+/* HICRB Bits */ -+#define HICRB_EN80HSGIO (1 << 13) /* Enable 80hSGIO */ -+ -+#define SGPIO_CLK_DIV(N) ((N) << 16) -+#define SGPIO_BYTES(N) ((N) << 6) -+#define SGPIO_ENABLE 1 -+#define GPIO254 0x254 -+ -+static void sgpio_init(void) -+{ -+ uint32_t value; -+ /* -+ 33.4.2 -+ LPC port80h direct to SGPIO -+ In AST2500 SGPIO, it supports output data from 80h. It always uses SGPIOA. -+ 1. Configure LPC snoop function. -+ (a) Set SNPWADR(0x1e789090)[15:0] to 0x80. -+ (b) Set HICR5(0x1e789080)[0] to 1 to enable snoop. -+ 2. Configure SGPIO -+ (a) Set GPIO254[9:6] to larger than or equal to 0x1. -+ (b) Set GPIO254[0] to 1 to enable SGPIO. -+ 3. Set SuperIO -+ (a) Set SIOR7 30h to 0x40. -+ */ -+ /* make sure multi-pin stuff goes in our favor */ -+ ast_scu_multi_func_sgpio(); -+ -+ /* set lpc snoop #0 to port 0x80 */ -+ value = readl(AST_LPC_BASE + SNPWADR) & 0xffff0000; -+ writel(value | LPC_SNOOP_ADDR, AST_LPC_BASE + SNPWADR); -+ -+ /* clear interrupt status */ -+ value = readl(AST_LPC_BASE + HICR6); -+ value |= HICR6_STR_SNP0W | HICR6_STR_SNP1W; -+ writel(value, AST_LPC_BASE + HICR6); -+ -+ /* enable lpc snoop #0 and SIOGIO */ -+ value = readl(AST_LPC_BASE + HICR5) & ~(HICR5_UNKVAL_MASK); -+ value |= HICR5_EN_SIOGIO | HICR5_EN_SNP0W; -+ writel(value, AST_LPC_BASE + HICR5); -+ -+ -+ /* enable port80h snoop on SGPIO */ -+ value = readl(AST_LPC_BASE + HICRB) | HICRB_EN80HSGIO; -+ writel(value, AST_LPC_BASE + HICRB); -+ -+ /* set the gpio clock to pclk/(2*(5+1)) or ~2 MHz */ -+ value = SGPIO_CLK_DIV(256) | SGPIO_BYTES(10) | SGPIO_ENABLE; -+ writel(value, AST_GPIO_BASE + GPIO254); -+} - - extern void espi_init(void); - void ast_g5_intel(void) - { - espi_init(); -+ sgpio_init(); - } diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch deleted file mode 100644 index e11f15870..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0009-Add-basic-GPIO-support.patch +++ /dev/null @@ -1,427 +0,0 @@ -From 15d04184a94aca6db889d77c2cc5a800b280da4b Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Fri, 16 Nov 2018 09:58:01 -0800 -Subject: [PATCH 01/30] Add basic GPIO support - -Add a table of well-known gpios (such as FP LEDs and FF UPD jumper) and -initialize them at boot. - -Add a mechanism to get/set well known gpios from command line. - -Change-Id: I4136a5ccb048b3604f13b17ea0c18a4bc596c249 -Signed-off-by: Vernon Mauery - -%% original patch: 0009-Add-basic-GPIO-support.patch ---- - board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-gpio.c | 202 +++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-gpio.h | 103 +++++++++++++++ - board/aspeed/ast-g5/ast-g5-intel.c | 45 +++++++ - board/aspeed/ast-g5/ast-g5.h | 1 + - 5 files changed, 352 insertions(+) - create mode 100644 board/aspeed/ast-g5/ast-g5-gpio.c - create mode 100644 board/aspeed/ast-g5/ast-g5-gpio.h - -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 58e0c648f4..2970ae5741 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -2,3 +2,4 @@ obj-y += ast-g5.o - obj-y += ast-g5-intel.o - obj-y += ast-g5-espi.o - obj-y += ast-g5-irq.o -+obj-y += ast-g5-gpio.o -diff --git a/board/aspeed/ast-g5/ast-g5-gpio.c b/board/aspeed/ast-g5/ast-g5-gpio.c -new file mode 100644 -index 0000000000..dc6962f4ba ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-gpio.c -@@ -0,0 +1,202 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "ast-g5.h" -+#include "ast-g5-gpio.h" -+ -+typedef struct _gpio_bases { -+ uint32_t u32ddr; /* data and direction registers */ -+ uint32_t u32intcfg; /* interrupt config */ -+ uint32_t u32debounce; /* debounce config */ -+ uint32_t u32cmdsrc; /* command source config */ -+} sGPIO_BASES; -+ -+static const sGPIO_BASES GPIO_BASES[] = { -+ /* ABCD */ -+ {AST_GPIO_BASE + 0x0000, AST_GPIO_BASE + 0x0008, -+ AST_GPIO_BASE + 0x0040, AST_GPIO_BASE + 0x0060}, -+ /* EFGH */ -+ {AST_GPIO_BASE + 0x0020, AST_GPIO_BASE + 0x0028, -+ AST_GPIO_BASE + 0x0048, AST_GPIO_BASE + 0x0068}, -+ /* IJKL */ -+ {AST_GPIO_BASE + 0x0070, AST_GPIO_BASE + 0x0098, -+ AST_GPIO_BASE + 0x00b0, AST_GPIO_BASE + 0x0090}, -+ /* MNOP */ -+ {AST_GPIO_BASE + 0x0078, AST_GPIO_BASE + 0x00e8, -+ AST_GPIO_BASE + 0x0100, AST_GPIO_BASE + 0x00e0}, -+ /* QRST */ -+ {AST_GPIO_BASE + 0x0080, AST_GPIO_BASE + 0x0118, -+ AST_GPIO_BASE + 0x0130, AST_GPIO_BASE + 0x0110}, -+ /* UVWX */ -+ {AST_GPIO_BASE + 0x0088, AST_GPIO_BASE + 0x0148, -+ AST_GPIO_BASE + 0x0160, AST_GPIO_BASE + 0x0140}, -+ /* YZAB */ -+ {AST_GPIO_BASE + 0x01e0, AST_GPIO_BASE + 0x0178, -+ AST_GPIO_BASE + 0x0190, AST_GPIO_BASE + 0x0170}, -+ /* AC__ */ -+ {AST_GPIO_BASE + 0x01e8, AST_GPIO_BASE + 0x01a8, -+ AST_GPIO_BASE + 0x01c0, AST_GPIO_BASE + 0x01a0}, -+}; -+ -+static size_t gpio_max = 0; -+static const GPIOValue * gpio_table = NULL; -+ -+void gpio_set_value(int n, int asserted) -+{ -+ uint8_t port; -+ uint8_t pin; -+ uint32_t base; -+ uint8_t shift; -+ uint8_t assert; -+ uint32_t gpio_value; -+ -+ if (n >= gpio_max || !gpio_table) { -+ return; -+ } -+ port = GPIO_PORT(gpio_table[n].u8PortPin); -+ assert = GPIO_ASSERT(gpio_table[n].u8PinCFG); -+ pin = GPIO_PIN(gpio_table[n].u8PortPin); -+ base = GPIO_BASES[GPIO_GROUP(port)].u32ddr; -+ shift = GPIO_SHIFT(port, pin); -+ -+ gpio_value = readl(base + GPIO_DATA_VALUE); -+ if ((assert && asserted) || !(assert || asserted)) { -+ // set the bit -+ gpio_value |= (1 << shift); -+ } else { -+ // clear the bit -+ gpio_value &= ~(1 << shift); -+ } -+ writel(gpio_value, base + GPIO_DATA_VALUE); -+} -+ -+int gpio_get_value(int n) -+{ -+ uint8_t port; -+ uint8_t pin; -+ uint32_t base; -+ uint8_t shift; -+ uint8_t assert; -+ uint32_t gpio_value; -+ -+ if (n >= gpio_max || !gpio_table) { -+ return -1; -+ } -+ port = GPIO_PORT(gpio_table[n].u8PortPin); -+ assert = GPIO_ASSERT(gpio_table[n].u8PinCFG); -+ pin = GPIO_PIN(gpio_table[n].u8PortPin); -+ base = GPIO_BASES[GPIO_GROUP(port)].u32ddr; -+ shift = GPIO_SHIFT(port, pin); -+ -+ gpio_value = readl(base + GPIO_DATA_VALUE); -+ gpio_value >>= shift; -+ gpio_value &= 1; -+ // the output here is the logical output, which is -+ // NOT (value XOR assert) -+ // This just gets there without a conditional -+ gpio_value ^= assert; -+ return !gpio_value; -+} -+ -+void gpio_init(const GPIOValue* table, size_t count) -+{ -+ uint32_t pclk, value; -+ int i; -+ -+ gpio_table = table; -+ gpio_max = count; -+ /* set up the debounce timers (in units of PCLK cycles) */ -+ pclk = ast_get_ahbclk(); -+ /* GPIO_DEBOUNCE_120us */ -+ writel((pclk / 1000000) * 120, AST_GPIO_BASE + GPIO_DEBOUNCE_TIMER_0); -+ /* GPIO_DEBOUNCE_8ms */ -+ writel((pclk / 1000000) * 8000, AST_GPIO_BASE + GPIO_DEBOUNCE_TIMER_1); -+ /* GPIO_DEBOUNCE_16ms */ -+ writel((pclk / 1000000) * 16000, AST_GPIO_BASE + GPIO_DEBOUNCE_TIMER_2); -+ -+ for (i = 0; i < gpio_max; i++) { -+ uint8_t port; -+ uint8_t pin; -+ uint32_t base; -+ uint8_t shift; -+ uint8_t assert; -+ uint8_t init_val; -+ -+ port = GPIO_PORT(gpio_table[i].u8PortPin); -+ pin = GPIO_PIN(gpio_table[i].u8PortPin); -+ base = GPIO_BASES[GPIO_GROUP(port)].u32ddr; -+ shift = GPIO_SHIFT(port, pin); -+ -+ /* set direction */ -+ value = readl(base + GPIO_DIRECTION); -+ if (gpio_table[i].u8PinCFG & GPCFG_OUTPUT_EN) -+ value |= (1 << shift); -+ else -+ value &= ~(1 << shift); -+ writel(value, base + GPIO_DIRECTION); -+ -+ /* set data value */ -+ value = readl(base + GPIO_DATA_VALUE); -+ assert = GPIO_ASSERT(gpio_table[i].u8PinCFG); -+ init_val = gpio_table[i].u8Value; -+ if ((assert && init_val) || !(assert || init_val)) -+ value |= (1 << shift); -+ else -+ value &= ~(1 << shift); -+ writel(value, base + GPIO_DATA_VALUE); -+ -+ /* set debounce */ -+ base = GPIO_BASES[GPIO_GROUP(port)].u32debounce; -+ value = readl(base + GPIO_DEBOUNCE_SEL_0); -+ if (gpio_table[i].u8Debounce & 0x01) -+ value |= (1 << shift); -+ else -+ value &= ~(1 << shift); -+ writel(value, base + GPIO_DEBOUNCE_SEL_0); -+ value = readl(base + GPIO_DEBOUNCE_SEL_1); -+ if (gpio_table[i].u8Debounce & 0x02) -+ value |= (1 << shift); -+ else -+ value &= ~(1 << shift); -+ writel(value, base + GPIO_DEBOUNCE_SEL_1); -+ } -+} -+ -+int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -+{ -+ int n; -+ if (argc < 3) { -+ return 1; -+ } -+ n = simple_strtoul(argv[2], NULL, 0); -+ if (argv[1][0] == 'g') { -+ printf("%d\n", gpio_get_value(n)); -+ return 0; -+ } -+ if (argc < 4) { -+ return 1; -+ } -+ if (argv[1][0] == 's') { -+ int value; -+ value = simple_strtoul(argv[3], NULL, 0); -+ gpio_set_value(n, value); -+ return 0; -+ } -+ -+ return 1; -+} -+U_BOOT_CMD(gpio, 4, 0, do_gpio, -+ "do stuff with gpios [n] [value]", -+ ""); -diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h -new file mode 100644 -index 0000000000..54b7388a22 ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-gpio.h -@@ -0,0 +1,103 @@ -+#ifndef __HW_GPIO_H__ -+#define __HW_GPIO_H__ -+ -+#define GPIO_PORT_A 0 -+#define GPIO_PORT_B 1 -+#define GPIO_PORT_C 2 -+#define GPIO_PORT_D 3 -+#define GPIO_PORT_E 4 -+#define GPIO_PORT_F 5 -+#define GPIO_PORT_G 6 -+#define GPIO_PORT_H 7 -+#define GPIO_PORT_I 8 -+#define GPIO_PORT_J 9 -+#define GPIO_PORT_K 10 -+#define GPIO_PORT_L 11 -+#define GPIO_PORT_M 12 -+#define GPIO_PORT_N 13 -+#define GPIO_PORT_O 14 -+#define GPIO_PORT_P 15 -+#define GPIO_PORT_Q 16 -+#define GPIO_PORT_R 17 -+#define GPIO_PORT_S 18 -+#define GPIO_PORT_T 19 -+#define GPIO_PORT_U 20 -+#define GPIO_PORT_V 21 -+#define GPIO_PORT_W 22 -+#define GPIO_PORT_X 23 -+#define GPIO_PORT_Y 24 -+#define GPIO_PORT_Z 25 -+#define GPIO_PORT_AA 26 -+#define GPIO_PORT_AB 27 -+#define GPIO_PORT_AC 28 -+ -+#define GPIO_PIN_0 0 -+#define GPIO_PIN_1 1 -+#define GPIO_PIN_2 2 -+#define GPIO_PIN_3 3 -+#define GPIO_PIN_4 4 -+#define GPIO_PIN_5 5 -+#define GPIO_PIN_6 6 -+#define GPIO_PIN_7 7 -+ -+#define GPIO_DEBOUNCE_TIMER_0 0x50 -+#define GPIO_DEBOUNCE_TIMER_1 0x54 -+#define GPIO_DEBOUNCE_TIMER_2 0x58 -+ -+/* relative to u32ddr base */ -+#define GPIO_DATA_VALUE 0x00 -+#define GPIO_DIRECTION 0x04 -+/* relative to u32intcfg base */ -+#define GPIO_INT_ENABLE 0x00 -+#define GPIO_INT_SENSE0 0x04 -+#define GPIO_INT_SENSE1 0x18 -+#define GPIO_INT_SENSE2 0x1c -+#define GPIO_INT_STATUS 0x20 -+#define GPIO_RESET_TOL 0x24 -+/* relative to u32debounce base */ -+#define GPIO_DEBOUNCE_SEL_0 0 -+#define GPIO_DEBOUNCE_SEL_1 4 -+/* relative to u32cmdsrc base */ -+#define GPIO_CMD_SRC_0 0 -+#define GPIO_CMD_SRC_1 4 -+ -+#define PORT_PIN(PORT, PIN) (((PORT) << 3) | ((PIN)&0x07)) -+#define GPIO_PIN(N) (N & 0x07) -+#define GPIO_PORT(N) (N >> 3) -+#define GPIO_SHIFT(PORT, PIN) ((PIN) + (((PORT) % 4) * 8)) -+#define GPIO_GROUP(PORT) ((PORT) / 4) -+#define GPIO_ASSERT(N) (((N) >> 4) & 0x01) -+ -+#define ID_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_6) -+#define GRN_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_4) -+#define AMB_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_5) -+#define FORCE_BMC_UPDATE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_0) -+#define TPM_EN_PULSE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_6) -+ -+ -+// GPIO Configuration Register bits -+#define GPCFG_EVENT_TO_SMI (1 << 7) // 1 == enabled -+#define GPCFG_EVENT_TO_IRQ (1 << 6) // 1 == enabled -+#define GPCFG_DEBOUNCE_EN (1 << 5) // 1 == input debounce, 0 == pulse output -+#define GPCFG_ACTIVE_HIGH (1 << 4) // 1 == Active high -+#define GPCFG_LEVEL_TRIG (1 << 3) // 1 == level (default), 0 == edge -+#define GPCFG_OUTPUT_EN (1 << 0) // 1 == Output enabled -+ -+// GPIO Debounce and Blink Configuration Register bits -+#define GPIO_DEBOUNCE_NONE 0x00 -+#define GPIO_DEBOUNCE_60US 0x01 -+#define GPIO_DEBOUNCE_8MS 0x02 -+#define GPIO_DEBOUNCE_16MS 0x03 -+ -+typedef struct { -+ uint8_t u8PortPin; -+ uint8_t u8PinCFG; -+ uint8_t u8Value; -+ uint8_t u8Debounce; -+} GPIOValue; -+ -+void gpio_init(const GPIOValue* table, size_t count); -+void gpio_set_value(int n, int asserted); -+int gpio_get_value(int n); -+ -+#endif /* __HW_GPIO_H__ */ -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index c2a8b33aec..1868c230eb 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -14,6 +14,50 @@ - #include - - #include "ast-g5.h" -+#include "ast-g5-gpio.h" -+ -+/* Names to match the GPIOs */ -+enum gpio_names { -+ GPIO_ID_LED = 0, -+ GPIO_GREEN_LED, -+ GPIO_AMBER_LED, -+ GPIO_FF_UPD_JUMPER, -+ GPIO_ENABLE_TPM_PULSE, -+}; -+ -+#define GPIO_CFG_DEFAULT (GPCFG_ACTIVE_HIGH | GPCFG_LEVEL_TRIG) -+// Active High, Level, Output Disabled -+ -+#define GPIO_CFG_LOW_INPUT (GPCFG_LEVEL_TRIG) -+// Active Low, Level, Output Disabled -+ -+#define GPIO_CFG_FP_LED (GPCFG_OUTPUT_EN) -+// Active High, Pull-up, Level, Output Enabled -+ -+// Format is: -+// GPIO PORT, GPIO PIN Number, GPIO PIN Configuration, GPIO PIN Value, GPIO -+// Debounce/Blink Setting -+static const GPIOValue gpio_table[] = { -+ /* ID LED pin S6 - low asserted, 0=on */ -+ [GPIO_ID_LED] = {ID_LED_PORT_PIN, GPIO_CFG_FP_LED, 0, -+ GPIO_DEBOUNCE_NONE}, -+ -+ /* Green LED pin S4 - high asserted, 0=off */ -+ [GPIO_GREEN_LED] = {GRN_LED_PORT_PIN, GPIO_CFG_FP_LED, 1, -+ GPIO_DEBOUNCE_NONE}, -+ -+ /* Amber LED pin S5 - high asserted, 0=off */ -+ [GPIO_AMBER_LED] = {AMB_LED_PORT_PIN, GPIO_CFG_FP_LED, 1, -+ GPIO_DEBOUNCE_NONE}, -+ -+ /* Force Update Jumper -- pin D0 */ -+ [GPIO_FF_UPD_JUMPER] = {FORCE_BMC_UPDATE_PORT_PIN, GPIO_CFG_LOW_INPUT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ -+ /* Enable Pulse -- pin D6 */ -+ [GPIO_ENABLE_TPM_PULSE] = {PORT_PIN(GPIO_PORT_D, GPIO_PIN_6), -+ GPIO_CFG_DEFAULT, 0, GPIO_DEBOUNCE_8MS}, -+}; - - #define LPC_SNOOP_ADDR 0x80 - #define HICR5 0x080 /* Host Interface Control Register 5 */ -@@ -107,6 +151,7 @@ static void sgpio_init(void) - extern void espi_init(void); - void ast_g5_intel(void) - { -+ gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); - espi_init(); - sgpio_init(); - } -diff --git a/board/aspeed/ast-g5/ast-g5.h b/board/aspeed/ast-g5/ast-g5.h -index 9fd10eccb3..908db1477b 100644 ---- a/board/aspeed/ast-g5/ast-g5.h -+++ b/board/aspeed/ast-g5/ast-g5.h -@@ -3,5 +3,6 @@ - - #include - #include "ast-g5-irq.h" -+#include "ast-g5-gpio.h" - - #endif /* _AST_G5_H_ */ --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch deleted file mode 100644 index c6ee49f57..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch +++ /dev/null @@ -1,96 +0,0 @@ -From d08d22af794eed7b928ab96030a103cfb7bf6ce1 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Fri, 16 Nov 2018 14:59:04 -0800 -Subject: [PATCH] Update Force Firmware Update Jumper to use new gpio API - -Add a function that allows easy reading of the FFUJ from other -functions, such as autoboot. - -Change-Id: I8ead931e9dd828522095a0ef386875be652ec885 -Signed-off-by: Vernon Mauery - ---- - arch/arm/include/asm/arch-aspeed/ast-g5-intel.h | 19 +++++++++++++++++++ - arch/arm/include/asm/arch-aspeed/platform.h | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 5 +++++ - common/autoboot.c | 6 ++++++ - 4 files changed, 31 insertions(+) - create mode 100644 arch/arm/include/asm/arch-aspeed/ast-g5-intel.h - -diff --git a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -new file mode 100644 -index 0000000..cd9a099 ---- /dev/null -+++ b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -@@ -0,0 +1,19 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#ifndef __AST_INTEL_G5_H__ -+#define __AST_INTEL_G5_H__ -+ -+#define AST_G5_INTEL 1 -+ -+#ifndef __ASSEMBLY__ -+int intel_force_firmware_jumper_enabled(void); -+#endif -+ -+#endif /* __AST_INTEL_G5_H__ */ -diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h -index 92ea33b..3b06e52 100644 ---- a/arch/arm/include/asm/arch-aspeed/platform.h -+++ b/arch/arm/include/asm/arch-aspeed/platform.h -@@ -27,6 +27,7 @@ - #include - #elif defined(AST_SOC_G5) - #include -+#include - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - #else - #err "No define for platform.h" -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 069e7a3..144765a 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -145,6 +145,11 @@ static void sgpio_init(void) - writel(value, AST_GPIO_BASE + GPIO254); - } - -+int intel_force_firmware_jumper_enabled(void) -+{ -+ return gpio_get_value(GPIO_FF_UPD_JUMPER); -+} -+ - extern void espi_init(void); - void ast_g5_intel(void) - { -diff --git a/common/autoboot.c b/common/autoboot.c -index c52bad8..d66c0fa 100644 ---- a/common/autoboot.c -+++ b/common/autoboot.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - - DECLARE_GLOBAL_DATA_PTR; - -@@ -259,6 +260,11 @@ static int abortboot(int bootdelay) - { - int abort = 0; - -+# ifdef AST_G5_INTEL -+ if (intel_force_firmware_jumper_enabled()) -+ return 1; -+# endif -+ - if (bootdelay >= 0) - abort = __abortboot(bootdelay); - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch deleted file mode 100644 index 26b4c4fc9..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch +++ /dev/null @@ -1,158 +0,0 @@ -From 320cf189fd017e3578b6949ff640213d7bddb20c Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Fri, 16 Nov 2018 14:44:49 -0800 -Subject: [PATCH] Add basic timer support for Aspeed g5 in U-Boot - -Timers will be used for timing events and making blinky LEDs. This just -adds the API and infrastructure. - -Change-Id: I8ff03b26070b43a47fb970ddf6124d6c3f29b058 -Signed-off-by: Vernon Mauery - ---- - board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 1 + - board/aspeed/ast-g5/ast-g5-timer.c | 66 ++++++++++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-timer.h | 27 ++++++++++++++++ - board/aspeed/ast-g5/ast-g5.h | 1 + - 5 files changed, 96 insertions(+) - create mode 100644 board/aspeed/ast-g5/ast-g5-timer.c - create mode 100644 board/aspeed/ast-g5/ast-g5-timer.h - -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 2970ae5..9022433 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -3,3 +3,4 @@ obj-y += ast-g5-intel.o - obj-y += ast-g5-espi.o - obj-y += ast-g5-irq.o - obj-y += ast-g5-gpio.o -+obj-y += ast-g5-timer.o -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 144765a..6e45cb4 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -15,6 +15,7 @@ - - #include "ast-g5.h" - #include "ast-g5-gpio.h" -+#include "ast-g5-timer.h" - - /* Names to match the GPIOs */ - enum gpio_names { -diff --git a/board/aspeed/ast-g5/ast-g5-timer.c b/board/aspeed/ast-g5/ast-g5-timer.c -new file mode 100644 -index 0000000..5615722 ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-timer.c -@@ -0,0 +1,66 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "ast-g5.h" -+#include "ast-g5-timer.h" -+#include "ast-g5-irq.h" -+ -+static const int timer_irqs[] = {16, 17, 18, 35, 37, 37, 38, 39}; -+/* offsets from AST_TIMER_BASE for each timer */ -+static const uint32_t timer_bases[] = {0, 0x10, 0x20, 0x40, -+ 0x50, 0x60, 0x70, 0x80}; -+#define TIMER_1MHZ_CLK_COUNT 1000000u -+#define TIMER_ENABLE 1 -+#define TIMER_1MHZ_CLK_SEL 2 -+#define TIMER_ENABLE_IRQ 4 -+#define TIMER_ENABLE_PULSE 8 -+#define TIMER_CONTROL 0x30 -+#define TIMER_RELOAD 0x04 -+ -+void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler) -+{ -+ if (n < 0 || n > 7) { -+ return; -+ } -+ uint32_t tctrl = readl(AST_TIMER_BASE + TIMER_CONTROL); -+ writel(tctrl & ~(0x0f << (n * 4)), AST_TIMER_BASE + TIMER_CONTROL); -+ -+ // figure out best base for requested frequency -+ // (this will give 1MHz clock preference if period is within 1ms of -+ // requested) -+ uint32_t v = TIMER_1MHZ_CLK_COUNT / freq; -+ if (v > 1000 || v * freq == TIMER_1MHZ_CLK_COUNT) { -+ tctrl |= (TIMER_1MHZ_CLK_SEL << (n * 4)); -+ } else { -+ uint32_t pclk = ast_get_ahbclk(); -+ v = pclk / freq; -+ } -+ writel(v, AST_TIMER_BASE + timer_bases[n] + TIMER_RELOAD); -+ if (handler) { -+ request_irq(timer_irqs[n], handler); -+ tctrl |= (TIMER_ENABLE_IRQ << (n * 4)); -+ } -+ tctrl |= (TIMER_ENABLE << (n * 4)); -+ writel(tctrl, AST_TIMER_BASE + TIMER_CONTROL); -+} -+ -+void timer_disable(int n) -+{ -+ if (n < 0 || n > 7) { -+ return; -+ } -+ uint32_t tctrl = readl(AST_TIMER_BASE + TIMER_CONTROL); -+ writel(tctrl & ~(0x0f << (n * 4)), AST_TIMER_BASE + TIMER_CONTROL); -+} -diff --git a/board/aspeed/ast-g5/ast-g5-timer.h b/board/aspeed/ast-g5/ast-g5-timer.h -new file mode 100644 -index 0000000..4b1ac28 ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-timer.h -@@ -0,0 +1,27 @@ -+/* -+ * Copyright 2018 Intel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#ifndef __AST_G5_TIMER_H__ -+#define __AST_G5_TIMER_H__ -+ -+#include -+ -+#define TIMER_1 0 -+#define TIMER_2 1 -+#define TIMER_3 2 -+#define TIMER_4 3 -+#define TIMER_5 4 -+#define TIMER_6 5 -+#define TIMER_7 6 -+#define TIMER_8 7 -+ -+void timer_enable(int n, uint32_t freq, interrupt_handler_t handler); -+void timer_disable(int n); -+ -+#endif /* __AST_G5_TIMER_H__ */ -diff --git a/board/aspeed/ast-g5/ast-g5.h b/board/aspeed/ast-g5/ast-g5.h -index 908db14..28fe5ea 100644 ---- a/board/aspeed/ast-g5/ast-g5.h -+++ b/board/aspeed/ast-g5/ast-g5.h -@@ -4,5 +4,6 @@ - #include - #include "ast-g5-irq.h" - #include "ast-g5-gpio.h" -+#include "ast-g5-timer.h" - - #endif /* _AST_G5_H_ */ diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch deleted file mode 100644 index e376001b3..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0012-Add-status-and-ID-LED-support.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 2db86017f1cd48da9f6c102665d5ae3d1efe48cc Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Wed, 14 Nov 2018 12:16:53 -0800 -Subject: [PATCH] Add status and ID LED support - -Add status (amber and green) and ID (blue) LED support. In the -bootloader phase, the LEDs should be blinking. When booting linux, they -should turn to a fixed state. - -Signed-off-by: Vernon Mauery -Signed-off-by: James Feist -Signed-off-by: AppaRao Puli -Change-Id: Ic9595621b21000ef465ff57ed2047855296e2714 ---- - board/aspeed/ast-g5/ast-g5-intel.c | 113 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 113 insertions(+) - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 6e45cb4..e749992 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -146,6 +146,112 @@ static void sgpio_init(void) - writel(value, AST_GPIO_BASE + GPIO254); - } - -+/* running the timer at 48 hertz will easily give a 24Hz blink */ -+#define TICK_HZ 48 -+#define BLINK_DELAY(HZ) ((int)((TICK_HZ / (HZ)) / 2) - 1) -+typedef enum { -+ /* -+ * Identifies the control request for the ID LED. -+ */ -+ EIDLED_Initialize = 0, -+ EIDLED_Tick, -+ EIDLED_Toggle, -+ EIDLED_Off, -+ EIDLED_On, -+ EIDLED_Blink, -+ EIDLED_Blink_24HZ = EIDLED_Blink + BLINK_DELAY(24), -+ EIDLED_Blink_12HZ = EIDLED_Blink + BLINK_DELAY(12), -+ EIDLED_Blink_6HZ = EIDLED_Blink + BLINK_DELAY(6), -+ EIDLED_Blink_3HZ = EIDLED_Blink + BLINK_DELAY(3), -+ EIDLED_Blink_1HZ = EIDLED_Blink + BLINK_DELAY(1), -+ EIDLED_Blink_0_5HZ = EIDLED_Blink + BLINK_DELAY(0.5), -+} EIDLEDControl; -+ -+struct led_info { -+ int gpio; -+ EIDLEDControl mode; -+ int count; -+ int state; -+}; -+ -+static struct led_info s_led_info[] = { -+ /* BMC Executing bootloader (Default) :- -+ * ChassisID: Blinking Blue 3Hz, StatusLED: Blinking Green 1Hz */ -+ [GPIO_ID_LED] = {GPIO_ID_LED, EIDLED_Blink_3HZ, 1, 0}, -+ [GPIO_GREEN_LED] = {GPIO_GREEN_LED, EIDLED_Blink_1HZ, 0, 0}, -+ [GPIO_AMBER_LED] = {GPIO_AMBER_LED, EIDLED_Off, 0, 0}, -+}; -+ -+extern void gpio_set_value(int n, int asserted); -+void id_led_control(int id, int action) -+{ -+ if (id >= ARRAY_SIZE(s_led_info)) { -+ return; -+ } -+ /* don't bother with LEDs that are not initialized */ -+ if (EIDLED_Initialize == s_led_info[id].mode) { -+ return; -+ } -+ -+ /* check for a blinker action */ -+ if (EIDLED_Tick == action) { -+ if (s_led_info[id].mode < EIDLED_Blink) { -+ return; -+ } -+ /* check countdown for blink */ -+ if (s_led_info[id].count == 0) { -+ s_led_info[id].count = -+ s_led_info[id].mode - EIDLED_Blink; -+ s_led_info[id].state = !s_led_info[id].state; -+ } else { -+ s_led_info[id].count--; -+ return; -+ } -+ } else if (EIDLED_Toggle == action) { -+ s_led_info[id].state = !s_led_info[id].state; -+ s_led_info[id].mode = -+ s_led_info[id].state ? EIDLED_On : EIDLED_Off; -+ } else if (action > EIDLED_Toggle) { -+ s_led_info[id].mode = action; -+ if (EIDLED_Off == action) { -+ s_led_info[id].state = 0; -+ } else if (EIDLED_On == action) { -+ s_led_info[id].state = 1; -+ } else if (action >= EIDLED_Blink) { -+ s_led_info[id].count = action - EIDLED_Blink; -+ /* wait for the next tick */ -+ return; -+ } -+ } else if (EIDLED_Initialize == action) { -+ if (s_led_info[id].mode >= EIDLED_Blink) { -+ s_led_info[id].count = -+ s_led_info[id].mode - EIDLED_Blink; -+ } -+ } -+ gpio_set_value(s_led_info[id].gpio, s_led_info[id].state); -+} -+ -+static void timer8_irq_handler(void *regs) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(s_led_info); i++) { -+ id_led_control(i, EIDLED_Tick); -+ } -+} -+ -+void timer8_init(void) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(s_led_info); i++) { -+ id_led_control(i, EIDLED_Initialize); -+ } -+ -+ /* set up the timer to fire at TICK_HZ HZ */ -+ timer_enable(TIMER_8, TICK_HZ, timer8_irq_handler); -+} -+ - int intel_force_firmware_jumper_enabled(void) - { - return gpio_get_value(GPIO_FF_UPD_JUMPER); -@@ -157,4 +263,11 @@ void ast_g5_intel(void) - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); - espi_init(); - sgpio_init(); -+ timer8_init(); -+ if (intel_force_firmware_jumper_enabled()) { -+ /* FFUJ mode:- ChassisID: Solid Blue, StatusLED: Solid Amber */ -+ id_led_control(GPIO_ID_LED, EIDLED_On); -+ id_led_control(GPIO_GREEN_LED, EIDLED_Off); -+ id_led_control(GPIO_AMBER_LED, EIDLED_On); -+ } - } --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch deleted file mode 100644 index 4714dd6cc..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0013-aspeed-Add-Pwm-Driver.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 039b9a278a4d075e455a38ec93171dc812aec8b2 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Fri, 16 Nov 2018 15:57:57 -0800 -Subject: [PATCH 1/1] aspeed: add Pwm Driver - -Change-Id: Ia8b80212f7c70aafcc6a71782936ec95cf9b7f38 -Signed-off-by: James Feist ---- - board/aspeed/ast-g5/ast-g5-intel.c | 113 +++++++++++++++++++++++++++++ - 1 file changed, 113 insertions(+) - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e74999223b..74e218dfd0 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -257,9 +257,122 @@ int intel_force_firmware_jumper_enabled(void) - return gpio_get_value(GPIO_FF_UPD_JUMPER); - } - -+/* PWM offsets */ -+ -+#define PWM_BASE_ADDR 0x1E786000 -+#define PWM_CONTROL 0x00 -+#define PWM_CLOCK_SELECTION 0x04 -+#define PWM_DUTY_CYCLE 0x08 -+#define PWM_M0 0x10 -+#define PWM_M1 0x14 -+#define PWM_N0 0x18 -+#define PWM_N1 0x1c -+#define PWM_CONTROL_EXT 0x40 -+#define PWM_CLOCK_SEL_EXT 0x44 -+#define PWM_O0 0x50 -+#define PWM_O1 0x54 -+#define PWM_CHANNEL_COUNT 8 -+ -+#define PWM_CLK_ENABLE BIT(0) -+#define PWM_DUTY(PCT) (((PCT) * 128) / 100) -+#define DEFAULT_PWM_DUTY_VALUE PWM_DUTY(57) -+ -+ -+static inline uint32_t ast_scu_read(uint32_t reg) -+{ -+ uint32_t val = readl(AST_SCU_BASE + reg); -+ -+ debug("ast_scu_read : reg = 0x%08x, val = 0x%08x\n", reg, val); -+ return val; -+} -+ -+static inline void ast_scu_write(uint32_t val, uint32_t reg) -+{ -+ debug("ast_scu_write : reg = 0x%08x, val = 0x%08x\n", reg, val); -+ -+ writel(SCU_PROTECT_UNLOCK, AST_SCU_BASE); -+ writel(val, AST_SCU_BASE + reg); -+#ifdef CONFIG_AST_SCU_LOCK -+ writel(0xaa, AST_SCU_BASE); -+#endif -+} -+ -+static void set_pwm_duty_cycle(int duty) -+{ -+ uint32_t chan; -+ uint32_t val; -+ -+ /* enable pwm channels */ -+ for (chan = 0; chan < PWM_CHANNEL_COUNT; chan++) { -+ uint32_t base = chan < 4 ? PWM_BASE_ADDR : PWM_BASE_ADDR + 0x40; -+ uint8_t ch_duty_shift = 16 * (chan & 0x1); -+ uint8_t ch_pair = (chan & 0x3) / 2; -+ -+ /* enable pwm for the channel */ -+ val = readl(base); -+ val |= ((1 << (chan & 0x3)) << 8); -+ writel(val, base); -+ -+ /* set duty cycle */ -+ val = readl(base + PWM_DUTY_CYCLE + ch_pair * 4); -+ val &= ~(0xffff << ch_duty_shift); -+ val |= (((uint32_t)duty) << 8) << ch_duty_shift; -+ writel(val, base + PWM_DUTY_CYCLE + ch_pair * 4); -+ } -+ -+} -+ -+static void pwm_init(void) -+{ -+ uint32_t val; -+ -+ /* select pwm 0-7 */ -+ val = ast_scu_read(AST_SCU_FUN_PIN_CTRL3); -+ val |= (SCU_FUN_PIN_VPIG7 | SCU_FUN_PIN_VPIG6 | SCU_FUN_PIN_VPIG5 -+ | SCU_FUN_PIN_VPIG4 | SCU_FUN_PIN_VPIG3 | SCU_FUN_PIN_VPIG2 -+ | SCU_FUN_PIN_VPIG1 | SCU_FUN_PIN_VPIG0); -+ ast_scu_write(val, AST_SCU_FUN_PIN_CTRL3); -+ -+ /* disable video output mux */ -+ val = ast_scu_read(AST_SCU_FUN_PIN_CTRL5); -+ val &= 0xffffffcf; -+ ast_scu_write(val, AST_SCU_FUN_PIN_CTRL5); -+ val = readl(AST_SCU_FUN_PIN_CTRL6); -+ val &= 0xfffffffc; -+ ast_scu_write(val, AST_SCU_FUN_PIN_CTRL6); -+ -+ /* SCU reset of PWM module */ -+ val = ast_scu_read(AST_SCU_RESET); -+ val |= SCU_RESET_PWM; -+ ast_scu_write(val, AST_SCU_RESET); -+ val &= ~SCU_RESET_PWM; -+ ast_scu_write(val, AST_SCU_RESET); -+ -+ /* set M, N, and 0 clock regs to 0 */ -+ writel(0, PWM_BASE_ADDR + PWM_M0); -+ writel(0, PWM_BASE_ADDR + PWM_N0); -+ writel(0, PWM_BASE_ADDR + PWM_O0); -+ -+ /* disable fans and tachos, set M type control */ -+ writel(0x1, PWM_BASE_ADDR + PWM_CONTROL); -+ writel(0x1, PWM_BASE_ADDR + PWM_CONTROL_EXT); -+ -+ set_pwm_duty_cycle(DEFAULT_PWM_DUTY_VALUE); -+ -+ /* set up clock type M: period = 127 units at 24MHz/8 (resulting ~23kHz period) */ -+ writel(0x7f30, PWM_BASE_ADDR + PWM_CLOCK_SELECTION); -+ -+ /* enable pwm-tacho */ -+ -+ val = readl(PWM_BASE_ADDR + PWM_CONTROL); -+ val |= PWM_CLK_ENABLE; -+ writel(val, PWM_BASE_ADDR + PWM_CONTROL); -+} -+ - extern void espi_init(void); - void ast_g5_intel(void) - { -+ pwm_init(); - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); - espi_init(); - sgpio_init(); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch deleted file mode 100644 index 22191f07a..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0014-Keep-interrupts-enabled-until-last-second.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 040c9c13778076403198ce93f43c4aa3a1ed3907 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Sat, 17 Nov 2018 14:17:27 -0800 -Subject: [PATCH] Keep interrupts enabled until last second - -The U-Boot bootm command disabled interrupts almost first thing. This -would prevent a person hitting the power button on the host immediatly -after AC on because the BMC would fail to respond to the espi interrupts -and the host would power off. - -Change-Id: I6c0fb5cca1be6c326da4c9a3d3dfbab89dac9928 -Signed-off-by: Vernon Mauery - ---- - board/aspeed/ast-g5/ast-g5-intel.c | 8 ++++++++ - common/bootm.c | 7 ------- - common/bootm_os.c | 1 + - 3 files changed, 9 insertions(+), 7 deletions(-) - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index c7ae566..01f8a13 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -255,6 +255,14 @@ int intel_force_firmware_jumper_enabled(void) - return gpio_get_value(GPIO_FF_UPD_JUMPER); - } - -+void arch_preboot_os(void) -+{ -+ // last second before booting... set the LEDs -+ id_led_control(GPIO_ID_LED, EIDLED_On); -+ id_led_control(GPIO_GREEN_LED, EIDLED_On); -+ id_led_control(GPIO_AMBER_LED, EIDLED_Off); -+} -+ - /* PWM offsets */ - - #define PWM_BASE_ADDR 0x1E786000 -diff --git a/common/bootm.c b/common/bootm.c -index 2431019..46909ec 100644 ---- a/common/bootm.c -+++ b/common/bootm.c -@@ -602,7 +602,6 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int states, bootm_headers_t *images, int boot_progress) - { - boot_os_fn *boot_fn; -- ulong iflag = 0; - int ret = 0, need_boot_fn; - - images->state |= states; -@@ -626,7 +625,6 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - if (!ret && (states & BOOTM_STATE_LOADOS)) { - ulong load_end; - -- iflag = bootm_disable_interrupts(); - ret = bootm_load_os(images, &load_end, 0); - if (ret == 0) - lmb_reserve(&images->lmb, images->os.load, -@@ -670,8 +668,6 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - BOOTM_STATE_OS_BD_T | BOOTM_STATE_OS_PREP | - BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO); - if (boot_fn == NULL && need_boot_fn) { -- if (iflag) -- enable_interrupts(); - printf("ERROR: booting os '%s' (%d) is not supported\n", - genimg_get_os_name(images->os.os), images->os.os); - bootstage_error(BOOTSTAGE_ID_CHECK_BOOT_OS); -@@ -711,9 +707,6 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - - /* Deal with any fallout */ - err: -- if (iflag) -- enable_interrupts(); -- - if (ret == BOOTM_ERR_UNIMPLEMENTED) - bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL); - else if (ret == BOOTM_ERR_RESET) -diff --git a/common/bootm_os.c b/common/bootm_os.c -index 9ec84bd..b56eb39 100644 ---- a/common/bootm_os.c -+++ b/common/bootm_os.c -@@ -476,6 +476,7 @@ __weak void arch_preboot_os(void) - int boot_selected_os(int argc, char * const argv[], int state, - bootm_headers_t *images, boot_os_fn *boot_fn) - { -+ disable_interrupts(); - arch_preboot_os(); - boot_fn(state, argc, argv, images); - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch deleted file mode 100644 index d93d9c4a1..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0015-Rewrite-memmove-to-optimize-on-word-transfers.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 711c7bc5a07b62e8369bc76a9db265c960bacef8 Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Mon, 19 Nov 2018 11:04:02 -0800 -Subject: [PATCH] Rewrite memmove to optimize on word transfers - -Reading from the flash at boot time was using byte-sized transfers, -which ultimately turns into four word transfers over spi for every real -word read. This change breaks memmove down into a header, body, and -trailer, where the body is all done with word-sized transfers. - -Change-Id: Ie0a1f3261e507fb34a908571883d9bf04a1059ee -Signed-off-by: Vernon Mauery - ---- - lib/string.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++---------- - 1 file changed, 64 insertions(+), 13 deletions(-) - -diff --git a/lib/string.c b/lib/string.c -index 67d5f6a..0bf472f 100644 ---- a/lib/string.c -+++ b/lib/string.c -@@ -505,26 +505,77 @@ void * memcpy(void *dest, const void *src, size_t count) - * - * Unlike memcpy(), memmove() copes with overlapping areas. - */ --void * memmove(void * dest,const void *src,size_t count) -+void *memmove(void *dest, const void *src, size_t count) - { -- char *tmp, *s; -- -- if (src == dest) -+ unsigned char *bdst = (unsigned char *)dest; -+ const unsigned char *bsrc = (const unsigned char *)src; -+ unsigned long *ldst; -+ const unsigned long *lsrc; -+ size_t unaligned_header = 0, unaligned_trailer = 0; -+ size_t unaligned_src = -+ (sizeof(*ldst) - (size_t)src) & (sizeof(*ldst) - 1); -+ size_t unaligned_dst = -+ (sizeof(*ldst) - (size_t)dest) & (sizeof(*ldst) - 1); -+ -+ if (src == dest || !count) - return dest; - -+ if (unaligned_src || unaligned_dst) { -+ if (unaligned_dst != unaligned_src) { -+ unaligned_header = count; -+ } else { -+ unaligned_header = unaligned_src; -+ if (unaligned_header > count) { -+ unaligned_header = count; -+ } -+ } -+ count -= unaligned_header; -+ } -+ if (count & (sizeof(*ldst) - 1)) { -+ unaligned_trailer = count & (sizeof(*ldst) - 1); -+ count -= unaligned_trailer; -+ } -+ - if (dest <= src) { -- tmp = (char *) dest; -- s = (char *) src; -- while (count--) -- *tmp++ = *s++; -+ /* possible un-aligned bytes */ -+ while (unaligned_header--) -+ *bdst++ = *bsrc++; -+ -+ /* aligned words */ -+ ldst = (unsigned long *)bdst; -+ lsrc = (const unsigned long *)bsrc; -+ while (count >= sizeof(*ldst)) { -+ count -= sizeof(*ldst); -+ *ldst++ = *lsrc++; - } -- else { -- tmp = (char *) dest + count; -- s = (char *) src + count; -- while (count--) -- *--tmp = *--s; -+ -+ /* possibly un-aligned bytes */ -+ bdst = (unsigned char *)ldst; -+ bsrc = (const unsigned char *)lsrc; -+ while (unaligned_trailer--) -+ *bdst++ = *bsrc++; -+ } else { -+ bdst += unaligned_header + count + unaligned_trailer; -+ bsrc += unaligned_header + count + unaligned_trailer; -+ -+ /* possibly un-aligned bytes */ -+ while (unaligned_trailer--) -+ *--bdst = *--bsrc; -+ -+ /* aligned words */ -+ ldst = (unsigned long *)bdst; -+ lsrc = (unsigned long *)bsrc; -+ while (count >= sizeof(*ldst)) { -+ count -= sizeof(*ldst); -+ *--ldst = *--lsrc; - } - -+ /* possibly un-aligned bytes */ -+ bdst = (unsigned char *)ldst; -+ bsrc = (const unsigned char *)lsrc; -+ while (unaligned_header--) -+ *--bdst = *--bsrc; -+ } - return dest; - } - #endif diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch deleted file mode 100644 index 8a63edbb7..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0019-u-boot-full-platform-reset-espi-oob-ready.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 9b05a276af65dd436f30b1b2680a09821c5a81aa Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Mon, 17 Dec 2018 20:37:23 -0800 -Subject: [PATCH] u-boot: full platform reset + espi oob-ready - -If the platform is strapped for fast reset, have platform-g5.S do a full -reset and then immediately set oob-ready so the espi master controller -can initiate communication. - -Signed-off-by: Vernon Mauery - ---- - arch/arm/mach-aspeed/platform_g5.S | 13 ++++++++++++- - 1 file changed, 12 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S -index 2ac1ca4..66427b6 100644 ---- a/arch/arm/mach-aspeed/platform_g5.S -+++ b/arch/arm/mach-aspeed/platform_g5.S -@@ -139,7 +139,7 @@ - But if FW has other initial code executed before platform.S, then it should use WDT_SOC mode. - Use WDT_Full may clear the initial result of prior initial code. - ******************************************************************************/ --//#define ASTMMC_INIT_RESET_MODE_FULL -+#define ASTMMC_INIT_RESET_MODE_FULL - - /****************************************************************************** - There is a compatibility issue for Hynix DDR4 SDRAM. -@@ -563,6 +563,17 @@ wait_first_reset: - *******************************************/ - - bypass_first_reset: -+ /* Timing from ESPI master requires OOB channel ready bit be set early */ -+ ldr r0, =0x1e6e2070 @ check strapping for eSPI mode -+ tst r0, #0x02000000 @ Test for bit 25 - eSPI Mode -+ beq espi_early_init_done @ if bit 25 clear, dont set OOB ready -+ -+ ldr r0, =0x1e6ee000 -+ ldr r1, [r0] @ ESPI000: ESPI Engine Control Reg -+ orr r1, r1, #0x00000010 @ Set OOB Channel Ready bit -+ str r1, [r0] -+espi_early_init_done: -+ - /* Enable Timer separate clear mode */ - ldr r0, =0x1e782038 - mov r1, #0xAE diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch deleted file mode 100644 index afdd610b3..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Add-system-reset-status-support.patch +++ /dev/null @@ -1,164 +0,0 @@ -From 54616ade08517374200a332e50f68ee9d0fbf5c5 Mon Sep 17 00:00:00 2001 -From: Yong Li -Date: Tue, 9 Apr 2019 14:42:05 +0800 -Subject: [PATCH] Add system reset status support - -Will display the reset reasons and other CPU information in u-boot, -and save the reset reasons into kernel command line, -for applications to query. - -Change-Id: I87ada3ecf14368519e4d09035bb1e09fdc05469b -Signed-off-by: Yong Li -Signed-off-by: AppaRao Puli - ---- - arch/arm/include/asm/arch-aspeed/platform.h | 2 + - arch/arm/mach-aspeed/ast-scu.c | 4 ++ - board/aspeed/ast-g5/ast-g5-intel.c | 73 +++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5.c | 7 +++ - 4 files changed, 86 insertions(+) - -diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h -index 3b06e52..4e4140d 100644 ---- a/arch/arm/include/asm/arch-aspeed/platform.h -+++ b/arch/arm/include/asm/arch-aspeed/platform.h -@@ -29,6 +29,8 @@ - #include - #include - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -+#define CONFIG_BOARD_LATE_INIT 1 /* Call board_late_init */ -+#define CONFIG_DISPLAY_CPUINFO 1 - #else - #err "No define for platform.h" - #endif -diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index 3a9ba05..976c59b 100644 ---- a/arch/arm/mach-aspeed/ast-scu.c -+++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -494,6 +494,9 @@ void ast_scu_sys_rest_info(void) - { - u32 rest = ast_scu_read(AST_SCU_SYS_CTRL); - -+#ifdef AST_SOC_G5 -+ printf("RST : 0x%02x\n", rest); -+#else - if (rest & SCU_SYS_EXT_RESET_FLAG) { - printf("RST : External\n"); - ast_scu_write(SCU_SYS_EXT_RESET_FLAG, AST_SCU_SYS_CTRL); -@@ -506,6 +509,7 @@ void ast_scu_sys_rest_info(void) - } else { - printf("RST : CLK en\n"); - } -+#endif - } - - u32 ast_scu_get_vga_memsize(void) -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 01f8a13..e0bf9ee 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -303,6 +303,79 @@ static inline void ast_scu_write(uint32_t val, uint32_t reg) - #endif - } - -+ -+static void update_bootargs_cmd(const char *key, const char *value) -+{ -+ int buf_len; -+ char *buf; -+ char *cmdline; -+ char comp_key[128]; -+ -+ if (!key || (key[0] == '\0')) { -+ printf("%s - Empty key not allowed\n", __func__); -+ return; -+ } -+ -+ cmdline = getenv("bootargs"); -+ -+ /* Allocate space for maximum possible new command line */ -+ if (value) -+ buf_len = strlen(cmdline) + strlen(key) + 3 + strlen(value); -+ else -+ buf_len = strlen(cmdline) + strlen(key) + 3; -+ -+ buf = malloc(buf_len); -+ if (!buf) { -+ printf("%s: out of memory\n", __func__); -+ return; -+ } -+ memset(buf, 0, buf_len); -+ -+ if (!cmdline) { -+ /* lets add key-value, though bootargs are empty */ -+ snprintf(buf, buf_len, "%s=%s", key, (value ? value : "")); -+ setenv("bootargs", buf); -+ free(buf); -+ return; -+ } -+ -+ snprintf(comp_key, sizeof(comp_key), "%s=", key); -+ char *start = strstr(cmdline, comp_key); -+ -+ /* Check for full word match. Match should be start of cmdline -+ * or there should be space before match */ -+ if (start && ((start == cmdline) || (*(start-1) == ' '))) { -+ char *end = strchr(start, ' '); -+ strncpy(buf, cmdline, (start - cmdline)); -+ -+ if (end) -+ snprintf(buf, buf_len, "%s%s=%s %s", buf, key, -+ (value ? value : ""), end+1); -+ else -+ snprintf(buf, buf_len, "%s%s=%s", buf, key, -+ (value ? value : "")); -+ } else { -+ snprintf(buf, buf_len, "%s %s=%s", cmdline, key, -+ (value ? value : "")); -+ } -+ -+ setenv("bootargs", buf); -+ free(buf); -+} -+ -+void ast_g5_intel_late_init(void) -+{ -+ char value[32]; -+ u32 reset_reason = 0; -+ -+ /* save and clear reset status */ -+ reset_reason = ast_scu_read(AST_SCU_SYS_CTRL); -+ snprintf(value, sizeof(value), "0x%x", reset_reason); -+ ast_scu_write(0, AST_SCU_SYS_CTRL); -+ -+ update_bootargs_cmd("resetreason", value); -+} -+ - static void pwm_init(void) - { - uint32_t val; -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index d41ef9c..0953677 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -19,6 +19,7 @@ - DECLARE_GLOBAL_DATA_PTR; - - extern void ast_g5_intel(void); -+extern void ast_g5_intel_late_init(void); - - int board_early_init_f(void) - { -@@ -40,6 +41,12 @@ int board_init(void) - return 0; - } - -+int board_late_init(void) -+{ -+ ast_g5_intel_late_init(); -+ return 0; -+} -+ - int dram_init(void) - { - u32 vga = ast_scu_get_vga_memsize(); diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch deleted file mode 100644 index 6949856db..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0020-Enable-PCIe-L1-support.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 647cc2538ed6b64054c742b4668386fda9394221 Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo -Date: Tue, 8 Jan 2019 13:33:15 -0800 -Subject: [PATCH] Enable PCIe L1 support - -This commit enables PCIe L1 support using magic registers. - -Signed-off-by: Jae Hyun Yoo - ---- - arch/arm/mach-aspeed/platform_g5.S | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm/mach-aspeed/platform_g5.S b/arch/arm/mach-aspeed/platform_g5.S -index 66427b6..b404353 100644 ---- a/arch/arm/mach-aspeed/platform_g5.S -+++ b/arch/arm/mach-aspeed/platform_g5.S -@@ -2432,6 +2432,18 @@ spi_cbr_end: - bic r1, r1, #0x00400000 - str r1, [r0] - -+ ldr r0, =0x1e6ed07c @ Enable PCIe L1 support -+ ldr r1, =0xa8 -+ str r1, [r0] -+ -+ ldr r0, =0x1e6ed068 -+ ldr r1, =0xc81f0a -+ str r1, [r0] -+ -+ ldr r0, =0x1e6ed07c -+ mov r1, #0 -+ str r1, [r0] -+ - /****************************************************************************** - Configure MAC timing - ******************************************************************************/ diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch deleted file mode 100644 index 915b0197f..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch +++ /dev/null @@ -1,71 +0,0 @@ -From c2e2496dfd8cde56e32274b11968185a77f40736 Mon Sep 17 00:00:00 2001 -From: Kuiying Wang -Date: Tue, 10 Dec 2019 14:58:10 +0800 -Subject: [PATCH] AST2600: Enable host searial port clock configuration in - u-boot - -In u-boot could read env variable "hostsearialcfg" and set the corresponding -clock for host searail port. - -Tested: -setenv hostsearialcfg 1, speed is set to 192Mhz (baud rate 921600) -other value, speed is set to 24Mhz(baud rate 115200) -by default is 24Mhz. - -Signed-off-by: Kuiying Wang ---- - board/aspeed/ast2600_intel/intel.c | 35 +++++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index a02e246d0d81..eb9b3959625e 100644 ---- a/board/aspeed/ast2600_intel/intel.c -+++ b/board/aspeed/ast2600_intel/intel.c -@@ -36,9 +36,44 @@ int gpio_abort(void) - } - - #define SCU_BASE 0x1E6E2000 -+#define SCU_338 0x338 //Generate UART 24 MHz Reference from UXCLK -+#define SCU_33C 0x33c //Generate UART 24 MHz Reference from HUXCLK -+#define SCU_338_R_VALUE_192MHZ 0x8e -+#define SCU_338_N_VALUE_192MHZ 0x3c3 -+#define SCU_338_R_VALUE_24MHZ 0x06 -+#define SCU_338_N_VALUE_24MHZ 0x145 -+#define HOST_SERIAL_HIGH_SPEED_192MHZ 1 -+#define R_VALUE_BITS 8 -+#define V_VALUE_BITS 10 -+#define R_V_VALUE_MASK (1 << (R_VALUE_BITS + V_VALUE_BITS)) -+ - int misc_init_r(void) - { - /* This is called near the end of the _r init sequence */ -+ /* By default host serail is set 24Mhz */ -+ uint32_t host_serial_cfg = 0; -+ char *host_serial_cfg_txt = NULL; -+ -+ /* Config the uart clock source based on environment configuration */ -+ host_serial_cfg_txt = env_get("hostserialcfg"); -+ -+ if (host_serial_cfg_txt != NULL) -+ host_serial_cfg = simple_strtoul(host_serial_cfg_txt, NULL, 16); -+ -+ if (host_serial_cfg > HOST_SERIAL_HIGH_SPEED_192MHZ || host_serial_cfg < 0) { -+ printf("Invalid hostserialcfg %x, 24Mhz is set by default!\n", host_serial_cfg); -+ host_serial_cfg = 0; -+ } -+ -+ if (host_serial_cfg & HOST_SERIAL_HIGH_SPEED_192MHZ) { -+ writel((readl(SCU_BASE | SCU_338) & R_V_VALUE_MASK) | -+ (SCU_338_N_VALUE_192MHZ << R_VALUE_BITS) | SCU_338_R_VALUE_192MHZ, -+ SCU_BASE | SCU_338); -+ } else { -+ writel((readl(SCU_BASE | SCU_338) & R_V_VALUE_MASK) | -+ (SCU_338_N_VALUE_24MHZ << R_VALUE_BITS) | SCU_338_R_VALUE_24MHZ, -+ SCU_BASE | SCU_338); -+ } - - return 0; - } --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch deleted file mode 100755 index 32a40261f..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-Config-host-uart-clock-source-using-environment-vari.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 30c634b4969b8a3cd3afc079d60d23d2cb9f5f5c Mon Sep 17 00:00:00 2001 -From: Yong Li -Date: Mon, 11 Feb 2019 15:19:56 +0800 -Subject: [PATCH] Config host uart clock source using environment variable - -In order to support high speed uart for host uarts, -the uart clock needs to be switched between 24M and 192M. -Config SCU4C based on environment variable hostserialcfg, -this variable is set by IPMI OEM commands. - -Tested: -Change the hostserialcfg variable to 0/1/2/3, -using the below commands: - -ipmitool raw 0x32 0x90 1 0; reboot -cat /sys/class/tty/ttyS*/uartclk, all should be 24MHz - -ipmitool raw 0x32 0x90 1 1; reboot -cat /sys/class/tty/ttyS*/uartclk, ttyS0/2/3 should be 192MHz - -ipmitool raw 0x32 0x90 1 2; reboot -cat /sys/class/tty/ttyS*/uartclk, ttyS1 should be 192MHz - -ipmitool raw 0x32 0x90 1 3; reboot -cat /sys/class/tty/ttyS*/uartclk, ttyS0/12/3 should be 192MHz - -Signed-off-by: Yong Li - ---- - arch/arm/include/asm/arch-aspeed/regs-scu.h | 5 ++++ - board/aspeed/ast-g5/ast-g5-intel.c | 39 +++++++++++++++++++++++++++++ - 2 files changed, 44 insertions(+) - -diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h -index 10b983a..8a596ce 100644 ---- a/arch/arm/include/asm/arch-aspeed/regs-scu.h -+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h -@@ -529,6 +529,11 @@ - /* AST_SCU_MAC_CLK 0x48 - MAC interface clock delay setting register */ - - /* AST_SCU_MISC2_CTRL 0x4C - Misc. 2 Control register */ -+#define SCU_UART5_HS_CLOCK (1 << 28) -+#define SCU_UART4_HS_CLOCK (1 << 27) -+#define SCU_UART3_HS_CLOCK (1 << 26) -+#define SCU_UART2_HS_CLOCK (1 << 25) -+#define SCU_UART1_HS_CLOCK (1 << 24) - #ifdef AST_SOC_G5 - #define SCU_PCIE_MAPPING_HIGH (1 << 15) - #define SCU_MALI_DTY_MODE (1 << 8) -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e0bf9ee..e19df03 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -103,6 +103,9 @@ static const GPIOValue gpio_table[] = { - #define SGPIO_ENABLE 1 - #define GPIO254 0x254 - -+#define HOST_SERIAL_A_HIGH_SPEED (1 << 0) -+#define HOST_SERIAL_B_HIGH_SPEED (1 << 1) -+ - static void sgpio_init(void) - { - uint32_t value; -@@ -368,6 +371,42 @@ void ast_g5_intel_late_init(void) - char value[32]; - u32 reset_reason = 0; - -+ /* By default host serail A and B use normal speed */ -+ uint32_t host_serial_cfg = 0; -+ char *host_serial_cfg_txt = NULL; -+ -+ /* Config the uart clock source based on environment configuration */ -+ host_serial_cfg_txt = getenv("hostserialcfg"); -+ -+ if (host_serial_cfg_txt != NULL) -+ host_serial_cfg = simple_strtoul(host_serial_cfg_txt, NULL, 16); -+ -+ if (host_serial_cfg > (HOST_SERIAL_A_HIGH_SPEED | HOST_SERIAL_B_HIGH_SPEED)) { -+ printf("Invalided hostserialcfg %x, use default!\n", host_serial_cfg); -+ host_serial_cfg = 0; -+ } -+ -+ /* SOL implementation requires uart1/uart3/uart4 have the same clock -+ * source for data forwarding, config uart3 and uart4 -+ */ -+ if (host_serial_cfg & HOST_SERIAL_A_HIGH_SPEED) { -+ ast_scu_write(ast_scu_read(AST_SCU_MISC2_CTRL) | -+ SCU_UART1_HS_CLOCK | SCU_UART3_HS_CLOCK | -+ SCU_UART4_HS_CLOCK, AST_SCU_MISC2_CTRL); -+ } else { -+ ast_scu_write(ast_scu_read(AST_SCU_MISC2_CTRL) & -+ ~SCU_UART1_HS_CLOCK & ~SCU_UART3_HS_CLOCK & -+ ~SCU_UART4_HS_CLOCK, AST_SCU_MISC2_CTRL); -+ } -+ -+ if (host_serial_cfg & HOST_SERIAL_B_HIGH_SPEED) { -+ ast_scu_write(ast_scu_read(AST_SCU_MISC2_CTRL) | -+ SCU_UART2_HS_CLOCK, AST_SCU_MISC2_CTRL); -+ } else { -+ ast_scu_write(ast_scu_read(AST_SCU_MISC2_CTRL) & -+ ~SCU_UART2_HS_CLOCK, AST_SCU_MISC2_CTRL); -+ } -+ - /* save and clear reset status */ - reset_reason = ast_scu_read(AST_SCU_SYS_CTRL); - snprintf(value, sizeof(value), "0x%x", reset_reason); diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch deleted file mode 100644 index 2b6382967..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-KCS-driver-support-in-uBoot.patch +++ /dev/null @@ -1,613 +0,0 @@ -From 6d8db23becf9665193023e350adcad00b75195b0 Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Wed, 13 Mar 2019 14:28:05 +0530 -Subject: [PATCH 1/1] KCS driver support in uBoot - -Added KCS support in uBoot. This will enable -KCS channels and set the specified registers -to do KCS communication in uBoot. It also -consist of read and write KCS message transations -work flow implementation( As specified in IPMI -specification Section 9.15). It is enabled -only when Force Firmware Update Jumper is ON. - -Tested By: -Stopped booting in uBoot and sent IPMI commands -via KCS interfaces using cmdtool.efi. - - Get Device ID: - Req: cmdtool.efi 20 18 1 - Res: 00 23 00 12 03 02 BF 57 01 00 7B 00 00 00 00 00 - - Get Self Test Results - Req: cmdtool.efi 20 18 4 - Res: 00 56 00 - - All other commands - Req: cmdtool.efi 20 18 2 - Res: C1 (Invalid). - -Signed-off-by: AppaRao Puli -Signed-off-by: James Feist ---- - board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 3 + - board/aspeed/ast-g5/ast-g5-kcs.c | 420 +++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ast-g5-kcs.h | 112 ++++++++ - 4 files changed, 536 insertions(+) - create mode 100644 board/aspeed/ast-g5/ast-g5-kcs.c - create mode 100644 board/aspeed/ast-g5/ast-g5-kcs.h - -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 90224333c4..05972b9d17 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -4,3 +4,4 @@ obj-y += ast-g5-espi.o - obj-y += ast-g5-irq.o - obj-y += ast-g5-gpio.o - obj-y += ast-g5-timer.o -+obj-y += ast-g5-kcs.o -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 032f716722..c149426947 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -256,6 +256,7 @@ int intel_force_firmware_jumper_enabled(void) - } - - extern void espi_init(void); -+extern void kcs_init(void); - void ast_g5_intel(void) - { - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); -@@ -264,5 +265,7 @@ void ast_g5_intel(void) - timer8_init(); - if (intel_force_firmware_jumper_enabled()) { - id_led_control(GPIO_AMBER_LED, EIDLED_On); -+ kcs_init(); -+ /* TODO: need to stop the booting here. */ - } - } -diff --git a/board/aspeed/ast-g5/ast-g5-kcs.c b/board/aspeed/ast-g5/ast-g5-kcs.c -new file mode 100644 -index 0000000000..7bff26f9db ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-kcs.c -@@ -0,0 +1,420 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include "ast-g5-kcs.h" -+ -+#ifdef DEBUG_KCS_ENABLED -+#define DBG_KCS printf -+#else -+#define DBG_KCS(...) -+#endif -+ -+/* TODO: Move to IPMI file. */ -+#define IPMI_CC_OK 0x00 -+#define IPMI_CC_INVALID 0xC1 -+#define IPMI_CC_UNSPECIFIED 0xFF -+ -+#define KCS_CHANNEL_NO_3 3 -+ -+static const u16 enabled_kcs_channel[] = { KCS_CHANNEL_NO_3 }; -+ -+static const struct kcs_io_reg ast_kcs_bmc_ioregs[KCS_CHANNEL_MAX] = { -+ { .idr = LPC_IDR1, .odr = LPC_ODR1, .str = LPC_STR1 }, -+ { .idr = LPC_IDR2, .odr = LPC_ODR2, .str = LPC_STR2 }, -+ { .idr = LPC_IDR3, .odr = LPC_ODR3, .str = LPC_STR3 }, -+ { .idr = LPC_IDR4, .odr = LPC_ODR4, .str = LPC_STR4 } -+}; -+ -+#define NO_OF_ENABLED_KCS_CHANNELS ARRAY_SIZE(enabled_kcs_channel) -+ -+static struct kcs_packet m_kcs_pkt[NO_OF_ENABLED_KCS_CHANNELS]; -+ -+static u16 read_status(u16 channel_num) -+{ -+ return readl(AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].str); -+} -+ -+static void write_status(u16 channel_num, u16 value) -+{ -+ writel(value, AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].str); -+} -+ -+static u16 read_data(u16 channel_num) -+{ -+ return readl(AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].idr); -+} -+ -+static void write_data(u16 channel_num, u16 value) -+{ -+ writel(value, AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].odr); -+} -+ -+static void set_kcs_state(u16 channel_num, u16 state) -+{ -+ u16 status = read_status(channel_num); -+ -+ status &= ~KCS_STATE_MASK; -+ status |= KCS_STATE(state) & KCS_STATE_MASK; -+ write_status(channel_num, status); -+} -+ -+static struct kcs_packet *get_kcs_packet(u16 channel_num) -+{ -+ for (u16 idx = 0; idx < NO_OF_ENABLED_KCS_CHANNELS; idx++) { -+ if (channel_num == enabled_kcs_channel[idx]) -+ return &m_kcs_pkt[idx]; -+ } -+ -+ /* very unlike code hits here. */ -+ DBG_KCS("ERROR: %s error. ChannelNo: %d\n", __func__, channel_num); -+ BUG(); -+} -+ -+static void kcs_force_abort(u16 channel_num) -+{ -+ struct kcs_packet *kcs_pkt = NULL; -+ -+ kcs_pkt = get_kcs_packet(channel_num); -+ DBG_KCS("ERROR: KCS communication aborted (Channel:%d, Error:%d)\n", -+ channel_num, kcs_pkt->error); -+ set_kcs_state(channel_num, KCS_STATE_ERROR); -+ read_data(channel_num); -+ write_data(channel_num, ZERO_DATA); -+ -+ kcs_pkt->phase = KCS_PHASE_ERROR; -+ kcs_pkt->read_req_done = false; -+ kcs_pkt->data_in_idx = 0; -+} -+ -+static void init_kcs_packet(u16 channel_num) -+{ -+ struct kcs_packet *kcs_pkt = NULL; -+ -+ kcs_pkt = get_kcs_packet(channel_num); -+ kcs_pkt->channel = channel_num; -+ kcs_pkt->read_req_done = false; -+ kcs_pkt->phase = KCS_PHASE_IDLE; -+ kcs_pkt->error = KCS_NO_ERROR; -+ kcs_pkt->data_in_idx = 0; -+ kcs_pkt->data_out_idx = 0; -+ kcs_pkt->data_out_len = 0; -+} -+ -+static void process_kcs_request(u16 channel_num) -+{ -+ struct kcs_packet *kcs_pkt = NULL; -+ int i; -+ -+ kcs_pkt = get_kcs_packet(channel_num); -+ if (!kcs_pkt->read_req_done) -+ return; -+ -+ DBG_KCS("%s:- chan:%d\n", __func__, channel_num); -+ -+#ifdef DEBUG_KCS_ENABLED -+ DBG_KCS("Request data(Len:%d): ", kcs_pkt->data_in_idx); -+ for (i = 0; i < kcs_pkt->data_in_idx; i++) -+ DBG_KCS(" 0x%02x", kcs_pkt->data_in[i]); -+ DBG_KCS("\n"); -+#endif -+ -+ /* -+ * TODO: Move it to IPMI Command Handler -+ * Below code is added for timebeing till -+ * we implement the IPMI command handler. -+ */ -+ kcs_pkt->data_out[0] = kcs_pkt->data_in[0]; /* netfn */ -+ kcs_pkt->data_out[1] = kcs_pkt->data_in[1]; /* cmd */ -+ kcs_pkt->data_out[2] = IPMI_CC_OK; /* cc */ -+ -+ if (((kcs_pkt->data_in[0] >> 2) == 0x06) && -+ (kcs_pkt->data_in[1] == 0x01)) { -+ /* Get Device ID */ -+ u8 device_id[15] = { 0x23, 0x00, 0x12, 0x03, 0x02, -+ 0xBF, 0x57, 0x01, 0x00, 0x7B, -+ 0x00, 0x00, 0x00, 0x00, 0x00 }; -+ for (i = 0; i < 15; i++) -+ kcs_pkt->data_out[i + 3] = device_id[i]; -+ kcs_pkt->data_out_len = 18; -+ } else if (((kcs_pkt->data_in[0] >> 2) == 0x06) && -+ (kcs_pkt->data_in[1] == 0x04)) { -+ /* Get Self Test Results */ -+ kcs_pkt->data_out[3] = 0x56; -+ kcs_pkt->data_out[4] = 0x00; -+ kcs_pkt->data_out_len = 5; -+ } else { -+ kcs_pkt->data_out[2] = -+ IPMI_CC_INVALID; /* Invalid or not supported. */ -+ kcs_pkt->data_out_len = 3; -+ } -+ /* END: TODO */ -+ -+#ifdef DEBUG_KCS_ENABLED -+ DBG_KCS("Response data(Len:%d): ", kcs_pkt->data_out_len); -+ for (i = 0; i < kcs_pkt->data_out_len; i++) -+ DBG_KCS(" 0x%02x", kcs_pkt->data_out[i]); -+ DBG_KCS("\n"); -+#endif -+ -+ kcs_pkt->phase = KCS_PHASE_READ; -+ write_data(channel_num, kcs_pkt->data_out[kcs_pkt->data_out_idx++]); -+ kcs_pkt->read_req_done = false; -+} -+ -+static void read_kcs_data(u16 channel_num) -+{ -+ struct kcs_packet *kcs_pkt = NULL; -+ -+ kcs_pkt = get_kcs_packet(channel_num); -+ -+ switch (kcs_pkt->phase) { -+ case KCS_PHASE_WRITE_START: -+ kcs_pkt->phase = KCS_PHASE_WRITE_DATA; -+ /* fall through */ -+ -+ case KCS_PHASE_WRITE_DATA: -+ if (kcs_pkt->data_in_idx >= MAX_KCS_PKT_SIZE) { -+ kcs_pkt->error = KCS_LENGTH_ERROR; -+ kcs_force_abort(channel_num); -+ return; -+ } -+ set_kcs_state(channel_num, KCS_STATE_WRITE); -+ write_data(channel_num, ZERO_DATA); -+ kcs_pkt->data_in[kcs_pkt->data_in_idx++] = -+ read_data(channel_num); -+ break; -+ -+ case KCS_PHASE_WRITE_END: -+ if (kcs_pkt->data_in_idx >= MAX_KCS_PKT_SIZE) { -+ kcs_pkt->error = KCS_LENGTH_ERROR; -+ kcs_force_abort(channel_num); -+ return; -+ } -+ set_kcs_state(channel_num, KCS_STATE_READ); -+ kcs_pkt->data_in[kcs_pkt->data_in_idx++] = -+ read_data(channel_num); -+ kcs_pkt->phase = KCS_PHASE_READ_WAIT; -+ kcs_pkt->read_req_done = true; -+ -+ process_kcs_request(channel_num); -+ break; -+ -+ case KCS_PHASE_READ: -+ if (kcs_pkt->data_out_idx == kcs_pkt->data_out_len) -+ set_kcs_state(channel_num, KCS_STATE_IDLE); -+ -+ u8 data = read_data(channel_num); -+ if (data != KCS_CTRL_CODE_READ) { -+ DBG_KCS("Invalid Read data. Phase:%d, Data:0x%02x\n", -+ kcs_pkt->phase, data); -+ set_kcs_state(channel_num, KCS_STATE_ERROR); -+ write_data(channel_num, ZERO_DATA); -+ break; -+ } -+ -+ if (kcs_pkt->data_out_idx == kcs_pkt->data_out_len) { -+ write_data(channel_num, ZERO_DATA); -+ kcs_pkt->phase = KCS_PHASE_IDLE; -+ break; -+ } -+ write_data(channel_num, -+ kcs_pkt->data_out[kcs_pkt->data_out_idx++]); -+ break; -+ -+ case KCS_PHASE_ABORT_1: -+ set_kcs_state(channel_num, KCS_STATE_READ); -+ read_data(channel_num); -+ write_data(channel_num, kcs_pkt->error); -+ kcs_pkt->phase = KCS_PHASE_ABORT_2; -+ break; -+ -+ case KCS_PHASE_ABORT_2: -+ set_kcs_state(channel_num, KCS_STATE_IDLE); -+ read_data(channel_num); -+ write_data(channel_num, ZERO_DATA); -+ kcs_pkt->phase = KCS_PHASE_IDLE; -+ break; -+ -+ default: -+ kcs_force_abort(channel_num); -+ } -+} -+ -+static void read_kcs_cmd(u16 channel_num) -+{ -+ struct kcs_packet *kcs_pkt = NULL; -+ -+ kcs_pkt = get_kcs_packet(channel_num); -+ -+ set_kcs_state(channel_num, KCS_STATE_WRITE); -+ write_data(channel_num, ZERO_DATA); -+ -+ u16 cmd = read_data(channel_num); -+ switch (cmd) { -+ case KCS_CTRL_CODE_WRITE_START: -+ init_kcs_packet(channel_num); -+ kcs_pkt->phase = KCS_PHASE_WRITE_START; -+ break; -+ -+ case KCS_CTRL_CODE_WRITE_END: -+ if (kcs_pkt->error != KCS_NO_ERROR) { -+ kcs_force_abort(channel_num); -+ return; -+ } -+ -+ kcs_pkt->phase = KCS_PHASE_WRITE_END; -+ break; -+ -+ case KCS_CTRL_CODE_GET_STATUS_ABORT: -+ kcs_pkt->phase = KCS_PHASE_ABORT_1; -+ kcs_pkt->error = KCS_ABORT_BY_CMD; -+ break; -+ -+ default: -+ kcs_pkt->error = KCS_ILLEGAL_CTRL_CMD; -+ kcs_force_abort(channel_num); -+ } -+} -+ -+static u16 kcs_irq_handler(struct pt_regs *regs) -+{ -+ for (u16 idx = 0; idx < NO_OF_ENABLED_KCS_CHANNELS; idx++) { -+ u16 channel_num = enabled_kcs_channel[idx]; -+ /* Look-up the interrupted KCS channel */ -+ u16 status = read_status(channel_num); -+ if (status & BIT_STATUS_IBF) { -+ if (status & BIT_STATUS_COD) -+ read_kcs_cmd(channel_num); -+ else -+ read_kcs_data(channel_num); -+ } -+ } -+ -+ return 0; -+} -+ -+static void set_kcs_channel_addr(u16 channel_num) -+{ -+ u32 val; -+ -+ switch (channel_num) { -+ case 1: -+ val = readl(AST_LPC_BASE + LPC_HICR4) & ~BIT_LADR12AS; -+ writel(val, AST_LPC_BASE + LPC_HICR4); -+ val = (KCS_CHANNEL1_ADDR >> 8); -+ writel(val, AST_LPC_BASE + LPC_LADR12H); -+ val = (KCS_CHANNEL1_ADDR & 0xFF); -+ writel(val, AST_LPC_BASE + LPC_LADR12L); -+ break; -+ -+ case 2: -+ val = readl(AST_LPC_BASE + LPC_HICR4) | BIT_LADR12AS; -+ writel(val, AST_LPC_BASE + LPC_HICR4); -+ val = (KCS_CHANNEL2_ADDR >> 8); -+ writel(val, AST_LPC_BASE + LPC_LADR12H); -+ val = (KCS_CHANNEL2_ADDR & 0xFF); -+ writel(val, AST_LPC_BASE + LPC_LADR12L); -+ break; -+ -+ case 3: -+ val = (KCS_CHANNEL3_ADDR >> 8); -+ writel(val, AST_LPC_BASE + LPC_LADR3H); -+ val = (KCS_CHANNEL3_ADDR & 0xFF); -+ writel(val, AST_LPC_BASE + LPC_LADR3L); -+ break; -+ -+ case 4: -+ val = (((KCS_CHANNEL4_ADDR + 1) << 16) | KCS_CHANNEL4_ADDR); -+ writel(val, AST_LPC_BASE + LPC_LADR4); -+ break; -+ -+ default: -+ DBG_KCS("Invalid channel (%d) specified\n", channel_num); -+ break; -+ } -+} -+ -+static void enable_kcs_channel(u16 channel_num, u16 enable) -+{ -+ u32 val; -+ -+ switch (channel_num) { -+ case 1: -+ if (enable) { -+ val = readl(AST_LPC_BASE + LPC_HICR2) | BIT_IBFIE1; -+ writel(val, AST_LPC_BASE + LPC_HICR2); -+ val = readl(AST_LPC_BASE + LPC_HICR0) | BIT_LPC1E; -+ writel(val, AST_LPC_BASE + LPC_HICR0); -+ } else { -+ val = readl(AST_LPC_BASE + LPC_HICR0) & ~BIT_LPC1E; -+ writel(val, AST_LPC_BASE + LPC_HICR0); -+ val = readl(AST_LPC_BASE + LPC_HICR2) & ~BIT_IBFIE1; -+ writel(val, AST_LPC_BASE + LPC_HICR2); -+ } -+ break; -+ -+ case 2: -+ if (enable) { -+ val = readl(AST_LPC_BASE + LPC_HICR2) | BIT_IBFIE2; -+ writel(val, AST_LPC_BASE + LPC_HICR2); -+ val = readl(AST_LPC_BASE + LPC_HICR0) | BIT_LPC2E; -+ writel(val, AST_LPC_BASE + LPC_HICR0); -+ } else { -+ val = readl(AST_LPC_BASE + LPC_HICR0) & ~BIT_LPC2E; -+ writel(val, AST_LPC_BASE + LPC_HICR0); -+ val = readl(AST_LPC_BASE + LPC_HICR2) & ~BIT_IBFIE2; -+ writel(val, AST_LPC_BASE + LPC_HICR2); -+ } -+ break; -+ -+ case 3: -+ if (enable) { -+ val = readl(AST_LPC_BASE + LPC_HICR2) | BIT_IBFIE3; -+ writel(val, AST_LPC_BASE + LPC_HICR2); -+ val = readl(AST_LPC_BASE + LPC_HICR0) | BIT_LPC3E; -+ writel(val, AST_LPC_BASE + LPC_HICR0); -+ val = readl(AST_LPC_BASE + LPC_HICR4) | BIT_KCSENBL; -+ writel(val, AST_LPC_BASE + LPC_HICR4); -+ } else { -+ val = readl(AST_LPC_BASE + LPC_HICR0) & ~BIT_LPC3E; -+ writel(val, AST_LPC_BASE + LPC_HICR0); -+ val = readl(AST_LPC_BASE + LPC_HICR4) & ~BIT_KCSENBL; -+ writel(val, AST_LPC_BASE + LPC_HICR4); -+ val = readl(AST_LPC_BASE + LPC_HICR2) & ~BIT_IBFIE3; -+ writel(val, AST_LPC_BASE + LPC_HICR2); -+ } -+ break; -+ -+ case 4: -+ if (enable) { -+ val = readl(AST_LPC_BASE + LPC_HICRB) | BIT_IBFIE4 | -+ BIT_LPC4E; -+ writel(val, AST_LPC_BASE + LPC_HICRB); -+ } else { -+ val = readl(AST_LPC_BASE + LPC_HICRB) & -+ ~(BIT_IBFIE4 | BIT_LPC4E); -+ writel(val, AST_LPC_BASE + LPC_HICRB); -+ } -+ break; -+ -+ default: -+ DBG_KCS("Invalid channel (%d) specified\n", channel_num); -+ } -+} -+ -+void kcs_init(void) -+{ -+ /* Initialize the KCS channels. */ -+ for (u16 idx = 0; idx < NO_OF_ENABLED_KCS_CHANNELS; idx++) { -+ u16 channel_num = enabled_kcs_channel[idx]; -+ DBG_KCS("%s Channel: %d\n", __func__, channel_num); -+ set_kcs_channel_addr(channel_num); -+ enable_kcs_channel(channel_num, 1); -+ -+ /* Set KCS channel state to idle */ -+ set_kcs_state(channel_num, KCS_STATE_IDLE); -+ } -+ -+ /* KCS interrupt */ -+ request_irq(IRQ_SRC_LPC, kcs_irq_handler); -+} -diff --git a/board/aspeed/ast-g5/ast-g5-kcs.h b/board/aspeed/ast-g5/ast-g5-kcs.h -new file mode 100644 -index 0000000000..bb697c455d ---- /dev/null -+++ b/board/aspeed/ast-g5/ast-g5-kcs.h -@@ -0,0 +1,112 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright (c) 2018-2019 Intel Corporation */ -+ -+#include -+#include -+ -+#include "ast-g5.h" -+ -+#define KCS_CHANNEL_MAX 4 -+#define IRQ_SRC_LPC 8 /* IRQ 8 */ -+#define MAX_KCS_PKT_SIZE (64 * 1024) -+/* KCS channel addresses */ -+#define KCS_CHANNEL1_ADDR 0xCA0 -+#define KCS_CHANNEL2_ADDR 0xCA8 -+#define KCS_CHANNEL3_ADDR 0xCA2 /* KCS SMS */ -+#define KCS_CHANNEL4_ADDR 0xCA4 /* KCS SMM */ -+ -+#define ZERO_DATA 0x00 -+ -+/* Aspeed KCS control registers */ -+#define LPC_HICR0 0x00 /* Host Interface Control Register 0 */ -+#define LPC_HICR1 0x04 /* Host Interface Control Register 1 */ -+#define LPC_HICR2 0x08 /* Host Interface Control Register 2 */ -+#define LPC_HICR3 0x0C /* Host Interface Control Register 3 */ -+#define LPC_HICR4 0x10 /* Host Interface Control Register 4 */ -+#define LPC_LADR3H 0x14 /* LPC channel #3 Address Register H */ -+#define LPC_LADR3L 0x18 /* LPC channel #3 Address Register H */ -+#define LPC_LADR12H 0x1C /* LPC channel #1#2 Address Register H */ -+#define LPC_LADR12L 0x20 /* LPC channel #1#2 Address Register L */ -+#define LPC_IDR1 0x24 /* Input Data Register 1 */ -+#define LPC_IDR2 0x28 /* Input Data Register 2 */ -+#define LPC_IDR3 0x2C /* Input Data Register 3 */ -+#define LPC_ODR1 0x30 /* Output Data Register 1 */ -+#define LPC_ODR2 0x34 /* Output Data Register 2 */ -+#define LPC_ODR3 0x38 /* Output Data Register 3 */ -+#define LPC_STR1 0x3C /* Status Register 1 */ -+#define LPC_STR2 0x40 /* Status Register 2 */ -+#define LPC_STR3 0x44 /* Status Register 3 */ -+#define LPC_HICRB 0x100 /* Host Interface Control Register B */ -+#define LPC_LADR4 0x110 /* LPC channel #4 Address Register */ -+#define LPC_IDR4 0x114 /* Input Data Register 4 */ -+#define LPC_ODR4 0x118 /* Output Data Register 4 */ -+#define LPC_STR4 0x11C /* Status Data Register 4 */ -+ -+/* LPC Bits */ -+#define BIT_LADR12AS BIT(7) /* Channel Address selection */ -+#define BIT_IBFIE1 BIT(1) /* Enable IDR1 Recv completion interrupt */ -+#define BIT_IBFIE2 BIT(2) /* Enable IDR2 Recv completion interrupt */ -+#define BIT_IBFIE3 BIT(3) /* Enable IBF13 interrupt */ -+#define BIT_LPC1E BIT(5) /* Enable LPC channel #1 */ -+#define BIT_LPC2E BIT(6) /* Enable LPC channel #2 */ -+#define BIT_LPC3E BIT(7) /* Enable LPC channel #2 */ -+#define BIT_KCSENBL BIT(2) /* Enable KCS interface in Channel #3 */ -+#define BIT_IBFIE4 BIT(1) -+#define BIT_LPC4E BIT(0) -+ -+#define BIT_STATUS_OBF BIT(0) /* Output Data Register full #1/#2/#3 */ -+#define BIT_STATUS_IBF BIT(1) /* Input Data Register full #1/#2/#3 */ -+#define BIT_STATUS_COD BIT(3) /* Command/Data - (1=command,0=data) */ -+ -+#define KCS_STATE_MASK 0xC0 /* BIT[6:7] of status register */ -+#define KCS_STATE(state) ((state) << 6) -+ -+/* IPMI2.0(section 9.7) - KCS interface State Bits */ -+#define KCS_STATE_IDLE 0x00 -+#define KCS_STATE_READ 0x01 -+#define KCS_STATE_WRITE 0x02 -+#define KCS_STATE_ERROR 0x03 -+ -+/* IPMI2.0(section 9.10) - KCS interface control codes */ -+#define KCS_CTRL_CODE_GET_STATUS_ABORT 0x60 -+#define KCS_CTRL_CODE_WRITE_START 0x61 -+#define KCS_CTRL_CODE_WRITE_END 0x62 -+#define KCS_CTRL_CODE_READ 0x68 -+ -+struct kcs_io_reg { -+ u32 idr; -+ u32 odr; -+ u32 str; -+}; -+ -+enum kcs_phase { -+ KCS_PHASE_IDLE = 0, -+ KCS_PHASE_WRITE_START = 1, -+ KCS_PHASE_WRITE_DATA = 2, -+ KCS_PHASE_WRITE_END = 3, -+ KCS_PHASE_READ_WAIT = 4, -+ KCS_PHASE_READ = 5, -+ KCS_PHASE_ABORT_1 = 6, -+ KCS_PHASE_ABORT_2 = 7, -+ KCS_PHASE_ERROR = 8 -+}; -+ -+enum kcs_error { -+ KCS_NO_ERROR = 0x00, -+ KCS_ABORT_BY_CMD = 0x01, -+ KCS_ILLEGAL_CTRL_CMD = 0x02, -+ KCS_LENGTH_ERROR = 0x06, -+ KCS_UNSPECIFIED_ERROR = 0xFF, -+}; -+ -+struct kcs_packet { -+ enum kcs_phase phase; -+ enum kcs_error error; -+ u16 channel; -+ bool read_req_done; -+ u16 data_in_idx; -+ u8 data_in[MAX_KCS_PKT_SIZE]; -+ u16 data_out_len; -+ u16 data_out_idx; -+ u8 data_out[MAX_KCS_PKT_SIZE]; -+}; --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch deleted file mode 100644 index afba07abf..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0022-u-boot-env-change-for-PFR-image.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 4cbfb21b7792e6dae74e2db6e2e2d6803bf6cc1d Mon Sep 17 00:00:00 2001 -From: Vikram Bodireddy -Date: Tue, 26 Mar 2019 20:34:51 +0530 -Subject: [PATCH] u-boot env change for PFR image - -Tested: verified BMC booting from 0x20b00000 - -Signed-off-by: Vikram Bodireddy ---- - include/configs/ast-common.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h -index 0bc7f2d..821ea8f 100644 ---- a/include/configs/ast-common.h -+++ b/include/configs/ast-common.h -@@ -108,7 +108,7 @@ - #define CONFIG_SYS_MAX_FLASH_BANKS (CONFIG_FMC_CS) - #define CONFIG_SYS_MAX_FLASH_SECT (8192) /* max number of sectors on one chip */ - #define CONFIG_ENV_IS_IN_FLASH 1 --#define CONFIG_ENV_OFFSET 0x2400000 /* environment starts here */ -+#define CONFIG_ENV_OFFSET 0xa0000 /* environment starts here */ - #define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) - #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -@@ -116,7 +116,7 @@ - #define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET_REDUND) - #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - --#define CONFIG_BOOTCOMMAND "bootm 20080000" -+#define CONFIG_BOOTCOMMAND "bootm 20b00000" - #define CONFIG_ENV_OVERWRITE - - #define ASPEED_ENV_SETTINGS \ --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch deleted file mode 100644 index f3fc0738b..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0023-Add-TPM-enable-pulse-triggering.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 6b0f858e2dda7afce82797835f950e3501b3046d Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo -Date: Fri, 29 Mar 2019 12:30:20 -0700 -Subject: [PATCH] Add TPM enable pulse triggering - -This commit adds onboard TPM enable pulse triggering. - -Signed-off-by: Jae Hyun Yoo - ---- - board/aspeed/ast-g5/ast-g5-intel.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index adc6d10..55afa09 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -53,8 +53,8 @@ static const GPIOValue gpio_table[] = { - GPIO_DEBOUNCE_8MS}, - - /* Enable Pulse -- pin D6 */ -- [GPIO_ENABLE_TPM_PULSE] = {PORT_PIN(GPIO_PORT_D, GPIO_PIN_6), -- GPIO_CFG_DEFAULT, 0, GPIO_DEBOUNCE_8MS}, -+ [GPIO_ENABLE_TPM_PULSE] = {TPM_EN_PULSE_PORT_PIN, GPCFG_OUTPUT_EN, 0, -+ GPIO_DEBOUNCE_NONE}, - }; - - #define LPC_SNOOP_ADDR 0x80 -@@ -232,6 +232,13 @@ void id_led_control(int id, int action) - gpio_set_value(s_led_info[id].gpio, s_led_info[id].state); - } - -+static void enable_onboard_tpm(void) -+{ -+ gpio_set_value(GPIO_ENABLE_TPM_PULSE, 1); -+ mdelay(50); -+ gpio_set_value(GPIO_ENABLE_TPM_PULSE, 0); -+} -+ - static void timer8_irq_handler(void *regs) - { - int i; -@@ -488,6 +495,7 @@ void ast_g5_intel(void) - espi_init(); - sgpio_init(); - timer8_init(); -+ enable_onboard_tpm(); - if (intel_force_firmware_jumper_enabled()) { - id_led_control(GPIO_AMBER_LED, EIDLED_On); - kcs_init(); diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch deleted file mode 100644 index 252a9ea1b..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0024-IPMI-command-handler-implementation-in-uboot.patch +++ /dev/null @@ -1,330 +0,0 @@ -From 2314db61ea792a98c35fcc75b0ac09cbc0db005d Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Tue, 21 May 2019 00:19:16 +0530 -Subject: [PATCH] IPMI command handler implementation in uboot - -IPMI command handler implemtation in uBoot. -Implemented IPMI commands: - 1) Get Device ID - 2) Get Self Test Result - -Tested By: -Ran the above IPMI command Via KCS channel -and got proper response. -- Get Device ID - Req: cmdtool.efi 20 18 1 - Res: 0x00 0x23 0x00 0x82 0x03 0x02 0x00 0x57 0x01 0x00 0x7b 0x00 0x00 0x00 0x00 0x00 -- Get Self Test Results - Req: cmdtool.efi 20 18 4 - Res: 00 56 00 - -Change-Id: I18b205bc45c34f7c4ef16adc29fa5bd494624ceb -Signed-off-by: AppaRao Puli - ---- - board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-kcs.c | 77 +++++++++++++----------- - board/aspeed/ast-g5/ipmi-handler.c | 118 +++++++++++++++++++++++++++++++++++++ - board/aspeed/ast-g5/ipmi-handler.h | 40 +++++++++++++ - 4 files changed, 202 insertions(+), 34 deletions(-) - create mode 100644 board/aspeed/ast-g5/ipmi-handler.c - create mode 100644 board/aspeed/ast-g5/ipmi-handler.h - -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 05972b9..f28fcfe 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -5,3 +5,4 @@ obj-y += ast-g5-irq.o - obj-y += ast-g5-gpio.o - obj-y += ast-g5-timer.o - obj-y += ast-g5-kcs.o -+obj-y += ipmi-handler.o -diff --git a/board/aspeed/ast-g5/ast-g5-kcs.c b/board/aspeed/ast-g5/ast-g5-kcs.c -index 7bff26f..98bf69b 100644 ---- a/board/aspeed/ast-g5/ast-g5-kcs.c -+++ b/board/aspeed/ast-g5/ast-g5-kcs.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0 - // Copyright (c) 2018-2019 Intel Corporation - --#include "ast-g5-kcs.h" -+#include "ipmi-handler.h" - - #ifdef DEBUG_KCS_ENABLED - #define DBG_KCS printf -@@ -9,11 +9,6 @@ - #define DBG_KCS(...) - #endif - --/* TODO: Move to IPMI file. */ --#define IPMI_CC_OK 0x00 --#define IPMI_CC_INVALID 0xC1 --#define IPMI_CC_UNSPECIFIED 0xFF -- - #define KCS_CHANNEL_NO_3 3 - - static const u16 enabled_kcs_channel[] = { KCS_CHANNEL_NO_3 }; -@@ -103,6 +98,7 @@ static void init_kcs_packet(u16 channel_num) - static void process_kcs_request(u16 channel_num) - { - struct kcs_packet *kcs_pkt = NULL; -+ struct ipmi_cmd_data ipmi_data; - int i; - - kcs_pkt = get_kcs_packet(channel_num); -@@ -117,37 +113,49 @@ static void process_kcs_request(u16 channel_num) - DBG_KCS(" 0x%02x", kcs_pkt->data_in[i]); - DBG_KCS("\n"); - #endif -+ u8 req_lun = kcs_pkt->data_in[0] & 0x03; /* LUN[1:0] */ -+ ipmi_data.net_fun = (kcs_pkt->data_in[0] >> 2); /* netfn[7:2] */ -+ ipmi_data.cmd = kcs_pkt->data_in[1]; /* cmd */ -+ /* We support only BMC LUN 00h */ -+ if (req_lun != LUN_BMC) { -+ kcs_pkt->data_out[0] = -+ GET_RESP_NETFN_LUN(req_lun, ipmi_data.net_fun); -+ kcs_pkt->data_out[1] = ipmi_data.cmd; /* cmd */ -+ kcs_pkt->data_out[2] = IPMI_CC_INVALID_CMD_LUN; /* CC code */ -+ kcs_pkt->data_out_len = 3; -+ goto done; -+ } - -- /* -- * TODO: Move it to IPMI Command Handler -- * Below code is added for timebeing till -- * we implement the IPMI command handler. -- */ -- kcs_pkt->data_out[0] = kcs_pkt->data_in[0]; /* netfn */ -- kcs_pkt->data_out[1] = kcs_pkt->data_in[1]; /* cmd */ -- kcs_pkt->data_out[2] = IPMI_CC_OK; /* cc */ -- -- if (((kcs_pkt->data_in[0] >> 2) == 0x06) && -- (kcs_pkt->data_in[1] == 0x01)) { -- /* Get Device ID */ -- u8 device_id[15] = { 0x23, 0x00, 0x12, 0x03, 0x02, -- 0xBF, 0x57, 0x01, 0x00, 0x7B, -- 0x00, 0x00, 0x00, 0x00, 0x00 }; -- for (i = 0; i < 15; i++) -- kcs_pkt->data_out[i + 3] = device_id[i]; -- kcs_pkt->data_out_len = 18; -- } else if (((kcs_pkt->data_in[0] >> 2) == 0x06) && -- (kcs_pkt->data_in[1] == 0x04)) { -- /* Get Self Test Results */ -- kcs_pkt->data_out[3] = 0x56; -- kcs_pkt->data_out[4] = 0x00; -- kcs_pkt->data_out_len = 5; -- } else { -- kcs_pkt->data_out[2] = -- IPMI_CC_INVALID; /* Invalid or not supported. */ -+ /* Boundary check */ -+ if ((kcs_pkt->data_in_idx - 2) > sizeof(ipmi_data.req_data)) { -+ kcs_pkt->data_out[0] = -+ GET_RESP_NETFN_LUN(req_lun, ipmi_data.net_fun); -+ kcs_pkt->data_out[1] = ipmi_data.cmd; /* cmd */ -+ kcs_pkt->data_out[2] = IPMI_CC_OUT_OF_SPACE; /* CC code */ - kcs_pkt->data_out_len = 3; -+ goto done; - } -- /* END: TODO */ -+ /* Fill in IPMI request data */ -+ ipmi_data.req_len = kcs_pkt->data_in_idx - 2; -+ for (i = 0; i < kcs_pkt->data_in_idx - 2; i++) -+ ipmi_data.req_data[i] = kcs_pkt->data_in[i + 2]; -+ -+ /* Call IPMI command handler */ -+ ipmi_cmd_handler(&ipmi_data); -+ -+ /* Get IPMI response and fill KCS out data */ -+ /* First 2 bytes in KCS response are netFn, Cmd */ -+ kcs_pkt->data_out[0] = GET_RESP_NETFN_LUN(req_lun, ipmi_data.net_fun); -+ kcs_pkt->data_out[1] = ipmi_data.cmd; -+ if ((ipmi_data.res_len + 2) > sizeof(kcs_pkt->data_out)) { -+ kcs_pkt->data_out[2] = IPMI_CC_UNSPECIFIED; /* CC code */ -+ kcs_pkt->data_out_len = 3; -+ goto done; -+ } -+ for (i = 0; i < ipmi_data.res_len; i++) -+ kcs_pkt->data_out[i + 2] = ipmi_data.res_data[i]; -+ -+ kcs_pkt->data_out_len = ipmi_data.res_len + 2; - - #ifdef DEBUG_KCS_ENABLED - DBG_KCS("Response data(Len:%d): ", kcs_pkt->data_out_len); -@@ -156,6 +164,7 @@ static void process_kcs_request(u16 channel_num) - DBG_KCS("\n"); - #endif - -+done: - kcs_pkt->phase = KCS_PHASE_READ; - write_data(channel_num, kcs_pkt->data_out[kcs_pkt->data_out_idx++]); - kcs_pkt->read_req_done = false; -diff --git a/board/aspeed/ast-g5/ipmi-handler.c b/board/aspeed/ast-g5/ipmi-handler.c -new file mode 100644 -index 0000000..9cccee9 ---- /dev/null -+++ b/board/aspeed/ast-g5/ipmi-handler.c -@@ -0,0 +1,118 @@ -+ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include "ipmi-handler.h" -+ -+/* IPMI network function codes */ -+#define NETFN_APP 0x06 -+ -+/* IPMI command codes */ -+#define CMD_GET_DEV_ID 0x01 -+#define CMD_GET_SELF_TEST_RESULTS 0x04 -+ -+typedef u16 (*fun_handler)(u8 *req, u16 req_len, u8 *res); -+ -+struct get_dev_id { -+ u8 completion_code; -+ u8 dev_id; -+ u8 dev_rev; -+ u8 fw_rev1; -+ u8 fw_rev2; -+ u8 ipmi_ver; -+ u8 dev_support; -+ u8 mfg_id[3]; -+ u8 product_id[2]; -+ u8 aux_fw_rev[4]; -+}; -+struct self_test_res { -+ u8 completion_code; -+ u8 res_byte[2]; -+}; -+ -+struct ipmi_cmd_table { -+ u8 net_fun; -+ u8 cmd; -+ fun_handler process_cmd; -+}; -+ -+static u16 get_device_id(u8 *req, u16 req_len, u8 *res) -+{ -+ /* Get Device ID */ -+ bool operation = 1; /* Firmware operation */ -+ u8 intel_mfg_id[3] = { 0x57, 0x01, 0x00 }; -+ u8 platform_id[2] = { 0x7B, 0x00 }; -+ u8 aux_fw_rev[4] = { 0x00, 0x00, 0x00, 0x00 }; -+ struct get_dev_id *result = (struct get_dev_id *)res; -+ -+ if (req_len != 0) { -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ result->completion_code = IPMI_CC_OK; -+ result->dev_id = 0x23; -+ result->dev_rev = 0x00; /* Not provides dev SDR */ -+ -+ result->ipmi_ver = 0x02; /* IPMI 2.0 */ -+ result->dev_support = 0x00; /* No dev support in this mode */ -+ memcpy(result->mfg_id, intel_mfg_id, sizeof(result->mfg_id)); -+ memcpy(result->aux_fw_rev, aux_fw_rev, sizeof(result->aux_fw_rev)); -+ -+ /* TODO: Get Firmware version from flash(PFM Header) */ -+ result->fw_rev1 = ((operation << 7) | (0x02 & 0x7F)); -+ result->fw_rev2 = 0x03; -+ /* TODO: Read Platform ID from GPIO */ -+ memcpy(result->product_id, platform_id, sizeof(result->product_id)); -+ -+ return sizeof(struct get_dev_id); -+} -+ -+static u16 get_self_test_result(u8 *req, u16 req_len, u8 *res) -+{ -+ /* Get Self Test Results */ -+ struct self_test_res *result = (struct self_test_res *)res; -+ -+ if (req_len != 0) { -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ result->completion_code = IPMI_CC_OK; -+ result->res_byte[0] = 0x56; /* Self test function not implemented. */ -+ result->res_byte[1] = 0x00; -+ -+ return sizeof(struct self_test_res); -+} -+ -+const struct ipmi_cmd_table cmd_info[] = { -+ { NETFN_APP, CMD_GET_DEV_ID, get_device_id }, -+ { NETFN_APP, CMD_GET_SELF_TEST_RESULTS, get_self_test_result } -+}; -+ -+#define CMD_TABLE_SIZE ARRAY_SIZE(cmd_info) -+ -+void ipmi_cmd_handler(struct ipmi_cmd_data *ipmi_data) -+{ -+ int i = 0; -+ for (i = 0; i < CMD_TABLE_SIZE; i++) { -+ if ((cmd_info[i].net_fun == ipmi_data->net_fun) && -+ (cmd_info[i].cmd == ipmi_data->cmd)) { -+ break; -+ } -+ } -+ -+ if (i == CMD_TABLE_SIZE) { -+ /* Invalid or not supported. */ -+ ipmi_data->res_data[0] = IPMI_CC_INVALID_CMD; -+ ipmi_data->res_len = 1; -+ return; -+ } -+ -+ /* Call the appropriate function handler */ -+ ipmi_data->res_len = -+ cmd_info[i].process_cmd(ipmi_data->req_data, ipmi_data->req_len, -+ &ipmi_data->res_data[0]); -+ -+ return; -+} -diff --git a/board/aspeed/ast-g5/ipmi-handler.h b/board/aspeed/ast-g5/ipmi-handler.h -new file mode 100644 -index 0000000..9d46d9b ---- /dev/null -+++ b/board/aspeed/ast-g5/ipmi-handler.h -@@ -0,0 +1,40 @@ -+ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright (c) 2018-2019 Intel Corporation */ -+ -+#include "ast-g5-kcs.h" -+ -+/* IPMI completion codes */ -+#define IPMI_CC_OK 0x00 -+#define IPMI_CC_NODE_BUSY 0xC0 -+#define IPMI_CC_INVALID_CMD 0xC1 -+#define IPMI_CC_INVALID_CMD_LUN 0xC2 -+#define IPMI_CC_OUT_OF_SPACE 0xC4 -+#define IPMI_CC_INVALID_DATA_LENGTH 0xC7 -+#define IPMI_CC_INVALID_DATA_FIELD 0xCC -+#define IPMI_CC_UNSPECIFIED 0xFF -+ -+/* BMC IPMB LUNs */ -+#define LUN_BMC 0x00 -+#define LUN_OEM1 0x01 -+#define LUN_SMS 0x02 -+#define LUN_OEM2 0x01 -+ -+ -+#define MAX_IPMI_REQ_DATA_SIZE MAX_KCS_PKT_SIZE -+#define MAX_IPMI_RES_DATA_SIZE 64 -+ -+/* Response netFn[7:2], Lun[1:0] */ -+#define GET_RESP_NETFN_LUN(lun, netfn) \ -+ ((lun & 0x03) | (((netfn + 1) << 2) & 0xFD)) -+ -+struct ipmi_cmd_data { -+ u8 net_fun; -+ u8 cmd; -+ u16 req_len; -+ u16 res_len; -+ u8 req_data[MAX_IPMI_REQ_DATA_SIZE]; -+ u8 res_data[MAX_IPMI_RES_DATA_SIZE]; -+}; -+ -+void ipmi_cmd_handler(struct ipmi_cmd_data *ipmi_data); diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch deleted file mode 100644 index 065f890bc..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0025-Manufacturing-mode-physical-presence-detection.patch +++ /dev/null @@ -1,114 +0,0 @@ -From b6f898ef15eede75700e9e13a8e0b69d88b12fd4 Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Thu, 20 Jun 2019 18:11:43 +0530 -Subject: [PATCH 15/30] Manufacturing mode physical presence detection - -Support for physical presence of manufacturing mode added. -Front panel power button press for 15 seconds will be detected -and marked as special mode for manufacturing request. -There will be 10 second Status LED blink for 10 seconds to -do the physical indication to the user. This indicates the -user that he has pressed power button long enough for -manufacturing mode detection. - -Tested: -1. Verified by holding the power button when u-boot boots for -15 seconds, and confirmed that bootargs passed to linux has -special=mfg string and status led blink physical indication -has been provided -2. Verified in normal condition special=mfg string is not passed -and no physical indication has been provided - -Change-Id: Id7e7c7e7860c7ef3ae8e3a7a7cfda7ff506c0f2b -Signed-off-by: Richard Marian Thomaiyar -Signed-off-by: AppaRao Puli - -%% original patch: 0025-Manufacturing-mode-physical-presence-detection.patch ---- - board/aspeed/ast-g5/ast-g5-gpio.h | 2 +- - board/aspeed/ast-g5/ast-g5-intel.c | 35 ++++++++++++++++++++++++++++++ - 2 files changed, 36 insertions(+), 1 deletion(-) - -diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h -index 54b7388a22..8ccf437346 100644 ---- a/board/aspeed/ast-g5/ast-g5-gpio.h -+++ b/board/aspeed/ast-g5/ast-g5-gpio.h -@@ -73,7 +73,7 @@ - #define AMB_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_5) - #define FORCE_BMC_UPDATE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_0) - #define TPM_EN_PULSE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_6) -- -+#define FP_PWR_BTN_PORT_PIN PORT_PIN(GPIO_PORT_E, GPIO_PIN_2) - - // GPIO Configuration Register bits - #define GPCFG_EVENT_TO_SMI (1 << 7) // 1 == enabled -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 45ecd83fd3..efc3315caf 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -24,6 +24,7 @@ enum gpio_names { - GPIO_AMBER_LED, - GPIO_FF_UPD_JUMPER, - GPIO_ENABLE_TPM_PULSE, -+ GPIO_FP_PWR_BTN, - }; - - #define GPIO_CFG_DEFAULT (GPCFG_ACTIVE_HIGH | GPCFG_LEVEL_TRIG) -@@ -58,6 +59,10 @@ static const GPIOValue gpio_table[] = { - /* Enable Pulse -- pin D6 */ - [GPIO_ENABLE_TPM_PULSE] = {TPM_EN_PULSE_PORT_PIN, GPCFG_OUTPUT_EN, 0, - GPIO_DEBOUNCE_NONE}, -+ /* Front Panel Power Button -- pin E2 */ -+ [GPIO_FP_PWR_BTN] = {FP_PWR_BTN_PORT_PIN, GPIO_CFG_LOW_INPUT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ - }; - - #define LPC_SNOOP_ADDR 0x80 -@@ -403,6 +408,30 @@ static void update_bootargs_cmd(const char *key, const char *value) - free(buf); - } - -+static bool is_mfg_mode_phy_req(void) -+{ -+ /* -+ * Assume mfg mode physical request is made, if power button -+ * is pressed continously for 15 seconds, indicate the -+ * same in bootargs -+ */ -+ const uint32_t delay_in_ms = 100; -+ const uint32_t read_count = ((15 * 1000) / delay_in_ms); -+ const uint32_t delay_for_indication = 10 * 1000; -+ for (uint32_t count = 0; count < read_count; ++count) { -+ if (!gpio_get_value(GPIO_FP_PWR_BTN)) -+ return false; -+ -+ mdelay(delay_in_ms); -+ } -+ debug("is_mfg_mode_phy_req : detected mfg mode request\n"); -+ id_led_control(GPIO_GREEN_LED, EIDLED_Blink_3HZ); -+ /* Delay the boot to do physical indication for mfg mode */ -+ mdelay(delay_for_indication); -+ -+ return true; -+} -+ - void ast_g5_intel_late_init(void) - { - char value[32]; -@@ -450,6 +479,12 @@ void ast_g5_intel_late_init(void) - ast_scu_write(0, AST_SCU_SYS_CTRL); - - update_bootargs_cmd("resetreason", value); -+ -+ /* Update the special mode in bootargs */ -+ if (is_mfg_mode_phy_req()) -+ update_bootargs_cmd("special", "mfg"); -+ else -+ update_bootargs_cmd("special", NULL); - } - - static void pwm_init(void) --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch deleted file mode 100644 index be2c4018d..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0026-Aspeed-I2C-support-in-U-Boot.patch +++ /dev/null @@ -1,1524 +0,0 @@ -From ea4f14a24b67d5085149d48c7fb38d00f3a7444a Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Mon, 6 May 2019 03:01:55 +0530 -Subject: [PATCH] Aspeed I2C support in U-Boot - -Adding Aspeed I2C support in u-boot and enabled -i2c command. It is mainly used for PFR to -communicate with PFR CPLD while BMC is in -"Force Firmware Update" mode. - -Tested: -Using i2c command in u-boot, validated -i2c functionalities like probe, read and write. - -Change-Id: Iad9af4a57a58bc8dc5c470bfadad9dac1371c238 -Signed-off-by: AppaRao Puli - ---- - arch/arm/include/asm/arch-aspeed/ast_g5_platform.h | 14 + - arch/arm/include/asm/arch-aspeed/ast_scu.h | 5 + - arch/arm/include/asm/arch-aspeed/regs-iic.h | 204 +++++ - arch/arm/mach-aspeed/ast-scu.c | 122 +++ - board/aspeed/ast-g5/ast-g5.c | 8 + - configs/ast_g5_phy_defconfig | 2 + - drivers/i2c/Kconfig | 5 + - drivers/i2c/Makefile | 1 + - drivers/i2c/ast_i2c.c | 852 +++++++++++++++++++++ - drivers/i2c/ast_i2c.h | 131 ++++ - include/configs/ast-common.h | 5 + - 11 files changed, 1349 insertions(+) - create mode 100644 arch/arm/include/asm/arch-aspeed/regs-iic.h - create mode 100644 drivers/i2c/ast_i2c.c - create mode 100644 drivers/i2c/ast_i2c.h - -diff --git a/arch/arm/include/asm/arch-aspeed/ast_g5_platform.h b/arch/arm/include/asm/arch-aspeed/ast_g5_platform.h -index 4210873..a84f471 100644 ---- a/arch/arm/include/asm/arch-aspeed/ast_g5_platform.h -+++ b/arch/arm/include/asm/arch-aspeed/ast_g5_platform.h -@@ -105,6 +105,20 @@ - #define AST_LPC_BASE 0x1E789000 /* LPC */ - #define AST_MBX_BASE 0x1E789200 /* Mailbox */ - #define AST_I2C_BASE 0x1E78A000 /* I2C */ -+#define AST_I2C_DEV0_BASE 0x1E78A040 /* I2C DEV1 */ -+#define AST_I2C_DEV1_BASE 0x1E78A080 /* I2C DEV2 */ -+#define AST_I2C_DEV2_BASE 0x1E78A0C0 /* I2C DEV3 */ -+#define AST_I2C_DEV3_BASE 0x1E78A100 /* I2C DEV4 */ -+#define AST_I2C_DEV4_BASE 0x1E78A140 /* I2C DEV5 */ -+#define AST_I2C_DEV5_BASE 0x1E78A180 /* I2C DEV6 */ -+#define AST_I2C_DEV6_BASE 0x1E78A1C0 /* I2C DEV7 */ -+#define AST_I2C_DEV7_BASE 0x1E78A300 /* I2C DEV8 */ -+#define AST_I2C_DEV8_BASE 0x1E78A340 /* I2C DEV9 */ -+#define AST_I2C_DEV9_BASE 0x1E78A380 /* I2C DEV10 */ -+#define AST_I2C_DEV10_BASE 0x1E78A3C0 /* I2C DEV11 */ -+#define AST_I2C_DEV11_BASE 0x1E78A400 /* I2C DEV12 */ -+#define AST_I2C_DEV12_BASE 0x1E78A440 /* I2C DEV13 */ -+#define AST_I2C_DEV13_BASE 0x1E78A480 /* I2C DEV14 */ - #define AST_PECI_BASE 0x1E78B000 /* PECI */ - #define AST_PCIARBITER_BASE 0x1E78C000 /* PCI ARBITER */ - #define AST_UART2_BASE 0x1E78D000 /* UART2 */ -diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h -index 369c4e3..b94d13e 100644 ---- a/arch/arm/include/asm/arch-aspeed/ast_scu.h -+++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h -@@ -28,6 +28,8 @@ - #ifndef __AST_SCU_H - #define __AST_SCU_H - -+#include -+ - extern void ast_scu_show_system_info (void); - extern void ast_scu_sys_rest_info(void); - extern void ast_scu_security_info(void); -@@ -39,13 +41,16 @@ extern u32 ast_get_clk_source(void); - extern u32 ast_get_h_pll_clk(void); - extern u32 ast_get_m_pll_clk(void); - extern u32 ast_get_ahbclk(void); -+extern u32 ast_get_pclk(void); - - extern u32 ast_scu_get_vga_memsize(void); - -+extern void ast_scu_init_i2c(void); - extern void ast_scu_init_eth(u8 num); - extern void ast_scu_multi_func_eth(u8 num); - extern void ast_scu_multi_func_romcs(u8 num); - extern void ast_scu_multi_func_sgpio(void); -+extern void ast_scu_multi_func_i2c(u8 bus_no); - - void ast_config_uart5_clk(void); - -diff --git a/arch/arm/include/asm/arch-aspeed/regs-iic.h b/arch/arm/include/asm/arch-aspeed/regs-iic.h -new file mode 100644 -index 0000000..5eb3f0a ---- /dev/null -+++ b/arch/arm/include/asm/arch-aspeed/regs-iic.h -@@ -0,0 +1,204 @@ -+/* arch/arm/plat-aspeed/include/mach/regs-iic.h -+ * -+ * Copyright (c) 2012 ASPEED Technology Inc. -+ * http://www.aspeedtech.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * ASPEED I2C Controller -+*/ -+ -+#ifndef __ASM_ARCH_REGS_IIC_H -+#define __ASM_ARCH_REGS_IIC_H __FILE__ -+ -+#ifdef CONFIG_ARCH_AST1010 -+#define AST_I2C_DMA_SIZE 512 -+#else -+#define AST_I2C_DMA_SIZE 4096 -+#endif -+#define AST_I2C_PAGE_SIZE 256 -+ -+#if defined(CONFIG_ARCH_AST2300) -+#define NUM_BUS 9 -+#elif defined(CONFIG_ARCH_AST2400) -+#define NUM_BUS 14 -+#elif defined(CONFIG_ARCH_AST1010) -+#define NUM_BUS 15 -+#elif defined(CONFIG_ARCH_AST1520) || defined(CONFIG_ARCH_AST3200) || defined(CONFIG_ARCH_AST2500) -+#define NUM_BUS 14 -+#elif defined(CONFIG_ARCH_AST1220) -+#define NUM_BUS 10 -+#else -+#err "NO define NUM_BUS" -+#endif -+ -+/* I2C Register */ -+#define I2C_FUN_CTRL_REG 0x00 -+#define I2C_AC_TIMING_REG1 0x04 -+#define I2C_AC_TIMING_REG2 0x08 -+#define I2C_INTR_CTRL_REG 0x0c -+#define I2C_INTR_STS_REG 0x10 -+#define I2C_CMD_REG 0x14 -+#define I2C_DEV_ADDR_REG 0x18 -+#define I2C_BUF_CTRL_REG 0x1c -+#define I2C_BYTE_BUF_REG 0x20 -+#define I2C_DMA_BASE_REG 0x24 -+#define I2C_DMA_LEN_REG 0x28 -+ -+ -+/* Gloable Register Definition */ -+/* 0x00 : I2C Interrupt Status Register */ -+/* 0x08 : I2C Interrupt Target Assignment */ -+#if defined(CONFIG_ARCH_AST2400) -+#define AST_I2CG_INTR14 (0x1 << 13) -+#define AST_I2CG_INTR13 (0x1 << 12) -+#define AST_I2CG_INTR12 (0x1 << 11) -+#define AST_I2CG_INTR11 (0x1 << 10) -+#define AST_I2CG_INTR10 (0x1 << 9) -+#elif defined(CONFIG_ARCH_AST1010) -+#define AST_I2CG_INTR14 (0x1 << 13) -+#define AST_I2CG_INTR13 (0x1 << 12) -+#define AST_I2CG_INTR12 (0x1 << 11) -+#define AST_I2CG_INTR11 (0x1 << 10) -+#define AST_I2CG_INTR10 (0x1 << 9) -+#endif -+#define AST_I2CG_INTR09 (0x1 << 8) -+#define AST_I2CG_INTR08 (0x1 << 7) -+#define AST_I2CG_INTR07 (0x1 << 6) -+#define AST_I2CG_INTR06 (0x1 << 5) -+#define AST_I2CG_INTR05 (0x1 << 4) -+#define AST_I2CG_INTR04 (0x1 << 3) -+#define AST_I2CG_INTR03 (0x1 << 2) -+#define AST_I2CG_INTR02 (0x1 << 1) -+#define AST_I2CG_INTR01 (0x1) -+ -+/* Device Register Definition */ -+/* 0x00 : I2CD Function Control Register */ -+#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) -+#define AST_I2CD_BUFF_SEL(x) (x << 20) // page 0 ~ 7 -+#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) -+#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) -+#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) -+#define AST_I2CD_MSB_STS (0x1 << 9) -+#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) -+#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) -+#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) -+#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) -+#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) -+#define AST_I2CD_DEF_ARP_EN (0x1 << 3) -+#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) -+#define AST_I2CD_SLAVE_EN (0x1 << 1) -+#define AST_I2CD_MASTER_EN (0x1) -+ -+/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ -+#define AST_I2CD_tBUF (0x1 << 28) // 0~7 -+#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7 -+#define AST_I2CD_tACST (0x1 << 20) // 0~7 -+#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7 -+#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7 -+#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7 -+#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3 -+#define AST_I2CD_CLK_BASE_DIV (0x1) // 0~0xf -+ -+/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ -+#define AST_I2CD_tTIMEOUT (0x1) // 0~7 -+#define AST_NO_TIMEOUT_CTRL 0x0 -+ -+ -+/* 0x0c : I2CD Interrupt Control Register */ -+#define AST_I2CD_SDA_DL_TO_INTR_EN (0x1 << 14) -+#define AST_I2CD_BUS_RECOVER_INTR_EN (0x1 << 13) -+#define AST_I2CD_SMBUS_ALT_INTR_EN (0x1 << 12) -+#define AST_I2CD_SLAVE_MATCH_INTR_EN (0x1 << 7) -+#define AST_I2CD_SCL_TO_INTR_EN (0x1 << 6) -+#define AST_I2CD_ABNORMAL_INTR_EN (0x1 << 5) -+#define AST_I2CD_NORMAL_STOP_INTR_EN (0x1 << 4) -+#define AST_I2CD_ARBIT_LOSS_INTR_EN (0x1 << 3) -+#define AST_I2CD_RX_DOWN_INTR_EN (0x1 << 2) -+#define AST_I2CD_TX_NAK_INTR_EN (0x1 << 1) -+#define AST_I2CD_TX_ACK_INTR_EN (0x1) -+ -+/* 0x10 : I2CD Interrupt Status Register : WC */ -+#define AST_I2CD_INTR_STS_SDA_DL_TO (0x1 << 14) -+#define AST_I2CD_INTR_STS_BUS_RECOVER (0x1 << 13) -+#define AST_I2CD_INTR_STS_SMBUS_ALT (0x1 << 12) -+#define AST_I2CD_INTR_STS_SMBUS_ARP_ADDR (0x1 << 11) -+#define AST_I2CD_INTR_STS_SMBUS_DEV_ALT (0x1 << 10) -+#define AST_I2CD_INTR_STS_SMBUS_DEF_ADDR (0x1 << 9) -+#define AST_I2CD_INTR_STS_GCALL_ADDR (0x1 << 8) -+#define AST_I2CD_INTR_STS_SLAVE_MATCH (0x1 << 7) -+#define AST_I2CD_INTR_STS_SCL_TO (0x1 << 6) -+#define AST_I2CD_INTR_STS_ABNORMAL (0x1 << 5) -+#define AST_I2CD_INTR_STS_NORMAL_STOP (0x1 << 4) -+#define AST_I2CD_INTR_STS_ARBIT_LOSS (0x1 << 3) -+#define AST_I2CD_INTR_STS_RX_DOWN (0x1 << 2) -+#define AST_I2CD_INTR_STS_TX_NAK (0x1 << 1) -+#define AST_I2CD_INTR_STS_TX_ACK (0x1) -+ -+/* 0x14 : I2CD Command/Status Register */ -+#define AST_I2CD_SDA_OE (0x1 << 28) -+#define AST_I2CD_SDA_O (0x1 << 27) -+#define AST_I2CD_SCL_OE (0x1 << 26) -+#define AST_I2CD_SCL_O (0x1 << 25) -+#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3 -+#define AST_I2CD_TX_STATUS (0x1 << 23) -+// Tx State Machine -+#define AST_I2CD_IDLE 0x0 -+#define AST_I2CD_MACTIVE 0x8 -+#define AST_I2CD_MSTART 0x9 -+#define AST_I2CD_MSTARTR 0xa -+#define AST_I2CD_MSTOP 0xb -+#define AST_I2CD_MTXD 0xc -+#define AST_I2CD_MRXACK 0xd -+#define AST_I2CD_MRXD 0xe -+#define AST_I2CD_MTXACK 0xf -+#define AST_I2CD_SWAIT 0x1 -+#define AST_I2CD_SRXD 0x4 -+#define AST_I2CD_STXACK 0x5 -+#define AST_I2CD_STXD 0x6 -+#define AST_I2CD_SRXACK 0x7 -+#define AST_I2CD_RECOVER 0x3 -+ -+#define AST_I2CD_SCL_LINE_STS (0x1 << 18) -+#define AST_I2CD_SDA_LINE_STS (0x1 << 17) -+#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) -+#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) -+#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) -+#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) -+#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) -+#define AST_I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) -+#define AST_I2CD_S_ALT_EN (0x1 << 10) -+// 0 : DMA Buffer, 1: Pool Buffer -+//AST1070 DMA register -+#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) -+#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) -+ -+/* Command Bit */ -+#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) -+#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) -+#define AST_I2CD_M_STOP_CMD (0x1 << 5) -+#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) -+#define AST_I2CD_M_RX_CMD (0x1 << 3) -+#define AST_I2CD_S_TX_CMD (0x1 << 2) -+#define AST_I2CD_M_TX_CMD (0x1 << 1) -+#define AST_I2CD_M_START_CMD (0x1) -+ -+/* 0x18 : I2CD Slave Device Address Register */ -+ -+/* 0x1C : I2CD Pool Buffer Control Register */ -+#define AST_I2CD_RX_BUF_ADDR_GET(x) ((x >> 24) & 0xff) -+#define AST_I2CD_RX_BUF_END_ADDR_SET(x) (x << 16) -+#define AST_I2CD_TX_DATA_BUF_END_SET(x) ((x & 0xff) << 8) -+#define AST_I2CD_TX_DATA_BUF_GET(x) ((x >> 8) & 0xff) -+#define AST_I2CD_BUF_BASE_ADDR_SET(x) (x & 0x3f) -+ -+/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ -+#define AST_I2CD_GET_MODE(x) ((x >> 8) & 0x1) -+ -+#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8) -+#define AST_I2CD_TX_BYTE_BUFFER (0xff) -+ -+ -+#endif /* __ASM_ARCH_REGS_IIC_H */ -diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index 976c59b..537cd4b 100644 ---- a/arch/arm/mach-aspeed/ast-scu.c -+++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -112,6 +112,12 @@ static struct soc_id soc_map_table[] = { - SOC_ID("AST2530-A2", 0x04030403), - }; - -+void ast_scu_init_i2c(void) -+{ -+ ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_I2C, -+ AST_SCU_RESET); -+} -+ - void ast_scu_init_eth(u8 num) - { - /* Set MAC delay Timing */ -@@ -292,6 +298,23 @@ u32 ast_get_ahbclk(void) - return ((hpll / axi_div) / ahb_div); - } - -+u32 ast_get_pclk(void) -+{ -+ unsigned int div, hpll; -+ -+ hpll = ast_get_h_pll_clk(); -+ div = SCU_GET_PCLK_DIV(ast_scu_read(AST_SCU_CLK_SEL)); -+#ifdef AST_SOC_G5 -+ div = (div+1) << 2; -+#else -+ div = (div+1) << 1; -+#endif -+ -+ debug("HPLL=%d, Div=%d, PCLK=%d\n", hpll, div, hpll/div); -+ return (hpll/div); -+} -+ -+ - #else /* ! AST_SOC_G5 */ - - u32 ast_get_h_pll_clk(void) -@@ -457,6 +480,105 @@ void ast_scu_multi_func_sgpio(void) - AST_SCU_FUN_PIN_CTRL2); - } - -+extern void ast_scu_multi_func_i2c(u8 bus_no) -+{ -+#ifdef CONFIG_ARCH_AST1010 -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL4) | -+ SCU_FUN_PIN_SCL13 | -+ SCU_FUN_PIN_SDA13 | -+ SCU_FUN_PIN_SCL14 | -+ SCU_FUN_PIN_SDA14, -+ AST_SCU_FUN_PIN_CTRL4); -+ -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL2) | -+ SCU_FUN_PIN_SCL1 | -+ SCU_FUN_PIN_SDA1 | -+ SCU_FUN_PIN_SCL2 | -+ SCU_FUN_PIN_SDA2 | -+ SCU_FUN_PIN_SCL3 | -+ SCU_FUN_PIN_SDA3 | -+ SCU_FUN_PIN_SCL4 | -+ SCU_FUN_PIN_SDA4 | -+ SCU_FUN_PIN_SCL5 | -+ SCU_FUN_PIN_SDA5 | -+ SCU_FUN_PIN_SCL6 | -+ SCU_FUN_PIN_SDA6 | -+ SCU_FUN_PIN_SCL7 | -+ SCU_FUN_PIN_SDA7 | -+ SCU_FUN_PIN_SCL8 | -+ SCU_FUN_PIN_SDA8 | -+ SCU_FUN_PIN_SALT1 | -+ SCU_FUN_PIN_SALT2 | -+ SCU_FUN_PIN_SALT3 | -+ SCU_FUN_PIN_SALT4, -+ AST_SCU_FUN_PIN_CTRL2); -+ -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | -+ SCU_FUN_PIN_SCL9 | -+ SCU_FUN_PIN_SDA9 | -+ SCU_FUN_PIN_SCL10 | -+ SCU_FUN_PIN_SDA10 | -+ SCU_FUN_PIN_SCL11 | -+ SCU_FUN_PIN_SDA11 | -+ SCU_FUN_PIN_SCL12 | -+ SCU_FUN_PIN_SDA12, -+ AST_SCU_FUN_PIN_CTRL1); -+#else -+ //TODO check ... //In AST2400 Due to share pin with SD , please not enable I2C 10 ~14 -+ // AST 2400 have 14 , AST 2300 9 ... -+ u32 pin_ctrl = ast_scu_read(AST_SCU_FUN_PIN_CTRL5); -+ switch (bus_no) { -+ case 0: -+ break; -+ case 1: -+ break; -+ case 2: -+ pin_ctrl |= SCU_FUC_PIN_I2C3; -+ break; -+ case 3: -+ pin_ctrl |= SCU_FUC_PIN_I2C4; -+ break; -+ case 4: -+ pin_ctrl |= SCU_FUC_PIN_I2C5; -+ break; -+ case 5: -+ pin_ctrl |= SCU_FUC_PIN_I2C6; -+ break; -+ case 6: -+ pin_ctrl |= SCU_FUC_PIN_I2C7; -+ break; -+ case 7: -+ pin_ctrl |= SCU_FUC_PIN_I2C8; -+ break; -+ case 8: -+ pin_ctrl |= SCU_FUC_PIN_I2C9; -+ break; -+ case 9: -+ pin_ctrl |= SCU_FUC_PIN_I2C10; -+ pin_ctrl &= ~SCU_FUC_PIN_SD1; -+ break; -+ case 10: -+ pin_ctrl |= SCU_FUC_PIN_I2C11; -+ pin_ctrl &= ~SCU_FUC_PIN_SD1; -+ break; -+ case 11: -+ pin_ctrl |= SCU_FUC_PIN_I2C12; -+ pin_ctrl &= ~SCU_FUC_PIN_SD1; -+ break; -+ case 12: -+ pin_ctrl |= SCU_FUC_PIN_I2C13; -+ pin_ctrl &= ~SCU_FUC_PIN_SD1; -+ break; -+ case 13: -+ pin_ctrl |= SCU_FUC_PIN_I2C14; -+ break; -+ } -+ -+ ast_scu_write(pin_ctrl, AST_SCU_FUN_PIN_CTRL5); -+#endif -+} -+ -+ - u32 ast_scu_revision_id(void) - { - int i; -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index 0953677..3c33546 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - - #include "ast-g5.h" - -@@ -37,6 +38,13 @@ int board_init(void) - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - gd->flags = 0; - -+ /* Initialize I2C */ -+#if defined(CONFIG_SYS_I2C) -+ i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr); -+#else -+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -+#endif -+ - ast_g5_intel(); - return 0; - } -diff --git a/configs/ast_g5_phy_defconfig b/configs/ast_g5_phy_defconfig -index 4aefcf4..1b96ab7 100644 ---- a/configs/ast_g5_phy_defconfig -+++ b/configs/ast_g5_phy_defconfig -@@ -13,3 +13,5 @@ CONFIG_OF_LIBFDT=y - CONFIG_SPI_FLASH=y - CONFIG_SYS_NS16550=y - CONFIG_USE_IRQ=y -+CONFIG_CMD_I2C=y -+CONFIG_SYS_I2C_AST=y -diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig -index 6e22bba..5368ba2 100644 ---- a/drivers/i2c/Kconfig -+++ b/drivers/i2c/Kconfig -@@ -58,6 +58,11 @@ config DM_I2C_GPIO - bindings are supported. - Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt - -+config SYS_I2C_AST -+ bool "Aspeed I2C bus driver" -+ help -+ Add support for Aspeed I2C busses on AST2500 processors. -+ - config SYS_I2C_FSL - bool "Freescale I2C bus driver" - depends on DM_I2C -diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile -index 167424d..b2a69ea 100644 ---- a/drivers/i2c/Makefile -+++ b/drivers/i2c/Makefile -@@ -11,6 +11,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o - obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o - - obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o -+obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o - obj-$(CONFIG_I2C_MV) += mv_i2c.o - obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o - obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o -diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c -new file mode 100644 -index 0000000..533419f ---- /dev/null -+++ b/drivers/i2c/ast_i2c.c -@@ -0,0 +1,852 @@ -+/* -+ * i2c_adap_ast.c -+ * -+ * I2C adapter for the ASPEED I2C bus access. -+ * -+ * Copyright (C) 2012-2020 ASPEED Technology Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * History: -+ * 2012.07.26: Initial version [Ryan Chen] -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+ -+// AST2400 buffer mode issue , force I2C slave write use byte mode , read use -+// buffer mode -+/* Use platform_data instead of module parameters */ -+/* Fast Mode = 400 kHz, Standard = 100 kHz */ -+// static int clock = 100; /* Default: 100 kHz */ -+ -+/***************************************************************************/ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#define I2C_TIMEOUT_COUNT 200 -+#define I2C_SLEEP_US 1000 -+ -+static unsigned int i2c_bus_num __attribute__((section(".data"))); -+ -+/* Information about i2c controller */ -+struct ast_i2c_bus { -+ u32 reg_base; /* virtual */ -+ u32 speed; -+ u32 state; /* I2C xfer mode state matchine */ -+ u16 addr; /* slave address */ -+ u16 flags; -+ u16 a_len; /* msg length */ -+ u8 *a_buf; /* pointer to msg data */ -+ u16 d_len; /* msg length */ -+ u8 *d_buf; /* pointer to msg data */ -+}; -+ -+static struct ast_i2c_bus ast_i2c[NUM_BUS] __attribute__((section(".data"))); -+ -+struct ast_i2c_timing_table { -+ u32 divisor; -+ u32 timing; -+}; -+ -+static struct ast_i2c_timing_table i2c_timing_table[] = { -+#if defined(AST_SOC_G5) -+ /* Divisor : Base Clock : tCK High : tCK Low */ -+ /* Divisor : [3:0] : [19:16]: [15:12] */ -+ { 6, 0x77700300 | (0x0) | (0x2 << 16) | (0x2 << 12) }, -+ { 7, 0x77700300 | (0x0) | (0x3 << 16) | (0x2 << 12) }, -+ { 8, 0x77700300 | (0x0) | (0x3 << 16) | (0x3 << 12) }, -+ { 9, 0x77700300 | (0x0) | (0x4 << 16) | (0x3 << 12) }, -+ { 10, 0x77700300 | (0x0) | (0x4 << 16) | (0x4 << 12) }, -+ { 11, 0x77700300 | (0x0) | (0x5 << 16) | (0x4 << 12) }, -+ { 12, 0x77700300 | (0x0) | (0x5 << 16) | (0x5 << 12) }, -+ { 13, 0x77700300 | (0x0) | (0x6 << 16) | (0x5 << 12) }, -+ { 14, 0x77700300 | (0x0) | (0x6 << 16) | (0x6 << 12) }, -+ { 15, 0x77700300 | (0x0) | (0x7 << 16) | (0x6 << 12) }, -+ { 16, 0x77700300 | (0x0) | (0x7 << 16) | (0x7 << 12) }, -+ { 17, 0x77700300 | (0x0) | (0x8 << 16) | (0x7 << 12) }, -+ { 18, 0x77700300 | (0x0) | (0x8 << 16) | (0x8 << 12) }, -+ { 19, 0x77700300 | (0x0) | (0x9 << 16) | (0x8 << 12) }, -+ { 20, 0x77700300 | (0x0) | (0x9 << 16) | (0x9 << 12) }, -+ { 21, 0x77700300 | (0x0) | (0xa << 16) | (0x9 << 12) }, -+ { 22, 0x77700300 | (0x0) | (0xa << 16) | (0xa << 12) }, -+ { 23, 0x77700300 | (0x0) | (0xb << 16) | (0xa << 12) }, -+ { 24, 0x77700300 | (0x0) | (0xb << 16) | (0xb << 12) }, -+ { 25, 0x77700300 | (0x0) | (0xc << 16) | (0xb << 12) }, -+ { 26, 0x77700300 | (0x0) | (0xc << 16) | (0xc << 12) }, -+ { 27, 0x77700300 | (0x0) | (0xd << 16) | (0xc << 12) }, -+ { 28, 0x77700300 | (0x0) | (0xd << 16) | (0xd << 12) }, -+ { 29, 0x77700300 | (0x0) | (0xe << 16) | (0xd << 12) }, -+ { 30, 0x77700300 | (0x0) | (0xe << 16) | (0xe << 12) }, -+ { 31, 0x77700300 | (0x0) | (0xf << 16) | (0xe << 12) }, -+ { 32, 0x77700300 | (0x0) | (0xf << 16) | (0xf << 12) }, -+ -+ { 34, 0x77700300 | (0x1) | (0x8 << 16) | (0x7 << 12) }, -+ { 36, 0x77700300 | (0x1) | (0x8 << 16) | (0x8 << 12) }, -+ { 38, 0x77700300 | (0x1) | (0x9 << 16) | (0x8 << 12) }, -+ { 40, 0x77700300 | (0x1) | (0x9 << 16) | (0x9 << 12) }, -+ { 42, 0x77700300 | (0x1) | (0xa << 16) | (0x9 << 12) }, -+ { 44, 0x77700300 | (0x1) | (0xa << 16) | (0xa << 12) }, -+ { 46, 0x77700300 | (0x1) | (0xb << 16) | (0xa << 12) }, -+ { 48, 0x77700300 | (0x1) | (0xb << 16) | (0xb << 12) }, -+ { 50, 0x77700300 | (0x1) | (0xc << 16) | (0xb << 12) }, -+ { 52, 0x77700300 | (0x1) | (0xc << 16) | (0xc << 12) }, -+ { 54, 0x77700300 | (0x1) | (0xd << 16) | (0xc << 12) }, -+ { 56, 0x77700300 | (0x1) | (0xd << 16) | (0xd << 12) }, -+ { 58, 0x77700300 | (0x1) | (0xe << 16) | (0xd << 12) }, -+ { 60, 0x77700300 | (0x1) | (0xe << 16) | (0xe << 12) }, -+ { 62, 0x77700300 | (0x1) | (0xf << 16) | (0xe << 12) }, -+ { 64, 0x77700300 | (0x1) | (0xf << 16) | (0xf << 12) }, -+ -+ { 68, 0x77700300 | (0x2) | (0x8 << 16) | (0x7 << 12) }, -+ { 72, 0x77700300 | (0x2) | (0x8 << 16) | (0x8 << 12) }, -+ { 76, 0x77700300 | (0x2) | (0x9 << 16) | (0x8 << 12) }, -+ { 80, 0x77700300 | (0x2) | (0x9 << 16) | (0x9 << 12) }, -+ { 84, 0x77700300 | (0x2) | (0xa << 16) | (0x9 << 12) }, -+ { 88, 0x77700300 | (0x2) | (0xa << 16) | (0xa << 12) }, -+ { 92, 0x77700300 | (0x2) | (0xb << 16) | (0xa << 12) }, -+ { 96, 0x77700300 | (0x2) | (0xb << 16) | (0xb << 12) }, -+ { 100, 0x77700300 | (0x2) | (0xc << 16) | (0xb << 12) }, -+ { 104, 0x77700300 | (0x2) | (0xc << 16) | (0xc << 12) }, -+ { 108, 0x77700300 | (0x2) | (0xd << 16) | (0xc << 12) }, -+ { 112, 0x77700300 | (0x2) | (0xd << 16) | (0xd << 12) }, -+ { 116, 0x77700300 | (0x2) | (0xe << 16) | (0xd << 12) }, -+ { 120, 0x77700300 | (0x2) | (0xe << 16) | (0xe << 12) }, -+ { 124, 0x77700300 | (0x2) | (0xf << 16) | (0xe << 12) }, -+ { 128, 0x77700300 | (0x2) | (0xf << 16) | (0xf << 12) }, -+ -+ { 136, 0x77700300 | (0x3) | (0x8 << 16) | (0x7 << 12) }, -+ { 144, 0x77700300 | (0x3) | (0x8 << 16) | (0x8 << 12) }, -+ { 152, 0x77700300 | (0x3) | (0x9 << 16) | (0x8 << 12) }, -+ { 160, 0x77700300 | (0x3) | (0x9 << 16) | (0x9 << 12) }, -+ { 168, 0x77700300 | (0x3) | (0xa << 16) | (0x9 << 12) }, -+ { 176, 0x77700300 | (0x3) | (0xa << 16) | (0xa << 12) }, -+ { 184, 0x77700300 | (0x3) | (0xb << 16) | (0xa << 12) }, -+ { 192, 0x77700300 | (0x3) | (0xb << 16) | (0xb << 12) }, -+ { 200, 0x77700300 | (0x3) | (0xc << 16) | (0xb << 12) }, -+ { 208, 0x77700300 | (0x3) | (0xc << 16) | (0xc << 12) }, -+ { 216, 0x77700300 | (0x3) | (0xd << 16) | (0xc << 12) }, -+ { 224, 0x77700300 | (0x3) | (0xd << 16) | (0xd << 12) }, -+ { 232, 0x77700300 | (0x3) | (0xe << 16) | (0xd << 12) }, -+ { 240, 0x77700300 | (0x3) | (0xe << 16) | (0xe << 12) }, -+ { 248, 0x77700300 | (0x3) | (0xf << 16) | (0xe << 12) }, -+ { 256, 0x77700300 | (0x3) | (0xf << 16) | (0xf << 12) }, -+ -+ { 272, 0x77700300 | (0x4) | (0x8 << 16) | (0x7 << 12) }, -+ { 288, 0x77700300 | (0x4) | (0x8 << 16) | (0x8 << 12) }, -+ { 304, 0x77700300 | (0x4) | (0x9 << 16) | (0x8 << 12) }, -+ { 320, 0x77700300 | (0x4) | (0x9 << 16) | (0x9 << 12) }, -+ { 336, 0x77700300 | (0x4) | (0xa << 16) | (0x9 << 12) }, -+ { 352, 0x77700300 | (0x4) | (0xa << 16) | (0xa << 12) }, -+ { 368, 0x77700300 | (0x4) | (0xb << 16) | (0xa << 12) }, -+ { 384, 0x77700300 | (0x4) | (0xb << 16) | (0xb << 12) }, -+ { 400, 0x77700300 | (0x4) | (0xc << 16) | (0xb << 12) }, -+ { 416, 0x77700300 | (0x4) | (0xc << 16) | (0xc << 12) }, -+ { 432, 0x77700300 | (0x4) | (0xd << 16) | (0xc << 12) }, -+ { 448, 0x77700300 | (0x4) | (0xd << 16) | (0xd << 12) }, -+ { 464, 0x77700300 | (0x4) | (0xe << 16) | (0xd << 12) }, -+ { 480, 0x77700300 | (0x4) | (0xe << 16) | (0xe << 12) }, -+ { 496, 0x77700300 | (0x4) | (0xf << 16) | (0xe << 12) }, -+ { 512, 0x77700300 | (0x4) | (0xf << 16) | (0xf << 12) }, -+ -+ { 544, 0x77700300 | (0x5) | (0x8 << 16) | (0x7 << 12) }, -+ { 576, 0x77700300 | (0x5) | (0x8 << 16) | (0x8 << 12) }, -+ { 608, 0x77700300 | (0x5) | (0x9 << 16) | (0x8 << 12) }, -+ { 640, 0x77700300 | (0x5) | (0x9 << 16) | (0x9 << 12) }, -+ { 672, 0x77700300 | (0x5) | (0xa << 16) | (0x9 << 12) }, -+ { 704, 0x77700300 | (0x5) | (0xa << 16) | (0xa << 12) }, -+ { 736, 0x77700300 | (0x5) | (0xb << 16) | (0xa << 12) }, -+ { 768, 0x77700300 | (0x5) | (0xb << 16) | (0xb << 12) }, -+ { 800, 0x77700300 | (0x5) | (0xc << 16) | (0xb << 12) }, -+ { 832, 0x77700300 | (0x5) | (0xc << 16) | (0xc << 12) }, -+ { 864, 0x77700300 | (0x5) | (0xd << 16) | (0xc << 12) }, -+ { 896, 0x77700300 | (0x5) | (0xd << 16) | (0xd << 12) }, -+ { 928, 0x77700300 | (0x5) | (0xe << 16) | (0xd << 12) }, -+ { 960, 0x77700300 | (0x5) | (0xe << 16) | (0xe << 12) }, -+ { 992, 0x77700300 | (0x5) | (0xf << 16) | (0xe << 12) }, -+ { 1024, 0x77700300 | (0x5) | (0xf << 16) | (0xf << 12) }, -+ -+ { 1088, 0x77700300 | (0x6) | (0x8 << 16) | (0x7 << 12) }, -+ { 1152, 0x77700300 | (0x6) | (0x8 << 16) | (0x8 << 12) }, -+ { 1216, 0x77700300 | (0x6) | (0x9 << 16) | (0x8 << 12) }, -+ { 1280, 0x77700300 | (0x6) | (0x9 << 16) | (0x9 << 12) }, -+ { 1344, 0x77700300 | (0x6) | (0xa << 16) | (0x9 << 12) }, -+ { 1408, 0x77700300 | (0x6) | (0xa << 16) | (0xa << 12) }, -+ { 1472, 0x77700300 | (0x6) | (0xb << 16) | (0xa << 12) }, -+ { 1536, 0x77700300 | (0x6) | (0xb << 16) | (0xb << 12) }, -+ { 1600, 0x77700300 | (0x6) | (0xc << 16) | (0xb << 12) }, -+ { 1664, 0x77700300 | (0x6) | (0xc << 16) | (0xc << 12) }, -+ { 1728, 0x77700300 | (0x6) | (0xd << 16) | (0xc << 12) }, -+ { 1792, 0x77700300 | (0x6) | (0xd << 16) | (0xd << 12) }, -+ { 1856, 0x77700300 | (0x6) | (0xe << 16) | (0xd << 12) }, -+ { 1920, 0x77700300 | (0x6) | (0xe << 16) | (0xe << 12) }, -+ { 1984, 0x77700300 | (0x6) | (0xf << 16) | (0xe << 12) }, -+ { 2048, 0x77700300 | (0x6) | (0xf << 16) | (0xf << 12) }, -+ -+ { 2176, 0x77700300 | (0x7) | (0x8 << 16) | (0x7 << 12) }, -+ { 2304, 0x77700300 | (0x7) | (0x8 << 16) | (0x8 << 12) }, -+ { 2432, 0x77700300 | (0x7) | (0x9 << 16) | (0x8 << 12) }, -+ { 2560, 0x77700300 | (0x7) | (0x9 << 16) | (0x9 << 12) }, -+ { 2688, 0x77700300 | (0x7) | (0xa << 16) | (0x9 << 12) }, -+ { 2816, 0x77700300 | (0x7) | (0xa << 16) | (0xa << 12) }, -+ { 2944, 0x77700300 | (0x7) | (0xb << 16) | (0xa << 12) }, -+ { 3072, 0x77700300 | (0x7) | (0xb << 16) | (0xb << 12) }, -+#else -+ /* Divisor : [3:0] : [18:16]: [13:12] */ -+ { 6, 0x77700300 | (0x0) | (0x2 << 16) | (0x2 << 12) }, -+ { 7, 0x77700300 | (0x0) | (0x3 << 16) | (0x2 << 12) }, -+ { 8, 0x77700300 | (0x0) | (0x3 << 16) | (0x3 << 12) }, -+ { 9, 0x77700300 | (0x0) | (0x4 << 16) | (0x3 << 12) }, -+ { 10, 0x77700300 | (0x0) | (0x4 << 16) | (0x4 << 12) }, -+ { 11, 0x77700300 | (0x0) | (0x5 << 16) | (0x4 << 12) }, -+ { 12, 0x77700300 | (0x0) | (0x5 << 16) | (0x5 << 12) }, -+ { 13, 0x77700300 | (0x0) | (0x6 << 16) | (0x5 << 12) }, -+ { 14, 0x77700300 | (0x0) | (0x6 << 16) | (0x6 << 12) }, -+ { 15, 0x77700300 | (0x0) | (0x7 << 16) | (0x6 << 12) }, -+ { 16, 0x77700300 | (0x0) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 18, 0x77700300 | (0x1) | (0x4 << 16) | (0x3 << 12) }, -+ { 20, 0x77700300 | (0x1) | (0x4 << 16) | (0x4 << 12) }, -+ { 22, 0x77700300 | (0x1) | (0x5 << 16) | (0x4 << 12) }, -+ { 24, 0x77700300 | (0x1) | (0x5 << 16) | (0x5 << 12) }, -+ { 26, 0x77700300 | (0x1) | (0x6 << 16) | (0x5 << 12) }, -+ { 28, 0x77700300 | (0x1) | (0x6 << 16) | (0x6 << 12) }, -+ { 30, 0x77700300 | (0x1) | (0x7 << 16) | (0x6 << 12) }, -+ { 32, 0x77700300 | (0x1) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 36, 0x77700300 | (0x2) | (0x4 << 16) | (0x3 << 12) }, -+ { 40, 0x77700300 | (0x2) | (0x4 << 16) | (0x4 << 12) }, -+ { 44, 0x77700300 | (0x2) | (0x5 << 16) | (0x4 << 12) }, -+ { 48, 0x77700300 | (0x2) | (0x5 << 16) | (0x5 << 12) }, -+ { 52, 0x77700300 | (0x2) | (0x6 << 16) | (0x5 << 12) }, -+ { 56, 0x77700300 | (0x2) | (0x6 << 16) | (0x6 << 12) }, -+ { 60, 0x77700300 | (0x2) | (0x7 << 16) | (0x6 << 12) }, -+ { 64, 0x77700300 | (0x2) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 72, 0x77700300 | (0x3) | (0x4 << 16) | (0x3 << 12) }, -+ { 80, 0x77700300 | (0x3) | (0x4 << 16) | (0x4 << 12) }, -+ { 88, 0x77700300 | (0x3) | (0x5 << 16) | (0x4 << 12) }, -+ { 96, 0x77700300 | (0x3) | (0x5 << 16) | (0x5 << 12) }, -+ { 104, 0x77700300 | (0x3) | (0x6 << 16) | (0x5 << 12) }, -+ { 112, 0x77700300 | (0x3) | (0x6 << 16) | (0x6 << 12) }, -+ { 120, 0x77700300 | (0x3) | (0x7 << 16) | (0x6 << 12) }, -+ { 128, 0x77700300 | (0x3) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 144, 0x77700300 | (0x4) | (0x4 << 16) | (0x3 << 12) }, -+ { 160, 0x77700300 | (0x4) | (0x4 << 16) | (0x4 << 12) }, -+ { 176, 0x77700300 | (0x4) | (0x5 << 16) | (0x4 << 12) }, -+ { 192, 0x77700300 | (0x4) | (0x5 << 16) | (0x5 << 12) }, -+ { 208, 0x77700300 | (0x4) | (0x6 << 16) | (0x5 << 12) }, -+ { 224, 0x77700300 | (0x4) | (0x6 << 16) | (0x6 << 12) }, -+ { 240, 0x77700300 | (0x4) | (0x7 << 16) | (0x6 << 12) }, -+ { 256, 0x77700300 | (0x4) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 288, 0x77700300 | (0x5) | (0x4 << 16) | (0x3 << 12) }, -+ { 320, 0x77700300 | (0x5) | (0x4 << 16) | (0x4 << 12) }, -+ { 352, 0x77700300 | (0x5) | (0x5 << 16) | (0x4 << 12) }, -+ { 384, 0x77700300 | (0x5) | (0x5 << 16) | (0x5 << 12) }, -+ { 416, 0x77700300 | (0x5) | (0x6 << 16) | (0x5 << 12) }, -+ { 448, 0x77700300 | (0x5) | (0x6 << 16) | (0x6 << 12) }, -+ { 480, 0x77700300 | (0x5) | (0x7 << 16) | (0x6 << 12) }, -+ { 512, 0x77700300 | (0x5) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 576, 0x77700300 | (0x6) | (0x4 << 16) | (0x3 << 12) }, -+ { 640, 0x77700300 | (0x6) | (0x4 << 16) | (0x4 << 12) }, -+ { 704, 0x77700300 | (0x6) | (0x5 << 16) | (0x4 << 12) }, -+ { 768, 0x77700300 | (0x6) | (0x5 << 16) | (0x5 << 12) }, -+ { 832, 0x77700300 | (0x6) | (0x6 << 16) | (0x5 << 12) }, -+ { 896, 0x77700300 | (0x6) | (0x6 << 16) | (0x6 << 12) }, -+ { 960, 0x77700300 | (0x6) | (0x7 << 16) | (0x6 << 12) }, -+ { 1024, 0x77700300 | (0x6) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 1152, 0x77700300 | (0x7) | (0x4 << 16) | (0x3 << 12) }, -+ { 1280, 0x77700300 | (0x7) | (0x4 << 16) | (0x4 << 12) }, -+ { 1408, 0x77700300 | (0x7) | (0x5 << 16) | (0x4 << 12) }, -+ { 1536, 0x77700300 | (0x7) | (0x5 << 16) | (0x5 << 12) }, -+ { 1664, 0x77700300 | (0x7) | (0x6 << 16) | (0x5 << 12) }, -+ { 1792, 0x77700300 | (0x7) | (0x6 << 16) | (0x6 << 12) }, -+ { 1920, 0x77700300 | (0x7) | (0x7 << 16) | (0x6 << 12) }, -+ { 2048, 0x77700300 | (0x7) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 2304, 0x77700300 | (0x8) | (0x4 << 16) | (0x3 << 12) }, -+ { 2560, 0x77700300 | (0x8) | (0x4 << 16) | (0x4 << 12) }, -+ { 2816, 0x77700300 | (0x8) | (0x5 << 16) | (0x4 << 12) }, -+ { 3072, 0x77700300 | (0x8) | (0x5 << 16) | (0x5 << 12) }, -+ { 3328, 0x77700300 | (0x8) | (0x6 << 16) | (0x5 << 12) }, -+ { 3584, 0x77700300 | (0x8) | (0x6 << 16) | (0x6 << 12) }, -+ { 3840, 0x77700300 | (0x8) | (0x7 << 16) | (0x6 << 12) }, -+ { 4096, 0x77700300 | (0x8) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 4608, 0x77700300 | (0x9) | (0x4 << 16) | (0x3 << 12) }, -+ { 5120, 0x77700300 | (0x9) | (0x4 << 16) | (0x4 << 12) }, -+ { 5632, 0x77700300 | (0x9) | (0x5 << 16) | (0x4 << 12) }, -+ { 6144, 0x77700300 | (0x9) | (0x5 << 16) | (0x5 << 12) }, -+ { 6656, 0x77700300 | (0x9) | (0x6 << 16) | (0x5 << 12) }, -+ { 7168, 0x77700300 | (0x9) | (0x6 << 16) | (0x6 << 12) }, -+ { 7680, 0x77700300 | (0x9) | (0x7 << 16) | (0x6 << 12) }, -+ { 8192, 0x77700300 | (0x9) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 9216, 0x77700300 | (0xa) | (0x4 << 16) | (0x3 << 12) }, -+ { 10240, 0x77700300 | (0xa) | (0x4 << 16) | (0x4 << 12) }, -+ { 11264, 0x77700300 | (0xa) | (0x5 << 16) | (0x4 << 12) }, -+ { 12288, 0x77700300 | (0xa) | (0x5 << 16) | (0x5 << 12) }, -+ { 13312, 0x77700300 | (0xa) | (0x6 << 16) | (0x5 << 12) }, -+ { 14336, 0x77700300 | (0xa) | (0x6 << 16) | (0x6 << 12) }, -+ { 15360, 0x77700300 | (0xa) | (0x7 << 16) | (0x6 << 12) }, -+ { 16384, 0x77700300 | (0xa) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 18432, 0x77700300 | (0xb) | (0x4 << 16) | (0x3 << 12) }, -+ { 20480, 0x77700300 | (0xb) | (0x4 << 16) | (0x4 << 12) }, -+ { 22528, 0x77700300 | (0xb) | (0x5 << 16) | (0x4 << 12) }, -+ { 24576, 0x77700300 | (0xb) | (0x5 << 16) | (0x5 << 12) }, -+ { 26624, 0x77700300 | (0xb) | (0x6 << 16) | (0x5 << 12) }, -+ { 28672, 0x77700300 | (0xb) | (0x6 << 16) | (0x6 << 12) }, -+ { 30720, 0x77700300 | (0xb) | (0x7 << 16) | (0x6 << 12) }, -+ { 32768, 0x77700300 | (0xb) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 36864, 0x77700300 | (0xc) | (0x4 << 16) | (0x3 << 12) }, -+ { 40960, 0x77700300 | (0xc) | (0x4 << 16) | (0x4 << 12) }, -+ { 45056, 0x77700300 | (0xc) | (0x5 << 16) | (0x4 << 12) }, -+ { 49152, 0x77700300 | (0xc) | (0x5 << 16) | (0x5 << 12) }, -+ { 53248, 0x77700300 | (0xc) | (0x6 << 16) | (0x5 << 12) }, -+ { 57344, 0x77700300 | (0xc) | (0x6 << 16) | (0x6 << 12) }, -+ { 61440, 0x77700300 | (0xc) | (0x7 << 16) | (0x6 << 12) }, -+ { 65536, 0x77700300 | (0xc) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 73728, 0x77700300 | (0xd) | (0x4 << 16) | (0x3 << 12) }, -+ { 81920, 0x77700300 | (0xd) | (0x4 << 16) | (0x4 << 12) }, -+ { 90112, 0x77700300 | (0xd) | (0x5 << 16) | (0x4 << 12) }, -+ { 98304, 0x77700300 | (0xd) | (0x5 << 16) | (0x5 << 12) }, -+ { 106496, 0x77700300 | (0xd) | (0x6 << 16) | (0x5 << 12) }, -+ { 114688, 0x77700300 | (0xd) | (0x6 << 16) | (0x6 << 12) }, -+ { 122880, 0x77700300 | (0xd) | (0x7 << 16) | (0x6 << 12) }, -+ { 131072, 0x77700300 | (0xd) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 147456, 0x77700300 | (0xe) | (0x4 << 16) | (0x3 << 12) }, -+ { 163840, 0x77700300 | (0xe) | (0x4 << 16) | (0x4 << 12) }, -+ { 180224, 0x77700300 | (0xe) | (0x5 << 16) | (0x4 << 12) }, -+ { 196608, 0x77700300 | (0xe) | (0x5 << 16) | (0x5 << 12) }, -+ { 212992, 0x77700300 | (0xe) | (0x6 << 16) | (0x5 << 12) }, -+ { 229376, 0x77700300 | (0xe) | (0x6 << 16) | (0x6 << 12) }, -+ { 245760, 0x77700300 | (0xe) | (0x7 << 16) | (0x6 << 12) }, -+ { 262144, 0x77700300 | (0xe) | (0x7 << 16) | (0x7 << 12) }, -+ -+ { 294912, 0x77700300 | (0xf) | (0x4 << 16) | (0x3 << 12) }, -+ { 327680, 0x77700300 | (0xf) | (0x4 << 16) | (0x4 << 12) }, -+ { 360448, 0x77700300 | (0xf) | (0x5 << 16) | (0x4 << 12) }, -+ { 393216, 0x77700300 | (0xf) | (0x5 << 16) | (0x5 << 12) }, -+ { 425984, 0x77700300 | (0xf) | (0x6 << 16) | (0x5 << 12) }, -+ { 458752, 0x77700300 | (0xf) | (0x6 << 16) | (0x6 << 12) }, -+ { 491520, 0x77700300 | (0xf) | (0x7 << 16) | (0x6 << 12) }, -+ { 524288, 0x77700300 | (0xf) | (0x7 << 16) | (0x7 << 12) }, -+#endif -+}; -+ -+static inline void ast_i2c_write(struct ast_i2c_bus *i2c_bus, u32 val, u32 reg) -+{ -+#if 0 -+ printf("%x: W : reg %x , val: %x\n", i2c_bus->reg_base, reg, val); -+#endif -+ __raw_writel(val, i2c_bus->reg_base + reg); -+} -+ -+static inline u32 ast_i2c_read(struct ast_i2c_bus *i2c_bus, u32 reg) -+{ -+#if 0 -+ u32 val = __raw_readl(i2c_bus->reg_base + reg); -+ printf("%x: R : reg %x , val: %x\n", i2c_bus->reg_base, reg, val); -+ return val; -+#else -+ return __raw_readl(i2c_bus->reg_base + reg); -+#endif -+} -+ -+static u32 select_i2c_clock(unsigned int bus_clk) -+{ -+#if 0 -+ unsigned int clk, inc = 0, div, divider_ratio; -+ u32 SCL_Low, SCL_High, data; -+ -+ clk = ast_get_pclk(); -+// debug("pclk = %d\n", clk); -+ divider_ratio = clk / bus_clk; -+ for (div = 0; divider_ratio >= 16; div++) -+ { -+ inc |= (divider_ratio & 1); -+ divider_ratio >>= 1; -+ } -+ divider_ratio += inc; -+ SCL_Low = (divider_ratio >> 1) - 1; -+ SCL_High = divider_ratio - SCL_Low - 2; -+ data = 0x77700300 | (SCL_High << 16) | (SCL_Low << 12) | div; -+// printk("I2CD04 for %d = %08X\n", target_speed, data); -+ return data; -+#else -+ int i; -+ unsigned int clk; -+ u32 data; -+ -+ clk = ast_get_pclk(); -+ // debug("pclk = %d\n", clk); -+ -+ for (i = 0; -+ i < sizeof(i2c_timing_table) / sizeof(struct ast_i2c_timing_table); -+ i++) { -+ if ((clk / i2c_timing_table[i].divisor) < bus_clk) { -+ break; -+ } -+ } -+ data = i2c_timing_table[i].timing; -+ // printk("divisor [%d], timing [%x]\n", i2c_timing_table[i].divisor, -+ // i2c_timing_table[i].timing); -+ return data; -+#endif -+} -+ -+static int ast_i2c_wait_isr(struct ast_i2c_bus *i2c_bus, u32 flag) -+{ -+ int timeout = 0; -+ -+ while (!(ast_i2c_read(i2c_bus, I2C_INTR_STS_REG) & flag) && -+ (timeout < I2C_TIMEOUT_COUNT)) { -+ udelay(I2C_SLEEP_US); -+ timeout++; -+ } -+ -+ /* Clear Interrupt */ -+ ast_i2c_write(i2c_bus, 0xfffffff, I2C_INTR_STS_REG); -+ -+ if (timeout >= I2C_TIMEOUT_COUNT) { -+ debug("%s timed out:- flag: %x\n", __func__, flag); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int ast_i2c_wait_tx(struct ast_i2c_bus *i2c_bus) -+{ -+ int sts; -+ int timeout = 0; -+ while (1) { -+ sts = ast_i2c_read(i2c_bus, I2C_INTR_STS_REG); -+ -+ if (timeout > I2C_TIMEOUT_COUNT) { -+ /* I2C Reset */ -+ debug("Timeout: Bus:%d, Addr:0x%02x\n", i2c_bus_num, -+ i2c_bus->addr); -+ ast_i2c_write(i2c_bus, 0, I2C_FUN_CTRL_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_MASTER_EN, -+ I2C_FUN_CTRL_REG); -+ -+ return -ETIMEDOUT; -+ } else if (sts & AST_I2CD_INTR_STS_TX_NAK) { -+ ast_i2c_write(i2c_bus, AST_I2CD_INTR_STS_TX_NAK, -+ I2C_INTR_STS_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_M_STOP_CMD, -+ I2C_CMD_REG); -+ ast_i2c_wait_isr(i2c_bus, -+ AST_I2CD_INTR_STS_NORMAL_STOP); -+ -+ return -EREMOTEIO; -+ } else if (sts & AST_I2CD_INTR_STS_TX_ACK) { -+ ast_i2c_write(i2c_bus, AST_I2CD_INTR_STS_TX_ACK, -+ I2C_INTR_STS_REG); -+ break; -+ } else { -+ timeout++; -+ } -+ udelay(I2C_SLEEP_US); -+ } -+ -+ return 0; -+} -+ -+static int ast_i2c_deblock(struct ast_i2c_bus *i2c_bus) -+{ -+ u32 csr; -+ int ret = 0; -+ -+ if ((csr = ast_i2c_read(i2c_bus, I2C_CMD_REG)) & -+ AST_I2CD_BUS_BUSY_STS) { -+ if ((csr & AST_I2CD_SDA_LINE_STS) && -+ (csr & AST_I2CD_SCL_LINE_STS)) { -+ /* Bus idle */ -+ debug("Bus(%d) idle\n", i2c_bus_num); -+ ret = 0; -+ } else if (csr & AST_I2CD_SDA_LINE_STS) { -+ /* send stop command */ -+ debug("Unterminated TXN in (%x), sending stop...\n", -+ csr); -+ ast_i2c_write(i2c_bus, AST_I2CD_M_STOP_CMD, -+ I2C_CMD_REG); -+ ret = ast_i2c_wait_isr(i2c_bus, -+ AST_I2CD_INTR_STS_NORMAL_STOP); -+ } else if (csr & AST_I2CD_SCL_LINE_STS) { -+ /* Possibly stuck slave */ -+ debug("Bus stuck (%x), attempting recovery...\n", csr); -+ ast_i2c_write(i2c_bus, AST_I2CD_BUS_RECOVER_CMD_EN, -+ I2C_CMD_REG); -+ ret = ast_i2c_wait_isr(i2c_bus, -+ AST_I2CD_INTR_STS_BUS_RECOVER); -+ } else { -+ debug("Bus(%d) slave(0x%02x) busy. Reseting bus...\n", -+ i2c_bus_num, i2c_bus->addr); -+ ast_i2c_write(i2c_bus, 0, I2C_FUN_CTRL_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_MASTER_EN, -+ I2C_FUN_CTRL_REG); -+ ret = 0; -+ } -+ } -+ -+ return ret; -+} -+ -+static int ast_i2c_xfer(struct ast_i2c_bus *i2c_bus) -+{ -+ int sts, i, ret = 0; -+ -+ /* Clear Interrupt */ -+ ast_i2c_write(i2c_bus, 0xfffffff, I2C_INTR_STS_REG); -+ -+ /* Check for bus busy */ -+ ret = ast_i2c_deblock(i2c_bus); -+ if (ret != 0) -+ return ret; -+ -+ // first start -+ debug(" %sing %d byte%s %s 0x%02x\n", i2c_bus->flags ? "read" : "write", -+ i2c_bus->d_len, i2c_bus->d_len > 1 ? "s" : "", -+ i2c_bus->flags ? "from" : "to", i2c_bus->addr); -+ -+ if (i2c_bus->flags) { -+ // READ -+ if (i2c_bus->a_len) { -+ // send start -+ ast_i2c_write(i2c_bus, (i2c_bus->addr << 1), -+ I2C_BYTE_BUF_REG); -+ ast_i2c_write(i2c_bus, -+ AST_I2CD_M_TX_CMD | AST_I2CD_M_START_CMD, -+ I2C_CMD_REG); -+ -+ /* Wait for ACK */ -+ ret = ast_i2c_wait_tx(i2c_bus); -+ if (ret != 0) -+ return ret; -+ -+ /* Send Offset */ -+ for (i = 0; i < i2c_bus->a_len; i++) { -+ debug("offset [%x]\n", i2c_bus->a_buf[i]); -+ ast_i2c_write(i2c_bus, i2c_bus->a_buf[i], -+ I2C_BYTE_BUF_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD, -+ I2C_CMD_REG); -+ ret = ast_i2c_wait_tx(i2c_bus); -+ if (ret != 0) -+ return ret; -+ } -+ } -+ -+ // repeat-start -+ ast_i2c_write(i2c_bus, (i2c_bus->addr << 1) | 0x1, -+ I2C_BYTE_BUF_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD | AST_I2CD_M_START_CMD, -+ I2C_CMD_REG); -+ ret = ast_i2c_wait_tx(i2c_bus); -+ if (ret != 0) -+ return ret; -+ -+ for (i = 0; i < i2c_bus->d_len; i++) { -+ if (i == (i2c_bus->d_len - 1)) { -+ ast_i2c_write(i2c_bus, -+ AST_I2CD_M_RX_CMD | -+ AST_I2CD_M_S_RX_CMD_LAST, -+ I2C_CMD_REG); -+ } else { -+ ast_i2c_write(i2c_bus, AST_I2CD_M_RX_CMD, -+ I2C_CMD_REG); -+ } -+ -+ ret = ast_i2c_wait_isr(i2c_bus, -+ AST_I2CD_INTR_STS_RX_DOWN); -+ if (ret != 0) -+ return ret; -+ -+ i2c_bus->d_buf[i] = -+ (ast_i2c_read(i2c_bus, I2C_BYTE_BUF_REG) & -+ AST_I2CD_RX_BYTE_BUFFER) >> -+ 8; -+ } -+ ast_i2c_write(i2c_bus, AST_I2CD_M_STOP_CMD, I2C_CMD_REG); -+ ret = ast_i2c_wait_isr(i2c_bus, AST_I2CD_INTR_STS_NORMAL_STOP); -+ if (ret != 0) -+ return ret; -+ -+ } else { -+ // Write -+ // send start -+ ast_i2c_write(i2c_bus, (i2c_bus->addr << 1), I2C_BYTE_BUF_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD | AST_I2CD_M_START_CMD, -+ I2C_CMD_REG); -+ -+ /* Wait for ACK */ -+ ret = ast_i2c_wait_tx(i2c_bus); -+ if (ret != 0) -+ return ret; -+ -+ /* Send Offset */ -+ for (i = 0; i < i2c_bus->a_len; i++) { -+ debug("offset [%x]\n", i2c_bus->a_buf[i]); -+ ast_i2c_write(i2c_bus, i2c_bus->a_buf[i], -+ I2C_BYTE_BUF_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD, I2C_CMD_REG); -+ ret = ast_i2c_wait_tx(i2c_bus); -+ if (ret != 0) -+ return ret; -+ } -+ -+ /* Tx data */ -+ for (i = 0; i < i2c_bus->d_len; i++) { -+ debug("Tx data [%x]\n", i2c_bus->d_buf[i]); -+ ast_i2c_write(i2c_bus, i2c_bus->d_buf[i], -+ I2C_BYTE_BUF_REG); -+ ast_i2c_write(i2c_bus, AST_I2CD_M_TX_CMD, I2C_CMD_REG); -+ ret = ast_i2c_wait_tx(i2c_bus); -+ if (ret != 0) -+ return ret; -+ } -+ ast_i2c_write(i2c_bus, AST_I2CD_M_STOP_CMD, I2C_CMD_REG); -+ ret = ast_i2c_wait_isr(i2c_bus, AST_I2CD_INTR_STS_NORMAL_STOP); -+ if (ret != 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/*****************************************************************************/ -+ -+unsigned int i2c_get_bus_speed(void) -+{ -+ return ast_i2c[i2c_bus_num].speed; -+} -+ -+int i2c_set_bus_speed(unsigned int speed) -+{ -+ struct ast_i2c_bus *i2c_bus = &ast_i2c[i2c_bus_num]; -+ -+ /* Set AC Timing */ -+ ast_i2c_write(i2c_bus, select_i2c_clock(speed), I2C_AC_TIMING_REG1); -+ ast_i2c_write(i2c_bus, AST_NO_TIMEOUT_CTRL, I2C_AC_TIMING_REG2); -+ -+ i2c_bus->speed = speed; -+ -+ return 0; -+} -+ -+unsigned int i2c_get_base(int bus_no) -+{ -+ switch (bus_no) { -+ case 0: -+ return AST_I2C_DEV0_BASE; -+ break; -+ case 1: -+ return AST_I2C_DEV1_BASE; -+ break; -+ case 2: -+ return AST_I2C_DEV2_BASE; -+ break; -+ case 3: -+ return AST_I2C_DEV3_BASE; -+ break; -+ case 4: -+ return AST_I2C_DEV4_BASE; -+ break; -+ case 5: -+ return AST_I2C_DEV5_BASE; -+ break; -+ case 6: -+ return AST_I2C_DEV6_BASE; -+ break; -+ case 7: -+ return AST_I2C_DEV7_BASE; -+ break; -+ case 8: -+ return AST_I2C_DEV8_BASE; -+ break; -+ case 9: -+ return AST_I2C_DEV9_BASE; -+ break; -+ case 10: -+ return AST_I2C_DEV10_BASE; -+ break; -+ case 11: -+ return AST_I2C_DEV11_BASE; -+ break; -+ case 12: -+ return AST_I2C_DEV12_BASE; -+ break; -+ case 13: -+ return AST_I2C_DEV13_BASE; -+ break; -+ default: -+ printf("i2c base error\n"); -+ break; -+ }; -+ return 0; -+} -+ -+void i2c_init(int speed, int slaveaddr) -+{ -+ int i = 0; -+ struct ast_i2c_bus *i2c_bus; -+ -+ // SCU I2C Reset -+ ast_scu_init_i2c(); -+ -+ /* This will override the speed selected in the fdt for that port */ -+ debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); -+ -+ for (i = 0; i < CONFIG_SYS_MAX_I2C_BUS; i++) { -+ i2c_bus = &ast_i2c[i]; -+ i2c_bus->reg_base = i2c_get_base(i); -+ -+ i2c_bus->speed = CONFIG_SYS_I2C_SPEED; -+ i2c_bus->state = 0; -+ -+ // I2C Multi-Pin -+ ast_scu_multi_func_i2c(i); -+ -+ // I2CG Reset -+ ast_i2c_write(i2c_bus, 0, I2C_FUN_CTRL_REG); -+ -+ // Enable Master Mode -+ ast_i2c_write(i2c_bus, AST_I2CD_MASTER_EN, I2C_FUN_CTRL_REG); -+ -+ // SLAVE mode enable -+#if 0 -+ if (slaveaddr) { -+ ast_i2c_write(i2c_bus, slaveaddr, I2C_DEV_ADDR_REG); -+ ast_i2c_write(i2c_bus, -+ ast_i2c_read(i2c_bus, I2C_FUN_CTRL_REG) | -+ AST_I2CD_SLAVE_EN, -+ I2C_FUN_CTRL_REG); -+ } -+#endif -+ -+ /* Set AC Timing */ -+ i2c_set_bus_speed(speed); -+ -+ // Clear Interrupt -+ ast_i2c_write(i2c_bus, 0xfffffff, I2C_INTR_STS_REG); -+ -+ /* Set interrupt generation of I2C controller */ -+ ast_i2c_write(i2c_bus, 0, I2C_INTR_CTRL_REG); -+ } -+ -+ i2c_bus_num = 0; -+ debug("end\n"); -+} -+ -+/* Probe to see if a chip is present. */ -+int i2c_probe(uchar addr) -+{ -+ uchar a_buf[1] = { 0 }; -+ -+ struct ast_i2c_bus *i2c_bus = &ast_i2c[i2c_bus_num]; -+ -+ debug("i2c_probe[bus:%d]: addr=0x%x\n", i2c_bus_num, addr); -+ -+ i2c_bus->addr = addr; -+ i2c_bus->flags = 1; -+ i2c_bus->a_len = 1; -+ i2c_bus->a_buf = (u8 *)&a_buf; -+ i2c_bus->d_len = 1; -+ i2c_bus->d_buf = (u8 *)&a_buf; -+ -+ return ast_i2c_xfer(i2c_bus); -+} -+ -+/* Read bytes */ -+int i2c_read(uchar addr, uint offset, int alen, uchar *buffer, int len) -+{ -+ uchar xoffset[4]; -+ struct ast_i2c_bus *i2c_bus = &ast_i2c[i2c_bus_num]; -+ -+ debug("i2c_read[bus:%d]: addr=0x%x, offset=0x%x, alen=0x%x len=0x%x\n", -+ i2c_bus_num, addr, offset, alen, len); -+ -+ if (alen > 4) { -+ debug("I2C read: addr len %d not supported\n", alen); -+ return 1; -+ } -+ -+ if (alen > 0) { -+ xoffset[0] = (offset >> 24) & 0xFF; -+ xoffset[1] = (offset >> 16) & 0xFF; -+ xoffset[2] = (offset >> 8) & 0xFF; -+ xoffset[3] = offset & 0xFF; -+ } -+ -+ i2c_bus->addr = addr; -+ i2c_bus->flags = 1; -+ i2c_bus->a_len = alen; -+ i2c_bus->a_buf = &xoffset[4 - alen]; -+ i2c_bus->d_len = len; -+ i2c_bus->d_buf = buffer; -+ -+ return ast_i2c_xfer(i2c_bus); -+} -+ -+/* Write bytes */ -+int i2c_write(uchar addr, uint offset, int alen, uchar *buffer, int len) -+{ -+ uchar xoffset[4]; -+ struct ast_i2c_bus *i2c_bus = &ast_i2c[i2c_bus_num]; -+ -+ debug("i2c_write[bus:%d]: addr=0x%x, offset=0x%x, alen=0x%x len=0x%x\n", -+ i2c_bus_num, addr, offset, alen, len); -+ -+ if (alen > 0) { -+ xoffset[0] = (offset >> 24) & 0xFF; -+ xoffset[1] = (offset >> 16) & 0xFF; -+ xoffset[2] = (offset >> 8) & 0xFF; -+ xoffset[3] = offset & 0xFF; -+ } -+ -+ i2c_bus->addr = addr; -+ i2c_bus->flags = 0; -+ i2c_bus->a_len = alen; -+ i2c_bus->a_buf = &xoffset[4 - alen]; -+ i2c_bus->d_len = len; -+ i2c_bus->d_buf = buffer; -+ -+ return ast_i2c_xfer(i2c_bus); -+} -+ -+#if defined(CONFIG_I2C_MULTI_BUS) -+/* -+ * Functions for multiple I2C bus handling -+ */ -+unsigned int i2c_get_bus_num(void) -+{ -+ return i2c_bus_num; -+} -+ -+int i2c_set_bus_num(unsigned int bus) -+{ -+ if (bus >= NUM_BUS) -+ return -1; -+ i2c_bus_num = bus; -+ -+ return 0; -+} -+#endif -diff --git a/drivers/i2c/ast_i2c.h b/drivers/i2c/ast_i2c.h -new file mode 100644 -index 0000000..7cff0e5 ---- /dev/null -+++ b/drivers/i2c/ast_i2c.h -@@ -0,0 +1,131 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (C) 2012-2020 ASPEED Technology Inc. -+ * Copyright 2016 IBM Corporation -+ * Copyright 2017 Google, Inc. -+ */ -+#ifndef __AST_I2C_H_ -+#define __AST_I2C_H_ -+ -+struct ast_i2c_regs { -+ u32 fcr; -+ u32 cactcr1; -+ u32 cactcr2; -+ u32 icr; -+ u32 isr; -+ u32 csr; -+ u32 sdar; -+ u32 pbcr; -+ u32 trbbr; -+#ifdef CONFIG_ASPEED_AST2500 -+ u32 dma_mbar; -+ u32 dma_tlr; -+#endif -+}; -+ -+/* Device Register Definition */ -+/* 0x00 : I2CD Function Control Register */ -+#define I2CD_BUFF_SEL_MASK (0x7 << 20) -+#define I2CD_BUFF_SEL(x) (x << 20) -+#define I2CD_M_SDA_LOCK_EN (0x1 << 16) -+#define I2CD_MULTI_MASTER_DIS (0x1 << 15) -+#define I2CD_M_SCL_DRIVE_EN (0x1 << 14) -+#define I2CD_MSB_STS (0x1 << 9) -+#define I2CD_SDA_DRIVE_1T_EN (0x1 << 8) -+#define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) -+#define I2CD_M_HIGH_SPEED_EN (0x1 << 6) -+#define I2CD_DEF_ADDR_EN (0x1 << 5) -+#define I2CD_DEF_ALERT_EN (0x1 << 4) -+#define I2CD_DEF_ARP_EN (0x1 << 3) -+#define I2CD_DEF_GCALL_EN (0x1 << 2) -+#define I2CD_SLAVE_EN (0x1 << 1) -+#define I2CD_MASTER_EN (0x1) -+ -+/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ -+/* Base register value. These bits are always set by the driver. */ -+#define I2CD_CACTC_BASE 0xfff00300 -+#define I2CD_TCKHIGH_SHIFT 16 -+#define I2CD_TCKLOW_SHIFT 12 -+#define I2CD_THDDAT_SHIFT 10 -+#define I2CD_TO_DIV_SHIFT 8 -+#define I2CD_BASE_DIV_SHIFT 0 -+ -+/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ -+#define I2CD_tTIMEOUT 1 -+#define I2CD_NO_TIMEOUT_CTRL 0 -+ -+/* 0x0c : I2CD Interrupt Control Register & -+ * 0x10 : I2CD Interrupt Status Register -+ * -+ * These share bit definitions, so use the same values for the enable & -+ * status bits. -+ */ -+#define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) -+#define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) -+#define I2CD_INTR_SMBUS_ALERT (0x1 << 12) -+#define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) -+#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) -+#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) -+#define I2CD_INTR_GCALL_ADDR (0x1 << 8) -+#define I2CD_INTR_SLAVE_MATCH (0x1 << 7) -+#define I2CD_INTR_SCL_TIMEOUT (0x1 << 6) -+#define I2CD_INTR_ABNORMAL (0x1 << 5) -+#define I2CD_INTR_NORMAL_STOP (0x1 << 4) -+#define I2CD_INTR_ARBIT_LOSS (0x1 << 3) -+#define I2CD_INTR_RX_DONE (0x1 << 2) -+#define I2CD_INTR_TX_NAK (0x1 << 1) -+#define I2CD_INTR_TX_ACK (0x1 << 0) -+ -+/* 0x14 : I2CD Command/Status Register */ -+#define I2CD_SDA_OE (0x1 << 28) -+#define I2CD_SDA_O (0x1 << 27) -+#define I2CD_SCL_OE (0x1 << 26) -+#define I2CD_SCL_O (0x1 << 25) -+#define I2CD_TX_TIMING (0x1 << 24) -+#define I2CD_TX_STATUS (0x1 << 23) -+ -+/* Tx State Machine */ -+#define I2CD_IDLE 0x0 -+#define I2CD_MACTIVE 0x8 -+#define I2CD_MSTART 0x9 -+#define I2CD_MSTARTR 0xa -+#define I2CD_MSTOP 0xb -+#define I2CD_MTXD 0xc -+#define I2CD_MRXACK 0xd -+#define I2CD_MRXD 0xe -+#define I2CD_MTXACK 0xf -+#define I2CD_SWAIT 0x1 -+#define I2CD_SRXD 0x4 -+#define I2CD_STXACK 0x5 -+#define I2CD_STXD 0x6 -+#define I2CD_SRXACK 0x7 -+#define I2CD_RECOVER 0x3 -+ -+#define I2CD_SCL_LINE_STS (0x1 << 18) -+#define I2CD_SDA_LINE_STS (0x1 << 17) -+#define I2CD_BUS_BUSY_STS (0x1 << 16) -+#define I2CD_SDA_OE_OUT_DIR (0x1 << 15) -+#define I2CD_SDA_O_OUT_DIR (0x1 << 14) -+#define I2CD_SCL_OE_OUT_DIR (0x1 << 13) -+#define I2CD_SCL_O_OUT_DIR (0x1 << 12) -+#define I2CD_BUS_RECOVER_CMD (0x1 << 11) -+#define I2CD_S_ALT_EN (0x1 << 10) -+#define I2CD_RX_DMA_ENABLE (0x1 << 9) -+#define I2CD_TX_DMA_ENABLE (0x1 << 8) -+ -+/* Command Bit */ -+#define I2CD_RX_BUFF_ENABLE (0x1 << 7) -+#define I2CD_TX_BUFF_ENABLE (0x1 << 6) -+#define I2CD_M_STOP_CMD (0x1 << 5) -+#define I2CD_M_S_RX_CMD_LAST (0x1 << 4) -+#define I2CD_M_RX_CMD (0x1 << 3) -+#define I2CD_S_TX_CMD (0x1 << 2) -+#define I2CD_M_TX_CMD (0x1 << 1) -+#define I2CD_M_START_CMD 0x1 -+ -+#define I2CD_RX_DATA_SHIFT 8 -+#define I2CD_RX_DATA_MASK (0xff << I2CD_RX_DATA_SHIFT) -+ -+#define I2C_HIGHSPEED_RATE 400000 -+ -+#endif /* __AST_I2C_H_ */ -diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h -index b7d7192..0bc7f2d 100644 ---- a/include/configs/ast-common.h -+++ b/include/configs/ast-common.h -@@ -84,6 +84,11 @@ - #define CONFIG_SYS_MAXARGS 16 - #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -+/* I2C config */ -+#define CONFIG_I2C_MULTI_BUS 1 -+#define CONFIG_SYS_MAX_I2C_BUS 8 -+#define CONFIG_SYS_I2C_SPEED 100000 -+ - /* - * Optional MTD and UBI support - */ --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch deleted file mode 100644 index ac458dd6c..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0027-CPLD-u-boot-commands-support-for-PFR.patch +++ /dev/null @@ -1,302 +0,0 @@ -From 0083904a79527cef9ca99e516ed015b56a6b95c7 Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Tue, 7 May 2019 11:26:35 +0530 -Subject: [PATCH] CPLD u-boot commands support for PFR - -Implemented the cpld command in u-boot for -communicating with PFR CPLD. - -Tested: -Simulated test on different I2C bus and slave -as we don't have hardware available yet. -ast# cpld dump -*** Dumping CPLD Registers *** -0x0000 | 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ----------------------------------------------------------- -0x0000 | 03 00 00 00 01 09 00 f5 01 09 19 cb 46 4c 45 -- -0x0001 | -- 52 4f 4e 49 43 53 cf 53 2d 31 31 30 30 41 44 -0x0002 | 55 -- 30 2d 32 30 31 ca 47 38 34 30 32 -- 2d -- -0x0003 | 30 37 c2 30 31 cc 45 58 57 44 36 34 39 30 30 38 -............................. -ast# cpld read 0x00 -CPLD read successful. Reg:0x00 Val:0x03 -ast# cpld write 0x00 0x04 -CPLD write successful. Reg:0x00 Val:0x04 -ast# cpld read 0x00 -CPLD read successful. Reg:0x00 Val:0x04 -ast# - -Signed-off-by: AppaRao Puli - -Signed-off-by: Vikram Bodireddy ---- - cmd/Makefile | 1 + - cmd/cpld.c | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 245 insertions(+) - create mode 100644 cmd/cpld.c - -diff --git a/cmd/Makefile b/cmd/Makefile -index a1731be701..c8ac0af55c 100644 ---- a/cmd/Makefile -+++ b/cmd/Makefile -@@ -66,6 +66,7 @@ obj-$(CONFIG_CMD_FUSE) += fuse.o - obj-$(CONFIG_CMD_GETTIME) += gettime.o - obj-$(CONFIG_CMD_GPIO) += gpio.o - obj-$(CONFIG_CMD_I2C) += i2c.o -+obj-$(CONFIG_CMD_I2C) += cpld.o - obj-$(CONFIG_CMD_IOTRACE) += iotrace.o - obj-$(CONFIG_CMD_HASH) += hash.o - obj-$(CONFIG_CMD_IDE) += ide.o -diff --git a/cmd/cpld.c b/cmd/cpld.c -new file mode 100644 -index 0000000000..1b225d20dc ---- /dev/null -+++ b/cmd/cpld.c -@@ -0,0 +1,244 @@ -+/* -+ * Copyright (c) 2018-2019 Intel Corporation -+ * Written by AppaRao Puli -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define PFR_CPLD_I2C_BUSNO 4 -+#define PFR_CPLD_SLAVE_ADDR 0x70 -+ -+#define CPLD_READ_TIMEOUT_ATTEMPTS 5 -+ -+/* Some CPLD registers are self cleared after read. -+ * We should skip them reading to avoid functionality impact.*/ -+/* TODO: Need to get this list from CPLD team. */ -+static uchar cpld_reg_skip_read[] = {}; -+ -+static bool skip_cpld_reg_read(u32 reg) -+{ -+ int size = ARRAY_SIZE(cpld_reg_skip_read); -+ for (int i = 0; i < size; i++) { -+ if (reg == cpld_reg_skip_read[i]) -+ return true; -+ } -+ -+ return false; -+} -+ -+static int do_cpld_write(cmd_tbl_t *cmdtp, int flag, int argc, -+ char *const argv[]) -+{ -+ int ret = 0; -+ int current_bus_no; -+ u32 reg_addr; -+ uchar value; -+ int chip = (PFR_CPLD_SLAVE_ADDR >> 1); -+ -+ if (argc != 3) -+ return CMD_RET_USAGE; -+ -+ reg_addr = simple_strtoul(argv[1], NULL, 16); -+ if (reg_addr > 0xFF) { -+ printf("Invalid register. Valid range[0x00-0xFF]."); -+ return CMD_RET_FAILURE; -+ } -+ value = simple_strtoul(argv[2], NULL, 16); -+ -+ /* Get current I2C bus number to restore later. */ -+ current_bus_no = i2c_get_bus_num(); -+ -+ /* Set I2C bus number to PFR CPLD I2C bus. */ -+ ret = i2c_set_bus_num(PFR_CPLD_I2C_BUSNO); -+ if (ret) { -+ printf("Failure changing bus number (%d)\n", ret); -+ ret = CMD_RET_FAILURE; -+ goto done; -+ } -+ -+ ret = i2c_write(chip, reg_addr, 1, &value, 1); -+ if (ret) { -+ printf("Error writing the chip: %d\n", ret); -+ ret = CMD_RET_FAILURE; -+ goto done; -+ } -+ -+ printf("CPLD write successful. Reg:0x%02x Val:0x%02x\n", reg_addr, -+ value); -+ -+done: -+ /* Restore I2C bus number */ -+ if (i2c_set_bus_num(current_bus_no)) -+ printf("Error in restoring bus number.\n"); -+ -+ return ret; -+} -+ -+static int do_cpld_read(cmd_tbl_t *cmdtp, int flag, int argc, -+ char *const argv[]) -+{ -+ int ret = 0; -+ int current_bus_no; -+ u32 reg_addr; -+ uchar value[1]; -+ int chip = (PFR_CPLD_SLAVE_ADDR >> 1); -+ -+ if (argc != 2) -+ return CMD_RET_USAGE; -+ -+ reg_addr = simple_strtoul(argv[1], NULL, 16); -+ if (reg_addr > 0xFF) { -+ printf("Invalid register. Valid range[0x00-0xFF]."); -+ return CMD_RET_FAILURE; -+ } -+ -+ /* Get current I2C bus number to restore later. */ -+ current_bus_no = i2c_get_bus_num(); -+ -+ /* Set I2C bus number to PFR CPLD I2C bus. */ -+ ret = i2c_set_bus_num(PFR_CPLD_I2C_BUSNO); -+ if (ret) { -+ printf("Failure changing bus number (%d)\n", ret); -+ ret = CMD_RET_FAILURE; -+ goto done; -+ } -+ -+ if (skip_cpld_reg_read(reg_addr)) { -+ printf("CPLD register(0x%02x) reading is not allowed.\n", -+ reg_addr); -+ ret = 0; -+ goto done; -+ } -+ -+ ret = i2c_read(chip, reg_addr, 1, value, 1); -+ if (ret) { -+ printf("Error reading the chip: %d\n", ret); -+ ret = CMD_RET_FAILURE; -+ goto done; -+ } -+ -+ printf("CPLD read successful. Reg:0x%02x Val:0x%02x\n", reg_addr, -+ value[0]); -+ -+done: -+ /* Restore I2C bus number */ -+ if (i2c_set_bus_num(current_bus_no)) -+ printf("Error in restoring bus number.\n"); -+ -+ return ret; -+} -+ -+static int do_cpld_dump(cmd_tbl_t *cmdtp, int flag, int argc, -+ char *const argv[]) -+{ -+ int ret = 0; -+ int current_bus_no; -+ u32 reg_addr = 0x00; -+ uchar value[1]; -+ int chip = (PFR_CPLD_SLAVE_ADDR >> 1); -+ -+ if (argc != 1) -+ return CMD_RET_USAGE; -+ -+ /* Get current I2C bus number to restore later. */ -+ current_bus_no = i2c_get_bus_num(); -+ -+ /* Set I2C bus number to PFR CPLD I2C bus. */ -+ ret = i2c_set_bus_num(PFR_CPLD_I2C_BUSNO); -+ if (ret) { -+ printf("Failure changing bus number (%d)\n", ret); -+ ret = CMD_RET_FAILURE; -+ goto done; -+ } -+ -+ printf("*** Dumping CPLD Registers ***\n", reg_addr, value); -+ printf("0x%04x | ", reg_addr); -+ for (int i = 0; i < 0x10; i++) -+ printf(" %02x", i); -+ printf("\n----------------------------------------------------------\n"); -+ -+ while (reg_addr <= 0xFF) { -+ if ((reg_addr % 16) == 0) -+ printf("0x%04x | ", (reg_addr / 16)); -+ -+ if (skip_cpld_reg_read(reg_addr)) { -+ printf(" --"); -+ } else { -+ int timeout = 0; -+ while (i2c_read(chip, reg_addr, 1, value, 1) != 0) { -+ if (timeout++ >= CPLD_READ_TIMEOUT_ATTEMPTS) { -+ printf("\nERROR: Reading the chip: %d\n", -+ ret); -+ ret = CMD_RET_FAILURE; -+ goto done; -+ } -+ /* Need delay for I2C devices continous read */ -+ mdelay(3 * timeout); -+ } -+ printf(" %02x", value[0]); -+ } -+ -+ reg_addr++; -+ if ((reg_addr % 16) == 0) -+ printf("\n"); -+ } -+ -+done: -+ /* Restore I2C bus number */ -+ if (i2c_set_bus_num(current_bus_no)) -+ printf("Error in restoring bus number.\n"); -+ -+ return ret; -+} -+static cmd_tbl_t cmd_cpld_sub[] = { -+ U_BOOT_CMD_MKENT(dump, 1, 1, do_cpld_dump, "", ""), -+ U_BOOT_CMD_MKENT(read, 2, 1, do_cpld_read, "", ""), -+ U_BOOT_CMD_MKENT(write, 3, 1, do_cpld_write, "", "") -+}; -+ -+/** -+ * do_cpld() - Handle the "cpld" command-line command -+ * @cmdtp: Command data struct pointer -+ * @flag: Command flag -+ * @argc: Command-line argument count -+ * @argv: Array of command-line arguments -+ * -+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative -+ * on error. -+ */ -+static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -+{ -+ cmd_tbl_t *c = NULL; -+ -+ if (argc < 2) -+ return CMD_RET_USAGE; -+ -+ /* Strip off leading 'cpld' command argument */ -+ argc--; -+ argv++; -+ -+ if (argc) -+ c = find_cmd_tbl(argv[0], cmd_cpld_sub, -+ ARRAY_SIZE(cmd_cpld_sub)); -+ -+ if (c) -+ return c->cmd(cmdtp, flag, argc, argv); -+ else -+ return CMD_RET_USAGE; -+} -+ -+#ifdef CONFIG_SYS_LONGHELP -+static char cpld_help_text[] = -+ "cpld dump - Dump all CPLD registers.\n" -+ "cpld read - Read CPLD register.\n" -+ "cpld write - Write CPLD register.\n"; -+#endif -+ -+U_BOOT_CMD(cpld, 4, 1, do_cpld, "PFR CPLD information", cpld_help_text); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch deleted file mode 100644 index 0113fc3fe..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 41c08f1fcb5fa0b07ea541fc3d8bc322ddf8701d Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Mon, 13 May 2019 23:49:02 +0530 -Subject: [PATCH] Enabling uart1&uart2 in u-boot for BIOS messages - -Added uart init function in u-boot aspeed code -to enable uart1 and uart2 for BIOS serial messages. - -Tested: -Forced BMC to stop in u-boot( using Force Firmware Update -Jumper), AC cycled system for multiple times, booted system -to uefi, checked bios serial logs working fine and accessed -keyboard in uefi without any issues. - -Signed-off-by: AppaRao Puli - ---- - board/aspeed/ast-g5/ast-g5-intel.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 812e3ef..e68ab85 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -453,6 +453,26 @@ void ast_g5_intel_late_init(void) - update_bootargs_cmd("special", NULL); - } - -+static void uart_init(void) -+{ -+ u32 val; -+ -+ /* Enable UART1 and UART2 for BIOS messages */ -+ val = ast_scu_read(AST_SCU_FUN_PIN_CTRL2); -+ -+ /* UART1 */ -+ val |= (SCU_FUN_PIN_UART1_NCTS | SCU_FUN_PIN_UART1_NDCD | -+ SCU_FUN_PIN_UART1_NDSR | SCU_FUN_PIN_UART1_NRI | -+ SCU_FUN_PIN_UART1_NDTR | SCU_FUN_PIN_UART1_NRTS | -+ SCU_FUN_PIN_UART1_TXD | SCU_FUN_PIN_UART1_RXD); -+ /* UART2 */ -+ val |= (SCU_FUN_PIN_UART2_NCTS | SCU_FUN_PIN_UART2_NDCD | -+ SCU_FUN_PIN_UART2_NDSR | SCU_FUN_PIN_UART2_NRI | -+ SCU_FUN_PIN_UART2_NDTR | SCU_FUN_PIN_UART2_NRTS | -+ SCU_FUN_PIN_UART2_TXD | SCU_FUN_PIN_UART2_RXD); -+ ast_scu_write(val, AST_SCU_FUN_PIN_CTRL2); -+} -+ - static void pwm_init(void) - { - uint32_t val; -@@ -521,6 +541,7 @@ extern void espi_init(void); - extern void kcs_init(void); - void ast_g5_intel(void) - { -+ uart_init(); - pwm_init(); - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); - espi_init(); diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch deleted file mode 100644 index 3c21a7c0a..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch +++ /dev/null @@ -1,1273 +0,0 @@ -From 0f64b0e0c0a122ce23b5ccc518f514ec296bc7f5 Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Tue, 21 May 2019 00:53:04 +0530 -Subject: [PATCH] FFUJ: FW IPMI commands and flash support in u-boot - -Firmware update and OEM ipmi commands implementation -for supporting Force Firmware Update Jumper(FFUJ) -mode. Also added support to update the fit images -in FFUJ mode. - -Firmware update commands: -1) Get BMC Execution Context(0x23) -2) Get Firmware Update Random Number(0x26) -3) Set Firmware Update Mode(0x27) -4) Exit Firmware Update Mode(0x28) -5) Set/Get Firmware Update Control(0x29) -6) Get Firmware Update status(0x2A) -7) Set Firmware Update Options(0x2B) -8) Firmware Image Write(0x2C) - -OEM Commands: -1) Get Buffer Size(0x66) - -Tested: - - Used cmdtool.efi to test the individual commands - implementation and negative cases. - - Used debug fwpiaupd.efi tool for validating Firmware - image transfer via KCS and flashing. - -Signed-off-by: AppaRao Puli ---- - arch/arm/include/asm/arch-aspeed/ast-g5-intel.h | 1 + - board/aspeed/ast-g5/Makefile | 2 + - board/aspeed/ast-g5/fw-update.c | 486 ++++++++++++++++++++++++ - board/aspeed/ast-g5/fw-update.h | 50 +++ - board/aspeed/ast-g5/ipmi-fwupd.c | 402 ++++++++++++++++++++ - board/aspeed/ast-g5/ipmi-fwupd.h | 81 ++++ - board/aspeed/ast-g5/ipmi-handler.c | 66 +++- - board/aspeed/ast-g5/ipmi-handler.h | 3 +- - common/autoboot.c | 13 + - configs/ast_g5_phy_defconfig | 1 + - 10 files changed, 1093 insertions(+), 12 deletions(-) - create mode 100644 board/aspeed/ast-g5/fw-update.c - create mode 100644 board/aspeed/ast-g5/fw-update.h - create mode 100644 board/aspeed/ast-g5/ipmi-fwupd.c - create mode 100644 board/aspeed/ast-g5/ipmi-fwupd.h - -diff --git a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -index cd9a099..a88521a 100644 ---- a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -+++ b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -@@ -14,6 +14,7 @@ - - #ifndef __ASSEMBLY__ - int intel_force_firmware_jumper_enabled(void); -+void start_fw_update_loop(void); - #endif - - #endif /* __AST_INTEL_G5_H__ */ -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index f28fcfe..0b2d936 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -6,3 +6,5 @@ obj-y += ast-g5-gpio.o - obj-y += ast-g5-timer.o - obj-y += ast-g5-kcs.o - obj-y += ipmi-handler.o -+obj-y += ipmi-fwupd.o -+obj-y += fw-update.o -diff --git a/board/aspeed/ast-g5/fw-update.c b/board/aspeed/ast-g5/fw-update.c -new file mode 100644 -index 0000000..9923993 ---- /dev/null -+++ b/board/aspeed/ast-g5/fw-update.c -@@ -0,0 +1,486 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include -+#include -+#include -+ -+#include "fw-update.h" -+ -+#define BOOTCMD_BOOTM_STR "bootm " -+#define RANDOM_NUM_TIMEOUT 30 /* in seconds */ -+#define WAIT_STATE_TIMEOUT 10000 /* 10 seconds */ -+ -+#define PROTECT_OFF 0 -+#define PROTECT_ON 1 -+ -+extern struct fwupd_global_setting g_fwupd_settings; -+extern u32 g_write_addr; -+ -+bool g_fwupd_settings_lock = false; -+unsigned long long etime; -+ -+bool fwupd_settings_trylock(void) -+{ -+ if (g_fwupd_settings_lock) -+ return false; -+ -+ g_fwupd_settings_lock = true; -+ return g_fwupd_settings_lock; -+} -+ -+void fwupd_settings_unlock(void) -+{ -+ g_fwupd_settings_lock = false; -+} -+ -+u8 get_active_boot_image(void) -+{ -+ char *bootcmd = getenv("bootcmd"); -+ char *start = strstr(bootcmd, BOOTCMD_BOOTM_STR); -+ u8 boot_image = PRIMARY_IMAGE; -+ -+ if (start) { -+ ulong boot_addr = simple_strtoul( -+ (start + strlen(BOOTCMD_BOOTM_STR)), NULL, 16); -+ if (boot_addr == SECONDARY_FITIMAGE_START_ADDR) -+ return SECONDARY_IMAGE; -+ } -+ return boot_image; -+} -+ -+static ulong get_flash_image_address(void) -+{ -+ char *bootcmd = getenv("bootcmd"); -+ char *start = strstr(bootcmd, BOOTCMD_BOOTM_STR); -+ ulong boot_addr = PRIMARY_FITIMAGE_START_ADDR; -+ -+ if (start) { -+ boot_addr = simple_strtoul((start + strlen(BOOTCMD_BOOTM_STR)), -+ NULL, 16); -+ /* We update in backup region and set the bootcmd accordingly */ -+ if (boot_addr == PRIMARY_FITIMAGE_START_ADDR) -+ boot_addr = SECONDARY_FITIMAGE_START_ADDR; -+ else -+ boot_addr = PRIMARY_FITIMAGE_START_ADDR; -+ } -+ -+ return boot_addr; -+} -+ -+static void update_processing_status(u8 status, u8 percent) -+{ -+ if (!fwupd_settings_trylock()) -+ return; -+ -+ g_fwupd_settings.processing_status = status; -+ g_fwupd_settings.percentage_completion = percent; -+ -+ fwupd_settings_unlock(); -+ return; -+} -+ -+static void reset_all_settings(void) -+{ -+ if (!fwupd_settings_trylock()) -+ return; -+ -+ memset(&g_fwupd_settings, 0, sizeof(g_fwupd_settings)); -+ g_fwupd_settings.fwupd_mode_active = false; -+ g_fwupd_settings.start_update = false; -+ -+ fwupd_settings_unlock(); -+} -+ -+unsigned int get_seed(void) -+{ -+ char seed_str[] = { "INTEL" }; -+ unsigned int seed; -+ -+ for (int i = 0; i < strlen(seed_str); i++) -+ seed += (seed_str[i] << (i * 8)); -+ -+ return seed; -+} -+ -+int generate_random_number(void) -+{ -+ srand(get_seed()); -+ -+ if (!fwupd_settings_trylock()) { -+ printf("%s(): Lock failed\n", __func__); -+ return -1; -+ } -+ for (int i = 0; i < RAND_NUMBER_SIZE; i++) -+ g_fwupd_settings.rand_num[i] = (u8)(rand() & 0xFF); -+ -+ g_fwupd_settings.random_number_valid = true; -+ -+ fwupd_settings_unlock(); -+ -+ /* Random number should be cleared after 30sec timeout */ -+ etime = endtick(RANDOM_NUM_TIMEOUT); -+ -+ return 0; -+} -+ -+static int sect_roundb(ulong *addr) -+{ -+ flash_info_t *info; -+ ulong bank, sector_end_addr; -+ char found; -+ int i; -+ -+ /* find the end addr of the sector where the *addr is */ -+ found = 0; -+ for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS && !found; ++bank) { -+ info = &flash_info[bank]; -+ for (i = 0; i < info->sector_count && !found; ++i) { -+ /* get the end address of the sector */ -+ if (i == info->sector_count - 1) { -+ sector_end_addr = -+ info->start[0] + info->size - 1; -+ } else { -+ sector_end_addr = info->start[i + 1] - 1; -+ } -+ -+ if (*addr <= sector_end_addr && -+ *addr >= info->start[i]) { -+ found = 1; -+ /* adjust *addr if necessary */ -+ if (*addr < sector_end_addr) -+ *addr = sector_end_addr; -+ } /* sector */ -+ } /* bank */ -+ } -+ if (!found) { -+ /* error, address not in flash */ -+ printf("Error: end address (0x%08lx) not in flash!\n", *addr); -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static int fill_flash_sect_ranges(ulong addr_first, ulong addr_last, -+ int *s_first, int *s_last, int *s_count) -+{ -+ flash_info_t *info; -+ ulong bank; -+ int rcode = 0; -+ -+ *s_count = 0; -+ -+ for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { -+ s_first[bank] = -1; /* first sector to erase */ -+ s_last[bank] = -1; /* last sector to erase */ -+ } -+ -+ for (bank = 0, info = &flash_info[0]; -+ (bank < CONFIG_SYS_MAX_FLASH_BANKS) && (addr_first <= addr_last); -+ ++bank, ++info) { -+ ulong b_end; -+ int sect; -+ short s_end; -+ -+ if (info->flash_id == FLASH_UNKNOWN) -+ continue; -+ -+ b_end = info->start[0] + info->size - 1; /* bank end addr */ -+ s_end = info->sector_count - 1; /* last sector */ -+ -+ for (sect = 0; sect < info->sector_count; ++sect) { -+ ulong end; /* last address in current sect */ -+ -+ end = (sect == s_end) ? b_end : -+ info->start[sect + 1] - 1; -+ -+ if (addr_first > end) -+ continue; -+ if (addr_last < info->start[sect]) -+ continue; -+ -+ if (addr_first == info->start[sect]) -+ s_first[bank] = sect; -+ if (addr_last == end) -+ s_last[bank] = sect; -+ } -+ if (s_first[bank] >= 0) { -+ if (s_last[bank] < 0) { -+ if (addr_last > b_end) { -+ s_last[bank] = s_end; -+ } else { -+ printf("Error: end address not on sector boundary\n"); -+ rcode = 1; -+ break; -+ } -+ } -+ if (s_last[bank] < s_first[bank]) { -+ printf("Error: end sector precedes start sector\n"); -+ rcode = 1; -+ break; -+ } -+ sect = s_last[bank]; -+ addr_first = (sect == s_end) ? b_end + 1 : -+ info->start[sect + 1]; -+ (*s_count) += s_last[bank] - s_first[bank] + 1; -+ } else if (addr_first >= info->start[0] && addr_first < b_end) { -+ printf("Error: start address not on sector boundary\n"); -+ rcode = 1; -+ break; -+ } else if (s_last[bank] >= 0) { -+ printf("Error: cannot span across banks when they are mapped in reverse order\n"); -+ rcode = 1; -+ break; -+ } -+ } -+ -+ return rcode; -+} -+ -+static int protect_flash_sector(int state, ulong addr_first, ulong addr_last) -+{ -+ flash_info_t *info; -+ ulong bank; -+ int s_first[CONFIG_SYS_MAX_FLASH_BANKS], -+ s_last[CONFIG_SYS_MAX_FLASH_BANKS]; -+ int protected = 0; -+ int planned; -+ int rcode, i; -+ -+ rcode = fill_flash_sect_ranges(addr_first, addr_last, s_first, s_last, -+ &planned); -+ -+ if (planned && (rcode == 0)) { -+ for (bank = 0, info = &flash_info[0]; -+ bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) { -+ if (info->flash_id == FLASH_UNKNOWN) -+ continue; -+ -+ if (s_first[bank] >= 0 && -+ s_first[bank] <= s_last[bank]) { -+ debug("%sProtecting sectors %d..%d in bank %ld\n", -+ state ? "" : "Un-", s_first[bank], -+ s_last[bank], bank + 1); -+ protected -+ += s_last[bank] - s_first[bank] + 1; -+ for (i = s_first[bank]; i <= s_last[bank]; ++i) -+ info->protect[i] = state; -+ } -+ } -+ printf("%sProtected %d sectors\n", state ? "" : "Un-", -+ protected); -+ } else if (rcode == 0) { -+ printf("Error: start and/or end address not on sector boundary\n"); -+ rcode = 1; -+ } -+ -+ return rcode; -+} -+ -+static int erase_flash_sector(ulong addr_first, ulong addr_last) -+{ -+ flash_info_t *info; -+ ulong bank; -+ int s_first[CONFIG_SYS_MAX_FLASH_BANKS]; -+ int s_last[CONFIG_SYS_MAX_FLASH_BANKS]; -+ int erased = 0; -+ int planned; -+ int rcode = 0; -+ -+ rcode = fill_flash_sect_ranges(addr_first, addr_last, s_first, s_last, -+ &planned); -+ -+ if (planned && (rcode == 0)) { -+ for (bank = 0, info = &flash_info[0]; -+ (bank < CONFIG_SYS_MAX_FLASH_BANKS) && (rcode == 0); -+ ++bank, ++info) { -+ if (s_first[bank] >= 0) { -+ erased += s_last[bank] - s_first[bank] + 1; -+ debug("Erase Flash from 0x%08lx to 0x%08lx " -+ "in Bank # %ld ", -+ info->start[s_first[bank]], -+ (s_last[bank] == info->sector_count) ? -+ info->start[0] + info->size - 1 : -+ info->start[s_last[bank] + 1] - 1, -+ bank + 1); -+ rcode = flash_erase(info, s_first[bank], -+ s_last[bank]); -+ } -+ } -+ if (rcode == 0) -+ printf("Erased %d sectors\n", erased); -+ } else if (rcode == 0) { -+ printf("Error: start and/or end address not on sector boundary\n"); -+ rcode = 1; -+ } -+ -+ return rcode; -+} -+ -+static int verify_image(void) -+{ -+ ulong src_addr = IMAGE_LOAD_RAM_ADDR; -+ void *hdr = (void *)src_addr; -+ -+ printf("\n## Checking Image at 0x%08lx ...\n", src_addr); -+ /* AT the moment, we only support FIT image flash */ -+ switch (genimg_get_format(hdr)) { -+ case IMAGE_FORMAT_FIT: -+ printf(" FIT image found\n"); -+ if (!fit_check_format(hdr)) { -+ printf("Bad FIT image format!\n"); -+ return -1; -+ } -+ -+ if (!fit_all_image_verify(hdr)) { -+ printf("Bad hash in FIT image!\n"); -+ return -1; -+ } -+ break; -+ default: -+ printf("Unknown image format!\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static int flash_image(void) -+{ -+ int rcode; -+ ulong max_size = MAX_FITIMAGE_SIZE; -+ ulong src_addr = IMAGE_LOAD_RAM_ADDR; -+ ulong addr_first = get_flash_image_address(); -+ ulong addr_last = addr_first + max_size - 1; -+ -+ if ((g_write_addr > max_size) || (g_write_addr == 0)) { -+ printf("ERROR: %s(): Invalid file uploaded. filesize(0x%08x)\n", -+ __func__, g_write_addr); -+ return -1; -+ } -+ -+ if (sect_roundb(&addr_last) > 0) { -+ printf("ERROR: %s(): sect_roundb failed\n", __func__); -+ return -1; -+ } -+ -+ if (addr_first >= addr_last) { -+ printf("ERROR: %s(): addr_first(0x%08lx) >= addr_last(0x%08lx)\n", -+ __func__, addr_first, addr_last); -+ return -1; -+ } -+ -+ /* Hack: To update the percentage update, -+ * treat logical division as below. -+ * Image verify - 10% -+ * Unprotecting flash sectors - 10% -+ * Erase flash sectors - 40% -+ * Copy to flash - 40% */ -+ -+ /* Unprotect the flash sectors */ -+ rcode = protect_flash_sector(PROTECT_OFF, addr_first, addr_last); -+ if (rcode != 0) { -+ printf("%s(): Protecting flash sector failed(%d).\n", __func__, -+ rcode); -+ return -1; -+ } -+ update_processing_status(IMG_PROGRAMMING, 20); -+ -+ /* erase flash sectors */ -+ rcode = erase_flash_sector(addr_first, addr_last); -+ if (rcode != 0) { -+ printf("%s(): Erasing flash sector failed(%d).\n", __func__, -+ rcode); -+ return -1; -+ } -+ update_processing_status(IMG_PROGRAMMING, 60); -+ -+ /* write to flash area */ -+ printf("Copy to Flash... "); -+ rcode = flash_write((char *)src_addr, addr_first, g_write_addr * 1); -+ if (rcode != 0) { -+ printf("%s(): Flash copy failed(%d).\n", __func__, rcode); -+ flash_perror(rcode); -+ return -1; -+ } -+ printf("done\n"); -+ return 0; -+} -+ -+void start_fw_update_loop(void) -+{ -+ int rc; -+ ulong boot_addr; -+ char boot_cmd[20]; -+ -+ while (1) { -+ if (g_fwupd_settings.random_number_valid) { -+ /* Random number should be cleared after 30seconds */ -+ if (get_ticks() >= etime) { -+ printf("Clearing random number\n"); -+ -+ if (!fwupd_settings_trylock()) -+ continue; -+ memcpy(g_fwupd_settings.rand_num, 0, -+ RAND_NUMBER_SIZE); -+ g_fwupd_settings.random_number_valid = false; -+ fwupd_settings_unlock(); -+ } -+ } -+ -+ if (g_fwupd_settings.start_update) { -+ update_processing_status(IMG_VALIDATING, 0); -+ -+ rc = verify_image(); -+ if (rc != 0) { -+ update_processing_status(UPDATE_ERROR, 100); -+ /* Adding delay to make consumer gets status */ -+ mdelay(WAIT_STATE_TIMEOUT); -+ -+ reset_all_settings(); -+ continue; -+ } -+ -+ update_processing_status(IMG_PROGRAMMING, 10); -+ -+ rc = flash_image(); -+ if (rc == 0) { -+ /* Update successful, change the boot command */ -+ boot_addr = get_flash_image_address(); -+ snprintf(boot_cmd, sizeof(boot_cmd), -+ "bootm %08x", boot_addr); -+ setenv("bootcmd", boot_cmd); -+ saveenv(); -+ -+ update_processing_status(UPDATE_SUCCESSFUL, -+ 100); -+ } else { -+ update_processing_status(UPDATE_ERROR, 100); -+ } -+ -+ /* Adding delay to make sure consumer gets status */ -+ mdelay(WAIT_STATE_TIMEOUT); -+ -+ reset_all_settings(); -+ -+ /* Reset BMC */ -+ do_reset(NULL, 0, 0, NULL); -+ } -+ mdelay(WAIT_STATE_TIMEOUT); -+ } -+ -+ return; -+} -+ -+#if 1 /* Debug purpose */ -+int do_fwupd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -+{ -+ if (argc != 1) -+ return 1; -+ -+ start_fw_update_loop(); -+ return 0; -+} -+U_BOOT_CMD(fwupd, 1, 0, do_fwupd, "Start Firmware update process", ""); -+#endif -diff --git a/board/aspeed/ast-g5/fw-update.h b/board/aspeed/ast-g5/fw-update.h -new file mode 100644 -index 0000000..ed033ad ---- /dev/null -+++ b/board/aspeed/ast-g5/fw-update.h -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include -+ -+/* SPI flash map */ -+#define MAX_FITIMAGE_SIZE 0x1B80000 -+#define PRIMARY_FITIMAGE_START_ADDR 0x20080000 -+#define SECONDARY_FITIMAGE_START_ADDR 0x22480000 -+#define IMAGE_LOAD_RAM_ADDR 0x83000000 -+ -+#define MAX_FILENAME_LENGTH 256 -+#define RAND_NUMBER_SIZE 8 -+ -+enum boot_image { -+ PRIMARY_IMAGE = 0x01, -+ SECONDARY_IMAGE = 0x02 -+}; -+ -+enum update_status { -+ INITIALIZING = 0, -+ IDLE, -+ IMG_DOWNLOADING, -+ IMG_VALIDATING, -+ IMG_PROGRAMMING, -+ UPDATE_SUCCESSFUL, -+ UPDATE_ERROR = 0x0F, -+ UPDATE_FORBIDDEN = 0x80, -+ AC_CYCLE_REQUIRED = 0x83 -+}; -+ -+struct fwupd_global_setting { -+ bool fwupd_mode_active; -+ bool start_update; -+ bool random_number_valid; -+ u8 ctrl_state; -+ u8 options_mask; -+ u8 options_value; -+ u8 processing_status; -+ u8 percentage_completion; -+ u8 integrity_check_status; -+ u8 filename_len; -+ u8 filename[MAX_FILENAME_LENGTH]; -+ u8 rand_num[RAND_NUMBER_SIZE]; -+}; -+ -+bool fwupd_settings_trylock(void); -+void fwupd_settings_unlock(void); -+u8 get_active_boot_image(void); -+int generate_random_number(void); -diff --git a/board/aspeed/ast-g5/ipmi-fwupd.c b/board/aspeed/ast-g5/ipmi-fwupd.c -new file mode 100644 -index 0000000..3eba056 ---- /dev/null -+++ b/board/aspeed/ast-g5/ipmi-fwupd.c -@@ -0,0 +1,402 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include "ipmi-fwupd.h" -+ -+struct fwupd_global_setting g_fwupd_settings; -+u32 g_write_addr = 0; -+ -+u16 fwupd_get_execution_ctx(u8 *req, u16 req_len, u8 *res) -+{ -+ int booting_image = 0x01; -+ struct fwupd_get_exe_ctx_res *result = -+ (struct fwupd_get_exe_ctx_res *)res; -+ -+ /* Get active image location(primary/secondary) */ -+ booting_image = get_active_boot_image(); -+ result->patition_ptr = booting_image; -+ result->exection_ctx = 0x11; /* Forced Firmware Update mode */ -+ -+ result->completion_code = IPMI_CC_OK; -+ return sizeof(struct fwupd_get_exe_ctx_res); -+} -+u16 fwupd_get_rand_number(u8 *req, u16 req_len, u8 *res) -+{ -+ struct fwupd_rand_num_res *result = (struct fwupd_rand_num_res *)res; -+ -+ if (req_len != 0) { -+ printf("%s(): Invalid request length\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Check is critical operation is going on */ -+ if (g_fwupd_settings.start_update) { -+ printf("%s(): Update in progress.\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Check is it already in fwupdate mode */ -+ if (g_fwupd_settings.fwupd_mode_active) { -+ printf("%s(): Already in firmware update mode\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ if (generate_random_number() != 0) { -+ printf("%s(): Random number generation failed\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ result->completion_code = IPMI_CC_OK; -+ memcpy(result->rand_num, g_fwupd_settings.rand_num, RAND_NUMBER_SIZE); -+ -+ return sizeof(struct fwupd_rand_num_res); -+} -+ -+u16 fwupd_enter_update_mode(u8 *req, u16 req_len, u8 *res) -+{ -+ struct fwupd_set_update_mode_res *result = -+ (struct fwupd_set_update_mode_res *)res; -+ -+ if (req_len != RAND_NUMBER_SIZE) { -+ printf("%s(): Invalid request length\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Check is critical operation is going on */ -+ if (g_fwupd_settings.start_update) { -+ printf("%s(): Update in progress.\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Check is it already in fwupdate mode */ -+ if (g_fwupd_settings.fwupd_mode_active) { -+ printf("%s(): Already in firmware update mode\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ /* This command should excute within 30 seconds -+ * after random number generation. */ -+ if (!g_fwupd_settings.random_number_valid) { -+ printf("%s(): No valid random number exist.\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_CODE; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Validate the key to enter this mode */ -+ for (int i = 0; i < RAND_NUMBER_SIZE; i++) { -+ if (req[i] != g_fwupd_settings.rand_num[i]) { -+ printf("%s(): Invalid key entered\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_CODE; -+ return sizeof(result->completion_code); -+ } -+ } -+ -+ if (!fwupd_settings_trylock()) { -+ printf("%s(): Lock failed\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ /* Reset all the settings */ -+ memset(&g_fwupd_settings, 0, sizeof(g_fwupd_settings)); -+ g_fwupd_settings.fwupd_mode_active = true; -+ fwupd_settings_unlock(); -+ -+ result->completion_code = IPMI_CC_OK; -+ -+ return sizeof(struct fwupd_set_update_mode_res); -+} -+ -+u16 fwupd_exit_update_mode(u8 *req, u16 req_len, u8 *res) -+{ -+ struct fwupd_exit_update_mode_res *result = -+ (struct fwupd_exit_update_mode_res *)res; -+ -+ if (req_len != 0) { -+ printf("%s(): Invalid request length\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!g_fwupd_settings.fwupd_mode_active) { -+ printf("%s(): Invalid command entered\n", __func__); -+ result->completion_code = IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!fwupd_settings_trylock()) { -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ g_fwupd_settings.fwupd_mode_active = false; -+ fwupd_settings_unlock(); -+ -+ result->completion_code = IPMI_CC_OK; -+ -+ return sizeof(struct fwupd_exit_update_mode_res); -+} -+u16 fwupd_set_options(u8 *req, u16 req_len, u8 *res) -+{ -+ struct fwupd_options_req *options_req = (struct fwupd_options_req *)req; -+ struct fwupd_options_res *result = (struct fwupd_options_res *)res; -+ -+ if (req_len < 2) { -+ printf("%s(): Invalid request length\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Check is critical operation is going on */ -+ if (g_fwupd_settings.start_update) { -+ printf("%s(): Update in progress.\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Setting any reserved bits will result the command being rejected */ -+ if (((options_req->options_mask & 0xF0) != 0) || -+ ((options_req->options_value & 0xF0) != 0)) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_FIELD; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!fwupd_settings_trylock()) { -+ printf("%s(): Lock failed\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ g_fwupd_settings.options_mask = options_req->options_mask; -+ g_fwupd_settings.options_value = options_req->options_value; -+ fwupd_settings_unlock(); -+ -+ result->completion_code = IPMI_CC_OK; -+ result->options_value = (g_fwupd_settings.options_mask & -+ g_fwupd_settings.options_value); -+ -+ return sizeof(struct fwupd_options_res); -+} -+ -+u16 fwupd_set_get_control(u8 *req, u16 req_len, u8 *res) -+{ -+ struct fwupd_control_req *ctrl_req = (struct fwupd_control_req *)req; -+ struct fwupd_control_res *result = (struct fwupd_control_res *)res; -+ -+ if (req_len < 1) { -+ printf("%s(): Invalid request length\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Check is critical operation is going on */ -+ if (g_fwupd_settings.start_update) { -+ printf("%s(): Update in progress.\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ if ((ctrl_req->ctrl_state == SET_FW_FILENAME) && (req_len < 3)) { -+ printf("%s(): Invalid request data\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } else if ((ctrl_req->ctrl_state != SET_FW_FILENAME) && -+ (req_len != 1)) { -+ printf("%s(): Invalid request data\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ if ((!g_fwupd_settings.fwupd_mode_active) && -+ (ctrl_req->ctrl_state != GET_CTRL_STATE)) { -+ printf("%s(): Invalid request. Control State: %d.\n", __func__, -+ ctrl_req->ctrl_state); -+ result->completion_code = IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ switch (ctrl_req->ctrl_state) { -+ case GET_CTRL_STATE: -+ break; -+ case IMG_TRANSFER_START: -+ if ((g_fwupd_settings.ctrl_state & -+ IMG_TRANSFER_CTRL_BIT_START)) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = -+ IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!fwupd_settings_trylock()) { -+ printf("%s(): Lock failed\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ g_fwupd_settings.processing_status = IMG_DOWNLOADING; -+ /* Reset control state during start */ -+ g_fwupd_settings.ctrl_state = 0x00; -+ g_fwupd_settings.ctrl_state |= IMG_TRANSFER_CTRL_BIT_START; -+ /* Set current write address to ZERO */ -+ g_write_addr = 0x00; -+ fwupd_settings_unlock(); -+ break; -+ case IMG_TRANSFER_END: -+ if (!(g_fwupd_settings.ctrl_state & -+ IMG_TRANSFER_CTRL_BIT_START)) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = -+ IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!fwupd_settings_trylock()) { -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ g_fwupd_settings.start_update = true; -+ g_fwupd_settings.ctrl_state |= IMG_TRANSFER_CTRL_BIT_END; -+ -+ g_fwupd_settings.ctrl_state &= ~(IMG_TRANSFER_CTRL_BIT_START | -+ IMG_TRANSFER_CTRL_BIT_ABORT); -+ fwupd_settings_unlock(); -+ break; -+ case IMG_TRANSFER_ABORT: -+ if (!(g_fwupd_settings.ctrl_state & -+ IMG_TRANSFER_CTRL_BIT_START)) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = -+ IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!fwupd_settings_trylock()) { -+ printf("%s(): Lock failed\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ g_fwupd_settings.processing_status = UPDATE_ERROR; -+ g_fwupd_settings.ctrl_state |= IMG_TRANSFER_CTRL_BIT_ABORT; -+ g_fwupd_settings.ctrl_state &= ~(IMG_TRANSFER_CTRL_BIT_START | -+ IMG_TRANSFER_CTRL_BIT_END); -+ fwupd_settings_unlock(); -+ break; -+ case SET_FW_FILENAME: -+ /* Not supporting now */ -+ if (ctrl_req->filename_len > sizeof(ctrl_req->filename)) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_FIELD; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!(g_fwupd_settings.ctrl_state & -+ IMG_TRANSFER_CTRL_BIT_START)) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = -+ IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!fwupd_settings_trylock()) { -+ printf("%s(): Lock failed\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ g_fwupd_settings.filename_len = ctrl_req->filename_len; -+ strncpy(g_fwupd_settings.filename, ctrl_req->filename, -+ ctrl_req->filename_len); -+ fwupd_settings_unlock(); -+ /* TODO: Used for TFTP update but not implemented yet. */ -+ /* TODO: Verify image and write to flash */ -+ break; -+ case USB_DEV_ATTACH: -+ /* Not supporting now */ -+ result->completion_code = IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ case USB_DEV_DETACH: -+ /* Not supporting now */ -+ result->completion_code = IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ break; -+ default: -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_FIELD; -+ return sizeof(result->completion_code); -+ } -+ -+ result->completion_code = IPMI_CC_OK; -+ result->curr_state = g_fwupd_settings.ctrl_state; -+ return sizeof(struct fwupd_control_res); -+} -+u16 fwupd_get_update_status(u8 *req, u16 req_len, u8 *res) -+{ -+ struct fwupd_get_update_status_res *result = -+ (struct fwupd_get_update_status_res *)res; -+ -+ if (req_len != 0) { -+ printf("%s(): Invalid request length\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ result->processing_status = g_fwupd_settings.processing_status; -+ result->percent_completion = g_fwupd_settings.percentage_completion; -+ result->check_status = 0; -+ /* We don't support error code messages cmd(0x0EH) in uboot.*/ -+ result->error_code = 0; -+ -+ result->completion_code = IPMI_CC_OK; -+ -+ return sizeof(struct fwupd_get_update_status_res); -+} -+ -+u16 fwupd_image_write(u8 *req, u16 req_len, u8 *res) -+{ -+ struct fwupd_image_write_res *result = -+ (struct fwupd_image_write_res *)res; -+ -+ if (req_len < 1) { -+ printf("%s(): Invalid request length\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Check is critical operation is going on */ -+ if (g_fwupd_settings.start_update) { -+ printf("%s(): Update in progress.\n", __func__); -+ result->completion_code = IPMI_CC_NODE_BUSY; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!g_fwupd_settings.fwupd_mode_active) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ if (!(g_fwupd_settings.ctrl_state & IMG_TRANSFER_CTRL_BIT_START)) { -+ printf("%s(): Invalid request\n", __func__); -+ result->completion_code = IPMI_CC_NOT_SUPPORTED_IN_STATE; -+ return sizeof(result->completion_code); -+ } -+ -+ if ((g_write_addr + req_len) > MAX_FITIMAGE_SIZE) { -+ printf("%s(): Request length exceeded max size\n", __func__); -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ u8 *mem_addr = (u8 *)((u32)IMAGE_LOAD_RAM_ADDR + g_write_addr); -+ -+ memcpy(mem_addr, req, req_len); -+ g_write_addr += req_len; -+ -+ result->completion_code = IPMI_CC_OK; -+ result->no_of_bytes_written = (u8)req_len; -+ -+ return sizeof(struct fwupd_image_write_res); -+} -diff --git a/board/aspeed/ast-g5/ipmi-fwupd.h b/board/aspeed/ast-g5/ipmi-fwupd.h -new file mode 100644 -index 0000000..e490f6b ---- /dev/null -+++ b/board/aspeed/ast-g5/ipmi-fwupd.h -@@ -0,0 +1,81 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include "ipmi-handler.h" -+#include "fw-update.h" -+ -+enum control_state { -+ GET_CTRL_STATE = 0, -+ IMG_TRANSFER_START, -+ IMG_TRANSFER_END, -+ IMG_TRANSFER_ABORT, -+ SET_FW_FILENAME, -+ USB_DEV_ATTACH, -+ USB_DEV_DETACH -+}; -+enum control_state_bit { -+ IMG_TRANSFER_CTRL_BIT_START = (0x01 << 0), -+ IMG_TRANSFER_CTRL_BIT_END = (0x01 << 1), -+ IMG_TRANSFER_CTRL_BIT_ABORT = (0x01 << 2), -+ USB_CTRL_BIT_ATTACH = (0x01 << 3) -+}; -+enum update_options_bit { -+ NO_DOWN_REVISION = 0, -+ DEFER_BMC_RESET = 1, -+ SHA32_INTEGRITY_CHECK = 2, -+ CRC32_INTEGRITY_CHECK = 3 -+}; -+ -+struct fwupd_get_exe_ctx_res { -+ u8 completion_code; -+ u8 exection_ctx; -+ u8 patition_ptr; -+}; -+struct fwupd_rand_num_res { -+ u8 completion_code; -+ u8 rand_num[RAND_NUMBER_SIZE]; -+}; -+struct fwupd_set_update_mode_res { -+ u8 completion_code; -+}; -+struct fwupd_exit_update_mode_res { -+ u8 completion_code; -+}; -+struct fwupd_options_req { -+ u8 options_mask; -+ u8 options_value; -+ u8 integrity_check_value[32]; -+}; -+struct fwupd_options_res { -+ u8 completion_code; -+ u8 options_value; -+}; -+struct fwupd_control_req { -+ u8 ctrl_state; -+ u8 filename_len; -+ u8 filename[MAX_FILENAME_LENGTH]; -+}; -+struct fwupd_control_res { -+ u8 completion_code; -+ u8 curr_state; -+}; -+struct fwupd_get_update_status_res { -+ u8 completion_code; -+ u8 processing_status; -+ u8 percent_completion; -+ u8 check_status; -+ u8 error_code; -+}; -+struct fwupd_image_write_res { -+ u8 completion_code; -+ u8 no_of_bytes_written; -+}; -+ -+u16 fwupd_get_execution_ctx(u8 *req, u16 req_len, u8 *res); -+u16 fwupd_get_rand_number(u8 *req, u16 req_len, u8 *res); -+u16 fwupd_enter_update_mode(u8 *req, u16 req_len, u8 *res); -+u16 fwupd_exit_update_mode(u8 *req, u16 req_len, u8 *res); -+u16 fwupd_set_options(u8 *req, u16 req_len, u8 *res); -+u16 fwupd_set_get_control(u8 *req, u16 req_len, u8 *res); -+u16 fwupd_get_update_status(u8 *req, u16 req_len, u8 *res); -+u16 fwupd_image_write(u8 *req, u16 req_len, u8 *res); -diff --git a/board/aspeed/ast-g5/ipmi-handler.c b/board/aspeed/ast-g5/ipmi-handler.c -index 9cccee9..5e78546 100644 ---- a/board/aspeed/ast-g5/ipmi-handler.c -+++ b/board/aspeed/ast-g5/ipmi-handler.c -@@ -1,18 +1,37 @@ -- - // SPDX-License-Identifier: GPL-2.0 - // Copyright (c) 2018-2019 Intel Corporation - --#include "ipmi-handler.h" -+#include "ipmi-fwupd.h" - - /* IPMI network function codes */ - #define NETFN_APP 0x06 -+#define NETFN_FIRMWARE 0x08 -+#define NETFN_INTEL_OEM 0x30 - - /* IPMI command codes */ --#define CMD_GET_DEV_ID 0x01 --#define CMD_GET_SELF_TEST_RESULTS 0x04 -+#define CMD_APP_GET_DEV_ID 0x01 -+#define CMD_APP_GET_SELF_TEST_RESULTS 0x04 -+#define CMD_FWUPD_GET_EXECUTION_CTX 0x23 -+#define CMD_FWUPD_GET_RANDOM_NUMBER 0x26 -+#define CMD_FWUPD_SET_UPDATE_MODE 0x27 -+#define CMD_FWUPD_EXIT_UPDATE_MODE 0x28 -+#define CMD_FWUPD_CONTROL_GET_SET 0x29 -+#define CMD_FWUPD_GET_UPDATE_STATUS 0x2A -+#define CMD_FWUPD_SET_OPTIONS 0x2B -+#define CMD_FWUPD_IMAGE_WRITE 0x2C -+#define CMD_INTL_OEM_GET_BUFFER_SIZE 0x66 -+ -+#define MAX_KCS_BUF_SIZE 1020 /* (0xFF * 4) */ -+#define MAX_IPMB_BUF_SIZE 1020 /* (0xFF * 4) */ - - typedef u16 (*fun_handler)(u8 *req, u16 req_len, u8 *res); - -+struct ipmi_cmd_table { -+ u8 net_fun; -+ u8 cmd; -+ fun_handler process_cmd; -+}; -+ - struct get_dev_id { - u8 completion_code; - u8 dev_id; -@@ -29,11 +48,10 @@ struct self_test_res { - u8 completion_code; - u8 res_byte[2]; - }; -- --struct ipmi_cmd_table { -- u8 net_fun; -- u8 cmd; -- fun_handler process_cmd; -+struct intc_get_buf_size_res { -+ u8 completion_code; -+ u8 kcs_size; -+ u8 ipmb_size; - }; - - static u16 get_device_id(u8 *req, u16 req_len, u8 *res) -@@ -84,10 +102,36 @@ static u16 get_self_test_result(u8 *req, u16 req_len, u8 *res) - - return sizeof(struct self_test_res); - } -+static u16 intel_get_buffer_size(u8 *req, u16 req_len, u8 *res) -+{ -+ struct intc_get_buf_size_res *result = -+ (struct intc_get_buf_size_res *)res; -+ -+ if (req_len != 0) { -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Size is multiples of four bytes */ -+ result->completion_code = IPMI_CC_OK; -+ result->kcs_size = MAX_KCS_BUF_SIZE / 4; -+ result->ipmb_size = MAX_IPMB_BUF_SIZE / 4; -+ -+ return sizeof(struct intc_get_buf_size_res); -+} - - const struct ipmi_cmd_table cmd_info[] = { -- { NETFN_APP, CMD_GET_DEV_ID, get_device_id }, -- { NETFN_APP, CMD_GET_SELF_TEST_RESULTS, get_self_test_result } -+ { NETFN_APP, CMD_APP_GET_DEV_ID, get_device_id }, -+ { NETFN_APP, CMD_APP_GET_SELF_TEST_RESULTS, get_self_test_result }, -+ { NETFN_FIRMWARE, CMD_FWUPD_GET_EXECUTION_CTX, fwupd_get_execution_ctx }, -+ { NETFN_FIRMWARE, CMD_FWUPD_GET_RANDOM_NUMBER, fwupd_get_rand_number }, -+ { NETFN_FIRMWARE, CMD_FWUPD_SET_UPDATE_MODE, fwupd_enter_update_mode }, -+ { NETFN_FIRMWARE, CMD_FWUPD_EXIT_UPDATE_MODE, fwupd_exit_update_mode }, -+ { NETFN_FIRMWARE, CMD_FWUPD_CONTROL_GET_SET, fwupd_set_get_control }, -+ { NETFN_FIRMWARE, CMD_FWUPD_GET_UPDATE_STATUS, fwupd_get_update_status }, -+ { NETFN_FIRMWARE, CMD_FWUPD_SET_OPTIONS, fwupd_set_options }, -+ { NETFN_FIRMWARE, CMD_FWUPD_IMAGE_WRITE, fwupd_image_write }, -+ { NETFN_INTEL_OEM, CMD_INTL_OEM_GET_BUFFER_SIZE, intel_get_buffer_size } - }; - - #define CMD_TABLE_SIZE ARRAY_SIZE(cmd_info) -diff --git a/board/aspeed/ast-g5/ipmi-handler.h b/board/aspeed/ast-g5/ipmi-handler.h -index 9d46d9b..8eea930 100644 ---- a/board/aspeed/ast-g5/ipmi-handler.h -+++ b/board/aspeed/ast-g5/ipmi-handler.h -@@ -1,4 +1,3 @@ -- - /* SPDX-License-Identifier: GPL-2.0 */ - /* Copyright (c) 2018-2019 Intel Corporation */ - -@@ -6,12 +5,14 @@ - - /* IPMI completion codes */ - #define IPMI_CC_OK 0x00 -+#define IPMI_CC_INVALID_CODE 0x80 - #define IPMI_CC_NODE_BUSY 0xC0 - #define IPMI_CC_INVALID_CMD 0xC1 - #define IPMI_CC_INVALID_CMD_LUN 0xC2 - #define IPMI_CC_OUT_OF_SPACE 0xC4 - #define IPMI_CC_INVALID_DATA_LENGTH 0xC7 - #define IPMI_CC_INVALID_DATA_FIELD 0xCC -+#define IPMI_CC_NOT_SUPPORTED_IN_STATE 0xD5 - #define IPMI_CC_UNSPECIFIED 0xFF - - /* BMC IPMB LUNs */ -diff --git a/common/autoboot.c b/common/autoboot.c -index d66c0fa..3647d5f 100644 ---- a/common/autoboot.c -+++ b/common/autoboot.c -@@ -349,6 +349,19 @@ void autoboot_command(const char *s) - { - debug("### main_loop: bootcmd=\"%s\"\n", s ? s : ""); - -+#ifdef AST_G5_INTEL -+ /* TODO: Make run_command_list as non-blocking(blocked by getc()) -+ * and make main u-boot loop to check both keyboard inputs as well -+ * as start_update firmware flags during FFUJ. -+ * This will make sure debug mode intact during FFUJ. -+ */ -+ if (intel_force_firmware_jumper_enabled()) { -+ printf("#### Force firmware update mode is enabled, " -+ "Serial console is disabled. ####\n"); -+ start_fw_update_loop(); -+ } -+#endif -+ - if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) { - #if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) - int prev = disable_ctrlc(1); /* disable Control C checking */ -diff --git a/configs/ast_g5_phy_defconfig b/configs/ast_g5_phy_defconfig -index 1b96ab7..5965a9b 100644 ---- a/configs/ast_g5_phy_defconfig -+++ b/configs/ast_g5_phy_defconfig -@@ -15,3 +15,4 @@ CONFIG_SYS_NS16550=y - CONFIG_USE_IRQ=y - CONFIG_CMD_I2C=y - CONFIG_SYS_I2C_AST=y -+CONFIG_LIB_RAND=y --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0030-Support-Get-Set-Security-mode-command.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0030-Support-Get-Set-Security-mode-command.patch deleted file mode 100644 index 519977e19..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0030-Support-Get-Set-Security-mode-command.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 294a5971c94099277ee5b5589c060896cf22c495 Mon Sep 17 00:00:00 2001 -From: Richard Marian Thomaiyar -Date: Thu, 20 Jun 2019 15:26:50 +0530 -Subject: [PATCH] Support Get/Set Security mode command - -Support added for get/set security mode oem command. This -command is used to read / write the RestrictionMode property -which is saved in U-Boot environment variable. U-Boot -command provides a way to downgrade RestrictionMode property -value, which is not allowed in normal mode from Host interface - -Tested: -1. Verified get security mode returns proper value read from -U-Boot environment variable. cmdtool.efi 20 C0 B3 -2. Verified set security mode updates U-Boot environment variable -and it is reflected in linux too cmdtool.efi 20 C0 B4 4 -3. Verified negative test cases with improper values and it -throws correct errors - -Signed-off-by: Richard Marian Thomaiyar - ---- - board/aspeed/ast-g5/ipmi-handler.c | 63 +++++++++++++++++++++++++++++++++++++- - 1 file changed, 62 insertions(+), 1 deletion(-) - -diff --git a/board/aspeed/ast-g5/ipmi-handler.c b/board/aspeed/ast-g5/ipmi-handler.c -index 5e78546..4e921bd 100644 ---- a/board/aspeed/ast-g5/ipmi-handler.c -+++ b/board/aspeed/ast-g5/ipmi-handler.c -@@ -20,10 +20,19 @@ - #define CMD_FWUPD_SET_OPTIONS 0x2B - #define CMD_FWUPD_IMAGE_WRITE 0x2C - #define CMD_INTL_OEM_GET_BUFFER_SIZE 0x66 -+#define CMD_INTL_OEM_GET_SEC_MODE 0xB3 -+#define CMD_INTL_OEM_SET_SEC_MODE 0xB4 - - #define MAX_KCS_BUF_SIZE 1020 /* (0xFF * 4) */ - #define MAX_IPMB_BUF_SIZE 1020 /* (0xFF * 4) */ - -+/* Restriction mode values */ -+#define RESTRICTION_MODE_MIN_VALUE 3 /*Provisioning*/ -+#define RESTRICION_MODE_MAX_VALUE 5 /*Provisioned host disabled */ -+ -+#define STR_ENV_PROVISION "provision" -+ -+ - typedef u16 (*fun_handler)(u8 *req, u16 req_len, u8 *res); - - struct ipmi_cmd_table { -@@ -53,6 +62,11 @@ struct intc_get_buf_size_res { - u8 kcs_size; - u8 ipmb_size; - }; -+struct intc_get_secuirty_mode_res { -+ u8 completion_code; -+ u8 restriction_mode; -+ u8 special_mode; -+}; - - static u16 get_device_id(u8 *req, u16 req_len, u8 *res) - { -@@ -120,6 +134,51 @@ static u16 intel_get_buffer_size(u8 *req, u16 req_len, u8 *res) - return sizeof(struct intc_get_buf_size_res); - } - -+static u16 intel_get_security_mode(u8 *req, u16 req_len, u8 *res) -+{ -+ char *cmdline = NULL; -+ struct intc_get_secuirty_mode_res *result = -+ (struct intc_get_secuirty_mode_res *)res; -+ -+ if (req_len != 0) { -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ cmdline = getenv(STR_ENV_PROVISION); -+ if (!cmdline) { -+ /* Default provision must be set only by linux */ -+ result->completion_code = IPMI_CC_UNSPECIFIED; -+ return sizeof(result->completion_code); -+ } -+ result->restriction_mode = simple_strtol(cmdline, NULL, 10); -+ /* special mode is non-volatile and not applicable in U-Boot */ -+ result->special_mode = 0; -+ result->completion_code = IPMI_CC_OK; -+ -+ return sizeof(*result); -+} -+ -+static u16 intel_set_security_mode(u8 *req, u16 req_len, u8 *res) -+{ -+ if (req_len != sizeof(*req)) { -+ *res = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(*res); -+ } -+ -+ if (*req > RESTRICION_MODE_MAX_VALUE || -+ *req < RESTRICTION_MODE_MIN_VALUE) { -+ *res = IPMI_CC_INVALID_DATA_FIELD; -+ return sizeof(*res); -+ } -+ -+ setenv_ulong(STR_ENV_PROVISION, *req); -+ saveenv(); -+ *res = IPMI_CC_OK; -+ -+ return sizeof(*res); -+} -+ - const struct ipmi_cmd_table cmd_info[] = { - { NETFN_APP, CMD_APP_GET_DEV_ID, get_device_id }, - { NETFN_APP, CMD_APP_GET_SELF_TEST_RESULTS, get_self_test_result }, -@@ -131,7 +190,9 @@ const struct ipmi_cmd_table cmd_info[] = { - { NETFN_FIRMWARE, CMD_FWUPD_GET_UPDATE_STATUS, fwupd_get_update_status }, - { NETFN_FIRMWARE, CMD_FWUPD_SET_OPTIONS, fwupd_set_options }, - { NETFN_FIRMWARE, CMD_FWUPD_IMAGE_WRITE, fwupd_image_write }, -- { NETFN_INTEL_OEM, CMD_INTL_OEM_GET_BUFFER_SIZE, intel_get_buffer_size } -+ { NETFN_INTEL_OEM, CMD_INTL_OEM_GET_BUFFER_SIZE, intel_get_buffer_size }, -+ { NETFN_INTEL_OEM, CMD_INTL_OEM_GET_SEC_MODE, intel_get_security_mode }, -+ { NETFN_INTEL_OEM, CMD_INTL_OEM_SET_SEC_MODE, intel_set_security_mode }, - }; - - #define CMD_TABLE_SIZE ARRAY_SIZE(cmd_info) diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0031-Make-it-so-TFTP-port-can-be-modified.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0031-Make-it-so-TFTP-port-can-be-modified.patch deleted file mode 100644 index b70427fe0..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0031-Make-it-so-TFTP-port-can-be-modified.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 1d680678abb76bdea7cf2128b7ce6db4a5652151 Mon Sep 17 00:00:00 2001 -From: James Feist -Date: Tue, 16 Jul 2019 16:30:02 -0700 -Subject: [PATCH 1/1] Make it so TFTP port can be modified - -This makes it so we can use non-privileged tftp ports. - -Tested: Can load fw from non-privileged port. - -Signed-off-by: James Feist ---- - include/configs/ast-g5-ncsi.h | 2 ++ - include/configs/ast-g5-phy.h | 2 ++ - 2 files changed, 4 insertions(+) - -diff --git a/include/configs/ast-g5-ncsi.h b/include/configs/ast-g5-ncsi.h -index 12d6684551..20864b2798 100644 ---- a/include/configs/ast-g5-ncsi.h -+++ b/include/configs/ast-g5-ncsi.h -@@ -28,4 +28,6 @@ - - #define CONFIG_HW_WATCHDOG - -+#define CONFIG_TFTP_PORT -+ - #endif /* __AST_G5_NCSI_CONFIG_H */ -diff --git a/include/configs/ast-g5-phy.h b/include/configs/ast-g5-phy.h -index 62ddb841e5..371f50a1db 100644 ---- a/include/configs/ast-g5-phy.h -+++ b/include/configs/ast-g5-phy.h -@@ -30,4 +30,6 @@ - /* platform.S */ - #define CONFIG_DRAM_ECC_SIZE 0x10000000 - -+#define CONFIG_TFTP_PORT -+ - #endif /* __AST_G5_PHY_CONFIG_H */ --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch deleted file mode 100644 index 392acb9ad..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch +++ /dev/null @@ -1,530 +0,0 @@ -From bd0d8af493387ab1602a0a40b4a548981c1e4d00 Mon Sep 17 00:00:00 2001 -From: AppaRao Puli -Date: Wed, 24 Jul 2019 20:11:30 +0530 -Subject: [PATCH] PFR FW update and checkpoint support in u-boot - -1) Added firmware update ipmi commands support -for PFR images. This enables PFR based firmware -updates for components BMC, BIOS and CPLD during -FFUJ mode. - -2) Added two PFR boot flow checkpoint in u-boot - - Set the booting starts checkpoint(0x01) - - Set FFUJ checkpoint(0x07) when jumper on. - -Tested: - -Tested: -1) Using debug fwpiaupd.efi utility, validated the PFR -BMC image update via KCS ( In FFUJ mode). -2) Loaded the image, dumped all cpld registers and -cross verified the check-points properly set or not. - -Signed-off-by: AppaRao Puli -Signed-off-by: Vikram Bodireddy ---- - board/aspeed/ast-g5/Makefile | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 10 +++ - board/aspeed/ast-g5/fw-update.c | 112 +++++++++++++++-------------- - board/aspeed/ast-g5/fw-update.h | 7 ++ - board/aspeed/ast-g5/ipmi-fwupd.c | 37 ++++++++++ - board/aspeed/ast-g5/ipmi-fwupd.h | 6 -- - board/aspeed/ast-g5/pfr-mgr.c | 73 +++++++++++++++++++ - board/aspeed/ast-g5/pfr-mgr.h | 73 +++++++++++++++++++ - 8 files changed, 258 insertions(+), 61 deletions(-) - create mode 100644 board/aspeed/ast-g5/pfr-mgr.c - create mode 100644 board/aspeed/ast-g5/pfr-mgr.h - -diff --git a/board/aspeed/ast-g5/Makefile b/board/aspeed/ast-g5/Makefile -index 0b2d936c23..9021d7fc08 100644 ---- a/board/aspeed/ast-g5/Makefile -+++ b/board/aspeed/ast-g5/Makefile -@@ -8,3 +8,4 @@ obj-y += ast-g5-kcs.o - obj-y += ipmi-handler.o - obj-y += ipmi-fwupd.o - obj-y += fw-update.o -+obj-y += pfr-mgr.o -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index dde5adbc70..6ef3ca9f73 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -16,6 +16,7 @@ - #include "ast-g5.h" - #include "ast-g5-gpio.h" - #include "ast-g5-timer.h" -+#include "pfr-mgr.h" - - /* Names to match the GPIOs */ - enum gpio_names { -@@ -634,6 +635,10 @@ void ast_g5_intel(void) - ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | - SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); - -+ /* To notify the CPLD about the start of bootloader -+ * and hardware initialization */ -+ set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, PFR_CPLD_CHKPOINT_START); -+ - uart_init(); - pwm_init(); - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); -@@ -649,6 +654,11 @@ void ast_g5_intel(void) - kcs_init(); - if (intel_get_platform_id() == COOPER_CITY_BOARD_ID) - set_pwm_duty_cycle(ELEVATED_PWM_DUTY_VALUE); -+ /* Notify CPLD about FFUJ jumper set and pause -+ * of booting for indefinitely time. It will be -+ * resumed once reset is done. */ -+ set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, -+ PFR_CPLD_CHKPOINT_FFUJ); - /* TODO: need to stop the booting here. */ - } - } -diff --git a/board/aspeed/ast-g5/fw-update.c b/board/aspeed/ast-g5/fw-update.c -index 99239938b5..89fe5fd4fd 100644 ---- a/board/aspeed/ast-g5/fw-update.c -+++ b/board/aspeed/ast-g5/fw-update.c -@@ -6,6 +6,7 @@ - #include - - #include "fw-update.h" -+#include "pfr-mgr.h" - - #define BOOTCMD_BOOTM_STR "bootm " - #define RANDOM_NUM_TIMEOUT 30 /* in seconds */ -@@ -15,7 +16,7 @@ - #define PROTECT_ON 1 - - extern struct fwupd_global_setting g_fwupd_settings; --extern u32 g_write_addr; -+extern struct fwupd_image_info g_img_info; - - bool g_fwupd_settings_lock = false; - unsigned long long etime; -@@ -36,16 +37,8 @@ void fwupd_settings_unlock(void) - - u8 get_active_boot_image(void) - { -- char *bootcmd = getenv("bootcmd"); -- char *start = strstr(bootcmd, BOOTCMD_BOOTM_STR); -+ /* For PFR, its always active region */ - u8 boot_image = PRIMARY_IMAGE; -- -- if (start) { -- ulong boot_addr = simple_strtoul( -- (start + strlen(BOOTCMD_BOOTM_STR)), NULL, 16); -- if (boot_addr == SECONDARY_FITIMAGE_START_ADDR) -- return SECONDARY_IMAGE; -- } - return boot_image; - } - -@@ -318,45 +311,22 @@ static int erase_flash_sector(ulong addr_first, ulong addr_last) - return rcode; - } - --static int verify_image(void) -+static int verify_image(ulong src_addr, ulong img_length) - { -- ulong src_addr = IMAGE_LOAD_RAM_ADDR; -- void *hdr = (void *)src_addr; -- -- printf("\n## Checking Image at 0x%08lx ...\n", src_addr); -- /* AT the moment, we only support FIT image flash */ -- switch (genimg_get_format(hdr)) { -- case IMAGE_FORMAT_FIT: -- printf(" FIT image found\n"); -- if (!fit_check_format(hdr)) { -- printf("Bad FIT image format!\n"); -- return -1; -- } -- -- if (!fit_all_image_verify(hdr)) { -- printf("Bad hash in FIT image!\n"); -- return -1; -- } -- break; -- default: -- printf("Unknown image format!\n"); -- return -1; -- } -- -+ /* TODO: Verify the hash alone here.*/ -+ /* Full image verification is done in CPLD. */ - return 0; - } - --static int flash_image(void) -+static int flash_image(ulong src_addr, ulong addr_first, ulong max_size, -+ ulong img_length) - { - int rcode; -- ulong max_size = MAX_FITIMAGE_SIZE; -- ulong src_addr = IMAGE_LOAD_RAM_ADDR; -- ulong addr_first = get_flash_image_address(); - ulong addr_last = addr_first + max_size - 1; - -- if ((g_write_addr > max_size) || (g_write_addr == 0)) { -+ if ((img_length > max_size) || (img_length == 0)) { - printf("ERROR: %s(): Invalid file uploaded. filesize(0x%08x)\n", -- __func__, g_write_addr); -+ __func__, img_length); - return -1; - } - -@@ -398,7 +368,7 @@ static int flash_image(void) - - /* write to flash area */ - printf("Copy to Flash... "); -- rcode = flash_write((char *)src_addr, addr_first, g_write_addr * 1); -+ rcode = flash_write((char *)src_addr, addr_first, img_length); - if (rcode != 0) { - printf("%s(): Flash copy failed(%d).\n", __func__, rcode); - flash_perror(rcode); -@@ -430,10 +400,27 @@ void start_fw_update_loop(void) - } - - if (g_fwupd_settings.start_update) { -+ printf("Starting image copy to staging area.....\n"); - update_processing_status(IMG_VALIDATING, 0); -- -- rc = verify_image(); -+ u8 update_intent = 0x00; -+ if ((g_fwupd_settings.options_mask & -+ g_fwupd_settings.options_value) & DEFER_BMC_RESET) -+ update_intent |= DEFER_UPDATES_TO_RESET; -+ -+ ulong offset = -+ get_flash_region_offset(g_img_info.img_type); -+ ulong max_size = -+ get_image_max_size(g_img_info.img_type); -+ ulong src_addr = IMAGE_LOAD_RAM_ADDR; -+ ulong flash_addr = PFR_IMAGE_STAGING_BASE_ADDR + offset; -+ -+ debug("FWUPD: offset:0x%08lx, max_size:0x%08lx, " -+ "src_addr:0x%08lx, flash_addr:0x%08lx\n", -+ offset, max_size, src_addr, flash_addr); -+ -+ rc = verify_image(src_addr, g_img_info.img_length); - if (rc != 0) { -+ printf("Image verification failed.\n"); - update_processing_status(UPDATE_ERROR, 100); - /* Adding delay to make consumer gets status */ - mdelay(WAIT_STATE_TIMEOUT); -@@ -441,31 +428,46 @@ void start_fw_update_loop(void) - reset_all_settings(); - continue; - } -+ printf("Image verification success.\n"); - - update_processing_status(IMG_PROGRAMMING, 10); - -- rc = flash_image(); -+ rc = flash_image(src_addr, flash_addr, max_size, -+ g_img_info.img_length); - if (rc == 0) { -- /* Update successful, change the boot command */ -- boot_addr = get_flash_image_address(); -- snprintf(boot_cmd, sizeof(boot_cmd), -- "bootm %08x", boot_addr); -- setenv("bootcmd", boot_cmd); -- saveenv(); -+ update_processing_status(IMG_PROGRAMMING, 90); -+ } else { -+ update_processing_status(UPDATE_ERROR, 100); -+ } - -+ printf("Image copy to staging area %s.\n", -+ ((rc == 0) ? "successful" : "failed")); -+ -+ /* Set the BMC update intent BIT to CPLD register */ -+ update_intent != get_update_intent(g_img_info.img_type); -+ -+ /* TODO: We ned a way to protect the staging area from -+ * next write data. After setting cpld intent bit, CPLD -+ * read the stagging region for associated image types -+ * and update active/recovery area. During this stage, -+ * staging area should be protected from next write. -+ * Working with CPLD team for identifying this state. */ -+ if (0 != set_cpld_reg(PFR_CPLD_BMC_UPDATE_INTENT_REG, -+ update_intent)) { -+ update_processing_status(UPDATE_ERROR, 100); -+ } else { -+ printf("CPLD: Update intent set successfully.\n"); - update_processing_status(UPDATE_SUCCESSFUL, - 100); -- } else { -- update_processing_status(UPDATE_ERROR, 100); -+ -+ if (update_intent & DEFER_UPDATES_TO_RESET) -+ printf("CPLD: Update defered to next reset.\n"); - } - - /* Adding delay to make sure consumer gets status */ - mdelay(WAIT_STATE_TIMEOUT); -- - reset_all_settings(); - -- /* Reset BMC */ -- do_reset(NULL, 0, 0, NULL); - } - mdelay(WAIT_STATE_TIMEOUT); - } -diff --git a/board/aspeed/ast-g5/fw-update.h b/board/aspeed/ast-g5/fw-update.h -index ed033adfed..45e46ba596 100644 ---- a/board/aspeed/ast-g5/fw-update.h -+++ b/board/aspeed/ast-g5/fw-update.h -@@ -28,6 +28,12 @@ enum update_status { - UPDATE_FORBIDDEN = 0x80, - AC_CYCLE_REQUIRED = 0x83 - }; -+enum update_options { -+ NO_DOWN_REVISION = BIT(0), -+ DEFER_BMC_RESET = BIT(1), -+ SHA32_INTEGRITY_CHECK = BIT(2), -+ CRC32_INTEGRITY_CHECK = BIT(3) -+}; - - struct fwupd_global_setting { - bool fwupd_mode_active; -@@ -48,3 +54,4 @@ bool fwupd_settings_trylock(void); - void fwupd_settings_unlock(void); - u8 get_active_boot_image(void); - int generate_random_number(void); -+ -diff --git a/board/aspeed/ast-g5/ipmi-fwupd.c b/board/aspeed/ast-g5/ipmi-fwupd.c -index 3eba056e7f..6afc8d66b7 100644 ---- a/board/aspeed/ast-g5/ipmi-fwupd.c -+++ b/board/aspeed/ast-g5/ipmi-fwupd.c -@@ -2,10 +2,14 @@ - // Copyright (c) 2018-2019 Intel Corporation - - #include "ipmi-fwupd.h" -+#include "pfr-mgr.h" - - struct fwupd_global_setting g_fwupd_settings; - u32 g_write_addr = 0; - -+struct fwupd_image_info g_img_info; -+static bool block0_mapped = false; -+ - u16 fwupd_get_execution_ctx(u8 *req, u16 req_len, u8 *res) - { - int booting_image = 0x01; -@@ -395,6 +399,39 @@ u16 fwupd_image_write(u8 *req, u16 req_len, u8 *res) - memcpy(mem_addr, req, req_len); - g_write_addr += req_len; - -+ /* Get the PFR block 0 data and read the uploaded image -+ * information( Image type, length, hash etc) */ -+ if ((g_write_addr >= sizeof(struct pfr_image_block0)) && -+ (!block0_mapped)) { -+ struct pfr_image_block0 *block0_data = -+ (struct pfr_image_block0 *)IMAGE_LOAD_RAM_ADDR; -+ u32 magic_num = (u32)((*block0_data->tag) | -+ LSH(*(block0_data->tag + 1), 8) | -+ LSH(*(block0_data->tag + 2), 16) | -+ LSH(*(block0_data->tag + 3), 24)); -+ /* Validate the magic number */ -+ if (magic_num != PFR_BLOCK0_MAGIC_NUM) { -+ result->completion_code = IPMI_CC_INVALID_DATA_LENGTH; -+ return sizeof(result->completion_code); -+ } -+ -+ /* Fill the image info structure for later use */ -+ g_img_info.magic_num = magic_num; -+ g_img_info.img_length = -+ (u32)((*block0_data->pc_length) | -+ LSH(*(block0_data->pc_length + 1), 8) | -+ LSH(*(block0_data->pc_length + 2), 16) | -+ LSH(*(block0_data->pc_length + 3), 24)); -+ g_img_info.img_type = -+ (u32)((*block0_data->pc_type) | -+ LSH(*(block0_data->pc_type + 1), 8) | -+ LSH(*(block0_data->pc_type + 2), 16) | -+ LSH(*(block0_data->pc_type + 3), 24)); -+ /* Add Authentication data struct length for full image */ -+ g_img_info.img_length += PFR_AUTH_DATA_STRUCT_LEN; -+ block0_mapped = true; -+ } -+ - result->completion_code = IPMI_CC_OK; - result->no_of_bytes_written = (u8)req_len; - -diff --git a/board/aspeed/ast-g5/ipmi-fwupd.h b/board/aspeed/ast-g5/ipmi-fwupd.h -index e490f6b527..7409d2e2f9 100644 ---- a/board/aspeed/ast-g5/ipmi-fwupd.h -+++ b/board/aspeed/ast-g5/ipmi-fwupd.h -@@ -19,12 +19,6 @@ enum control_state_bit { - IMG_TRANSFER_CTRL_BIT_ABORT = (0x01 << 2), - USB_CTRL_BIT_ATTACH = (0x01 << 3) - }; --enum update_options_bit { -- NO_DOWN_REVISION = 0, -- DEFER_BMC_RESET = 1, -- SHA32_INTEGRITY_CHECK = 2, -- CRC32_INTEGRITY_CHECK = 3 --}; - - struct fwupd_get_exe_ctx_res { - u8 completion_code; -diff --git a/board/aspeed/ast-g5/pfr-mgr.c b/board/aspeed/ast-g5/pfr-mgr.c -new file mode 100644 -index 0000000000..77131688e7 ---- /dev/null -+++ b/board/aspeed/ast-g5/pfr-mgr.c -@@ -0,0 +1,73 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include "pfr-mgr.h" -+ -+int set_cpld_reg(u8 reg_addr, u8 value) -+{ -+ int ret = 0; -+ int chip = (PFR_CPLD_SLAVE_ADDR >> 1); -+ -+ /* Get current I2C bus number to restore later. */ -+ int current_bus_no = i2c_get_bus_num(); -+ -+ /* Set I2C bus number to PFR CPLD I2C bus. */ -+ ret = i2c_set_bus_num(PFR_CPLD_I2C_BUSNO); -+ if (ret) { -+ printf("Failed to change I2C bus number (%d)\n", ret); -+ goto done; -+ } -+ -+ ret = i2c_write(chip, reg_addr, 1, &value, 1); -+ if (ret) { -+ printf("Error writing the chip: %d\n", ret); -+ goto done; -+ } -+ -+done: -+ /* Restore I2C bus number */ -+ if (i2c_set_bus_num(current_bus_no)) -+ printf("Failed to restore I2C bus number.\n"); -+ -+ return ret; -+} -+ -+ulong get_update_intent(u32 type) -+{ -+ ulong intent = 0; -+ if (type == PFR_CPLD_UPDATE_CAPSULE) -+ intent = CPLD_IMAGE_UPDATE; -+ else if (type == PFR_PCH_UPDATE_CAPSULE) -+ intent = PCH_SPI_FLASH_ACTIVE; -+ else if (type == PFR_BMC_UPDATE_CAPSULE) -+ intent = BMC_SPI_FLASH_ACTIVE; -+ -+ return intent; -+} -+ -+ulong get_image_max_size(u32 type) -+{ -+ ulong max_size = MAX_BMC_IMAGE_SIZE; -+ if (type == PFR_CPLD_UPDATE_CAPSULE) -+ max_size = MAX_CPLD_IMAGE_SIZE; -+ else if (type == PFR_PCH_UPDATE_CAPSULE) -+ max_size = MAX_BIOS_IMAGE_SIZE; -+ else if (type == PFR_BMC_UPDATE_CAPSULE) -+ max_size = MAX_BMC_IMAGE_SIZE; -+ -+ return max_size; -+} -+ -+ulong get_flash_region_offset(u32 type) -+{ -+ ulong offset = 0; -+ if (type == PFR_CPLD_UPDATE_CAPSULE) -+ offset = PFR_CPLD_IMAGE_REGION_OFFSET; -+ else if (type == PFR_PCH_UPDATE_CAPSULE) -+ offset = PFR_BIOS_IMAGE_REGION_OFFSET; -+ else if (type == PFR_BMC_UPDATE_CAPSULE) -+ offset = PFR_BMC_IMAGE_REGION_OFFSET; -+ -+ return offset; -+} -+ -diff --git a/board/aspeed/ast-g5/pfr-mgr.h b/board/aspeed/ast-g5/pfr-mgr.h -new file mode 100644 -index 0000000000..5c5b98bbe0 ---- /dev/null -+++ b/board/aspeed/ast-g5/pfr-mgr.h -@@ -0,0 +1,73 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright (c) 2018-2019 Intel Corporation -+ -+#include -+ -+/* CPLD I2C device defines */ -+#define PFR_CPLD_I2C_BUSNO 4 -+#define PFR_CPLD_SLAVE_ADDR 0x70 -+ -+/* CPLD registers */ -+#define PFR_CPLD_BOOT_CHECKPOINT_REG 0x0F -+#define PFR_CPLD_BMC_UPDATE_INTENT_REG 0x13 -+ -+/* PFR checkpoints */ -+#define PFR_CPLD_CHKPOINT_START 0x01 -+#define PFR_CPLD_CHKPOINT_FFUJ 0x07 -+#define PFR_CPLD_CHKPOINT_FINISHED 0x09 -+ -+#define PFR_BLOCK0_MAGIC_NUM 0xB6EAFD19 -+#define PFR_AUTH_DATA_STRUCT_LEN 1024 /* Block0 & Block1 */ -+ -+/* SPI Flash MAP */ -+#define PFR_IMAGE_STAGING_BASE_ADDR 0x24A00000 /* 54MB */ -+#define MAX_BMC_IMAGE_SIZE 0x2000000 /* 32MB */ -+#define MAX_BIOS_IMAGE_SIZE 0x1000000 /* 16MB */ -+#define MAX_CPLD_IMAGE_SIZE 0x400000 /* 4MB */ -+#define PFR_BMC_IMAGE_REGION_OFFSET 0 -+#define PFR_BIOS_IMAGE_REGION_OFFSET \ -+ (PFR_BMC_IMAGE_REGION_OFFSET + MAX_BMC_IMAGE_SIZE) -+#define PFR_CPLD_IMAGE_REGION_OFFSET \ -+ (PFR_BIOS_IMAGE_REGION_OFFSET + MAX_BIOS_IMAGE_SIZE) -+ -+#define LSH(data, num) ((data) << (num)) -+ -+/* Bit mapping for CPLD 'BMC update intent' */ -+enum cpld_update_intent { -+ PCH_SPI_FLASH_ACTIVE = BIT(0), -+ PCH_SPI_FLASH_RECOVERY = BIT(1), -+ CPLD_IMAGE_UPDATE = BIT(2), -+ BMC_SPI_FLASH_ACTIVE = BIT(3), -+ BMC_SPI_FLASH_RECOVERY = BIT(4), -+ DEFER_UPDATES_TO_RESET = BIT(7) -+}; -+ -+enum pfr_block0_pc_type { -+ PFR_CPLD_UPDATE_CAPSULE = 0x00, -+ PFR_PCH_PFM = 0x01, -+ PFR_PCH_UPDATE_CAPSULE = 0x02, -+ PFR_BMC_PFM = 0x03, -+ PFR_BMC_UPDATE_CAPSULE = 0x04 -+}; -+ -+/* PFR image block 0 - As defined in HAS */ -+struct pfr_image_block0 { -+ u8 tag[4]; -+ u8 pc_length[4]; -+ u8 pc_type[4]; -+ u8 reserved_1[4]; -+ u8 hash_256[32]; -+ u8 hash_384[48]; -+ u8 reserved_2[32]; -+}; -+ -+struct fwupd_image_info { -+ u32 magic_num; -+ u32 img_length; -+ u32 img_type; -+}; -+ -+int set_cpld_reg(u8 reg_addr, u8 value); -+ulong get_update_intent(u32 type); -+ulong get_flash_region_offset(u32 type); -+ulong get_image_max_size(u32 type); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0033-Reboot-into-UBOOT-on-Watchdog-Failures.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0033-Reboot-into-UBOOT-on-Watchdog-Failures.patch deleted file mode 100644 index e673da7ee..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0033-Reboot-into-UBOOT-on-Watchdog-Failures.patch +++ /dev/null @@ -1,110 +0,0 @@ -From c82bf9de515cbbdb4ea1a350be83fb89f4a83631 Mon Sep 17 00:00:00 2001 -From: James Feist -Date: Wed, 31 Jul 2019 16:01:49 -0700 -Subject: [PATCH 1/1] Reboot into UBOOT on Watchdog Failures - -We use watchdog1 to reboot when there is a watchdog -error. Reboot into u-boot as we are using that as -safe mode. - -Tested: watchdog -T 0 -F /dev/watchdog1 reboots into -uboot after 3 times - -Signed-off-by: James Feist ---- - .../include/asm/arch-aspeed/ast-g5-intel.h | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 31 +++++++++++++++++++ - common/autoboot.c | 2 ++ - 3 files changed, 34 insertions(+) - -diff --git a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -index a88521a1b3..64f4ed17bf 100644 ---- a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -+++ b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -@@ -14,6 +14,7 @@ - - #ifndef __ASSEMBLY__ - int intel_force_firmware_jumper_enabled(void); -+int intel_failed_boot(void); - void start_fw_update_loop(void); - #endif - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index e68ab8546a..c003d9a7bc 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -111,6 +111,24 @@ static const GPIOValue gpio_table[] = { - #define HOST_SERIAL_A_HIGH_SPEED (1 << 0) - #define HOST_SERIAL_B_HIGH_SPEED (1 << 1) - -+#define WATCHDOG_RESET_BIT 0x8 -+#define BOOT_FAILURE_LIMIT 0x3 -+ -+static int get_boot_failures(void) -+{ -+ return getenv_ulong("bootfailures", 10, 0); -+} -+ -+static void set_boot_failures(u32 count) -+{ -+ if (count > BOOT_FAILURE_LIMIT) -+ return; -+ -+ setenv_ulong("bootfailures", count); -+ saveenv(); -+} -+ -+ - static void sgpio_init(void) - { - uint32_t value; -@@ -270,6 +288,11 @@ int intel_force_firmware_jumper_enabled(void) - return gpio_get_value(GPIO_FF_UPD_JUMPER); - } - -+int intel_failed_boot(void) -+{ -+ return get_boot_failures() >= BOOT_FAILURE_LIMIT; -+} -+ - void arch_preboot_os(void) - { - // last second before booting... set the LEDs -@@ -402,6 +425,7 @@ void ast_g5_intel_late_init(void) - { - char value[32]; - u32 reset_reason = 0; -+ u32 boot_failures = 0; - - /* By default host serail A and B use normal speed */ - uint32_t host_serial_cfg = 0; -@@ -446,6 +470,13 @@ void ast_g5_intel_late_init(void) - - update_bootargs_cmd("resetreason", value); - -+ boot_failures = get_boot_failures(); -+ -+ if (reset_reason & WATCHDOG_RESET_BIT) -+ set_boot_failures(boot_failures + 1); -+ else -+ set_boot_failures(0); -+ - /* Update the special mode in bootargs */ - if (is_mfg_mode_phy_req()) - update_bootargs_cmd("special", "mfg"); -diff --git a/common/autoboot.c b/common/autoboot.c -index 45a600e663..03fd164501 100644 ---- a/common/autoboot.c -+++ b/common/autoboot.c -@@ -263,6 +263,8 @@ static int abortboot(int bootdelay) - # ifdef AST_G5_INTEL - if (intel_force_firmware_jumper_enabled()) - return 1; -+ if (intel_failed_boot()) -+ return 1; - # endif - - if (bootdelay >= 0) --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0034-Disable-uart-debug-interface.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0034-Disable-uart-debug-interface.patch deleted file mode 100644 index 941dc7d0d..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0034-Disable-uart-debug-interface.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 961561c437c8a3f3de1753c502a20c334966354e Mon Sep 17 00:00:00 2001 -From: Yong Li -Date: Tue, 20 Aug 2019 16:10:03 +0800 -Subject: [PATCH 1/2] Disable uart debug interface - -AST2500 SOC integrates a UART debug interface which can -input commands to AST2500 by using simple terminal -program without the assistance of CPU. - -For security requirements, we need to disable this feature, -set SCU2C[]10 = 1 to disable it. - -Tested: -Flash the u-boot.bin and dump SCU2C as below: -md 0x1e6e202c -1e6e202c: 00200400 - -Signed-off-by: Yong Li -Signed-off-by: Vikram Bodireddy ---- - arch/arm/include/asm/arch-aspeed/regs-scu.h | 1 + - board/aspeed/ast-g5/ast-g5-intel.c | 4 ++++ - 2 files changed, 5 insertions(+) - -diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h -index 8a596ceafc..8333ba1c59 100644 ---- a/arch/arm/include/asm/arch-aspeed/regs-scu.h -+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h -@@ -467,6 +467,7 @@ - #define SCU_MISC_VUART_TO_CTRL (0x1 << 13) - #define SCU_MISC_DIV13_EN (0x1 << 12) - #define SCU_MISC_Y_CLK_INVERT (0x1 << 11) -+#define SCU_MISC_UART_DEBUG_DIS (0x1 << 10) - #define SCU_MISC_OUT_DELAY (0x1 << 9) - #define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8) - #define SCU_MISC_2D_CRT_EN (0x1 << 7) -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 324387a4bc..c58fd3591b 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -578,6 +578,10 @@ extern void espi_init(void); - extern void kcs_init(void); - void ast_g5_intel(void) - { -+ /* Disable uart port debug function */ -+ ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | -+ SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); -+ - uart_init(); - pwm_init(); - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch deleted file mode 100644 index 85cf0cc5e..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0035-PFR-platform-EXTRST-reset-mask-selection.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 3886bca377525ca9a70a6e04403606e456c535ad Mon Sep 17 00:00:00 2001 -From: Vikram Bodireddy -Date: Thu, 5 Sep 2019 15:03:21 +0530 -Subject: [PATCH] PFR platform - EXTRST# reset mask selection - -This is a fix taken from Purely PFR. -This commit will enable specific reset mask for EXTRST# signal. -On PFR platforms, EXTRST# signal is used by PFR CPLD to put BMC -in reset during firmware authentications, recovery and firmware -update flow, during which certain modules of BMC should be chosen -to be reset so that Host functionality would be intact. - -Signed-off-by: Vikram Bodireddy ---- - .../include/asm/arch-aspeed/ast-g5-intel.h | 31 +++++++++++++++++++ - arch/arm/include/asm/arch-aspeed/regs-scu.h | 29 +++++++++++++++++ - board/aspeed/ast-g5/ast-g5-intel.c | 9 ++++++ - 3 files changed, 69 insertions(+) - -diff --git a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -index 64f4ed17bf..b9386b2cf6 100644 ---- a/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -+++ b/arch/arm/include/asm/arch-aspeed/ast-g5-intel.h -@@ -12,6 +12,37 @@ - - #define AST_G5_INTEL 1 - -+/* EXTRST# mask for PFR platform -+ * EXTRST# is used by PFR CPLD to keep BMC in -+ * reset during firmware authentication, updates and recovery -+ * this mask selects the modules to be reset along with BMC so that -+ * Host functions are intact. -+ * (this is fix from Purley PFR ) -+ */ -+#define AST_WDT_RESET_MASK ( \ -+ WDT_RESET_MASK_SPI | \ -+ WDT_RESET_MASK_XDMA | \ -+ WDT_RESET_MASK_MCTP | \ -+ WDT_RESET_MASK_ADC | \ -+ WDT_RESET_MASK_JTAG | \ -+ WDT_RESET_MASK_PECI | \ -+ WDT_RESET_MASK_CRT | \ -+ WDT_RESET_MASK_MIC | \ -+ WDT_RESET_MASK_SDIO | \ -+ WDT_RESET_MASK_HAC | \ -+ WDT_RESET_MASK_VIDEO | \ -+ WDT_RESET_MASK_HID11 | \ -+ WDT_RESET_MASK_USB11 | \ -+ WDT_RESET_MASK_USB20 | \ -+ WDT_RESET_MASK_GRAPHICS | \ -+ WDT_RESET_MASK_MAC2 | \ -+ WDT_RESET_MASK_MAC1 | \ -+ WDT_RESET_MASK_I2C | \ -+ WDT_RESET_MASK_AHB | \ -+ WDT_RESET_MASK_COPROC | \ -+ WDT_RESET_MASK_ARM | \ -+ 0) -+ - #ifndef __ASSEMBLY__ - int intel_force_firmware_jumper_enabled(void); - int intel_failed_boot(void); -diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h -index 1bdb1d8574..0a4fb6f773 100644 ---- a/arch/arm/include/asm/arch-aspeed/regs-scu.h -+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h -@@ -144,6 +144,35 @@ - #define SCU_RESET_AHB (0x1 << 1) - #define SCU_RESET_SRAM_CTRL (0x1 << 0) - -+/* AST_WDT/EXTRST - 0x9C selection masks */ -+#define WDT_RESET_MASK_MISC (1 << 25) /* Misc. SOC controller (WDT, RTC, Timer, UART, SRAM.) */ -+#define WDT_RESET_MASK_SPI (1 << 24) /* SPI controller */ -+#define WDT_RESET_MASK_XDMA (1 << 23) /* X-DMA controller */ -+#define WDT_RESET_MASK_MCTP (1 << 22) /* MCTP controller */ -+#define WDT_RESET_MASK_GPIO (1 << 21) /* GPIO controller */ -+#define WDT_RESET_MASK_ADC (1 << 20) /* ADC controller */ -+#define WDT_RESET_MASK_JTAG (1 << 19) /* JTAG master controller */ -+#define WDT_RESET_MASK_PECI (1 << 18) /* PECI controller */ -+#define WDT_RESET_MASK_PWM (1 << 17) /* PWM controller */ -+#define WDT_RESET_MASK_CRT (1 << 16) /* CRT mode 2D engine */ -+#define WDT_RESET_MASK_MIC (1 << 15) /* MIC controller */ -+#define WDT_RESET_MASK_SDIO (1 << 14) /* SD/SDIO controller */ -+#define WDT_RESET_MASK_LPC (1 << 13) /* LPC controller */ -+#define WDT_RESET_MASK_HAC (1 << 12) /* HAC engine */ -+#define WDT_RESET_MASK_VIDEO (1 << 11) /* Video engine */ -+#define WDT_RESET_MASK_HID11 (1 << 10) /* USB1.1 HID/USB2.0 Host EHCI2 controller */ -+#define WDT_RESET_MASK_USB11 (1 << 9) /* USB1.1 Host controller */ -+#define WDT_RESET_MASK_USB20 (1 << 8) /* USB2.0 Host/Hub controller */ -+#define WDT_RESET_MASK_GRAPHICS (1 << 7) /* Graphics CRT controller */ -+#define WDT_RESET_MASK_MAC2 (1 << 6) /* MAC#2 controller */ -+#define WDT_RESET_MASK_MAC1 (1 << 5) /* MAC#1 controller */ -+#define WDT_RESET_MASK_I2C (1 << 4) /* I2C controller */ -+#define WDT_RESET_MASK_AHB (1 << 3) /* AHB bridges */ -+#define WDT_RESET_MASK_SDRAM (1 << 2) /* SDRAM controller */ -+#define WDT_RESET_MASK_COPROC (1 << 1) /* Coprocessor */ -+#define WDT_RESET_MASK_ARM (1 << 0) /* ARM */ -+#define WDT_RESET_MASK_ALL 0x03ffffff /* all the bits above: 0-25*/ -+ - /* AST_SCU_RESET2 0xD4 - Reset Control register set 2 */ - #define SCU_RESET_CRT3 (0x1 << 8) - #define SCU_RESET_CRT2 (0x1 << 7) -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index f8dbae8163..e697bd17e5 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -684,6 +684,15 @@ void ast_g5_intel(void) - { - int platform_id; - -+ /* EXTRST# mask for PFR platform -+ * EXTRST# is used by PFR CPLD to keep BMC in -+ * reset during firmware authentication, updates and recovery -+ * this mask selects the modules to be reset along with BMC so that -+ * Host functions are intact. -+ * (this is fix from Purley PFR ) -+ */ -+ ast_scu_write(AST_WDT_RESET_MASK, AST_SCU_WDT_RESET); -+ - /* Disable uart port debug function */ - ast_scu_write(ast_scu_read(AST_SCU_MISC1_CTRL) | - SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0036-Re-Enable-KCS.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0036-Re-Enable-KCS.patch deleted file mode 100644 index 976277f9e..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0036-Re-Enable-KCS.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 6bd4135cd2b8e3a95f5c29e7edaa678e0ca6eded Mon Sep 17 00:00:00 2001 -From: James Feist -Date: Thu, 19 Sep 2019 10:15:19 -0700 -Subject: [PATCH 1/1] Re-Enable KCS - -Phosphor-isolation isolates too much and seems to -make KCS not work. This removes the lines from that -patch that seem to be of question. - -Tested: AC/Cycled, cmdtool.efi 20 18 1 works - -Signed-off-by: James Feist ---- - board/aspeed/ast-g5/ast-g5.c | 5 ----- - 1 file changed, 5 deletions(-) - -diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c -index ead2e1bb63..00bd92ae5f 100644 ---- a/board/aspeed/ast-g5/ast-g5.c -+++ b/board/aspeed/ast-g5/ast-g5.c -@@ -41,11 +41,6 @@ int board_init(void) - bool sdmc_unlocked; - u32 val; - -- /* iLPC2AHB */ -- val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1); -- val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO; -- writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1); -- - val = readl(AST_LPC_BASE + AST_LPC_HICRB); - val |= LPC_HICRB_ILPC2AHB; - writel(val, AST_LPC_BASE + AST_LPC_HICRB); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch deleted file mode 100644 index 9c176e998..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 4b96a19bdde82d7fed24cb70e0bcaef16d8711c3 Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo -Date: Fri, 4 Oct 2019 15:54:43 -0700 -Subject: [PATCH] aspeed/ast-scu.c: fix MAC1LINK and MAC2LINK pin pads setting - -Intel platforms don't use these pins as PHY link monitoring inputs -so this commit disables them in SCU pin control register so that -the pins can be used as GPIOs. - -Signed-off-by: Jae Hyun Yoo ---- - arch/arm/mach-aspeed/ast-scu.c | 37 +++++++++---------------------------- - 1 file changed, 9 insertions(+), 28 deletions(-) - -diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c -index 537cd4b3e1c7..28c48c115406 100644 ---- a/arch/arm/mach-aspeed/ast-scu.c -+++ b/arch/arm/mach-aspeed/ast-scu.c -@@ -419,49 +419,30 @@ void ast_scu_multi_func_eth(u8 num) - { - switch (num) { - case 0: -- if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC0_RGMII) { -+ if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC0_RGMII) - printf("MAC0 : RGMII\n"); -- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | -- SCU_FUN_PIN_MAC0_PHY_LINK, -- AST_SCU_FUN_PIN_CTRL1); -- } else { -+ else - printf("MAC0 : RMII/NCSI\n"); -- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & -- ~SCU_FUN_PIN_MAC0_PHY_LINK, -- AST_SCU_FUN_PIN_CTRL1); -- } -- --#ifdef AST_SOC_G5 -- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | -- SCU_FUN_PIN_MAC0_PHY_LINK, AST_SCU_FUN_PIN_CTRL1); - --#endif -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & -+ ~SCU_FUN_PIN_MAC0_PHY_LINK, -+ AST_SCU_FUN_PIN_CTRL1); - ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | - SCU_FUN_PIN_MAC0_MDIO | SCU_FUN_PIN_MAC0_MDC, - AST_SCU_FUN_PIN_CTRL3); -- - break; - case 1: -- if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC1_RGMII) { -+ if (ast_scu_read(AST_SCU_HW_STRAP1) & SCU_HW_STRAP_MAC1_RGMII) - printf("MAC1 : RGMII\n"); -- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | -- SCU_FUN_PIN_MAC1_PHY_LINK, -- AST_SCU_FUN_PIN_CTRL1); -- } else { -+ else - printf("MAC1 : RMII/NCSI\n"); -- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & -- ~SCU_FUN_PIN_MAC1_PHY_LINK, -- AST_SCU_FUN_PIN_CTRL1); -- } - -- ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | -- SCU_FUN_PIN_MAC1_PHY_LINK, -+ ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & -+ ~SCU_FUN_PIN_MAC1_PHY_LINK, - AST_SCU_FUN_PIN_CTRL1); -- - ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | - SCU_FUC_PIN_MAC1_MDIO, - AST_SCU_FUN_PIN_CTRL5); -- - break; - } - } --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0038-Increase-default-fan-speed-for-cooper-city.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0038-Increase-default-fan-speed-for-cooper-city.patch deleted file mode 100644 index 53cdd763e..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0038-Increase-default-fan-speed-for-cooper-city.patch +++ /dev/null @@ -1,131 +0,0 @@ -From e465945672408b632d5e3c2cf7f08ade1268419e Mon Sep 17 00:00:00 2001 -From: James Feist -Date: Thu, 24 Oct 2019 14:39:22 -0700 -Subject: [PATCH 1/1] Increase default fan speed for cooper city - -This increases the uboot fan speed for cooper city -as it has high core count CPUS. - -Tested: In uboot fans appeared to run faster - -Signed-off-by: James Feist ---- - board/aspeed/ast-g5/ast-g5-gpio.h | 6 ++++ - board/aspeed/ast-g5/ast-g5-intel.c | 46 ++++++++++++++++++++++++++++++ - 2 files changed, 52 insertions(+) - -diff --git a/board/aspeed/ast-g5/ast-g5-gpio.h b/board/aspeed/ast-g5/ast-g5-gpio.h -index ed2499f5cc..9088cdd3e3 100644 ---- a/board/aspeed/ast-g5/ast-g5-gpio.h -+++ b/board/aspeed/ast-g5/ast-g5-gpio.h -@@ -70,9 +70,15 @@ - #define ID_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_6) - #define GRN_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_4) - #define AMB_LED_PORT_PIN PORT_PIN(GPIO_PORT_S, GPIO_PIN_5) -+#define PLATFORM_ID0_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_0) -+#define PLATFORM_ID1_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_1) -+#define PLATFORM_ID2_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_2) -+#define PLATFORM_ID3_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_3) -+#define PLATFORM_ID4_PORT_PIN PORT_PIN(GPIO_PORT_B, GPIO_PIN_4) - #define FORCE_BMC_UPDATE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_0) - #define TPM_EN_PULSE_PORT_PIN PORT_PIN(GPIO_PORT_D, GPIO_PIN_6) - #define FP_PWR_BTN_PORT_PIN PORT_PIN(GPIO_PORT_E, GPIO_PIN_2) -+#define PLATFORM_ID5_PORT_PIN PORT_PIN(GPIO_PORT_G, GPIO_PIN_5) - - // GPIO Configuration Register bits - #define GPCFG_EVENT_TO_SMI (1 << 7) // 1 == enabled -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index c58fd3591b..9d5db68b7e 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -25,6 +25,12 @@ enum gpio_names { - GPIO_FF_UPD_JUMPER, - GPIO_ENABLE_TPM_PULSE, - GPIO_FP_PWR_BTN, -+ GPIO_PLATFORM_ID_0, -+ GPIO_PLATFORM_ID_1, -+ GPIO_PLATFORM_ID_2, -+ GPIO_PLATFORM_ID_3, -+ GPIO_PLATFORM_ID_4, -+ GPIO_PLATFORM_ID_5, - }; - - #define GPIO_CFG_DEFAULT (GPCFG_ACTIVE_HIGH | GPCFG_LEVEL_TRIG) -@@ -60,6 +66,21 @@ static const GPIOValue gpio_table[] = { - [GPIO_FP_PWR_BTN] = {FP_PWR_BTN_PORT_PIN, GPIO_CFG_DEFAULT, 0, - GPIO_DEBOUNCE_8MS}, - -+ /* Platform ID Pins */ -+ [GPIO_PLATFORM_ID_0] = {PLATFORM_ID0_PORT_PIN, GPIO_CFG_DEFAULT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ [GPIO_PLATFORM_ID_1] = {PLATFORM_ID1_PORT_PIN, GPIO_CFG_DEFAULT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ [GPIO_PLATFORM_ID_2] = {PLATFORM_ID2_PORT_PIN, GPIO_CFG_DEFAULT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ [GPIO_PLATFORM_ID_3] = {PLATFORM_ID3_PORT_PIN, GPIO_CFG_DEFAULT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ [GPIO_PLATFORM_ID_4] = {PLATFORM_ID4_PORT_PIN, GPIO_CFG_DEFAULT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ [GPIO_PLATFORM_ID_5] = {PLATFORM_ID5_PORT_PIN, GPIO_CFG_DEFAULT, 0, -+ GPIO_DEBOUNCE_8MS}, -+ -+ - }; - - #define LPC_SNOOP_ADDR 0x80 -@@ -114,6 +135,8 @@ static const GPIOValue gpio_table[] = { - #define WATCHDOG_RESET_BIT 0x8 - #define BOOT_FAILURE_LIMIT 0x3 - -+#define COOPER_CITY_BOARD_ID 40 -+ - static int get_boot_failures(void) - { - return getenv_ulong("bootfailures", 10, 0); -@@ -295,6 +318,26 @@ int intel_failed_boot(void) - return get_boot_failures() >= BOOT_FAILURE_LIMIT; - } - -+int intel_get_platform_id(void) -+{ -+ int id = 0; -+ int temp = 0; -+ int gpios[] = {GPIO_PLATFORM_ID_0, -+ GPIO_PLATFORM_ID_1, -+ GPIO_PLATFORM_ID_2, -+ GPIO_PLATFORM_ID_3, -+ GPIO_PLATFORM_ID_4, -+ GPIO_PLATFORM_ID_5}; -+ int ii; -+ for (ii = 0; ii < ARRAY_SIZE(gpios); ii++){ -+ temp = gpio_get_value(gpios[ii]); -+ if(temp < 0) -+ return temp; -+ id |= temp << ii; -+ } -+ return id; -+} -+ - void arch_preboot_os(void) - { - // last second before booting... set the LEDs -@@ -322,6 +365,7 @@ void arch_preboot_os(void) - #define PWM_CLK_ENABLE BIT(0) - #define PWM_DUTY(PCT) (((PCT) * 128) / 100) - #define DEFAULT_PWM_DUTY_VALUE PWM_DUTY(57) -+#define ELEVATED_PWM_DUTY_VALUE PWM_DUTY(80) - - - static inline uint32_t ast_scu_read(uint32_t reg) -@@ -595,6 +639,8 @@ void ast_g5_intel(void) - id_led_control(GPIO_GREEN_LED, EIDLED_Off); - id_led_control(GPIO_AMBER_LED, EIDLED_On); - kcs_init(); -+ if (intel_get_platform_id() == COOPER_CITY_BOARD_ID) -+ set_pwm_duty_cycle(ELEVATED_PWM_DUTY_VALUE); - /* TODO: need to stop the booting here. */ - } - } --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch deleted file mode 100644 index b36627d17..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 933d80ac82dbe1f74c653b0ac505fde406e2553c Mon Sep 17 00:00:00 2001 -From: Vernon Mauery -Date: Mon, 27 Jan 2020 15:13:10 -0800 -Subject: [PATCH] Initialize the BMC/host mailbox at reset time - -When the BMC comes out of reset, the mailbox registers need to be set so -the communications with the host can start properly. - -Tested: boot the BMC and take note that the mailbox registers are no - longer random garbage. - -Signed-off-by: Vernon Mauery ---- - board/aspeed/ast-g5/ast-g5-intel.c | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index ce87a46cd1..1086742045 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -575,6 +575,33 @@ static void pwm_init(void) - writel(val, PWM_BASE_ADDR + PWM_CONTROL); - } - -+#define AST_MBX_COUNT 16 -+#define MB_HINIT_BP_REG1 (0) -+#define MB_HINIT_BP_REG2 (1) // reserved for future bit definition. -+#define MB_FW_MJ_VER_REG (2) -+#define MB_FW_MN_VER_REG (3) -+#define MB_HINIT_ERR_REG (4) -+#define MB_BOOTL_BP_REG1 (5) -+#define MB_BOOTL_BP_REG2 (6) // tracks which image selected -+#define MB_BOOTL_ERR_REG (7) -+#define MB_RUNTM_BP_REG1 (8) -+#define MB_RUNTM_BP_REG2 (9) // reserved for future bit definition. -+#define MB_RUNTM_ERR_REG (10) -+static void mailbox_init(void) -+{ -+ /* clear out default mbox values */ -+ int i; -+ for (i = 0; i < AST_MBX_COUNT; i++) -+ { -+ writel(0, AST_MBX_BASE + 4 * i); -+ } -+ /* by the time this is called, all the hardware init is done -+ * so we can mark that as complete */ -+ writel(0xff, AST_MBX_BASE + 4 * MB_HINIT_BP_REG1); -+ /* mark progress up through booting linux */ -+ writel(0x1f, AST_MBX_BASE + 4 * MB_BOOTL_BP_REG1); -+} -+ - extern void espi_init(void); - extern void kcs_init(void); - void ast_g5_intel(void) -@@ -597,6 +624,7 @@ void ast_g5_intel(void) - set_cpld_reg(PFR_CPLD_BOOT_CHECKPOINT_REG, PFR_CPLD_CHKPOINT_START); - - uart_init(); -+ mailbox_init(); - pwm_init(); - gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); - espi_init(); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0041-Disabling-boot-delay.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0041-Disabling-boot-delay.patch deleted file mode 100644 index 69ec33a17..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0041-Disabling-boot-delay.patch +++ /dev/null @@ -1,27 +0,0 @@ -From e21ee4b456addc93a9afed0cb52ac2a53d3b785a Mon Sep 17 00:00:00 2001 -From: arun-pm -Date: Thu, 30 Jan 2020 10:32:13 +0530 -Subject: [PATCH] Disabling boot delay - -Boot delay is changed to -2 so that BMC will not stop in u-boot by pressing -ESC key. ---- - include/configs/ast-common.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h -index 0bc7f2d75f..dce6bbf5aa 100644 ---- a/include/configs/ast-common.h -+++ b/include/configs/ast-common.h -@@ -70,7 +70,7 @@ - /* - * Environment Config - */ --#define CONFIG_BOOTDELAY 2 -+#define CONFIG_BOOTDELAY -2 - - /* - * Miscellaneous configurable options --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch deleted file mode 100644 index 1b4201f5e..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 23e29ce85056f2b296d938e1244b5b2f2160069e Mon Sep 17 00:00:00 2001 -From: Kuiying Wang -Date: Wed, 4 Mar 2020 13:21:12 +0800 -Subject: [PATCH] AST2600: PFR u-boot env changes as per PFR BMC image - -u-boot env changes as per PFR BMC flash layout. - -Signed-off-by: Kuiying Wang -Signed-off-by: Vikram Bodireddy ---- - include/configs/aspeed-common.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h -index 0ece4a1b94..6291e0e7d9 100644 ---- a/include/configs/aspeed-common.h -+++ b/include/configs/aspeed-common.h -@@ -53,13 +53,13 @@ - * Miscellaneous configurable options - */ - #ifndef CONFIG_BOOTCOMMAND --#define CONFIG_BOOTCOMMAND "bootm 20080000" -+#define CONFIG_BOOTCOMMAND "bootm 20b00000" - #endif - #define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define CONFIG_ENV_ADDR_REDUND - #define CONFIG_ENV_OVERWRITE - #define AST_FMC_CS0_BASE 0x20000000 /* CS0 */ --#define CONFIG_ENV_OFFSET 0x2400000 -+#define CONFIG_ENV_OFFSET 0xa0000 - #define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) - #define CONFIG_ENV_SIZE 0x10000 - #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) --- -2.20.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch deleted file mode 100644 index 3833d2a31..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 51ae3c80f20be3b8e010aa57041fa9c38076cc76 Mon Sep 17 00:00:00 2001 -From: Vikram Bodireddy -Date: Wed, 18 Mar 2020 21:47:11 +0530 -Subject: [PATCH] PFR- Skip counting WDT2 event when EXTRST# is set - -PFR CPLD drives EXTRST# of BMC to reset it during -firmware update and during recovery. On ast2500 the -EXTRST# is also setting WDT2/3 flags which is counted -as boot failures by u-boot and aborts the boot if -boot failures are more than 3. This change will skip -counting WDT2 flag if EXTRST# is also set in SCU3C. - -Tested: Verified BMC updates 4 times and checked that - the boot is not aborted at u-boot. - -Signed-off-by: Vikram Bodireddy ---- - board/aspeed/ast-g5/ast-g5-intel.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c -index 575061ff88..872c7a843a 100644 ---- a/board/aspeed/ast-g5/ast-g5-intel.c -+++ b/board/aspeed/ast-g5/ast-g5-intel.c -@@ -145,6 +145,7 @@ static const GPIOValue gpio_table[] = { - #define HOST_SERIAL_B_HIGH_SPEED (1 << 1) - - #define WATCHDOG_RESET_BIT 0x8 -+#define EXTRST_RESET_BIT 0x2 - #define BOOT_FAILURE_LIMIT 0x3 - - #define BRIGHTON_CITY_BOARD_ID 0 -@@ -572,7 +573,8 @@ void ast_g5_intel_late_init(void) - - boot_failures = get_boot_failures(); - -- if (reset_reason & WATCHDOG_RESET_BIT) -+ if ((reset_reason & WATCHDOG_RESET_BIT) && -+ !(reset_reason & EXTRST_RESET_BIT)) - set_boot_failures(boot_failures + 1); - else - set_boot_failures(0); --- -2.17.1 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg deleted file mode 100644 index 99ac5a220..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_MISC_INIT_R=y -CONFIG_LED=y -CONFIG_LED_BLINK=y -CONFIG_LED_GPIO=y -CONFIG_CMD_LED=y -CONFIG_TARGET_AST2600_INTEL=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SYS_ARCH_TIMER=y -CONFIG_USE_IRQ=y -CONFIG_CMD_IRQ=y -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x2400000 -CONFIG_BOOTCOMMAND="bootm 20080000" -CONFIG_TARGET_EVB_AST2600A1=n -CONFIG_PHY_NCSI=n -CONFIG_CMD_USB=n -CONFIG_CMD_EXT4=n -CONFIG_CMD_EXT4_WRITE=n -CONFIG_CMD_FAT=n -CONFIG_CMD_FS_GENERIC=n -CONFIG_CMD_MTDPARTS=n -CONFIG_EFI_PARTITION=n -CONFIG_USB=n -CONFIG_DM_USB=n -CONFIG_USB_EHCI_HCD=n -CONFIG_USB_STORAGE=n \ No newline at end of file diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-%.bbappend new file mode 100644 index 000000000..eee5194fb --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-%.bbappend @@ -0,0 +1,5 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +SRC_URI += " \ + file://fw_env.config \ + " diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend deleted file mode 100644 index e8f2bb571..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend +++ /dev/null @@ -1,26 +0,0 @@ -FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:" - -# the meta-phosphor layer adds this patch, which conflicts -# with the intel layout for environment - -SRC_URI_append_intel-ast2600 = " \ - file://fw_env.config \ - file://intel.cfg \ - file://0001-Add-ast2600-intel-as-a-new-board.patch \ - file://0021-AST2600-Enable-host-searial-port-clock-configuration.patch \ - file://0003-ast2600-intel-layout-environment-addr.patch \ - file://0004-AST2600-Adjust-default-GPIO-settings.patch \ - file://0005-Ast2600-Enable-interrupt-in-u-boot.patch \ - file://0006-SPI-Quad-IO-Mode.patch \ - file://0007-ast2600-Override-OTP-strap-settings.patch \ - file://0008-AST2600-Add-TPM-pulse-trigger.patch \ - " - -PFR_SRC_URI = " \ - file://0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch \ - " -SRC_URI_append_intel-ast2600 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" - -do_install_append () { - install -m 0644 ${WORKDIR}/fw_env.config ${S}/tools/env/fw_env.config -} diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend deleted file mode 100644 index f1035476a..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend +++ /dev/null @@ -1,72 +0,0 @@ -FILESEXTRAPATHS_append_intel-ast2500:= "${THISDIR}/files:" - -# the meta-phosphor layer adds this patch, which conflicts -# with the intel layout for environment -SRC_URI_remove_intel-ast2500 = " file://0001-configs-ast-Add-redundnant-env.patch" - -SRC_URI_append_intel-ast2500 = " \ - file://fw_env.config \ - file://0001-flash-use-readX-writeX-not-udelay.patch \ - file://0002-intel-layout-environment-addr.patch \ - file://0004-Make-sure-debug-uart-is-using-24MHz-clock-source.patch \ - file://0005-enable-passthrough-in-uboot.patch \ - file://0006-Add-Aspeed-g5-interrupt-support.patch \ - file://0007-Add-espi-support.patch \ - file://0008-add-sgio-support-for-port80-snoop-post-LEDs.patch \ - file://0009-Add-basic-GPIO-support.patch \ - file://0010-Update-Force-Firmware-Update-Jumper-to-use-new-gpio.patch \ - file://0011-Add-basic-timer-support-for-Aspeed-g5-in-U-Boot.patch \ - file://0012-Add-status-and-ID-LED-support.patch \ - file://0013-aspeed-Add-Pwm-Driver.patch \ - file://0014-Keep-interrupts-enabled-until-last-second.patch \ - file://0015-Rewrite-memmove-to-optimize-on-word-transfers.patch \ - file://0019-u-boot-full-platform-reset-espi-oob-ready.patch \ - file://0020-Enable-PCIe-L1-support.patch \ - file://0020-Add-system-reset-status-support.patch \ - file://0021-Config-host-uart-clock-source-using-environment-vari.patch \ - file://0022-KCS-driver-support-in-uBoot.patch \ - file://0023-Add-TPM-enable-pulse-triggering.patch \ - file://0024-IPMI-command-handler-implementation-in-uboot.patch \ - file://0025-Manufacturing-mode-physical-presence-detection.patch \ - file://0026-Aspeed-I2C-support-in-U-Boot.patch \ - file://0027-CPLD-u-boot-commands-support-for-PFR.patch \ - file://0028-Enabling-uart1-uart2-in-u-boot-for-BIOS-messages.patch \ - file://0029-FFUJ-FW-IPMI-commands-and-flash-support-in-u-boot.patch \ - file://0030-Support-Get-Set-Security-mode-command.patch \ - file://0031-Make-it-so-TFTP-port-can-be-modified.patch \ - file://0033-Reboot-into-UBOOT-on-Watchdog-Failures.patch \ - file://0034-Disable-uart-debug-interface.patch \ - file://0036-Re-Enable-KCS.patch \ - file://0037-aspeed-ast-scu.c-fix-MAC1LINK-and-MAC2LINK-pin-pads-.patch \ - file://0038-Increase-default-fan-speed-for-cooper-city.patch \ - file://0040-Initialize-the-BMC-host-mailbox-at-reset-time.patch \ - " -PFR_SRC_URI = " \ - file://0022-u-boot-env-change-for-PFR-image.patch \ - file://0032-PFR-FW-update-and-checkpoint-support-in-u-boot.patch \ - file://0035-PFR-platform-EXTRST-reset-mask-selection.patch \ - file://0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch \ - " -AUTOBOOT_SRC_URI = " \ - file://0041-Disabling-boot-delay.patch \ - " -SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" -SRC_URI_append_intel-ast2500 += "${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'debug-tweaks', '', AUTOBOOT_SRC_URI, d)}" -do_install_append () { - install -m 0644 ${WORKDIR}/fw_env.config ${S}/tools/env/fw_env.config -} - -require recipes-core/os-release/version-vars.inc - -python do_version () { - with open(d.expand('${S}/board/aspeed/ast-g5/intel-version.h'), 'w') as f: - f.write(d.expand('#define VER_MAJOR ${IPMI_MAJOR}\n')) - f.write(d.expand('#define VER_MINOR ${IPMI_MINOR}\n')) - f.write(d.expand('#define VER_AUX13 ${IPMI_AUX13}\n')) - f.write(d.expand('#define VER_AUX14 ${IPMI_AUX14}\n')) - f.write(d.expand('#define VER_AUX15 ${IPMI_AUX15}\n')) - f.write(d.expand('#define VER_AUX16 ${IPMI_AUX16}\n')) -} - -do_version[vardepsexclude] = "IPMI_MAJOR IPMI_MINOR IPMI_AUX13 IPMI_AUX14 IPMI_AUX15 IPMI_AUX16 PRODUCT_GENERATION VERSION VERSION_ID BUILD_ID" -addtask do_version after do_configure before do_compile diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend deleted file mode 100644 index a69056ecc..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend +++ /dev/null @@ -1,18 +0,0 @@ -FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:" - -SRC_URI_append_intel-ast2600 = " \ - file://fw_env.config \ - file://intel.cfg \ - file://0001-Add-ast2600-intel-as-a-new-board.patch \ - file://0003-ast2600-intel-layout-environment-addr.patch \ - " -PFR_SRC_URI = " \ - file://0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch \ - " -SRC_URI_append_intel-ast2600 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" - -do_install_append () { - install -m 0644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config - install -m 0644 ${WORKDIR}/fw_env.config ${S}/tools/env/fw_env.config -} -RDEPENDS_${PN} = "udev-aspeed-mtd-partitions" diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend deleted file mode 120000 index 742334ade..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend +++ /dev/null @@ -1 +0,0 @@ -u-boot-aspeed_%.bbappend \ No newline at end of file -- cgit v1.2.3