From 225376f0a37ee9b6f20626e5f377d8833ea1727f Mon Sep 17 00:00:00 2001 From: Ed Tanous Date: Mon, 18 Mar 2019 13:46:22 -0700 Subject: Update to internal Signed-off-by: Ed Tanous --- .../0001-Create-intel-purley-dts.patch | 31 +- .../recipes-kernel/linux/linux-aspeed/wolfpass.cfg | 9 + .../entity-manager/TNP-baseboard.json | 1945 ++++++++++++++++++++ .../configuration/entity-manager_%.bbappend | 3 +- .../fru/default-fru/S2600TNP.fru.bin | Bin 0 -> 512 bytes .../recipes-phosphor/fru/default-fru/checkFru.sh | 11 +- 6 files changed, 1984 insertions(+), 15 deletions(-) create mode 100644 meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager/TNP-baseboard.json create mode 100644 meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/S2600TNP.fru.bin (limited to 'meta-openbmc-mods/meta-wolfpass') diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-Create-intel-purley-dts.patch b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-Create-intel-purley-dts.patch index dc3f9846d..518b0067e 100644 --- a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-Create-intel-purley-dts.patch +++ b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/0001-Create-intel-purley-dts.patch @@ -1,4 +1,4 @@ -From 939070905b0d6d70b2e39d424e0797451efdedf8 Mon Sep 17 00:00:00 2001 +From fb77288a4cb922bea97003a6ece97c527df8a0f2 Mon Sep 17 00:00:00 2001 From: Yuan Li Date: Tue, 19 Sep 2017 15:55:39 +0800 Subject: [PATCH] ARM: dts: purley: Merge all dts node in the unified patch. @@ -21,22 +21,23 @@ The below changes to the dts file are merged together: * uart4/serail3 * enable high speed uart clock * timer pwm +* cpu0/1fault LEDs Signed-off-by: Yuan Li Signed-off-by: Yong Li Signed-off-by: James Feist Signed-off-by: Jae Hyun Yoo --- - arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 347 ++++++++++++++++++++++++++ - 1 file changed, 347 insertions(+) + arch/arm/boot/dts/aspeed-bmc-intel-purley.dts | 357 ++++++++++++++++++++++++++ + 1 file changed, 357 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-purley.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts new file mode 100644 -index 000000000000..8a18645e6316 +index 000000000000..4d70d776e330 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-intel-purley.dts -@@ -0,0 +1,347 @@ +@@ -0,0 +1,357 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" @@ -100,16 +101,27 @@ index 000000000000..8a18645e6316 + compatible = "gpio-leds"; + + identify { ++ default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + }; + + status_amber { ++ default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; + }; + + status_green { ++ default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; + }; ++ ++ cpu0fault { ++ gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpu1fault { ++ gpios = <&gpio ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>; ++ }; + }; + + beeper { @@ -263,10 +275,12 @@ index 000000000000..8a18645e6316 +}; + +&i2c1 { ++ multi-master; + status = "okay"; +}; + +&i2c2 { ++ multi-master; + status = "okay"; +}; + @@ -297,17 +311,14 @@ index 000000000000..8a18645e6316 +}; + +&i2c6 { ++ multi-master; + status = "okay"; +}; + +&i2c7 { + multi-master; ++ #retries = <3>; + status = "okay"; -+ -+ smlink1-pmbus1@10 { -+ compatible = "slave-mqueue"; -+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; -+ }; +}; + +&gfx { diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/wolfpass.cfg b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/wolfpass.cfg index 9549d4d7b..480d4cc18 100644 --- a/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/wolfpass.cfg +++ b/meta-openbmc-mods/meta-wolfpass/recipes-kernel/linux/linux-aspeed/wolfpass.cfg @@ -8,6 +8,7 @@ CONFIG_ASPEED_ADC=y CONFIG_SGPIO_ASPEED=y CONFIG_CRC8=y CONFIG_PECI=y +CONFIG_PECI_CHARDEV=y CONFIG_PECI_ASPEED=y CONFIG_SENSORS_PECI_CPUTEMP=y CONFIG_SENSORS_PECI_DIMMTEMP=y @@ -58,3 +59,11 @@ CONFIG_PWM=y CONFIG_PWM_FTTMR010=y CONFIG_INPUT_MISC=y CONFIG_INPUT_PWM_BEEPER=y +CONFIG_VFAT_FS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y + diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager/TNP-baseboard.json b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager/TNP-baseboard.json new file mode 100644 index 000000000..01b899061 --- /dev/null +++ b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager/TNP-baseboard.json @@ -0,0 +1,1945 @@ +{ + "Exposes": [ + { + "Address": "0x4A", + "Bus": 6, + "Name": "BMC Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Index": 0, + "Name": "Baseboard 12 Volt", + "PowerState": "On", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Name": "CPU 1 Fan Connector", + "Pwm": 7, + "Status": "disabled", + "Tachs": [ + 13 + ], + "Type": "IntelFanConnector" + }, + { + "Name": "CPU 2 Fan Connector", + "Pwm": 8, + "Status": "disabled", + "Tachs": [ + 14 + ], + "Type": "IntelFanConnector" + }, + { + "Address": "0x49", + "Bus": 6, + "Name": "Left Rear Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Index": 4, + "Name": "P0V83_LAN_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 0.901 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 0.875 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.786 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.763 + } + ], + "Type": "ADC" + }, + { + "Index": 3, + "Name": "P105_PCH_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.139 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.106 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.995 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.966 + } + ], + "Type": "ADC" + }, + { + "Index": 5, + "Name": "P12V_AUX", + "ScaleFactor": 0.1124, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 13.494 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 13.101 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 10.945 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 10.616 + } + ], + "Type": "ADC" + }, + { + "Index": 6, + "Name": "P1V8_PCH", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.961 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.904 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.699 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.648 + } + ], + "Type": "ADC" + }, + { + "Index": 1, + "Name": "P3V3", + "PowerState": "On", + "ScaleFactor": 0.4107, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 3.647 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 3.541 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 3.066 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 2.974 + } + ], + "Type": "ADC" + }, + { + "Index": 7, + "Name": "P3VBAT", + "ScaleFactor": 0.3333, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 3.296 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 3.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 2.457 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 2.138 + } + ], + "Type": "ADC" + }, + { + "Index": 8, + "Name": "PVCCIN_CPU0", + "PowerState": "On", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 2.151 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 2.088 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.418 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.376 + } + ], + "Type": "ADC" + }, + { + "Index": 9, + "Name": "PVCCIN_CPU1", + "PowerState": "On", + "ScaleFactor": 0.7505, + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 2.151 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 2.088 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.418 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.376 + } + ], + "Type": "ADC" + }, + { + "Index": 14, + "Name": "PVCCIO_CPU0", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.19 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.155 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.752 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.729 + } + ], + "Type": "ADC" + }, + { + "Index": 15, + "Name": "PVCCIO_CPU1", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.19 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.155 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.752 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.729 + } + ], + "Type": "ADC" + }, + { + "Index": 10, + "Name": "PVDQ_ABCD_CPU0", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 12, + "Name": "PVDQ_ABCD_CPU1", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 11, + "Name": "PVDQ_EFGH_CPU0", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 13, + "Name": "PVDQ_EFGH_CPU1", + "PowerState": "On", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.301 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.263 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 1.138 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 1.104 + } + ], + "Type": "ADC" + }, + { + "Index": 2, + "Name": "PVNN_PCH_AUX", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 1.081 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 1.049 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 0.807 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0.783 + } + ], + "Type": "ADC" + }, + { + "Address": "0x4D", + "Bus": 6, + "Name": "Right Rear Board Temp", + "Name1": "Right Rear TMP421 Internal Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP421" + }, + { + "Address": "0x48", + "Bus": 6, + "Name": "Voltage Regulator 1 Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x4B", + "Bus": 6, + "Name": "Voltage Regulator 2 Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "TMP75" + }, + { + "Address": "0x30", + "Bus": 0, + "CpuID": 0, + "Name": "Skylake CPU 0", + "Thresholds": [ + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper critical", + "Severity": 1, + "Value": 99 + }, + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper non critical", + "Severity": 0, + "Value": 89 + } + ], + "Type": "SkylakeCPU" + }, + { + "Address": "0x31", + "Bus": 0, + "CpuID": 1, + "Name": "Skylake CPU 1", + "Thresholds": [ + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper critical", + "Severity": 1, + "Value": 99 + }, + { + "Direction": "greater than", + "Label": "DIMM", + "Name": "upper non critical", + "Severity": 0, + "Value": 89 + } + ], + "Type": "SkylakeCPU" + }, + { + "Direction": "In", + "Index": 32, + "Name": "Reset Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 33, + "Name": "Reset Out", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Both", + "Index": 34, + "Name": "Power Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Both", + "Index": 35, + "Name": "Power Up", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 40, + "Name": "NMI Out", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 50, + "Name": "PCH Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 51, + "Name": "Lcp Enter Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 52, + "Name": "Lcp Left Button", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 53, + "Name": "Lcp Right Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 49, + "Name": "Cpu Caterr", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 48, + "Name": "Cpu Err2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 63, + "Name": "PU 240VA Status", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 208, + "Name": "P3v3bat BridgeEn", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 214, + "Name": "Nmi Button", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 215, + "Name": "Post complete", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 217, + "Name": "Nmi Button", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 218, + "Name": "ID Button", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 219, + "Name": "Power Good", + "Polarity": "High", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 232, + "Name": "Post Complete led0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 233, + "Name": "Post Complete led1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 233, + "Name": "CPU1 Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 234, + "Name": "Post Complete led2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 234, + "Name": "CPU1 VR Hot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 235, + "Name": "Post Complete led3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 236, + "Name": "Post Complete led4", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 236, + "Name": "CPU1 Mem VR Hot1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 237, + "Name": "Post Complete led5", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 237, + "Name": "CPU1 Mem VR Hot2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 238, + "Name": "Post Complete led6", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 239, + "Name": "Post Complete led7", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 232, + "Name": "CPU1 Present", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 235, + "Name": "CPU1 FIVR Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 238, + "Name": "CPU1 ID0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 240, + "Name": "CPU1 CH1 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 240, + "Name": "CPU1 Mismatch", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 241, + "Name": "CPU1 CH1 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 241, + "Name": "CPU1 DIMM Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 242, + "Name": "CPU1 CH2 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 242, + "Name": "CPU2 Present", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 243, + "Name": "CPU1 CH2 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 243, + "Name": "CPU2 Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 244, + "Name": "CPU1 CH3 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 244, + "Name": "CPU2 VR Hot", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 245, + "Name": "CPU1 CH3 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 245, + "Name": "CPU2 FIVR Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 246, + "Name": "CPU1 CH4 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 246, + "Name": "CPU2 Mem VR Hot1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 247, + "Name": "CPU1 CH4 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 247, + "Name": "CPU1 Mem VR Hot2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 248, + "Name": "CPU1 CH5 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 248, + "Name": "CPU2 ID0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 249, + "Name": "CPU1 CH5 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 250, + "Name": "CPU1 CH6 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 250, + "Name": "CPU2 Mismatch", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 251, + "Name": "CPU1 CH6 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 251, + "Name": "CPU2 DIMM Thermaltrip", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 252, + "Name": "Fan1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 253, + "Name": "Fan2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 254, + "Name": "Fan3 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 255, + "Name": "Fan4 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 256, + "Name": "Fan5 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 257, + "Name": "Fan6 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 258, + "Name": "Fan7 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 259, + "Name": "Fan8 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 260, + "Name": "CPU2 CH1 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 261, + "Name": "CPU1 CH1 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 262, + "Name": "CPU2 CH2 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 263, + "Name": "CPU2 CH2 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 264, + "Name": "CPU2 CH3 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 265, + "Name": "CPU2 CH3 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 266, + "Name": "CPU2 CH4 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 267, + "Name": "CPU2 CH4 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 268, + "Name": "CPU2 CH5 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 269, + "Name": "CPU2 CH5 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 270, + "Name": "CPU2 CH6 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 271, + "Name": "CPU2 CH6 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 272, + "Name": "CPU3 CH1 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 272, + "Name": "PLD Minor Revison Bit 0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 273, + "Name": "CPU3 CH1 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 273, + "Name": "PLD Minor Revison Bit 1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 274, + "Name": "CPU3 CH2 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 274, + "Name": "PLD Minor Revison Bit 2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 275, + "Name": "CPU3 CH2 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 275, + "Name": "PLD Minor Revison Bit 3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 276, + "Name": "CPU3 CH3 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 276, + "Name": "PLD Major Revison Bit 0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 277, + "Name": "CPU3 CH3 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 277, + "Name": "PLD Major Revison Bit 1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 278, + "Name": "CPU3 CH4 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 278, + "Name": "PLD Major Revison Bit 2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 279, + "Name": "CPU3 CH4 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 279, + "Name": "PLD Major Revison Bit 2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 280, + "Name": "CPU3 CH5 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 280, + "Name": "Main PLD Minor Revison Bit 0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 281, + "Name": "CPU3 CH5 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 281, + "Name": "Main PLD Minor Revison Bit 1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 282, + "Name": "CPU3 CH6 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 282, + "Name": "Main PLD Minor Revison Bit 2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 283, + "Name": "CPU3 CH6 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 283, + "Name": "Main PLD Minor Revison Bit 3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 284, + "Name": "CPU4 CH1 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 284, + "Name": "Main PLD Major Revison Bit 0", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 285, + "Name": "CPU4 CH1 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 285, + "Name": "Main PLD Major Revison Bit 1", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 286, + "Name": "CPU4 CH2 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 286, + "Name": "Main PLD Major Revison Bit 2", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 287, + "Name": "CPU4 CH2 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 287, + "Name": "Main PLD Major Revison Bit 3", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 288, + "Name": "CPU4 CH3 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 289, + "Name": "CPU4 CH3 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 289, + "Name": "Memory Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 290, + "Name": "CPU4 CH4 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 290, + "Name": "CPU Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 291, + "Name": "CPU4 CH4 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 291, + "Name": "P5V P3V3 Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 292, + "Name": "CPU4 CH5 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 292, + "Name": "PSU Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 293, + "Name": "CPU4 CH5 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 293, + "Name": "SAS Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 294, + "Name": "CPU4 CH6 DIMM1 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 294, + "Name": "Lan Aux Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Out", + "Index": 295, + "Name": "CPU4 CH6 DIMM2 FAULT", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Direction": "Input", + "Index": 295, + "Name": "PCH Pwr Fault", + "Polarity": "Low", + "Type": "Gpio" + }, + { + "Address": "0x8", + "Class": "METemp", + "Name": "SSB Temp", + "PowerState": "BiosPost", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 103 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 98 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x7c", + "Class": "PxeBridgeTemp", + "Name": "CPU1 P12V PVCCIO VR Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x70", + "Class": "PxeBridgeTemp", + "Name": "CPU1 P12V PVCCIN VR Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x74", + "Class": "PxeBridgeTemp", + "Name": "CPU1 VR Mem ABC Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x78", + "Class": "PxeBridgeTemp", + "Name": "CPU1 VR Mem DEF Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x9c", + "Class": "PxeBridgeTemp", + "Name": "CPU2 P12V PVCCIO VR Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x50", + "Class": "PxeBridgeTemp", + "Name": "CPU2 P12V PVCCIN VR Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x94", + "Class": "PxeBridgeTemp", + "Name": "CPU2 VR Mem ABC Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x98", + "Class": "PxeBridgeTemp", + "Name": "CPU2 VR Mem DEF Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0xAC", + "Class": "PxeBridgeTemp", + "Name": "VR P1V05 Temp", + "Thresholds": [ + { + "Direction": "greater than", + "Name": "upper critical", + "Severity": 1, + "Value": 115 + }, + { + "Direction": "greater than", + "Name": "upper non critical", + "Severity": 0, + "Value": 110 + }, + { + "Direction": "less than", + "Name": "lower non critical", + "Severity": 0, + "Value": 5 + }, + { + "Direction": "less than", + "Name": "lower critical", + "Severity": 1, + "Value": 0 + } + ], + "Type": "IpmbSensor" + }, + { + "Address": "0x71", + "Bus": 2, + "ChannelNames": [ + "M2_Slot1", + "M2_Slot2", + "", + "" + ], + "Name": "M.2 Mux", + "Type": "PCA9543Mux" + } + ], + "Name": "TNP Baseboard", + "Probe": "xyz.openbmc_project.FruDevice({'PRODUCT_PRODUCT_NAME': '.*TNP'})", + "Type": "Board", + "xyz.openbmc_project.Inventory.Decorator.Asset": { + "Manufacturer": "$PRODUCT_MANUFACTURER", + "Model": "$PRODUCT_PRODUCT_NAME", + "PartNumber": "$PRODUCT_PART_NUMBER", + "SerialNumber": "$PRODUCT_SERIAL_NUMBER" + } +} diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager_%.bbappend b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager_%.bbappend index d9fe8e10f..51c47c35e 100644 --- a/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager_%.bbappend +++ b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/configuration/entity-manager_%.bbappend @@ -1,6 +1,7 @@ FILESEXTRAPATHS_append := ":${THISDIR}/${PN}" SRC_URI_append = " file://WC-Baseboard.json \ - file://WP-Baseboard.json" + file://WP-Baseboard.json \ + file://TNP-baseboard.json" RDEPENDS_${PN} += " default-fru" diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/S2600TNP.fru.bin b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/S2600TNP.fru.bin new file mode 100644 index 000000000..afd58e6b9 Binary files /dev/null and b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/S2600TNP.fru.bin differ diff --git a/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/checkFru.sh b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/checkFru.sh index b619dac8b..1eb79b299 100755 --- a/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/checkFru.sh +++ b/meta-openbmc-mods/meta-wolfpass/recipes-phosphor/fru/default-fru/checkFru.sh @@ -2,7 +2,7 @@ # this script checks the gpio id and loads the correct baseboard fru fruFile="/etc/fru/baseboard.fru.bin" -idGpio=( 8 9 10 11 12) +idGpio=( 8 9 10 11 12 53) result=0 idx=0 @@ -21,14 +21,17 @@ do done # wp -if (($result == 30)); then +if (($result == 62)); then cat S2600WP.fru.bin > $fruFile # wc -elif (($result == 13)); then +elif (($result == 45)); then cat S2600WC.fru.bin > $fruFile # cyp -elif (($result == 28)); then +elif (($result == 60)); then cat S2600CYP.fru.bin > $fruFile +# tnp +elif (($result == 12)); then + cat S2600TNP.fru.bin > $fruFile # default to wft else cat S2600WFT.fru.bin > $fruFile -- cgit v1.2.3