From 5ccf3f257977e925c34031887d47f4279562d9c9 Mon Sep 17 00:00:00 2001
From: George Hung <george.hung@quantatw.com>
Date: Thu, 21 May 2020 18:59:15 +0800
Subject: meta-quanta: gbs: add xml for igps and patch/dts for u-boot

1.XML:
  change the SPI speed to 19Mhz

2.U-boot:
  dts/pinctrl: add GBS dts/pinctrl support

Nuvoton u-boot srcrev bump adb4ac1af3...6870e66f6b:
https://gerrit.openbmc-project.xyz/c/openbmc/meta-nuvoton/+/34756

3.modify u-boot environment partiions offset for GBS

(From meta-quanta rev: 705d71a8a0ee00f89f06c95601aa1375a440611a)

Signed-off-by: George Hung <george.hung@quantatw.com>
Change-Id: I47960d63b557f6de1c9d84b290094253f4ffba58
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
---
 meta-quanta/meta-gbs/conf/machine/gbs.conf         |  10 +-
 .../npcm7xx-igps-native/BootBlockAndHeader_GBS.xml | 276 +++++++++++++++++++++
 .../images/npcm7xx-igps-native/UbootHeader_GBS.xml | 194 +++++++++++++++
 .../images/npcm7xx-igps-native_%.bbappend          |  12 +
 .../u-boot/u-boot-fw-utils-nuvoton/fw_env.config   |  24 ++
 .../u-boot/u-boot-fw-utils-nuvoton_%.bbappend      |   6 +
 6 files changed, 518 insertions(+), 4 deletions(-)
 create mode 100644 meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/BootBlockAndHeader_GBS.xml
 create mode 100644 meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/UbootHeader_GBS.xml
 create mode 100644 meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native_%.bbappend
 create mode 100644 meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton/fw_env.config
 create mode 100644 meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton_%.bbappend

(limited to 'meta-quanta/meta-gbs')

diff --git a/meta-quanta/meta-gbs/conf/machine/gbs.conf b/meta-quanta/meta-gbs/conf/machine/gbs.conf
index 32dae060f..d5a6e7859 100644
--- a/meta-quanta/meta-gbs/conf/machine/gbs.conf
+++ b/meta-quanta/meta-gbs/conf/machine/gbs.conf
@@ -1,17 +1,19 @@
 KMACHINE = "nuvoton"
 KERNEL_DEVICETREE = "${KMACHINE}-npcm730-gbs.dtb"
 
-UBOOT_MACHINE = "PolegSVB_config"
+UBOOT_MACHINE = "PolegSVB_spinor_minimal_config"
+UBOOT_DEVICETREE = "nuvoton-npcm730-gbs"
 IGPS_MACHINE = "GBS"
 
-FLASH_SIZE = "32768"
-
 MACHINEOVERRIDES .= ":npcm7xx"
 
 require conf/machine/include/npcm7xx.inc
 require conf/machine/include/obmc-bsp-common.inc
 
-SERIAL_CONSOLES = "115200;ttyS0"
+# Overwrite flash offsets
+FLASH_ROFS_OFFSET = "7296"
+FLASH_RWFS_OFFSET = "61440"
+FLASH_SIZE = "65536"
 
 OBMC_MACHINE_FEATURES += "\
         obmc-phosphor-fan-mgmt \
diff --git a/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/BootBlockAndHeader_GBS.xml b/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/BootBlockAndHeader_GBS.xml
new file mode 100644
index 000000000..3c1e3be9e
--- /dev/null
+++ b/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/BootBlockAndHeader_GBS.xml
@@ -0,0 +1,276 @@
+<!-- SPDX-License-Identifier: GPL-2.0
+#
+# Nuvoton IGPS: Image Generation And Programming Scripts For Poleg BMC
+#
+# Copyright (C) 2018 Nuvoton Technologies, All Rights Reserved
+#--------------------------------------------------------------------------->
+
+<?xml version="1.0" encoding="UTF-8"?>
+
+<Bin_Ecc_Map>
+	<!-- BMC mandatory fields -->
+	<ImageProperties>
+		<BinSize>0</BinSize>         <!-- If 0 the binary size will be calculated by the tool -->
+		<PadValue>0xFF</PadValue>	<!-- Byte value to pad the empty areas, default is 0 -->
+	</ImageProperties>
+		
+	<BinField>
+		<!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or 
+			     uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) -->
+		<name>StartTag</name>         <!-- name of field -->
+		<config>
+			<offset>0</offset>           
+			<size>0x8</size> 
+		</config>
+		<content format='bytes'>0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42</content>  <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Code destination address, 32-bit aligned: for BootBlock should be 0xFFFD5E00 so code will run in 0xFFFD6000 as linked for -->
+		<name>DestAddr</name>         <!-- name of field -->
+		<config>
+			<offset>0x140</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0xFFFD5E00</content>     <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- BootBlock or u-boot Code size -->
+		<name>CodeSize</name>         <!-- name of field -->
+		<config>
+			<offset>0x144</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='FileSize'>Poleg_bootblock.bin</content>	<!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- The BootBlock or u-boot binary file -->
+		<name>Code</name>             <!-- name of field -->
+		<config>
+			<offset>0x200</offset>       
+			<size format='FileSize'>Poleg_bootblock.bin</size>                 <!-- size in the header calculated by tool-->
+		</config>
+		<content format='FileContent'>Poleg_bootblock.bin</content>  <!-- content the user should fill -->
+	</BinField>	
+	
+	<!-- BMC optional fields -->
+	<BinField>
+		<!-- Word contents copied by ROM code to FIU0 FIU_DRD_CFG register -->
+		<name>FIU0_DRD_CFG_Set</name>  <!-- name of field -->
+		<config>
+			<offset>0x108</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0x0300100B</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines the clock divide ratio from AHB to FIU0 clock -->
+		<name>FIU_Clk_Divider</name>  <!-- name of field -->
+		<config>
+			<offset>0x10C</offset>       
+			<size>0x1</size> 
+		</config>
+		<content format='bytes'>0x0A</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Version (Major.Minor) -->
+		<name>Version</name>          <!-- name of field -->
+		<config>
+			<offset>0x148</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0x0201</content>               <!-- content the user should fill -->
+	</BinField>
+		
+	<BinField>
+		<!-- Board manufaturer ( Dell = 0, Nuvoton = 100, Google = 1, MS = 2) -->
+		<name>BOARD_VENDOR</name>          <!-- name of field -->
+		<config>
+			<offset>0x14C</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>100</content>                              <!--Board_manufacturer: Nuvoton-->
+	</BinField>
+	<BinField>
+		<!-- Board type ( DRB = 0, SVB = 1, EB = 2,HORIZON = 3, SANDSTORM = 4, ROCKAWAY = 100 RunBMC = 10) -->
+		<!-- WARNING: Currently this value is only printed to serial. Set BOARD_VENDOR to 1 get Dell specific customization. -->
+		<name>BOARD_TYPE</name>          <!-- name of field -->
+		<config>
+			<offset>0x150</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0x64</content>                                   <!--Board_type: EB-->
+	</BinField>
+	
+	<!-- the next two fields are available since version 10.7.0 -->
+	<BinField>
+		<!-- supported values: 333,444,500,600,666,700,720,750,775,787,800,825,850,900,950,1000,1060 -->
+		<name>MC_FREQ_IN_MHZ</name>          <!-- name of field -->
+		<config>
+			<offset>0x11C</offset>       
+			<size>0x2</size> 
+		</config>
+		<content format='32bit'>800</content> 
+	</BinField>
+	<BinField>
+		<!-- supporeted values: 333,500,600,666,700,720,750,800,825,850,900,950,1000,1060 -->
+		<name>CPU_FREQ_IN_MHZ</name>          <!-- name of field -->
+		<config>
+			<offset>0x154</offset>       
+			<size>0x2</size> 
+		</config>
+		<content format='32bit'>800</content>
+	</BinField>
+	
+	<BinField>
+		<!-- MC_CONFIG. 
+			Bit 0: MC_DISABLE_CAPABILITY_INPUT_DQS_ENHANCE_TRAINING (0x01)
+			Bit 1:  MC_CAPABILITY_IGNORE_ECC_DEVICE         (0x02) -->
+		<name>MC_CONFIG</name>          <!-- name of field -->
+		<config>
+			<offset>0x156</offset>       
+			<size>0x1</size> 
+		</config>
+		<content format='32bit'>0x01</content>  
+	</BinField>
+
+	<BinField>
+		<!-- HOST_IF.
+			0xFF: LPC backward compatible
+			0x00: LPC. 
+			0x01: eSPI
+			0x02: GPIOs TRIS.  -->
+		<name>HOST_IF</name>          <!-- name of field -->
+		<config>
+			<offset>0x157</offset>       
+			<size>0x1</size> 
+		</config>
+		<content format='32bit'>0x00</content>
+	</BinField>
+	
+	<BinField>
+		<!-- SECURITY_LEVEL_T.
+			0xFF: SECURITY_LEVEL_UNKNOWN: backward compatible
+			0x00: SECURITY_LEVEL_NONE. 
+			0x01: SECURITY_LEVEL_STANDARD
+			0x02: SECURITY_LEVEL_NIST. (require BootBlock with NIST support) -->
+		<name>SECURITY_LEVEL_T</name>          <!-- name of field -->
+		<config>
+			<offset>0x15C</offset>       
+			<size>0x1</size> 
+		</config>
+		<content format='32bit'>0xFF</content>
+	</BinField>
+		
+	<BinField>
+		<!-- Key revoke (bitwise). Set bit 0 to revoke key 0 etc. -->
+		<name>SECURITY_REVOKE_KEYS</name>          <!-- name of field -->
+		<config>
+			<offset>0x1D7</offset>       
+			<size>0x1</size> 
+		</config>
+		<content format='bytes'>0x00</content>
+	</BinField>
+	
+	<BinField>
+		<!-- security log offset -->
+		<name>SECURITY_LOG</name>          <!-- name of field -->
+		<config>
+			<offset>0x1D8</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0x090000</content>
+	</BinField>
+	<BinField>
+		<!-- hole 0 size: used for NIST security. -->
+		<name>SECURITY_LOG_SIZE</name>          <!-- name of field -->
+		<config>
+			<offset>0x1DC</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0x3000</content>
+	</BinField>	
+	
+	
+	<BinField>
+		<!-- hole 0: used for NIST security. -->
+		<name>HOLE0</name>          <!-- name of field -->
+		<config>
+			<offset>0x1E0</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0x0A0000</content>
+	</BinField>
+	<BinField>
+		<!-- hole 0 size: used for NIST security. -->
+		<name>HOLE0_SIZE</name>          <!-- name of field -->
+		<config>
+			<offset>0x1E4</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0xF70000</content>
+	</BinField>
+	
+	<BinField>
+		<!-- hole 1: used for NIST security. -->
+		<name>HOLE1</name>          <!-- name of field -->
+		<config>
+			<offset>0x1E8</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0</content>
+	</BinField>
+	<BinField>
+		<!-- hole 1 size: used for NIST security. -->
+		<name>HOLE1_SIZE</name>          <!-- name of field -->
+		<config>
+			<offset>0x1EC</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0</content>
+	</BinField>
+	
+	
+	<BinField>
+		<!-- hole 2: used for NIST security. -->
+		<name>HOLE2</name>          <!-- name of field -->
+		<config>
+			<offset>0x1F0</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0xFFFFFFFF</content>
+	</BinField>
+	<BinField>
+		<!-- hole 2 size: used for NIST security. -->
+		<name>HOLE2_SIZE</name>          <!-- name of field -->
+		<config>
+			<offset>0x1F4</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0</content>
+	</BinField>
+	
+	<BinField>
+		<!-- hole 3: used for NIST security. -->
+		<name>HOLE3</name>          <!-- name of field -->
+		<config>
+			<offset>0x1F8</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0</content>
+	</BinField>
+	<BinField>
+		<!-- hole 3 size: used for NIST security. -->
+		<name>HOLE3_SIZE</name>          <!-- name of field -->
+		<config>
+			<offset>0x1FC</offset>       
+			<size>0x4</size> 
+		</config>
+		<content format='32bit'>0</content>
+	</BinField>
+	
+</Bin_Ecc_Map>
diff --git a/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/UbootHeader_GBS.xml b/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/UbootHeader_GBS.xml
new file mode 100644
index 000000000..b99e7e618
--- /dev/null
+++ b/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/UbootHeader_GBS.xml
@@ -0,0 +1,194 @@
+<!-- SPDX-License-Identifier: GPL-2.0
+#
+# Nuvoton IGPS: Image Generation And Programming Scripts For Poleg BMC
+#
+# Copyright (C) 2018 Nuvoton Technologies, All Rights Reserved
+#--------------------------------------------------------------------------->
+
+<?xml version="1.0" encoding="UTF-8"?>
+
+<Bin_Ecc_Map>
+	<!-- BMC mandatory fields -->
+	<ImageProperties>
+		<BinSize>0</BinSize>         <!-- If 0 the binary size will be calculated by the tool -->
+		<PadValue>0xFF</PadValue>	<!-- Byte value to pad the empty areas, default is 0 -->
+	</ImageProperties>
+		
+	<BinField>
+		<!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or 
+			     uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) -->
+		<name>StartTag</name>         <!-- name of field -->
+		<config>
+			<offset>0</offset>            <!-- offset in the header -->
+			<size>0x8</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B</content>  <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Code destination address, 32-bit aligned: for u-boot should be 0x80005000 so code will run in 0x80005200 as linked for -->
+		<name>DestAddr</name>         <!-- name of field -->
+		<config>
+			<offset>0x140</offset>        <!-- offset in the header -->
+			<size>0x4</size>              <!-- size in the header -->
+		</config>
+		<content format='32bit'>0x8000</content>  <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- BootBlock or u-boot Code size -->
+		<name>CodeSize</name>         <!-- name of field -->
+		<config>
+			<offset>0x144</offset>        <!-- offset in the header -->
+			<size>0x4</size>              <!-- size in the header -->
+		</config>
+		<content format='FileSize'>u-boot.bin</content>	<!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- The BootBlock or u-boot binary file -->
+		<name>Code</name>             <!-- name of field -->
+		<config>
+			<offset>0x200</offset>        <!-- offset in the header -->
+			<size format='FileSize'>u-boot.bin</size>                 <!-- size in the header calculated by tool-->
+		</config>
+		<content format='FileContent'>u-boot.bin</content>  <!-- content the user should fill -->
+	</BinField>	
+	
+	<!-- BMC optional fields -->
+	<BinField>
+		<!-- Word contents copied by ROM code to FIU0 FIU_DRD_CFG register -->
+		<name>FIU0_DRD_CFG_Set</name>  <!-- name of field -->
+		<config>
+			<offset>0x108</offset>        <!-- offset in the header -->
+			<size>0x4</size>              <!-- size in the header -->
+		</config>
+		<content format='32bit'>0x0300100B</content>               <!-- content the user should fill 0x030032EB -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines the clock divide ratio from AHB to FIU0 clock -->
+		<name>FIU0_Clk_Divider</name>  <!-- name of field -->
+		<config>
+			<offset>0x10C</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines if FIU0 CS1 is enabled -->
+		<name>fiu0_cs1_en</name>  <!-- name of field -->
+		<config>
+			<offset>0x10D</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines if FIU0 CS2 is enabled -->
+		<name>fiu0_cs2_en</name>  <!-- name of field -->
+		<config>
+			<offset>0x10E</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines if FIU0 CS3 is enabled -->
+		<name>fiu0_cs3_en</name>  <!-- name of field -->
+		<config>
+			<offset>0x10F</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<!-- BMC optional fields -->
+	<BinField>
+		<!-- Word contents copied by ROM code to FIU3 FIU_DRD_CFG register -->
+		<name>FIU3_DRD_CFG_Set</name>  <!-- name of field -->
+		<config>
+			<offset>0x110</offset>        <!-- offset in the header -->
+			<size>0x4</size>              <!-- size in the header -->
+		</config>
+		<content format='32bit'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<!-- BMC optional fields -->
+	<BinField>
+		<!-- Word contents copied by ROM code to FIU3 FIU_DRD_CFG register -->
+		<name>FIU3_DWR_CFG_Set</name>  <!-- name of field -->
+		<config>
+			<offset>0x114</offset>        <!-- offset in the header -->
+			<size>0x4</size>              <!-- size in the header -->
+		</config>
+		<content format='32bit'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines the clock divide ratio from AHB to FIU3 clock -->
+		<name>FIU3_Clk_Divider</name>  <!-- name of field -->
+		<config>
+			<offset>0x118</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+
+	<BinField>
+		<!-- Defines if FIU3 CS1 is enabled -->
+		<name>fiu3_cs1_en</name>  <!-- name of field -->
+		<config>
+			<offset>0x119</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines if FIU3 CS2 is enabled -->
+		<name>fiu3_cs2_en</name>  <!-- name of field -->
+		<config>
+			<offset>0x11A</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Defines if FIU3 CS3 is enabled -->
+		<name>fiu3_cs3_en</name>  <!-- name of field -->
+		<config>
+			<offset>0x11B</offset>        <!-- offset in the header -->
+			<size>0x1</size>              <!-- size in the header -->
+		</config>
+		<content format='bytes'>0x0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	<BinField>
+		<!-- Version (Major.Minor) -->
+		<name>Version</name>          <!-- name of field -->
+		<config>
+			<offset>0x148</offset>        <!-- offset in the header -->
+			<size>0x4</size>              <!-- size in the header -->
+		</config>
+		<content format='32bit'>0</content>               <!-- content the user should fill -->
+	</BinField>
+	
+		<!-- BMC optional fields -->
+	<BinField>
+		<!-- Word contents copied by BB code to FIU0 FIU_DWR_CFG register -->
+		<name>FIU0_DWR_CFG_Set</name>  <!-- name of field -->
+		<config>
+			<offset>0x14C</offset>        <!-- offset in the header -->
+			<size>0x4</size>              <!-- size in the header -->
+		</config>
+		<content format='32bit'>0x03001102</content>               <!-- content the user should fill -->
+	</BinField>
+	
+	
+</Bin_Ecc_Map>
diff --git a/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native_%.bbappend b/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native_%.bbappend
new file mode 100644
index 000000000..06bc31f6a
--- /dev/null
+++ b/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native_%.bbappend
@@ -0,0 +1,12 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI_append += "file://BootBlockAndHeader_GBS.xml"
+SRC_URI_append += "file://UbootHeader_GBS.xml"
+
+# Prepare the Bootblock XMLs.
+do_gbs_prepare_xmls() {
+    cp ${WORKDIR}/BootBlockAndHeader_GBS.xml ${S}/ImageGeneration/references/
+    cp ${WORKDIR}/UbootHeader_GBS.xml ${S}/ImageGeneration/references/
+}
+
+addtask do_gbs_prepare_xmls after do_patch before do_install
diff --git a/meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton/fw_env.config b/meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton/fw_env.config
new file mode 100644
index 000000000..0c384273f
--- /dev/null
+++ b/meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton/fw_env.config
@@ -0,0 +1,24 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
+# Futhermore, if the Flash sector size is ommitted, this value is assumed to
+# be the same as the Environment size, which is valid for NOR and SPI-dataflash
+
+# NOR example
+# MTD device name	Device offset	Env. size	Flash sector size	Number of sectors
+/dev/mtd2		0x0000		0x40000		0x4000
+
+# MTD SPI-dataflash example
+# MTD device name	Device offset	Env. size	Flash sector size	Number of sectors
+#/dev/mtd5		0x4200		0x4200
+#/dev/mtd6		0x4200		0x4200
+
+# NAND example
+#/dev/mtd0		0x4000		0x4000		0x20000			2
+
+# Block device example
+#/dev/mmcblk0		0xc0000		0x20000
+
+# VFAT example
+#/boot/uboot.env	0x0000          0x4000
diff --git a/meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton_%.bbappend b/meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton_%.bbappend
new file mode 100644
index 000000000..8b66271a5
--- /dev/null
+++ b/meta-quanta/meta-gbs/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton_%.bbappend
@@ -0,0 +1,6 @@
+FILESEXTRAPATHS_prepend_gbs := "${THISDIR}/${PN}:"
+SRC_URI_append_gbs = " file://fw_env.config"
+
+do_install_append_gbs() {
+	install -m 644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config
+}
-- 
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